1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * AMD SoC Power Management Controller Driver 4 * 5 * Copyright (c) 2023, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Mario Limonciello <mario.limonciello@amd.com> 9 */ 10 11 #ifndef PMC_H 12 #define PMC_H 13 14 #include <linux/types.h> 15 #include <linux/mutex.h> 16 17 struct amd_pmc_dev { 18 void __iomem *regbase; 19 void __iomem *smu_virt_addr; 20 void __iomem *stb_virt_addr; 21 void __iomem *fch_virt_addr; 22 bool msg_port; 23 u32 base_addr; 24 u32 cpu_id; 25 u32 active_ips; 26 u32 dram_size; 27 u32 num_ips; 28 u32 s2d_msg_id; 29 /* SMU version information */ 30 u8 smu_program; 31 u8 major; 32 u8 minor; 33 u8 rev; 34 struct device *dev; 35 struct pci_dev *rdev; 36 struct mutex lock; /* generic mutex lock */ 37 struct dentry *dbgfs_dir; 38 struct quirk_entry *quirks; 39 bool disable_8042_wakeup; 40 }; 41 42 void amd_pmc_process_restore_quirks(struct amd_pmc_dev *dev); 43 void amd_pmc_quirks_init(struct amd_pmc_dev *dev); 44 45 /* List of supported CPU ids */ 46 #define AMD_CPU_ID_RV 0x15D0 47 #define AMD_CPU_ID_RN 0x1630 48 #define AMD_CPU_ID_PCO AMD_CPU_ID_RV 49 #define AMD_CPU_ID_CZN AMD_CPU_ID_RN 50 #define AMD_CPU_ID_YC 0x14B5 51 #define AMD_CPU_ID_CB 0x14D8 52 #define AMD_CPU_ID_PS 0x14E8 53 #define AMD_CPU_ID_SP 0x14A4 54 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 55 56 #endif /* PMC_H */ 57