1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * AMD SoC Power Management Controller Driver 4 * 5 * Copyright (c) 2020, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/acpi.h> 14 #include <linux/array_size.h> 15 #include <linux/bitfield.h> 16 #include <linux/bits.h> 17 #include <linux/debugfs.h> 18 #include <linux/delay.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/limits.h> 22 #include <linux/module.h> 23 #include <linux/pci.h> 24 #include <linux/platform_device.h> 25 #include <linux/rtc.h> 26 #include <linux/serio.h> 27 #include <linux/suspend.h> 28 #include <linux/seq_file.h> 29 #include <linux/uaccess.h> 30 31 #include <asm/amd_node.h> 32 33 #include "pmc.h" 34 35 static const struct amd_pmc_bit_map soc15_ip_blk_v2[] = { 36 {"DISPLAY", BIT(0)}, 37 {"CPU", BIT(1)}, 38 {"GFX", BIT(2)}, 39 {"VDD", BIT(3)}, 40 {"VDD_CCX", BIT(4)}, 41 {"ACP", BIT(5)}, 42 {"VCN_0", BIT(6)}, 43 {"VCN_1", BIT(7)}, 44 {"ISP", BIT(8)}, 45 {"NBIO", BIT(9)}, 46 {"DF", BIT(10)}, 47 {"USB3_0", BIT(11)}, 48 {"USB3_1", BIT(12)}, 49 {"LAPIC", BIT(13)}, 50 {"USB3_2", BIT(14)}, 51 {"USB4_RT0", BIT(15)}, 52 {"USB4_RT1", BIT(16)}, 53 {"USB4_0", BIT(17)}, 54 {"USB4_1", BIT(18)}, 55 {"MPM", BIT(19)}, 56 {"JPEG_0", BIT(20)}, 57 {"JPEG_1", BIT(21)}, 58 {"IPU", BIT(22)}, 59 {"UMSCH", BIT(23)}, 60 {"VPE", BIT(24)}, 61 }; 62 63 static const struct amd_pmc_bit_map soc15_ip_blk[] = { 64 {"DISPLAY", BIT(0)}, 65 {"CPU", BIT(1)}, 66 {"GFX", BIT(2)}, 67 {"VDD", BIT(3)}, 68 {"ACP", BIT(4)}, 69 {"VCN", BIT(5)}, 70 {"ISP", BIT(6)}, 71 {"NBIO", BIT(7)}, 72 {"DF", BIT(8)}, 73 {"USB3_0", BIT(9)}, 74 {"USB3_1", BIT(10)}, 75 {"LAPIC", BIT(11)}, 76 {"USB3_2", BIT(12)}, 77 {"USB3_3", BIT(13)}, 78 {"USB3_4", BIT(14)}, 79 {"USB4_0", BIT(15)}, 80 {"USB4_1", BIT(16)}, 81 {"MPM", BIT(17)}, 82 {"JPEG", BIT(18)}, 83 {"IPU", BIT(19)}, 84 {"UMSCH", BIT(20)}, 85 {"VPE", BIT(21)}, 86 }; 87 88 static bool disable_workarounds; 89 module_param(disable_workarounds, bool, 0644); 90 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs"); 91 92 static struct amd_pmc_dev pmc; 93 94 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset) 95 { 96 return ioread32(dev->regbase + reg_offset); 97 } 98 99 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val) 100 { 101 iowrite32(val, dev->regbase + reg_offset); 102 } 103 104 static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev) 105 { 106 switch (dev->cpu_id) { 107 case AMD_CPU_ID_PCO: 108 case AMD_CPU_ID_RN: 109 case AMD_CPU_ID_YC: 110 case AMD_CPU_ID_CB: 111 dev->num_ips = 12; 112 dev->ips_ptr = soc15_ip_blk; 113 dev->smu_msg = 0x538; 114 break; 115 case AMD_CPU_ID_PS: 116 dev->num_ips = 21; 117 dev->ips_ptr = soc15_ip_blk; 118 dev->smu_msg = 0x538; 119 break; 120 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: 121 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: 122 if (boot_cpu_data.x86_model == 0x70) { 123 dev->num_ips = ARRAY_SIZE(soc15_ip_blk_v2); 124 dev->ips_ptr = soc15_ip_blk_v2; 125 } else { 126 dev->num_ips = ARRAY_SIZE(soc15_ip_blk); 127 dev->ips_ptr = soc15_ip_blk; 128 } 129 dev->smu_msg = 0x938; 130 break; 131 } 132 } 133 134 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev) 135 { 136 if (dev->cpu_id == AMD_CPU_ID_PCO) { 137 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n"); 138 return -EINVAL; 139 } 140 141 /* Get Active devices list from SMU */ 142 if (!dev->active_ips) 143 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, true); 144 145 /* Get dram address */ 146 if (!dev->smu_virt_addr) { 147 u32 phys_addr_low, phys_addr_hi; 148 u64 smu_phys_addr; 149 150 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, true); 151 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, true); 152 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low); 153 154 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, 155 sizeof(struct smu_metrics)); 156 if (!dev->smu_virt_addr) 157 return -ENOMEM; 158 } 159 160 /* Start the logging */ 161 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, false); 162 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, false); 163 164 return 0; 165 } 166 167 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table) 168 { 169 int rc; 170 171 if (!pdev->smu_virt_addr) { 172 rc = amd_pmc_setup_smu_logging(pdev); 173 if (rc) 174 return rc; 175 } 176 177 if (pdev->cpu_id == AMD_CPU_ID_PCO) 178 return -ENODEV; 179 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics)); 180 return 0; 181 } 182 183 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev) 184 { 185 struct smu_metrics table; 186 187 if (get_metrics_table(pdev, &table)) 188 return; 189 190 if (!table.s0i3_last_entry_status) 191 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n"); 192 pm_report_hw_sleep_time(table.s0i3_last_entry_status ? 193 table.timein_s0i3_lastcapture : 0); 194 } 195 196 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev) 197 { 198 int rc; 199 u32 val; 200 201 if (dev->cpu_id == AMD_CPU_ID_PCO) 202 return -ENODEV; 203 204 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, true); 205 if (rc) 206 return rc; 207 208 dev->smu_program = (val >> 24) & GENMASK(7, 0); 209 dev->major = (val >> 16) & GENMASK(7, 0); 210 dev->minor = (val >> 8) & GENMASK(7, 0); 211 dev->rev = (val >> 0) & GENMASK(7, 0); 212 213 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n", 214 dev->smu_program, dev->major, dev->minor, dev->rev); 215 216 return 0; 217 } 218 219 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr, 220 char *buf) 221 { 222 struct amd_pmc_dev *dev = dev_get_drvdata(d); 223 int rc; 224 225 if (!dev->major) { 226 rc = amd_pmc_get_smu_version(dev); 227 if (rc) 228 return rc; 229 } 230 return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev); 231 } 232 233 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr, 234 char *buf) 235 { 236 struct amd_pmc_dev *dev = dev_get_drvdata(d); 237 int rc; 238 239 if (!dev->major) { 240 rc = amd_pmc_get_smu_version(dev); 241 if (rc) 242 return rc; 243 } 244 return sysfs_emit(buf, "%u\n", dev->smu_program); 245 } 246 247 static DEVICE_ATTR_RO(smu_fw_version); 248 static DEVICE_ATTR_RO(smu_program); 249 250 static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 251 { 252 struct device *dev = kobj_to_dev(kobj); 253 struct amd_pmc_dev *pdev = dev_get_drvdata(dev); 254 255 if (pdev->cpu_id == AMD_CPU_ID_PCO) 256 return 0; 257 return 0444; 258 } 259 260 static struct attribute *pmc_attrs[] = { 261 &dev_attr_smu_fw_version.attr, 262 &dev_attr_smu_program.attr, 263 NULL, 264 }; 265 266 static struct attribute_group pmc_attr_group = { 267 .attrs = pmc_attrs, 268 .is_visible = pmc_attr_is_visible, 269 }; 270 271 static const struct attribute_group *pmc_groups[] = { 272 &pmc_attr_group, 273 NULL, 274 }; 275 276 static int smu_fw_info_show(struct seq_file *s, void *unused) 277 { 278 struct amd_pmc_dev *dev = s->private; 279 struct smu_metrics table; 280 int idx; 281 282 if (get_metrics_table(dev, &table)) 283 return -EINVAL; 284 285 seq_puts(s, "\n=== SMU Statistics ===\n"); 286 seq_printf(s, "Table Version: %d\n", table.table_version); 287 seq_printf(s, "Hint Count: %d\n", table.hint_count); 288 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" : 289 "Unknown/Fail"); 290 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture); 291 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture); 292 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n", 293 table.timeto_resume_to_os_lastcapture); 294 295 seq_puts(s, "\n=== Active time (in us) ===\n"); 296 for (idx = 0 ; idx < dev->num_ips ; idx++) { 297 if (dev->ips_ptr[idx].bit_mask & dev->active_ips) 298 seq_printf(s, "%-8s : %lld\n", dev->ips_ptr[idx].name, 299 table.timecondition_notmet_lastcapture[idx]); 300 } 301 302 return 0; 303 } 304 DEFINE_SHOW_ATTRIBUTE(smu_fw_info); 305 306 static int s0ix_stats_show(struct seq_file *s, void *unused) 307 { 308 struct amd_pmc_dev *dev = s->private; 309 u64 entry_time, exit_time, residency; 310 311 /* Use FCH registers to get the S0ix stats */ 312 if (!dev->fch_virt_addr) { 313 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW; 314 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH; 315 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo); 316 317 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE); 318 if (!dev->fch_virt_addr) 319 return -ENOMEM; 320 } 321 322 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET); 323 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET); 324 325 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET); 326 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET); 327 328 /* It's in 48MHz. We need to convert it */ 329 residency = exit_time - entry_time; 330 do_div(residency, 48); 331 332 seq_puts(s, "=== S0ix statistics ===\n"); 333 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time); 334 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time); 335 seq_printf(s, "Residency Time: %lld\n", residency); 336 337 return 0; 338 } 339 DEFINE_SHOW_ATTRIBUTE(s0ix_stats); 340 341 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev, 342 struct seq_file *s) 343 { 344 u32 val; 345 int rc; 346 347 switch (pdev->cpu_id) { 348 case AMD_CPU_ID_CZN: 349 /* we haven't yet read SMU version */ 350 if (!pdev->major) { 351 rc = amd_pmc_get_smu_version(pdev); 352 if (rc) 353 return rc; 354 } 355 if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37)) 356 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN); 357 else 358 return -EINVAL; 359 break; 360 case AMD_CPU_ID_YC: 361 case AMD_CPU_ID_CB: 362 case AMD_CPU_ID_PS: 363 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC); 364 break; 365 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: 366 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: 367 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_1AH); 368 break; 369 default: 370 return -EINVAL; 371 } 372 373 if (dev) 374 pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val); 375 376 if (s) 377 seq_printf(s, "SMU idlemask : 0x%x\n", val); 378 379 return 0; 380 } 381 382 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused) 383 { 384 return amd_pmc_idlemask_read(s->private, NULL, s); 385 } 386 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask); 387 388 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev) 389 { 390 debugfs_remove_recursive(dev->dbgfs_dir); 391 } 392 393 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) 394 { 395 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL); 396 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev, 397 &smu_fw_info_fops); 398 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev, 399 &s0ix_stats_fops); 400 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev, 401 &amd_pmc_idlemask_fops); 402 } 403 404 static char *amd_pmc_get_msg_port(struct amd_pmc_dev *dev) 405 { 406 switch (dev->msg_port) { 407 case MSG_PORT_PMC: 408 return "PMC"; 409 case MSG_PORT_S2D: 410 return "S2D"; 411 default: 412 return "Invalid message port"; 413 } 414 } 415 416 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev) 417 { 418 u32 value, message, argument, response; 419 420 if (dev->msg_port == MSG_PORT_S2D) { 421 message = dev->stb_arg.msg; 422 argument = dev->stb_arg.arg; 423 response = dev->stb_arg.resp; 424 } else { 425 message = dev->smu_msg; 426 argument = AMD_PMC_REGISTER_ARGUMENT; 427 response = AMD_PMC_REGISTER_RESPONSE; 428 } 429 430 value = amd_pmc_reg_read(dev, response); 431 dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", amd_pmc_get_msg_port(dev), value); 432 433 value = amd_pmc_reg_read(dev, argument); 434 dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", amd_pmc_get_msg_port(dev), value); 435 436 value = amd_pmc_reg_read(dev, message); 437 dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", amd_pmc_get_msg_port(dev), value); 438 } 439 440 int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret) 441 { 442 int rc; 443 u32 val, message, argument, response; 444 445 guard(mutex)(&dev->lock); 446 447 if (dev->msg_port == MSG_PORT_S2D) { 448 message = dev->stb_arg.msg; 449 argument = dev->stb_arg.arg; 450 response = dev->stb_arg.resp; 451 } else { 452 message = dev->smu_msg; 453 argument = AMD_PMC_REGISTER_ARGUMENT; 454 response = AMD_PMC_REGISTER_RESPONSE; 455 } 456 457 /* Wait until we get a valid response */ 458 rc = readx_poll_timeout(ioread32, dev->regbase + response, 459 val, val != 0, PMC_MSG_DELAY_MIN_US, 460 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 461 if (rc) { 462 dev_err(dev->dev, "failed to talk to SMU\n"); 463 return rc; 464 } 465 466 /* Write zero to response register */ 467 amd_pmc_reg_write(dev, response, 0); 468 469 /* Write argument into response register */ 470 amd_pmc_reg_write(dev, argument, arg); 471 472 /* Write message ID to message ID register */ 473 amd_pmc_reg_write(dev, message, msg); 474 475 /* Wait until we get a valid response */ 476 rc = readx_poll_timeout(ioread32, dev->regbase + response, 477 val, val != 0, PMC_MSG_DELAY_MIN_US, 478 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 479 if (rc) { 480 dev_err(dev->dev, "SMU response timed out\n"); 481 return rc; 482 } 483 484 switch (val) { 485 case AMD_PMC_RESULT_OK: 486 if (ret) { 487 /* PMFW may take longer time to return back the data */ 488 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US); 489 *data = amd_pmc_reg_read(dev, argument); 490 } 491 break; 492 case AMD_PMC_RESULT_CMD_REJECT_BUSY: 493 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val); 494 rc = -EBUSY; 495 break; 496 case AMD_PMC_RESULT_CMD_UNKNOWN: 497 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val); 498 rc = -EINVAL; 499 break; 500 case AMD_PMC_RESULT_CMD_REJECT_PREREQ: 501 case AMD_PMC_RESULT_FAILED: 502 default: 503 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val); 504 rc = -EIO; 505 break; 506 } 507 508 amd_pmc_dump_registers(dev); 509 return rc; 510 } 511 512 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev) 513 { 514 switch (dev->cpu_id) { 515 case AMD_CPU_ID_PCO: 516 return MSG_OS_HINT_PCO; 517 case AMD_CPU_ID_RN: 518 case AMD_CPU_ID_YC: 519 case AMD_CPU_ID_CB: 520 case AMD_CPU_ID_PS: 521 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: 522 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: 523 return MSG_OS_HINT_RN; 524 } 525 return -EINVAL; 526 } 527 528 static int amd_pmc_wa_irq1(struct amd_pmc_dev *pdev) 529 { 530 struct device *d; 531 int rc; 532 533 /* cezanne platform firmware has a fix in 64.66.0 */ 534 if (pdev->cpu_id == AMD_CPU_ID_CZN) { 535 if (!pdev->major) { 536 rc = amd_pmc_get_smu_version(pdev); 537 if (rc) 538 return rc; 539 } 540 541 if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65)) 542 return 0; 543 } 544 545 d = bus_find_device_by_name(&serio_bus, NULL, "serio0"); 546 if (!d) 547 return 0; 548 if (device_may_wakeup(d)) { 549 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n"); 550 disable_irq_wake(1); 551 device_set_wakeup_enable(d, false); 552 } 553 put_device(d); 554 555 return 0; 556 } 557 558 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg) 559 { 560 struct rtc_device *rtc_device; 561 time64_t then, now, duration; 562 struct rtc_wkalrm alarm; 563 struct rtc_time tm; 564 int rc; 565 566 /* we haven't yet read SMU version */ 567 if (!pdev->major) { 568 rc = amd_pmc_get_smu_version(pdev); 569 if (rc) 570 return rc; 571 } 572 573 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53)) 574 return 0; 575 576 rtc_device = rtc_class_open("rtc0"); 577 if (!rtc_device) 578 return 0; 579 rc = rtc_read_alarm(rtc_device, &alarm); 580 if (rc) 581 return rc; 582 if (!alarm.enabled) { 583 dev_dbg(pdev->dev, "alarm not enabled\n"); 584 return 0; 585 } 586 rc = rtc_read_time(rtc_device, &tm); 587 if (rc) 588 return rc; 589 then = rtc_tm_to_time64(&alarm.time); 590 now = rtc_tm_to_time64(&tm); 591 duration = then-now; 592 593 /* in the past */ 594 if (then < now) 595 return 0; 596 597 /* will be stored in upper 16 bits of s0i3 hint argument, 598 * so timer wakeup from s0i3 is limited to ~18 hours or less 599 */ 600 if (duration <= 4 || duration > U16_MAX) 601 return -EINVAL; 602 603 *arg |= (duration << 16); 604 rc = rtc_alarm_irq_enable(rtc_device, 0); 605 pm_pr_dbg("wakeup timer programmed for %lld seconds\n", duration); 606 607 return rc; 608 } 609 610 static void amd_pmc_s2idle_prepare(void) 611 { 612 struct amd_pmc_dev *pdev = &pmc; 613 int rc; 614 u8 msg; 615 u32 arg = 1; 616 617 /* Reset and Start SMU logging - to monitor the s0i3 stats */ 618 amd_pmc_setup_smu_logging(pdev); 619 620 /* Activate CZN specific platform bug workarounds */ 621 if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) { 622 rc = amd_pmc_verify_czn_rtc(pdev, &arg); 623 if (rc) { 624 dev_err(pdev->dev, "failed to set RTC: %d\n", rc); 625 return; 626 } 627 } 628 629 msg = amd_pmc_get_os_hint(pdev); 630 rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, false); 631 if (rc) { 632 dev_err(pdev->dev, "suspend failed: %d\n", rc); 633 return; 634 } 635 636 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_PREPARE); 637 if (rc) 638 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 639 } 640 641 static void amd_pmc_s2idle_check(void) 642 { 643 struct amd_pmc_dev *pdev = &pmc; 644 struct smu_metrics table; 645 int rc; 646 647 /* CZN: Ensure that future s0i3 entry attempts at least 10ms passed */ 648 if (pdev->cpu_id == AMD_CPU_ID_CZN && !get_metrics_table(pdev, &table) && 649 table.s0i3_last_entry_status) 650 usleep_range(10000, 20000); 651 652 /* Dump the IdleMask before we add to the STB */ 653 amd_pmc_idlemask_read(pdev, pdev->dev, NULL); 654 655 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_CHECK); 656 if (rc) 657 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 658 } 659 660 static int amd_pmc_dump_data(struct amd_pmc_dev *pdev) 661 { 662 if (pdev->cpu_id == AMD_CPU_ID_PCO) 663 return -ENODEV; 664 665 return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, false); 666 } 667 668 static void amd_pmc_s2idle_restore(void) 669 { 670 struct amd_pmc_dev *pdev = &pmc; 671 int rc; 672 u8 msg; 673 674 msg = amd_pmc_get_os_hint(pdev); 675 rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, false); 676 if (rc) 677 dev_err(pdev->dev, "resume failed: %d\n", rc); 678 679 /* Let SMU know that we are looking for stats */ 680 amd_pmc_dump_data(pdev); 681 682 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_RESTORE); 683 if (rc) 684 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 685 686 /* Notify on failed entry */ 687 amd_pmc_validate_deepest(pdev); 688 689 amd_pmc_process_restore_quirks(pdev); 690 } 691 692 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = { 693 .prepare = amd_pmc_s2idle_prepare, 694 .check = amd_pmc_s2idle_check, 695 .restore = amd_pmc_s2idle_restore, 696 }; 697 698 static int amd_pmc_suspend_handler(struct device *dev) 699 { 700 struct amd_pmc_dev *pdev = dev_get_drvdata(dev); 701 int rc; 702 703 /* 704 * Must be called only from the same set of dev_pm_ops handlers 705 * as i8042_pm_suspend() is called: currently just from .suspend. 706 */ 707 if (pdev->disable_8042_wakeup && !disable_workarounds) { 708 rc = amd_pmc_wa_irq1(pdev); 709 if (rc) { 710 dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc); 711 return rc; 712 } 713 } 714 715 return 0; 716 } 717 718 static const struct dev_pm_ops amd_pmc_pm = { 719 .suspend = amd_pmc_suspend_handler, 720 }; 721 722 static const struct pci_device_id pmc_pci_ids[] = { 723 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) }, 724 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) }, 725 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) }, 726 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) }, 727 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) }, 728 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) }, 729 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) }, 730 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) }, 731 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) }, 732 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) }, 733 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) }, 734 { } 735 }; 736 737 static int amd_pmc_probe(struct platform_device *pdev) 738 { 739 struct amd_pmc_dev *dev = &pmc; 740 struct pci_dev *rdev; 741 u32 base_addr_lo, base_addr_hi; 742 u64 base_addr; 743 int err; 744 u32 val; 745 746 dev->dev = &pdev->dev; 747 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); 748 if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) { 749 err = -ENODEV; 750 goto err_pci_dev_put; 751 } 752 753 dev->cpu_id = rdev->device; 754 if (dev->cpu_id == AMD_CPU_ID_SP || dev->cpu_id == AMD_CPU_ID_SHP) { 755 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n"); 756 err = -ENODEV; 757 goto err_pci_dev_put; 758 } 759 760 dev->rdev = rdev; 761 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val); 762 if (err) { 763 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO); 764 err = pcibios_err_to_errno(err); 765 goto err_pci_dev_put; 766 } 767 768 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK; 769 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val); 770 if (err) { 771 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI); 772 err = pcibios_err_to_errno(err); 773 goto err_pci_dev_put; 774 } 775 776 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK; 777 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo); 778 779 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET, 780 AMD_PMC_MAPPING_SIZE); 781 if (!dev->regbase) { 782 err = -ENOMEM; 783 goto err_pci_dev_put; 784 } 785 786 err = devm_mutex_init(dev->dev, &dev->lock); 787 if (err) 788 goto err_pci_dev_put; 789 790 /* Get num of IP blocks within the SoC */ 791 amd_pmc_get_ip_info(dev); 792 793 platform_set_drvdata(pdev, dev); 794 if (IS_ENABLED(CONFIG_SUSPEND)) { 795 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops); 796 if (err) 797 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n"); 798 if (!disable_workarounds) 799 amd_pmc_quirks_init(dev); 800 } 801 802 amd_pmc_dbgfs_register(dev); 803 err = amd_stb_s2d_init(dev); 804 if (err) 805 goto err_pci_dev_put; 806 807 if (IS_ENABLED(CONFIG_AMD_MP2_STB)) 808 amd_mp2_stb_init(dev); 809 pm_report_max_hw_sleep(U64_MAX); 810 return 0; 811 812 err_pci_dev_put: 813 pci_dev_put(rdev); 814 return err; 815 } 816 817 static void amd_pmc_remove(struct platform_device *pdev) 818 { 819 struct amd_pmc_dev *dev = platform_get_drvdata(pdev); 820 821 if (IS_ENABLED(CONFIG_SUSPEND)) 822 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops); 823 amd_pmc_dbgfs_unregister(dev); 824 pci_dev_put(dev->rdev); 825 if (IS_ENABLED(CONFIG_AMD_MP2_STB)) 826 amd_mp2_stb_deinit(dev); 827 } 828 829 static const struct acpi_device_id amd_pmc_acpi_ids[] = { 830 {"AMDI0005", 0}, 831 {"AMDI0006", 0}, 832 {"AMDI0007", 0}, 833 {"AMDI0008", 0}, 834 {"AMDI0009", 0}, 835 {"AMDI000A", 0}, 836 {"AMDI000B", 0}, 837 {"AMD0004", 0}, 838 {"AMD0005", 0}, 839 { } 840 }; 841 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids); 842 843 static struct platform_driver amd_pmc_driver = { 844 .driver = { 845 .name = "amd_pmc", 846 .acpi_match_table = amd_pmc_acpi_ids, 847 .dev_groups = pmc_groups, 848 .pm = pm_sleep_ptr(&amd_pmc_pm), 849 }, 850 .probe = amd_pmc_probe, 851 .remove = amd_pmc_remove, 852 }; 853 module_platform_driver(amd_pmc_driver); 854 855 MODULE_LICENSE("GPL v2"); 856 MODULE_DESCRIPTION("AMD PMC Driver"); 857