1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * AMD SoC Power Management Controller Driver 4 * 5 * Copyright (c) 2020, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <asm/amd_nb.h> 14 #include <linux/acpi.h> 15 #include <linux/bitfield.h> 16 #include <linux/bits.h> 17 #include <linux/debugfs.h> 18 #include <linux/delay.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/limits.h> 22 #include <linux/module.h> 23 #include <linux/pci.h> 24 #include <linux/platform_device.h> 25 #include <linux/rtc.h> 26 #include <linux/serio.h> 27 #include <linux/suspend.h> 28 #include <linux/seq_file.h> 29 #include <linux/uaccess.h> 30 31 #include "pmc.h" 32 33 /* SMU communication registers */ 34 #define AMD_PMC_REGISTER_MESSAGE 0x538 35 #define AMD_PMC_REGISTER_RESPONSE 0x980 36 #define AMD_PMC_REGISTER_ARGUMENT 0x9BC 37 38 /* PMC Scratch Registers */ 39 #define AMD_PMC_SCRATCH_REG_CZN 0x94 40 #define AMD_PMC_SCRATCH_REG_YC 0xD14 41 42 /* STB Registers */ 43 #define AMD_PMC_STB_PMI_0 0x03E30600 44 #define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001 45 #define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002 46 #define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003 47 #define AMD_PMC_STB_DUMMY_PC 0xC6000007 48 49 /* STB S2D(Spill to DRAM) has different message port offset */ 50 #define AMD_S2D_REGISTER_MESSAGE 0xA20 51 #define AMD_S2D_REGISTER_RESPONSE 0xA80 52 #define AMD_S2D_REGISTER_ARGUMENT 0xA88 53 54 /* STB Spill to DRAM Parameters */ 55 #define S2D_TELEMETRY_BYTES_MAX 0x100000U 56 #define S2D_RSVD_RAM_SPACE 0x100000 57 #define S2D_TELEMETRY_DRAMBYTES_MAX 0x1000000 58 59 /* STB Spill to DRAM Message Definition */ 60 #define STB_FORCE_FLUSH_DATA 0xCF 61 62 /* Base address of SMU for mapping physical address to virtual address */ 63 #define AMD_PMC_MAPPING_SIZE 0x01000 64 #define AMD_PMC_BASE_ADDR_OFFSET 0x10000 65 #define AMD_PMC_BASE_ADDR_LO 0x13B102E8 66 #define AMD_PMC_BASE_ADDR_HI 0x13B102EC 67 #define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0) 68 #define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20) 69 70 /* SMU Response Codes */ 71 #define AMD_PMC_RESULT_OK 0x01 72 #define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC 73 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD 74 #define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE 75 #define AMD_PMC_RESULT_FAILED 0xFF 76 77 /* FCH SSC Registers */ 78 #define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30 79 #define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34 80 #define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38 81 #define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C 82 #define FCH_SSC_MAPPING_SIZE 0x800 83 #define FCH_BASE_PHY_ADDR_LOW 0xFED81100 84 #define FCH_BASE_PHY_ADDR_HIGH 0x00000000 85 86 /* SMU Message Definations */ 87 #define SMU_MSG_GETSMUVERSION 0x02 88 #define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04 89 #define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05 90 #define SMU_MSG_LOG_START 0x06 91 #define SMU_MSG_LOG_RESET 0x07 92 #define SMU_MSG_LOG_DUMP_DATA 0x08 93 #define SMU_MSG_GET_SUP_CONSTRAINTS 0x09 94 95 #define PMC_MSG_DELAY_MIN_US 50 96 #define RESPONSE_REGISTER_LOOP_MAX 20000 97 98 #define DELAY_MIN_US 2000 99 #define DELAY_MAX_US 3000 100 #define FIFO_SIZE 4096 101 102 enum amd_pmc_def { 103 MSG_TEST = 0x01, 104 MSG_OS_HINT_PCO, 105 MSG_OS_HINT_RN, 106 }; 107 108 enum s2d_arg { 109 S2D_TELEMETRY_SIZE = 0x01, 110 S2D_PHYS_ADDR_LOW, 111 S2D_PHYS_ADDR_HIGH, 112 S2D_NUM_SAMPLES, 113 S2D_DRAM_SIZE, 114 }; 115 116 struct amd_pmc_stb_v2_data { 117 size_t size; 118 u8 data[] __counted_by(size); 119 }; 120 121 struct amd_pmc_bit_map { 122 const char *name; 123 u32 bit_mask; 124 }; 125 126 static const struct amd_pmc_bit_map soc15_ip_blk[] = { 127 {"DISPLAY", BIT(0)}, 128 {"CPU", BIT(1)}, 129 {"GFX", BIT(2)}, 130 {"VDD", BIT(3)}, 131 {"ACP", BIT(4)}, 132 {"VCN", BIT(5)}, 133 {"ISP", BIT(6)}, 134 {"NBIO", BIT(7)}, 135 {"DF", BIT(8)}, 136 {"USB3_0", BIT(9)}, 137 {"USB3_1", BIT(10)}, 138 {"LAPIC", BIT(11)}, 139 {"USB3_2", BIT(12)}, 140 {"USB3_3", BIT(13)}, 141 {"USB3_4", BIT(14)}, 142 {"USB4_0", BIT(15)}, 143 {"USB4_1", BIT(16)}, 144 {"MPM", BIT(17)}, 145 {"JPEG", BIT(18)}, 146 {"IPU", BIT(19)}, 147 {"UMSCH", BIT(20)}, 148 {} 149 }; 150 151 static bool enable_stb; 152 module_param(enable_stb, bool, 0644); 153 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism"); 154 155 static bool disable_workarounds; 156 module_param(disable_workarounds, bool, 0644); 157 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs"); 158 159 static bool dump_custom_stb; 160 module_param(dump_custom_stb, bool, 0644); 161 MODULE_PARM_DESC(dump_custom_stb, "Enable to dump full STB buffer"); 162 163 static struct amd_pmc_dev pmc; 164 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret); 165 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf); 166 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data); 167 168 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset) 169 { 170 return ioread32(dev->regbase + reg_offset); 171 } 172 173 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val) 174 { 175 iowrite32(val, dev->regbase + reg_offset); 176 } 177 178 struct smu_metrics { 179 u32 table_version; 180 u32 hint_count; 181 u32 s0i3_last_entry_status; 182 u32 timein_s0i2; 183 u64 timeentering_s0i3_lastcapture; 184 u64 timeentering_s0i3_totaltime; 185 u64 timeto_resume_to_os_lastcapture; 186 u64 timeto_resume_to_os_totaltime; 187 u64 timein_s0i3_lastcapture; 188 u64 timein_s0i3_totaltime; 189 u64 timein_swdrips_lastcapture; 190 u64 timein_swdrips_totaltime; 191 u64 timecondition_notmet_lastcapture[32]; 192 u64 timecondition_notmet_totaltime[32]; 193 } __packed; 194 195 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp) 196 { 197 struct amd_pmc_dev *dev = filp->f_inode->i_private; 198 u32 size = FIFO_SIZE * sizeof(u32); 199 u32 *buf; 200 int rc; 201 202 buf = kzalloc(size, GFP_KERNEL); 203 if (!buf) 204 return -ENOMEM; 205 206 rc = amd_pmc_read_stb(dev, buf); 207 if (rc) { 208 kfree(buf); 209 return rc; 210 } 211 212 filp->private_data = buf; 213 return rc; 214 } 215 216 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 217 loff_t *pos) 218 { 219 if (!filp->private_data) 220 return -EINVAL; 221 222 return simple_read_from_buffer(buf, size, pos, filp->private_data, 223 FIFO_SIZE * sizeof(u32)); 224 } 225 226 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp) 227 { 228 kfree(filp->private_data); 229 return 0; 230 } 231 232 static const struct file_operations amd_pmc_stb_debugfs_fops = { 233 .owner = THIS_MODULE, 234 .open = amd_pmc_stb_debugfs_open, 235 .read = amd_pmc_stb_debugfs_read, 236 .release = amd_pmc_stb_debugfs_release, 237 }; 238 239 /* Enhanced STB Firmware Reporting Mechanism */ 240 static int amd_pmc_stb_handle_efr(struct file *filp) 241 { 242 struct amd_pmc_dev *dev = filp->f_inode->i_private; 243 struct amd_pmc_stb_v2_data *stb_data_arr; 244 u32 fsize; 245 246 fsize = dev->dram_size - S2D_RSVD_RAM_SPACE; 247 stb_data_arr = kmalloc(struct_size(stb_data_arr, data, fsize), GFP_KERNEL); 248 if (!stb_data_arr) 249 return -ENOMEM; 250 251 stb_data_arr->size = fsize; 252 memcpy_fromio(stb_data_arr->data, dev->stb_virt_addr, fsize); 253 filp->private_data = stb_data_arr; 254 255 return 0; 256 } 257 258 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp) 259 { 260 struct amd_pmc_dev *dev = filp->f_inode->i_private; 261 u32 fsize, num_samples, val, stb_rdptr_offset = 0; 262 struct amd_pmc_stb_v2_data *stb_data_arr; 263 int ret; 264 265 /* Write dummy postcode while reading the STB buffer */ 266 ret = amd_pmc_write_stb(dev, AMD_PMC_STB_DUMMY_PC); 267 if (ret) 268 dev_err(dev->dev, "error writing to STB: %d\n", ret); 269 270 /* Spill to DRAM num_samples uses separate SMU message port */ 271 dev->msg_port = 1; 272 273 ret = amd_pmc_send_cmd(dev, 0, &val, STB_FORCE_FLUSH_DATA, 1); 274 if (ret) 275 dev_dbg_once(dev->dev, "S2D force flush not supported: %d\n", ret); 276 277 /* 278 * We have a custom stb size and the PMFW is supposed to give 279 * the enhanced dram size. Note that we land here only for the 280 * platforms that support enhanced dram size reporting. 281 */ 282 if (dump_custom_stb) 283 return amd_pmc_stb_handle_efr(filp); 284 285 /* Get the num_samples to calculate the last push location */ 286 ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, dev->s2d_msg_id, true); 287 /* Clear msg_port for other SMU operation */ 288 dev->msg_port = 0; 289 if (ret) { 290 dev_err(dev->dev, "error: S2D_NUM_SAMPLES not supported : %d\n", ret); 291 return ret; 292 } 293 294 fsize = min(num_samples, S2D_TELEMETRY_BYTES_MAX); 295 stb_data_arr = kmalloc(struct_size(stb_data_arr, data, fsize), GFP_KERNEL); 296 if (!stb_data_arr) 297 return -ENOMEM; 298 299 stb_data_arr->size = fsize; 300 301 /* 302 * Start capturing data from the last push location. 303 * This is for general cases, where the stb limits 304 * are meant for standard usage. 305 */ 306 if (num_samples > S2D_TELEMETRY_BYTES_MAX) { 307 /* First read oldest data starting 1 behind last write till end of ringbuffer */ 308 stb_rdptr_offset = num_samples % S2D_TELEMETRY_BYTES_MAX; 309 fsize = S2D_TELEMETRY_BYTES_MAX - stb_rdptr_offset; 310 311 memcpy_fromio(stb_data_arr->data, dev->stb_virt_addr + stb_rdptr_offset, fsize); 312 /* Second copy the newer samples from offset 0 - last write */ 313 memcpy_fromio(stb_data_arr->data + fsize, dev->stb_virt_addr, stb_rdptr_offset); 314 } else { 315 memcpy_fromio(stb_data_arr->data, dev->stb_virt_addr, fsize); 316 } 317 318 filp->private_data = stb_data_arr; 319 320 return 0; 321 } 322 323 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size, 324 loff_t *pos) 325 { 326 struct amd_pmc_stb_v2_data *data = filp->private_data; 327 328 return simple_read_from_buffer(buf, size, pos, data->data, data->size); 329 } 330 331 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp) 332 { 333 kfree(filp->private_data); 334 return 0; 335 } 336 337 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = { 338 .owner = THIS_MODULE, 339 .open = amd_pmc_stb_debugfs_open_v2, 340 .read = amd_pmc_stb_debugfs_read_v2, 341 .release = amd_pmc_stb_debugfs_release_v2, 342 }; 343 344 static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev) 345 { 346 switch (dev->cpu_id) { 347 case AMD_CPU_ID_PCO: 348 case AMD_CPU_ID_RN: 349 case AMD_CPU_ID_YC: 350 case AMD_CPU_ID_CB: 351 dev->num_ips = 12; 352 dev->s2d_msg_id = 0xBE; 353 break; 354 case AMD_CPU_ID_PS: 355 dev->num_ips = 21; 356 dev->s2d_msg_id = 0x85; 357 break; 358 } 359 } 360 361 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev) 362 { 363 if (dev->cpu_id == AMD_CPU_ID_PCO) { 364 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n"); 365 return -EINVAL; 366 } 367 368 /* Get Active devices list from SMU */ 369 if (!dev->active_ips) 370 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, true); 371 372 /* Get dram address */ 373 if (!dev->smu_virt_addr) { 374 u32 phys_addr_low, phys_addr_hi; 375 u64 smu_phys_addr; 376 377 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, true); 378 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, true); 379 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low); 380 381 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, 382 sizeof(struct smu_metrics)); 383 if (!dev->smu_virt_addr) 384 return -ENOMEM; 385 } 386 387 /* Start the logging */ 388 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, false); 389 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, false); 390 391 return 0; 392 } 393 394 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table) 395 { 396 if (!pdev->smu_virt_addr) { 397 int ret = amd_pmc_setup_smu_logging(pdev); 398 399 if (ret) 400 return ret; 401 } 402 403 if (pdev->cpu_id == AMD_CPU_ID_PCO) 404 return -ENODEV; 405 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics)); 406 return 0; 407 } 408 409 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev) 410 { 411 struct smu_metrics table; 412 413 if (get_metrics_table(pdev, &table)) 414 return; 415 416 if (!table.s0i3_last_entry_status) 417 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n"); 418 pm_report_hw_sleep_time(table.s0i3_last_entry_status ? 419 table.timein_s0i3_lastcapture : 0); 420 } 421 422 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev) 423 { 424 int rc; 425 u32 val; 426 427 if (dev->cpu_id == AMD_CPU_ID_PCO) 428 return -ENODEV; 429 430 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, true); 431 if (rc) 432 return rc; 433 434 dev->smu_program = (val >> 24) & GENMASK(7, 0); 435 dev->major = (val >> 16) & GENMASK(7, 0); 436 dev->minor = (val >> 8) & GENMASK(7, 0); 437 dev->rev = (val >> 0) & GENMASK(7, 0); 438 439 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n", 440 dev->smu_program, dev->major, dev->minor, dev->rev); 441 442 return 0; 443 } 444 445 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr, 446 char *buf) 447 { 448 struct amd_pmc_dev *dev = dev_get_drvdata(d); 449 450 if (!dev->major) { 451 int rc = amd_pmc_get_smu_version(dev); 452 453 if (rc) 454 return rc; 455 } 456 return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev); 457 } 458 459 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr, 460 char *buf) 461 { 462 struct amd_pmc_dev *dev = dev_get_drvdata(d); 463 464 if (!dev->major) { 465 int rc = amd_pmc_get_smu_version(dev); 466 467 if (rc) 468 return rc; 469 } 470 return sysfs_emit(buf, "%u\n", dev->smu_program); 471 } 472 473 static DEVICE_ATTR_RO(smu_fw_version); 474 static DEVICE_ATTR_RO(smu_program); 475 476 static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 477 { 478 struct device *dev = kobj_to_dev(kobj); 479 struct amd_pmc_dev *pdev = dev_get_drvdata(dev); 480 481 if (pdev->cpu_id == AMD_CPU_ID_PCO) 482 return 0; 483 return 0444; 484 } 485 486 static struct attribute *pmc_attrs[] = { 487 &dev_attr_smu_fw_version.attr, 488 &dev_attr_smu_program.attr, 489 NULL, 490 }; 491 492 static struct attribute_group pmc_attr_group = { 493 .attrs = pmc_attrs, 494 .is_visible = pmc_attr_is_visible, 495 }; 496 497 static const struct attribute_group *pmc_groups[] = { 498 &pmc_attr_group, 499 NULL, 500 }; 501 502 static int smu_fw_info_show(struct seq_file *s, void *unused) 503 { 504 struct amd_pmc_dev *dev = s->private; 505 struct smu_metrics table; 506 int idx; 507 508 if (get_metrics_table(dev, &table)) 509 return -EINVAL; 510 511 seq_puts(s, "\n=== SMU Statistics ===\n"); 512 seq_printf(s, "Table Version: %d\n", table.table_version); 513 seq_printf(s, "Hint Count: %d\n", table.hint_count); 514 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" : 515 "Unknown/Fail"); 516 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture); 517 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture); 518 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n", 519 table.timeto_resume_to_os_lastcapture); 520 521 seq_puts(s, "\n=== Active time (in us) ===\n"); 522 for (idx = 0 ; idx < dev->num_ips ; idx++) { 523 if (soc15_ip_blk[idx].bit_mask & dev->active_ips) 524 seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name, 525 table.timecondition_notmet_lastcapture[idx]); 526 } 527 528 return 0; 529 } 530 DEFINE_SHOW_ATTRIBUTE(smu_fw_info); 531 532 static int s0ix_stats_show(struct seq_file *s, void *unused) 533 { 534 struct amd_pmc_dev *dev = s->private; 535 u64 entry_time, exit_time, residency; 536 537 /* Use FCH registers to get the S0ix stats */ 538 if (!dev->fch_virt_addr) { 539 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW; 540 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH; 541 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo); 542 543 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE); 544 if (!dev->fch_virt_addr) 545 return -ENOMEM; 546 } 547 548 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET); 549 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET); 550 551 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET); 552 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET); 553 554 /* It's in 48MHz. We need to convert it */ 555 residency = exit_time - entry_time; 556 do_div(residency, 48); 557 558 seq_puts(s, "=== S0ix statistics ===\n"); 559 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time); 560 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time); 561 seq_printf(s, "Residency Time: %lld\n", residency); 562 563 return 0; 564 } 565 DEFINE_SHOW_ATTRIBUTE(s0ix_stats); 566 567 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev, 568 struct seq_file *s) 569 { 570 u32 val; 571 int rc; 572 573 switch (pdev->cpu_id) { 574 case AMD_CPU_ID_CZN: 575 /* we haven't yet read SMU version */ 576 if (!pdev->major) { 577 rc = amd_pmc_get_smu_version(pdev); 578 if (rc) 579 return rc; 580 } 581 if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37)) 582 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN); 583 else 584 return -EINVAL; 585 break; 586 case AMD_CPU_ID_YC: 587 case AMD_CPU_ID_CB: 588 case AMD_CPU_ID_PS: 589 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC); 590 break; 591 default: 592 return -EINVAL; 593 } 594 595 if (dev) 596 pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val); 597 598 if (s) 599 seq_printf(s, "SMU idlemask : 0x%x\n", val); 600 601 return 0; 602 } 603 604 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused) 605 { 606 return amd_pmc_idlemask_read(s->private, NULL, s); 607 } 608 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask); 609 610 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev) 611 { 612 debugfs_remove_recursive(dev->dbgfs_dir); 613 } 614 615 static bool amd_pmc_is_stb_supported(struct amd_pmc_dev *dev) 616 { 617 switch (dev->cpu_id) { 618 case AMD_CPU_ID_YC: 619 case AMD_CPU_ID_CB: 620 case AMD_CPU_ID_PS: 621 return true; 622 default: 623 return false; 624 } 625 } 626 627 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) 628 { 629 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL); 630 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev, 631 &smu_fw_info_fops); 632 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev, 633 &s0ix_stats_fops); 634 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev, 635 &amd_pmc_idlemask_fops); 636 /* Enable STB only when the module_param is set */ 637 if (enable_stb) { 638 if (amd_pmc_is_stb_supported(dev)) 639 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev, 640 &amd_pmc_stb_debugfs_fops_v2); 641 else 642 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev, 643 &amd_pmc_stb_debugfs_fops); 644 } 645 } 646 647 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev) 648 { 649 u32 value, message, argument, response; 650 651 if (dev->msg_port) { 652 message = AMD_S2D_REGISTER_MESSAGE; 653 argument = AMD_S2D_REGISTER_ARGUMENT; 654 response = AMD_S2D_REGISTER_RESPONSE; 655 } else { 656 message = AMD_PMC_REGISTER_MESSAGE; 657 argument = AMD_PMC_REGISTER_ARGUMENT; 658 response = AMD_PMC_REGISTER_RESPONSE; 659 } 660 661 value = amd_pmc_reg_read(dev, response); 662 dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", dev->msg_port ? "S2D" : "PMC", value); 663 664 value = amd_pmc_reg_read(dev, argument); 665 dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", dev->msg_port ? "S2D" : "PMC", value); 666 667 value = amd_pmc_reg_read(dev, message); 668 dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", dev->msg_port ? "S2D" : "PMC", value); 669 } 670 671 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret) 672 { 673 int rc; 674 u32 val, message, argument, response; 675 676 mutex_lock(&dev->lock); 677 678 if (dev->msg_port) { 679 message = AMD_S2D_REGISTER_MESSAGE; 680 argument = AMD_S2D_REGISTER_ARGUMENT; 681 response = AMD_S2D_REGISTER_RESPONSE; 682 } else { 683 message = AMD_PMC_REGISTER_MESSAGE; 684 argument = AMD_PMC_REGISTER_ARGUMENT; 685 response = AMD_PMC_REGISTER_RESPONSE; 686 } 687 688 /* Wait until we get a valid response */ 689 rc = readx_poll_timeout(ioread32, dev->regbase + response, 690 val, val != 0, PMC_MSG_DELAY_MIN_US, 691 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 692 if (rc) { 693 dev_err(dev->dev, "failed to talk to SMU\n"); 694 goto out_unlock; 695 } 696 697 /* Write zero to response register */ 698 amd_pmc_reg_write(dev, response, 0); 699 700 /* Write argument into response register */ 701 amd_pmc_reg_write(dev, argument, arg); 702 703 /* Write message ID to message ID register */ 704 amd_pmc_reg_write(dev, message, msg); 705 706 /* Wait until we get a valid response */ 707 rc = readx_poll_timeout(ioread32, dev->regbase + response, 708 val, val != 0, PMC_MSG_DELAY_MIN_US, 709 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 710 if (rc) { 711 dev_err(dev->dev, "SMU response timed out\n"); 712 goto out_unlock; 713 } 714 715 switch (val) { 716 case AMD_PMC_RESULT_OK: 717 if (ret) { 718 /* PMFW may take longer time to return back the data */ 719 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US); 720 *data = amd_pmc_reg_read(dev, argument); 721 } 722 break; 723 case AMD_PMC_RESULT_CMD_REJECT_BUSY: 724 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val); 725 rc = -EBUSY; 726 goto out_unlock; 727 case AMD_PMC_RESULT_CMD_UNKNOWN: 728 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val); 729 rc = -EINVAL; 730 goto out_unlock; 731 case AMD_PMC_RESULT_CMD_REJECT_PREREQ: 732 case AMD_PMC_RESULT_FAILED: 733 default: 734 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val); 735 rc = -EIO; 736 goto out_unlock; 737 } 738 739 out_unlock: 740 mutex_unlock(&dev->lock); 741 amd_pmc_dump_registers(dev); 742 return rc; 743 } 744 745 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev) 746 { 747 switch (dev->cpu_id) { 748 case AMD_CPU_ID_PCO: 749 return MSG_OS_HINT_PCO; 750 case AMD_CPU_ID_RN: 751 case AMD_CPU_ID_YC: 752 case AMD_CPU_ID_CB: 753 case AMD_CPU_ID_PS: 754 return MSG_OS_HINT_RN; 755 } 756 return -EINVAL; 757 } 758 759 static int amd_pmc_wa_irq1(struct amd_pmc_dev *pdev) 760 { 761 struct device *d; 762 int rc; 763 764 /* cezanne platform firmware has a fix in 64.66.0 */ 765 if (pdev->cpu_id == AMD_CPU_ID_CZN) { 766 if (!pdev->major) { 767 rc = amd_pmc_get_smu_version(pdev); 768 if (rc) 769 return rc; 770 } 771 772 if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65)) 773 return 0; 774 } 775 776 d = bus_find_device_by_name(&serio_bus, NULL, "serio0"); 777 if (!d) 778 return 0; 779 if (device_may_wakeup(d)) { 780 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n"); 781 disable_irq_wake(1); 782 device_set_wakeup_enable(d, false); 783 } 784 put_device(d); 785 786 return 0; 787 } 788 789 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg) 790 { 791 struct rtc_device *rtc_device; 792 time64_t then, now, duration; 793 struct rtc_wkalrm alarm; 794 struct rtc_time tm; 795 int rc; 796 797 /* we haven't yet read SMU version */ 798 if (!pdev->major) { 799 rc = amd_pmc_get_smu_version(pdev); 800 if (rc) 801 return rc; 802 } 803 804 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53)) 805 return 0; 806 807 rtc_device = rtc_class_open("rtc0"); 808 if (!rtc_device) 809 return 0; 810 rc = rtc_read_alarm(rtc_device, &alarm); 811 if (rc) 812 return rc; 813 if (!alarm.enabled) { 814 dev_dbg(pdev->dev, "alarm not enabled\n"); 815 return 0; 816 } 817 rc = rtc_read_time(rtc_device, &tm); 818 if (rc) 819 return rc; 820 then = rtc_tm_to_time64(&alarm.time); 821 now = rtc_tm_to_time64(&tm); 822 duration = then-now; 823 824 /* in the past */ 825 if (then < now) 826 return 0; 827 828 /* will be stored in upper 16 bits of s0i3 hint argument, 829 * so timer wakeup from s0i3 is limited to ~18 hours or less 830 */ 831 if (duration <= 4 || duration > U16_MAX) 832 return -EINVAL; 833 834 *arg |= (duration << 16); 835 rc = rtc_alarm_irq_enable(rtc_device, 0); 836 pm_pr_dbg("wakeup timer programmed for %lld seconds\n", duration); 837 838 return rc; 839 } 840 841 static void amd_pmc_s2idle_prepare(void) 842 { 843 struct amd_pmc_dev *pdev = &pmc; 844 int rc; 845 u8 msg; 846 u32 arg = 1; 847 848 /* Reset and Start SMU logging - to monitor the s0i3 stats */ 849 amd_pmc_setup_smu_logging(pdev); 850 851 /* Activate CZN specific platform bug workarounds */ 852 if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) { 853 rc = amd_pmc_verify_czn_rtc(pdev, &arg); 854 if (rc) { 855 dev_err(pdev->dev, "failed to set RTC: %d\n", rc); 856 return; 857 } 858 } 859 860 msg = amd_pmc_get_os_hint(pdev); 861 rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, false); 862 if (rc) { 863 dev_err(pdev->dev, "suspend failed: %d\n", rc); 864 return; 865 } 866 867 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_PREPARE); 868 if (rc) 869 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 870 } 871 872 static void amd_pmc_s2idle_check(void) 873 { 874 struct amd_pmc_dev *pdev = &pmc; 875 struct smu_metrics table; 876 int rc; 877 878 /* CZN: Ensure that future s0i3 entry attempts at least 10ms passed */ 879 if (pdev->cpu_id == AMD_CPU_ID_CZN && !get_metrics_table(pdev, &table) && 880 table.s0i3_last_entry_status) 881 usleep_range(10000, 20000); 882 883 /* Dump the IdleMask before we add to the STB */ 884 amd_pmc_idlemask_read(pdev, pdev->dev, NULL); 885 886 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_CHECK); 887 if (rc) 888 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 889 } 890 891 static int amd_pmc_dump_data(struct amd_pmc_dev *pdev) 892 { 893 if (pdev->cpu_id == AMD_CPU_ID_PCO) 894 return -ENODEV; 895 896 return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, false); 897 } 898 899 static void amd_pmc_s2idle_restore(void) 900 { 901 struct amd_pmc_dev *pdev = &pmc; 902 int rc; 903 u8 msg; 904 905 msg = amd_pmc_get_os_hint(pdev); 906 rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, false); 907 if (rc) 908 dev_err(pdev->dev, "resume failed: %d\n", rc); 909 910 /* Let SMU know that we are looking for stats */ 911 amd_pmc_dump_data(pdev); 912 913 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_RESTORE); 914 if (rc) 915 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 916 917 /* Notify on failed entry */ 918 amd_pmc_validate_deepest(pdev); 919 920 amd_pmc_process_restore_quirks(pdev); 921 } 922 923 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = { 924 .prepare = amd_pmc_s2idle_prepare, 925 .check = amd_pmc_s2idle_check, 926 .restore = amd_pmc_s2idle_restore, 927 }; 928 929 static int amd_pmc_suspend_handler(struct device *dev) 930 { 931 struct amd_pmc_dev *pdev = dev_get_drvdata(dev); 932 933 if (pdev->disable_8042_wakeup && !disable_workarounds) { 934 int rc = amd_pmc_wa_irq1(pdev); 935 936 if (rc) { 937 dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc); 938 return rc; 939 } 940 } 941 942 return 0; 943 } 944 945 static DEFINE_SIMPLE_DEV_PM_OPS(amd_pmc_pm, amd_pmc_suspend_handler, NULL); 946 947 static const struct pci_device_id pmc_pci_ids[] = { 948 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) }, 949 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) }, 950 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) }, 951 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) }, 952 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) }, 953 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) }, 954 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) }, 955 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) }, 956 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) }, 957 { } 958 }; 959 960 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev) 961 { 962 u32 phys_addr_low, phys_addr_hi; 963 u64 stb_phys_addr; 964 u32 size = 0; 965 int ret; 966 967 /* Spill to DRAM feature uses separate SMU message port */ 968 dev->msg_port = 1; 969 970 /* Get num of IP blocks within the SoC */ 971 amd_pmc_get_ip_info(dev); 972 973 amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, dev->s2d_msg_id, true); 974 if (size != S2D_TELEMETRY_BYTES_MAX) 975 return -EIO; 976 977 /* Get DRAM size */ 978 ret = amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, dev->s2d_msg_id, true); 979 if (ret || !dev->dram_size) 980 dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX; 981 982 /* Get STB DRAM address */ 983 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, dev->s2d_msg_id, true); 984 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, dev->s2d_msg_id, true); 985 986 stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low); 987 988 /* Clear msg_port for other SMU operation */ 989 dev->msg_port = 0; 990 991 dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, dev->dram_size); 992 if (!dev->stb_virt_addr) 993 return -ENOMEM; 994 995 return 0; 996 } 997 998 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data) 999 { 1000 int err; 1001 1002 err = amd_smn_write(0, AMD_PMC_STB_PMI_0, data); 1003 if (err) { 1004 dev_err(dev->dev, "failed to write data in stb: 0x%X\n", AMD_PMC_STB_PMI_0); 1005 return pcibios_err_to_errno(err); 1006 } 1007 1008 return 0; 1009 } 1010 1011 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf) 1012 { 1013 int i, err; 1014 1015 for (i = 0; i < FIFO_SIZE; i++) { 1016 err = amd_smn_read(0, AMD_PMC_STB_PMI_0, buf++); 1017 if (err) { 1018 dev_err(dev->dev, "error reading data from stb: 0x%X\n", AMD_PMC_STB_PMI_0); 1019 return pcibios_err_to_errno(err); 1020 } 1021 } 1022 1023 return 0; 1024 } 1025 1026 static int amd_pmc_probe(struct platform_device *pdev) 1027 { 1028 struct amd_pmc_dev *dev = &pmc; 1029 struct pci_dev *rdev; 1030 u32 base_addr_lo, base_addr_hi; 1031 u64 base_addr; 1032 int err; 1033 u32 val; 1034 1035 dev->dev = &pdev->dev; 1036 1037 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); 1038 if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) { 1039 err = -ENODEV; 1040 goto err_pci_dev_put; 1041 } 1042 1043 dev->cpu_id = rdev->device; 1044 1045 if (dev->cpu_id == AMD_CPU_ID_SP) { 1046 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n"); 1047 err = -ENODEV; 1048 goto err_pci_dev_put; 1049 } 1050 1051 dev->rdev = rdev; 1052 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val); 1053 if (err) { 1054 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO); 1055 err = pcibios_err_to_errno(err); 1056 goto err_pci_dev_put; 1057 } 1058 1059 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK; 1060 1061 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val); 1062 if (err) { 1063 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI); 1064 err = pcibios_err_to_errno(err); 1065 goto err_pci_dev_put; 1066 } 1067 1068 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK; 1069 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo); 1070 1071 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET, 1072 AMD_PMC_MAPPING_SIZE); 1073 if (!dev->regbase) { 1074 err = -ENOMEM; 1075 goto err_pci_dev_put; 1076 } 1077 1078 mutex_init(&dev->lock); 1079 1080 if (enable_stb && amd_pmc_is_stb_supported(dev)) { 1081 err = amd_pmc_s2d_init(dev); 1082 if (err) 1083 goto err_pci_dev_put; 1084 } 1085 1086 platform_set_drvdata(pdev, dev); 1087 if (IS_ENABLED(CONFIG_SUSPEND)) { 1088 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops); 1089 if (err) 1090 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n"); 1091 if (!disable_workarounds) 1092 amd_pmc_quirks_init(dev); 1093 } 1094 1095 amd_pmc_dbgfs_register(dev); 1096 pm_report_max_hw_sleep(U64_MAX); 1097 return 0; 1098 1099 err_pci_dev_put: 1100 pci_dev_put(rdev); 1101 return err; 1102 } 1103 1104 static void amd_pmc_remove(struct platform_device *pdev) 1105 { 1106 struct amd_pmc_dev *dev = platform_get_drvdata(pdev); 1107 1108 if (IS_ENABLED(CONFIG_SUSPEND)) 1109 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops); 1110 amd_pmc_dbgfs_unregister(dev); 1111 pci_dev_put(dev->rdev); 1112 mutex_destroy(&dev->lock); 1113 } 1114 1115 static const struct acpi_device_id amd_pmc_acpi_ids[] = { 1116 {"AMDI0005", 0}, 1117 {"AMDI0006", 0}, 1118 {"AMDI0007", 0}, 1119 {"AMDI0008", 0}, 1120 {"AMDI0009", 0}, 1121 {"AMDI000A", 0}, 1122 {"AMD0004", 0}, 1123 {"AMD0005", 0}, 1124 { } 1125 }; 1126 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids); 1127 1128 static struct platform_driver amd_pmc_driver = { 1129 .driver = { 1130 .name = "amd_pmc", 1131 .acpi_match_table = amd_pmc_acpi_ids, 1132 .dev_groups = pmc_groups, 1133 .pm = pm_sleep_ptr(&amd_pmc_pm), 1134 }, 1135 .probe = amd_pmc_probe, 1136 .remove_new = amd_pmc_remove, 1137 }; 1138 module_platform_driver(amd_pmc_driver); 1139 1140 MODULE_LICENSE("GPL v2"); 1141 MODULE_DESCRIPTION("AMD PMC Driver"); 1142