1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * AMD SoC Power Management Controller Driver 4 * 5 * Copyright (c) 2020, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <asm/amd_nb.h> 14 #include <linux/acpi.h> 15 #include <linux/bitfield.h> 16 #include <linux/bits.h> 17 #include <linux/debugfs.h> 18 #include <linux/delay.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/limits.h> 22 #include <linux/module.h> 23 #include <linux/pci.h> 24 #include <linux/platform_device.h> 25 #include <linux/rtc.h> 26 #include <linux/serio.h> 27 #include <linux/suspend.h> 28 #include <linux/seq_file.h> 29 #include <linux/uaccess.h> 30 31 #include "pmc.h" 32 33 /* SMU communication registers */ 34 #define AMD_PMC_REGISTER_RESPONSE 0x980 35 #define AMD_PMC_REGISTER_ARGUMENT 0x9BC 36 37 /* PMC Scratch Registers */ 38 #define AMD_PMC_SCRATCH_REG_CZN 0x94 39 #define AMD_PMC_SCRATCH_REG_YC 0xD14 40 #define AMD_PMC_SCRATCH_REG_1AH 0xF14 41 42 /* STB Registers */ 43 #define AMD_PMC_STB_PMI_0 0x03E30600 44 #define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001 45 #define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002 46 #define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003 47 #define AMD_PMC_STB_DUMMY_PC 0xC6000007 48 49 /* STB S2D(Spill to DRAM) has different message port offset */ 50 #define AMD_S2D_REGISTER_MESSAGE 0xA20 51 #define AMD_S2D_REGISTER_RESPONSE 0xA80 52 #define AMD_S2D_REGISTER_ARGUMENT 0xA88 53 54 /* STB Spill to DRAM Parameters */ 55 #define S2D_TELEMETRY_BYTES_MAX 0x100000U 56 #define S2D_RSVD_RAM_SPACE 0x100000 57 #define S2D_TELEMETRY_DRAMBYTES_MAX 0x1000000 58 59 /* STB Spill to DRAM Message Definition */ 60 #define STB_FORCE_FLUSH_DATA 0xCF 61 62 /* Base address of SMU for mapping physical address to virtual address */ 63 #define AMD_PMC_MAPPING_SIZE 0x01000 64 #define AMD_PMC_BASE_ADDR_OFFSET 0x10000 65 #define AMD_PMC_BASE_ADDR_LO 0x13B102E8 66 #define AMD_PMC_BASE_ADDR_HI 0x13B102EC 67 #define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0) 68 #define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20) 69 70 /* SMU Response Codes */ 71 #define AMD_PMC_RESULT_OK 0x01 72 #define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC 73 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD 74 #define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE 75 #define AMD_PMC_RESULT_FAILED 0xFF 76 77 /* FCH SSC Registers */ 78 #define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30 79 #define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34 80 #define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38 81 #define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C 82 #define FCH_SSC_MAPPING_SIZE 0x800 83 #define FCH_BASE_PHY_ADDR_LOW 0xFED81100 84 #define FCH_BASE_PHY_ADDR_HIGH 0x00000000 85 86 /* SMU Message Definations */ 87 #define SMU_MSG_GETSMUVERSION 0x02 88 #define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04 89 #define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05 90 #define SMU_MSG_LOG_START 0x06 91 #define SMU_MSG_LOG_RESET 0x07 92 #define SMU_MSG_LOG_DUMP_DATA 0x08 93 #define SMU_MSG_GET_SUP_CONSTRAINTS 0x09 94 95 #define PMC_MSG_DELAY_MIN_US 50 96 #define RESPONSE_REGISTER_LOOP_MAX 20000 97 98 #define DELAY_MIN_US 2000 99 #define DELAY_MAX_US 3000 100 #define FIFO_SIZE 4096 101 102 enum amd_pmc_def { 103 MSG_TEST = 0x01, 104 MSG_OS_HINT_PCO, 105 MSG_OS_HINT_RN, 106 }; 107 108 enum s2d_arg { 109 S2D_TELEMETRY_SIZE = 0x01, 110 S2D_PHYS_ADDR_LOW, 111 S2D_PHYS_ADDR_HIGH, 112 S2D_NUM_SAMPLES, 113 S2D_DRAM_SIZE, 114 }; 115 116 struct amd_pmc_stb_v2_data { 117 size_t size; 118 u8 data[] __counted_by(size); 119 }; 120 121 struct amd_pmc_bit_map { 122 const char *name; 123 u32 bit_mask; 124 }; 125 126 static const struct amd_pmc_bit_map soc15_ip_blk[] = { 127 {"DISPLAY", BIT(0)}, 128 {"CPU", BIT(1)}, 129 {"GFX", BIT(2)}, 130 {"VDD", BIT(3)}, 131 {"ACP", BIT(4)}, 132 {"VCN", BIT(5)}, 133 {"ISP", BIT(6)}, 134 {"NBIO", BIT(7)}, 135 {"DF", BIT(8)}, 136 {"USB3_0", BIT(9)}, 137 {"USB3_1", BIT(10)}, 138 {"LAPIC", BIT(11)}, 139 {"USB3_2", BIT(12)}, 140 {"USB3_3", BIT(13)}, 141 {"USB3_4", BIT(14)}, 142 {"USB4_0", BIT(15)}, 143 {"USB4_1", BIT(16)}, 144 {"MPM", BIT(17)}, 145 {"JPEG", BIT(18)}, 146 {"IPU", BIT(19)}, 147 {"UMSCH", BIT(20)}, 148 {"VPE", BIT(21)}, 149 {} 150 }; 151 152 static bool enable_stb; 153 module_param(enable_stb, bool, 0644); 154 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism"); 155 156 static bool disable_workarounds; 157 module_param(disable_workarounds, bool, 0644); 158 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs"); 159 160 static bool dump_custom_stb; 161 module_param(dump_custom_stb, bool, 0644); 162 MODULE_PARM_DESC(dump_custom_stb, "Enable to dump full STB buffer"); 163 164 static struct amd_pmc_dev pmc; 165 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret); 166 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf); 167 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data); 168 169 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset) 170 { 171 return ioread32(dev->regbase + reg_offset); 172 } 173 174 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val) 175 { 176 iowrite32(val, dev->regbase + reg_offset); 177 } 178 179 struct smu_metrics { 180 u32 table_version; 181 u32 hint_count; 182 u32 s0i3_last_entry_status; 183 u32 timein_s0i2; 184 u64 timeentering_s0i3_lastcapture; 185 u64 timeentering_s0i3_totaltime; 186 u64 timeto_resume_to_os_lastcapture; 187 u64 timeto_resume_to_os_totaltime; 188 u64 timein_s0i3_lastcapture; 189 u64 timein_s0i3_totaltime; 190 u64 timein_swdrips_lastcapture; 191 u64 timein_swdrips_totaltime; 192 u64 timecondition_notmet_lastcapture[32]; 193 u64 timecondition_notmet_totaltime[32]; 194 } __packed; 195 196 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp) 197 { 198 struct amd_pmc_dev *dev = filp->f_inode->i_private; 199 u32 size = FIFO_SIZE * sizeof(u32); 200 u32 *buf; 201 int rc; 202 203 buf = kzalloc(size, GFP_KERNEL); 204 if (!buf) 205 return -ENOMEM; 206 207 rc = amd_pmc_read_stb(dev, buf); 208 if (rc) { 209 kfree(buf); 210 return rc; 211 } 212 213 filp->private_data = buf; 214 return rc; 215 } 216 217 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 218 loff_t *pos) 219 { 220 if (!filp->private_data) 221 return -EINVAL; 222 223 return simple_read_from_buffer(buf, size, pos, filp->private_data, 224 FIFO_SIZE * sizeof(u32)); 225 } 226 227 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp) 228 { 229 kfree(filp->private_data); 230 return 0; 231 } 232 233 static const struct file_operations amd_pmc_stb_debugfs_fops = { 234 .owner = THIS_MODULE, 235 .open = amd_pmc_stb_debugfs_open, 236 .read = amd_pmc_stb_debugfs_read, 237 .release = amd_pmc_stb_debugfs_release, 238 }; 239 240 /* Enhanced STB Firmware Reporting Mechanism */ 241 static int amd_pmc_stb_handle_efr(struct file *filp) 242 { 243 struct amd_pmc_dev *dev = filp->f_inode->i_private; 244 struct amd_pmc_stb_v2_data *stb_data_arr; 245 u32 fsize; 246 247 fsize = dev->dram_size - S2D_RSVD_RAM_SPACE; 248 stb_data_arr = kmalloc(struct_size(stb_data_arr, data, fsize), GFP_KERNEL); 249 if (!stb_data_arr) 250 return -ENOMEM; 251 252 stb_data_arr->size = fsize; 253 memcpy_fromio(stb_data_arr->data, dev->stb_virt_addr, fsize); 254 filp->private_data = stb_data_arr; 255 256 return 0; 257 } 258 259 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp) 260 { 261 struct amd_pmc_dev *dev = filp->f_inode->i_private; 262 u32 fsize, num_samples, val, stb_rdptr_offset = 0; 263 struct amd_pmc_stb_v2_data *stb_data_arr; 264 int ret; 265 266 /* Write dummy postcode while reading the STB buffer */ 267 ret = amd_pmc_write_stb(dev, AMD_PMC_STB_DUMMY_PC); 268 if (ret) 269 dev_err(dev->dev, "error writing to STB: %d\n", ret); 270 271 /* Spill to DRAM num_samples uses separate SMU message port */ 272 dev->msg_port = 1; 273 274 ret = amd_pmc_send_cmd(dev, 0, &val, STB_FORCE_FLUSH_DATA, 1); 275 if (ret) 276 dev_dbg_once(dev->dev, "S2D force flush not supported: %d\n", ret); 277 278 /* 279 * We have a custom stb size and the PMFW is supposed to give 280 * the enhanced dram size. Note that we land here only for the 281 * platforms that support enhanced dram size reporting. 282 */ 283 if (dump_custom_stb) 284 return amd_pmc_stb_handle_efr(filp); 285 286 /* Get the num_samples to calculate the last push location */ 287 ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, dev->s2d_msg_id, true); 288 /* Clear msg_port for other SMU operation */ 289 dev->msg_port = 0; 290 if (ret) { 291 dev_err(dev->dev, "error: S2D_NUM_SAMPLES not supported : %d\n", ret); 292 return ret; 293 } 294 295 fsize = min(num_samples, S2D_TELEMETRY_BYTES_MAX); 296 stb_data_arr = kmalloc(struct_size(stb_data_arr, data, fsize), GFP_KERNEL); 297 if (!stb_data_arr) 298 return -ENOMEM; 299 300 stb_data_arr->size = fsize; 301 302 /* 303 * Start capturing data from the last push location. 304 * This is for general cases, where the stb limits 305 * are meant for standard usage. 306 */ 307 if (num_samples > S2D_TELEMETRY_BYTES_MAX) { 308 /* First read oldest data starting 1 behind last write till end of ringbuffer */ 309 stb_rdptr_offset = num_samples % S2D_TELEMETRY_BYTES_MAX; 310 fsize = S2D_TELEMETRY_BYTES_MAX - stb_rdptr_offset; 311 312 memcpy_fromio(stb_data_arr->data, dev->stb_virt_addr + stb_rdptr_offset, fsize); 313 /* Second copy the newer samples from offset 0 - last write */ 314 memcpy_fromio(stb_data_arr->data + fsize, dev->stb_virt_addr, stb_rdptr_offset); 315 } else { 316 memcpy_fromio(stb_data_arr->data, dev->stb_virt_addr, fsize); 317 } 318 319 filp->private_data = stb_data_arr; 320 321 return 0; 322 } 323 324 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size, 325 loff_t *pos) 326 { 327 struct amd_pmc_stb_v2_data *data = filp->private_data; 328 329 return simple_read_from_buffer(buf, size, pos, data->data, data->size); 330 } 331 332 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp) 333 { 334 kfree(filp->private_data); 335 return 0; 336 } 337 338 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = { 339 .owner = THIS_MODULE, 340 .open = amd_pmc_stb_debugfs_open_v2, 341 .read = amd_pmc_stb_debugfs_read_v2, 342 .release = amd_pmc_stb_debugfs_release_v2, 343 }; 344 345 static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev) 346 { 347 switch (dev->cpu_id) { 348 case AMD_CPU_ID_PCO: 349 case AMD_CPU_ID_RN: 350 case AMD_CPU_ID_YC: 351 case AMD_CPU_ID_CB: 352 dev->num_ips = 12; 353 dev->s2d_msg_id = 0xBE; 354 dev->smu_msg = 0x538; 355 break; 356 case AMD_CPU_ID_PS: 357 dev->num_ips = 21; 358 dev->s2d_msg_id = 0x85; 359 dev->smu_msg = 0x538; 360 break; 361 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: 362 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: 363 dev->num_ips = 22; 364 dev->s2d_msg_id = 0xDE; 365 dev->smu_msg = 0x938; 366 break; 367 } 368 } 369 370 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev) 371 { 372 if (dev->cpu_id == AMD_CPU_ID_PCO) { 373 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n"); 374 return -EINVAL; 375 } 376 377 /* Get Active devices list from SMU */ 378 if (!dev->active_ips) 379 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, true); 380 381 /* Get dram address */ 382 if (!dev->smu_virt_addr) { 383 u32 phys_addr_low, phys_addr_hi; 384 u64 smu_phys_addr; 385 386 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, true); 387 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, true); 388 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low); 389 390 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, 391 sizeof(struct smu_metrics)); 392 if (!dev->smu_virt_addr) 393 return -ENOMEM; 394 } 395 396 /* Start the logging */ 397 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, false); 398 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, false); 399 400 return 0; 401 } 402 403 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table) 404 { 405 if (!pdev->smu_virt_addr) { 406 int ret = amd_pmc_setup_smu_logging(pdev); 407 408 if (ret) 409 return ret; 410 } 411 412 if (pdev->cpu_id == AMD_CPU_ID_PCO) 413 return -ENODEV; 414 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics)); 415 return 0; 416 } 417 418 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev) 419 { 420 struct smu_metrics table; 421 422 if (get_metrics_table(pdev, &table)) 423 return; 424 425 if (!table.s0i3_last_entry_status) 426 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n"); 427 pm_report_hw_sleep_time(table.s0i3_last_entry_status ? 428 table.timein_s0i3_lastcapture : 0); 429 } 430 431 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev) 432 { 433 int rc; 434 u32 val; 435 436 if (dev->cpu_id == AMD_CPU_ID_PCO) 437 return -ENODEV; 438 439 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, true); 440 if (rc) 441 return rc; 442 443 dev->smu_program = (val >> 24) & GENMASK(7, 0); 444 dev->major = (val >> 16) & GENMASK(7, 0); 445 dev->minor = (val >> 8) & GENMASK(7, 0); 446 dev->rev = (val >> 0) & GENMASK(7, 0); 447 448 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n", 449 dev->smu_program, dev->major, dev->minor, dev->rev); 450 451 return 0; 452 } 453 454 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr, 455 char *buf) 456 { 457 struct amd_pmc_dev *dev = dev_get_drvdata(d); 458 459 if (!dev->major) { 460 int rc = amd_pmc_get_smu_version(dev); 461 462 if (rc) 463 return rc; 464 } 465 return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev); 466 } 467 468 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr, 469 char *buf) 470 { 471 struct amd_pmc_dev *dev = dev_get_drvdata(d); 472 473 if (!dev->major) { 474 int rc = amd_pmc_get_smu_version(dev); 475 476 if (rc) 477 return rc; 478 } 479 return sysfs_emit(buf, "%u\n", dev->smu_program); 480 } 481 482 static DEVICE_ATTR_RO(smu_fw_version); 483 static DEVICE_ATTR_RO(smu_program); 484 485 static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 486 { 487 struct device *dev = kobj_to_dev(kobj); 488 struct amd_pmc_dev *pdev = dev_get_drvdata(dev); 489 490 if (pdev->cpu_id == AMD_CPU_ID_PCO) 491 return 0; 492 return 0444; 493 } 494 495 static struct attribute *pmc_attrs[] = { 496 &dev_attr_smu_fw_version.attr, 497 &dev_attr_smu_program.attr, 498 NULL, 499 }; 500 501 static struct attribute_group pmc_attr_group = { 502 .attrs = pmc_attrs, 503 .is_visible = pmc_attr_is_visible, 504 }; 505 506 static const struct attribute_group *pmc_groups[] = { 507 &pmc_attr_group, 508 NULL, 509 }; 510 511 static int smu_fw_info_show(struct seq_file *s, void *unused) 512 { 513 struct amd_pmc_dev *dev = s->private; 514 struct smu_metrics table; 515 int idx; 516 517 if (get_metrics_table(dev, &table)) 518 return -EINVAL; 519 520 seq_puts(s, "\n=== SMU Statistics ===\n"); 521 seq_printf(s, "Table Version: %d\n", table.table_version); 522 seq_printf(s, "Hint Count: %d\n", table.hint_count); 523 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" : 524 "Unknown/Fail"); 525 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture); 526 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture); 527 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n", 528 table.timeto_resume_to_os_lastcapture); 529 530 seq_puts(s, "\n=== Active time (in us) ===\n"); 531 for (idx = 0 ; idx < dev->num_ips ; idx++) { 532 if (soc15_ip_blk[idx].bit_mask & dev->active_ips) 533 seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name, 534 table.timecondition_notmet_lastcapture[idx]); 535 } 536 537 return 0; 538 } 539 DEFINE_SHOW_ATTRIBUTE(smu_fw_info); 540 541 static int s0ix_stats_show(struct seq_file *s, void *unused) 542 { 543 struct amd_pmc_dev *dev = s->private; 544 u64 entry_time, exit_time, residency; 545 546 /* Use FCH registers to get the S0ix stats */ 547 if (!dev->fch_virt_addr) { 548 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW; 549 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH; 550 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo); 551 552 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE); 553 if (!dev->fch_virt_addr) 554 return -ENOMEM; 555 } 556 557 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET); 558 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET); 559 560 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET); 561 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET); 562 563 /* It's in 48MHz. We need to convert it */ 564 residency = exit_time - entry_time; 565 do_div(residency, 48); 566 567 seq_puts(s, "=== S0ix statistics ===\n"); 568 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time); 569 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time); 570 seq_printf(s, "Residency Time: %lld\n", residency); 571 572 return 0; 573 } 574 DEFINE_SHOW_ATTRIBUTE(s0ix_stats); 575 576 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev, 577 struct seq_file *s) 578 { 579 u32 val; 580 int rc; 581 582 switch (pdev->cpu_id) { 583 case AMD_CPU_ID_CZN: 584 /* we haven't yet read SMU version */ 585 if (!pdev->major) { 586 rc = amd_pmc_get_smu_version(pdev); 587 if (rc) 588 return rc; 589 } 590 if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37)) 591 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN); 592 else 593 return -EINVAL; 594 break; 595 case AMD_CPU_ID_YC: 596 case AMD_CPU_ID_CB: 597 case AMD_CPU_ID_PS: 598 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC); 599 break; 600 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: 601 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: 602 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_1AH); 603 break; 604 default: 605 return -EINVAL; 606 } 607 608 if (dev) 609 pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val); 610 611 if (s) 612 seq_printf(s, "SMU idlemask : 0x%x\n", val); 613 614 return 0; 615 } 616 617 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused) 618 { 619 return amd_pmc_idlemask_read(s->private, NULL, s); 620 } 621 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask); 622 623 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev) 624 { 625 debugfs_remove_recursive(dev->dbgfs_dir); 626 } 627 628 static bool amd_pmc_is_stb_supported(struct amd_pmc_dev *dev) 629 { 630 switch (dev->cpu_id) { 631 case AMD_CPU_ID_YC: 632 case AMD_CPU_ID_CB: 633 case AMD_CPU_ID_PS: 634 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: 635 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: 636 return true; 637 default: 638 return false; 639 } 640 } 641 642 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) 643 { 644 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL); 645 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev, 646 &smu_fw_info_fops); 647 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev, 648 &s0ix_stats_fops); 649 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev, 650 &amd_pmc_idlemask_fops); 651 /* Enable STB only when the module_param is set */ 652 if (enable_stb) { 653 if (amd_pmc_is_stb_supported(dev)) 654 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev, 655 &amd_pmc_stb_debugfs_fops_v2); 656 else 657 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev, 658 &amd_pmc_stb_debugfs_fops); 659 } 660 } 661 662 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev) 663 { 664 u32 value, message, argument, response; 665 666 if (dev->msg_port) { 667 message = AMD_S2D_REGISTER_MESSAGE; 668 argument = AMD_S2D_REGISTER_ARGUMENT; 669 response = AMD_S2D_REGISTER_RESPONSE; 670 } else { 671 message = dev->smu_msg; 672 argument = AMD_PMC_REGISTER_ARGUMENT; 673 response = AMD_PMC_REGISTER_RESPONSE; 674 } 675 676 value = amd_pmc_reg_read(dev, response); 677 dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", dev->msg_port ? "S2D" : "PMC", value); 678 679 value = amd_pmc_reg_read(dev, argument); 680 dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", dev->msg_port ? "S2D" : "PMC", value); 681 682 value = amd_pmc_reg_read(dev, message); 683 dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", dev->msg_port ? "S2D" : "PMC", value); 684 } 685 686 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret) 687 { 688 int rc; 689 u32 val, message, argument, response; 690 691 mutex_lock(&dev->lock); 692 693 if (dev->msg_port) { 694 message = AMD_S2D_REGISTER_MESSAGE; 695 argument = AMD_S2D_REGISTER_ARGUMENT; 696 response = AMD_S2D_REGISTER_RESPONSE; 697 } else { 698 message = dev->smu_msg; 699 argument = AMD_PMC_REGISTER_ARGUMENT; 700 response = AMD_PMC_REGISTER_RESPONSE; 701 } 702 703 /* Wait until we get a valid response */ 704 rc = readx_poll_timeout(ioread32, dev->regbase + response, 705 val, val != 0, PMC_MSG_DELAY_MIN_US, 706 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 707 if (rc) { 708 dev_err(dev->dev, "failed to talk to SMU\n"); 709 goto out_unlock; 710 } 711 712 /* Write zero to response register */ 713 amd_pmc_reg_write(dev, response, 0); 714 715 /* Write argument into response register */ 716 amd_pmc_reg_write(dev, argument, arg); 717 718 /* Write message ID to message ID register */ 719 amd_pmc_reg_write(dev, message, msg); 720 721 /* Wait until we get a valid response */ 722 rc = readx_poll_timeout(ioread32, dev->regbase + response, 723 val, val != 0, PMC_MSG_DELAY_MIN_US, 724 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 725 if (rc) { 726 dev_err(dev->dev, "SMU response timed out\n"); 727 goto out_unlock; 728 } 729 730 switch (val) { 731 case AMD_PMC_RESULT_OK: 732 if (ret) { 733 /* PMFW may take longer time to return back the data */ 734 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US); 735 *data = amd_pmc_reg_read(dev, argument); 736 } 737 break; 738 case AMD_PMC_RESULT_CMD_REJECT_BUSY: 739 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val); 740 rc = -EBUSY; 741 goto out_unlock; 742 case AMD_PMC_RESULT_CMD_UNKNOWN: 743 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val); 744 rc = -EINVAL; 745 goto out_unlock; 746 case AMD_PMC_RESULT_CMD_REJECT_PREREQ: 747 case AMD_PMC_RESULT_FAILED: 748 default: 749 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val); 750 rc = -EIO; 751 goto out_unlock; 752 } 753 754 out_unlock: 755 mutex_unlock(&dev->lock); 756 amd_pmc_dump_registers(dev); 757 return rc; 758 } 759 760 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev) 761 { 762 switch (dev->cpu_id) { 763 case AMD_CPU_ID_PCO: 764 return MSG_OS_HINT_PCO; 765 case AMD_CPU_ID_RN: 766 case AMD_CPU_ID_YC: 767 case AMD_CPU_ID_CB: 768 case AMD_CPU_ID_PS: 769 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: 770 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: 771 return MSG_OS_HINT_RN; 772 } 773 return -EINVAL; 774 } 775 776 static int amd_pmc_wa_irq1(struct amd_pmc_dev *pdev) 777 { 778 struct device *d; 779 int rc; 780 781 /* cezanne platform firmware has a fix in 64.66.0 */ 782 if (pdev->cpu_id == AMD_CPU_ID_CZN) { 783 if (!pdev->major) { 784 rc = amd_pmc_get_smu_version(pdev); 785 if (rc) 786 return rc; 787 } 788 789 if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65)) 790 return 0; 791 } 792 793 d = bus_find_device_by_name(&serio_bus, NULL, "serio0"); 794 if (!d) 795 return 0; 796 if (device_may_wakeup(d)) { 797 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n"); 798 disable_irq_wake(1); 799 device_set_wakeup_enable(d, false); 800 } 801 put_device(d); 802 803 return 0; 804 } 805 806 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg) 807 { 808 struct rtc_device *rtc_device; 809 time64_t then, now, duration; 810 struct rtc_wkalrm alarm; 811 struct rtc_time tm; 812 int rc; 813 814 /* we haven't yet read SMU version */ 815 if (!pdev->major) { 816 rc = amd_pmc_get_smu_version(pdev); 817 if (rc) 818 return rc; 819 } 820 821 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53)) 822 return 0; 823 824 rtc_device = rtc_class_open("rtc0"); 825 if (!rtc_device) 826 return 0; 827 rc = rtc_read_alarm(rtc_device, &alarm); 828 if (rc) 829 return rc; 830 if (!alarm.enabled) { 831 dev_dbg(pdev->dev, "alarm not enabled\n"); 832 return 0; 833 } 834 rc = rtc_read_time(rtc_device, &tm); 835 if (rc) 836 return rc; 837 then = rtc_tm_to_time64(&alarm.time); 838 now = rtc_tm_to_time64(&tm); 839 duration = then-now; 840 841 /* in the past */ 842 if (then < now) 843 return 0; 844 845 /* will be stored in upper 16 bits of s0i3 hint argument, 846 * so timer wakeup from s0i3 is limited to ~18 hours or less 847 */ 848 if (duration <= 4 || duration > U16_MAX) 849 return -EINVAL; 850 851 *arg |= (duration << 16); 852 rc = rtc_alarm_irq_enable(rtc_device, 0); 853 pm_pr_dbg("wakeup timer programmed for %lld seconds\n", duration); 854 855 return rc; 856 } 857 858 static void amd_pmc_s2idle_prepare(void) 859 { 860 struct amd_pmc_dev *pdev = &pmc; 861 int rc; 862 u8 msg; 863 u32 arg = 1; 864 865 /* Reset and Start SMU logging - to monitor the s0i3 stats */ 866 amd_pmc_setup_smu_logging(pdev); 867 868 /* Activate CZN specific platform bug workarounds */ 869 if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) { 870 rc = amd_pmc_verify_czn_rtc(pdev, &arg); 871 if (rc) { 872 dev_err(pdev->dev, "failed to set RTC: %d\n", rc); 873 return; 874 } 875 } 876 877 msg = amd_pmc_get_os_hint(pdev); 878 rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, false); 879 if (rc) { 880 dev_err(pdev->dev, "suspend failed: %d\n", rc); 881 return; 882 } 883 884 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_PREPARE); 885 if (rc) 886 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 887 } 888 889 static void amd_pmc_s2idle_check(void) 890 { 891 struct amd_pmc_dev *pdev = &pmc; 892 struct smu_metrics table; 893 int rc; 894 895 /* CZN: Ensure that future s0i3 entry attempts at least 10ms passed */ 896 if (pdev->cpu_id == AMD_CPU_ID_CZN && !get_metrics_table(pdev, &table) && 897 table.s0i3_last_entry_status) 898 usleep_range(10000, 20000); 899 900 /* Dump the IdleMask before we add to the STB */ 901 amd_pmc_idlemask_read(pdev, pdev->dev, NULL); 902 903 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_CHECK); 904 if (rc) 905 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 906 } 907 908 static int amd_pmc_dump_data(struct amd_pmc_dev *pdev) 909 { 910 if (pdev->cpu_id == AMD_CPU_ID_PCO) 911 return -ENODEV; 912 913 return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, false); 914 } 915 916 static void amd_pmc_s2idle_restore(void) 917 { 918 struct amd_pmc_dev *pdev = &pmc; 919 int rc; 920 u8 msg; 921 922 msg = amd_pmc_get_os_hint(pdev); 923 rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, false); 924 if (rc) 925 dev_err(pdev->dev, "resume failed: %d\n", rc); 926 927 /* Let SMU know that we are looking for stats */ 928 amd_pmc_dump_data(pdev); 929 930 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_RESTORE); 931 if (rc) 932 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 933 934 /* Notify on failed entry */ 935 amd_pmc_validate_deepest(pdev); 936 937 amd_pmc_process_restore_quirks(pdev); 938 } 939 940 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = { 941 .prepare = amd_pmc_s2idle_prepare, 942 .check = amd_pmc_s2idle_check, 943 .restore = amd_pmc_s2idle_restore, 944 }; 945 946 static int amd_pmc_suspend_handler(struct device *dev) 947 { 948 struct amd_pmc_dev *pdev = dev_get_drvdata(dev); 949 950 if (pdev->disable_8042_wakeup && !disable_workarounds) { 951 int rc = amd_pmc_wa_irq1(pdev); 952 953 if (rc) { 954 dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc); 955 return rc; 956 } 957 } 958 959 return 0; 960 } 961 962 static DEFINE_SIMPLE_DEV_PM_OPS(amd_pmc_pm, amd_pmc_suspend_handler, NULL); 963 964 static const struct pci_device_id pmc_pci_ids[] = { 965 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) }, 966 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) }, 967 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) }, 968 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) }, 969 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) }, 970 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) }, 971 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) }, 972 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) }, 973 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) }, 974 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) }, 975 { } 976 }; 977 978 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev) 979 { 980 u32 phys_addr_low, phys_addr_hi; 981 u64 stb_phys_addr; 982 u32 size = 0; 983 int ret; 984 985 /* Spill to DRAM feature uses separate SMU message port */ 986 dev->msg_port = 1; 987 988 amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, dev->s2d_msg_id, true); 989 if (size != S2D_TELEMETRY_BYTES_MAX) 990 return -EIO; 991 992 /* Get DRAM size */ 993 ret = amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, dev->s2d_msg_id, true); 994 if (ret || !dev->dram_size) 995 dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX; 996 997 /* Get STB DRAM address */ 998 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, dev->s2d_msg_id, true); 999 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, dev->s2d_msg_id, true); 1000 1001 if (!phys_addr_hi && !phys_addr_low) { 1002 dev_err(dev->dev, "STB is not enabled on the system; disable enable_stb or contact system vendor\n"); 1003 return -EINVAL; 1004 } 1005 1006 stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low); 1007 1008 /* Clear msg_port for other SMU operation */ 1009 dev->msg_port = 0; 1010 1011 dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, dev->dram_size); 1012 if (!dev->stb_virt_addr) 1013 return -ENOMEM; 1014 1015 return 0; 1016 } 1017 1018 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data) 1019 { 1020 int err; 1021 1022 err = amd_smn_write(0, AMD_PMC_STB_PMI_0, data); 1023 if (err) { 1024 dev_err(dev->dev, "failed to write data in stb: 0x%X\n", AMD_PMC_STB_PMI_0); 1025 return pcibios_err_to_errno(err); 1026 } 1027 1028 return 0; 1029 } 1030 1031 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf) 1032 { 1033 int i, err; 1034 1035 for (i = 0; i < FIFO_SIZE; i++) { 1036 err = amd_smn_read(0, AMD_PMC_STB_PMI_0, buf++); 1037 if (err) { 1038 dev_err(dev->dev, "error reading data from stb: 0x%X\n", AMD_PMC_STB_PMI_0); 1039 return pcibios_err_to_errno(err); 1040 } 1041 } 1042 1043 return 0; 1044 } 1045 1046 static int amd_pmc_probe(struct platform_device *pdev) 1047 { 1048 struct amd_pmc_dev *dev = &pmc; 1049 struct pci_dev *rdev; 1050 u32 base_addr_lo, base_addr_hi; 1051 u64 base_addr; 1052 int err; 1053 u32 val; 1054 1055 dev->dev = &pdev->dev; 1056 1057 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); 1058 if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) { 1059 err = -ENODEV; 1060 goto err_pci_dev_put; 1061 } 1062 1063 dev->cpu_id = rdev->device; 1064 1065 if (dev->cpu_id == AMD_CPU_ID_SP) { 1066 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n"); 1067 err = -ENODEV; 1068 goto err_pci_dev_put; 1069 } 1070 1071 dev->rdev = rdev; 1072 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val); 1073 if (err) { 1074 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO); 1075 err = pcibios_err_to_errno(err); 1076 goto err_pci_dev_put; 1077 } 1078 1079 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK; 1080 1081 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val); 1082 if (err) { 1083 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI); 1084 err = pcibios_err_to_errno(err); 1085 goto err_pci_dev_put; 1086 } 1087 1088 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK; 1089 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo); 1090 1091 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET, 1092 AMD_PMC_MAPPING_SIZE); 1093 if (!dev->regbase) { 1094 err = -ENOMEM; 1095 goto err_pci_dev_put; 1096 } 1097 1098 mutex_init(&dev->lock); 1099 1100 /* Get num of IP blocks within the SoC */ 1101 amd_pmc_get_ip_info(dev); 1102 1103 if (enable_stb && amd_pmc_is_stb_supported(dev)) { 1104 err = amd_pmc_s2d_init(dev); 1105 if (err) 1106 goto err_pci_dev_put; 1107 } 1108 1109 platform_set_drvdata(pdev, dev); 1110 if (IS_ENABLED(CONFIG_SUSPEND)) { 1111 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops); 1112 if (err) 1113 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n"); 1114 if (!disable_workarounds) 1115 amd_pmc_quirks_init(dev); 1116 } 1117 1118 amd_pmc_dbgfs_register(dev); 1119 if (IS_ENABLED(CONFIG_AMD_MP2_STB)) 1120 amd_mp2_stb_init(dev); 1121 pm_report_max_hw_sleep(U64_MAX); 1122 return 0; 1123 1124 err_pci_dev_put: 1125 pci_dev_put(rdev); 1126 return err; 1127 } 1128 1129 static void amd_pmc_remove(struct platform_device *pdev) 1130 { 1131 struct amd_pmc_dev *dev = platform_get_drvdata(pdev); 1132 1133 if (IS_ENABLED(CONFIG_SUSPEND)) 1134 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops); 1135 amd_pmc_dbgfs_unregister(dev); 1136 pci_dev_put(dev->rdev); 1137 if (IS_ENABLED(CONFIG_AMD_MP2_STB)) 1138 amd_mp2_stb_deinit(dev); 1139 mutex_destroy(&dev->lock); 1140 } 1141 1142 static const struct acpi_device_id amd_pmc_acpi_ids[] = { 1143 {"AMDI0005", 0}, 1144 {"AMDI0006", 0}, 1145 {"AMDI0007", 0}, 1146 {"AMDI0008", 0}, 1147 {"AMDI0009", 0}, 1148 {"AMDI000A", 0}, 1149 {"AMDI000B", 0}, 1150 {"AMD0004", 0}, 1151 {"AMD0005", 0}, 1152 { } 1153 }; 1154 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids); 1155 1156 static struct platform_driver amd_pmc_driver = { 1157 .driver = { 1158 .name = "amd_pmc", 1159 .acpi_match_table = amd_pmc_acpi_ids, 1160 .dev_groups = pmc_groups, 1161 .pm = pm_sleep_ptr(&amd_pmc_pm), 1162 }, 1163 .probe = amd_pmc_probe, 1164 .remove_new = amd_pmc_remove, 1165 }; 1166 module_platform_driver(amd_pmc_driver); 1167 1168 MODULE_LICENSE("GPL v2"); 1169 MODULE_DESCRIPTION("AMD PMC Driver"); 1170