1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * AMD SoC Power Management Controller Driver 4 * 5 * Copyright (c) 2020, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/acpi.h> 14 #include <linux/array_size.h> 15 #include <linux/bitfield.h> 16 #include <linux/bits.h> 17 #include <linux/debugfs.h> 18 #include <linux/delay.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/limits.h> 22 #include <linux/module.h> 23 #include <linux/pci.h> 24 #include <linux/platform_device.h> 25 #include <linux/rtc.h> 26 #include <linux/serio.h> 27 #include <linux/suspend.h> 28 #include <linux/seq_file.h> 29 #include <linux/uaccess.h> 30 31 #include <asm/amd/node.h> 32 33 #include "pmc.h" 34 35 static const struct amd_pmc_bit_map soc15_ip_blk_v2[] = { 36 {"DISPLAY", BIT(0)}, 37 {"CPU", BIT(1)}, 38 {"GFX", BIT(2)}, 39 {"VDD", BIT(3)}, 40 {"VDD_CCX", BIT(4)}, 41 {"ACP", BIT(5)}, 42 {"VCN_0", BIT(6)}, 43 {"VCN_1", BIT(7)}, 44 {"ISP", BIT(8)}, 45 {"NBIO", BIT(9)}, 46 {"DF", BIT(10)}, 47 {"USB3_0", BIT(11)}, 48 {"USB3_1", BIT(12)}, 49 {"LAPIC", BIT(13)}, 50 {"USB3_2", BIT(14)}, 51 {"USB4_RT0", BIT(15)}, 52 {"USB4_RT1", BIT(16)}, 53 {"USB4_0", BIT(17)}, 54 {"USB4_1", BIT(18)}, 55 {"MPM", BIT(19)}, 56 {"JPEG_0", BIT(20)}, 57 {"JPEG_1", BIT(21)}, 58 {"IPU", BIT(22)}, 59 {"UMSCH", BIT(23)}, 60 {"VPE", BIT(24)}, 61 }; 62 63 static const struct amd_pmc_bit_map soc15_ip_blk[] = { 64 {"DISPLAY", BIT(0)}, 65 {"CPU", BIT(1)}, 66 {"GFX", BIT(2)}, 67 {"VDD", BIT(3)}, 68 {"ACP", BIT(4)}, 69 {"VCN", BIT(5)}, 70 {"ISP", BIT(6)}, 71 {"NBIO", BIT(7)}, 72 {"DF", BIT(8)}, 73 {"USB3_0", BIT(9)}, 74 {"USB3_1", BIT(10)}, 75 {"LAPIC", BIT(11)}, 76 {"USB3_2", BIT(12)}, 77 {"USB3_3", BIT(13)}, 78 {"USB3_4", BIT(14)}, 79 {"USB4_0", BIT(15)}, 80 {"USB4_1", BIT(16)}, 81 {"MPM", BIT(17)}, 82 {"JPEG", BIT(18)}, 83 {"IPU", BIT(19)}, 84 {"UMSCH", BIT(20)}, 85 {"VPE", BIT(21)}, 86 }; 87 88 static bool disable_workarounds; 89 module_param(disable_workarounds, bool, 0644); 90 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs"); 91 92 static struct amd_pmc_dev pmc; 93 94 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset) 95 { 96 return ioread32(dev->regbase + reg_offset); 97 } 98 99 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val) 100 { 101 iowrite32(val, dev->regbase + reg_offset); 102 } 103 104 static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev) 105 { 106 switch (dev->cpu_id) { 107 case AMD_CPU_ID_PCO: 108 case AMD_CPU_ID_RN: 109 case AMD_CPU_ID_YC: 110 case AMD_CPU_ID_CB: 111 dev->num_ips = 12; 112 dev->ips_ptr = soc15_ip_blk; 113 dev->smu_msg = 0x538; 114 break; 115 case AMD_CPU_ID_PS: 116 dev->num_ips = 21; 117 dev->ips_ptr = soc15_ip_blk; 118 dev->smu_msg = 0x538; 119 break; 120 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: 121 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: 122 if (boot_cpu_data.x86_model == 0x70) { 123 dev->num_ips = ARRAY_SIZE(soc15_ip_blk_v2); 124 dev->ips_ptr = soc15_ip_blk_v2; 125 } else { 126 dev->num_ips = ARRAY_SIZE(soc15_ip_blk); 127 dev->ips_ptr = soc15_ip_blk; 128 } 129 dev->smu_msg = 0x938; 130 break; 131 } 132 } 133 134 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev) 135 { 136 if (dev->cpu_id == AMD_CPU_ID_PCO) { 137 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n"); 138 return -EINVAL; 139 } 140 141 /* Get Active devices list from SMU */ 142 if (!dev->active_ips) 143 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, true); 144 145 /* Get dram address */ 146 if (!dev->smu_virt_addr) { 147 u32 phys_addr_low, phys_addr_hi; 148 u64 smu_phys_addr; 149 150 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, true); 151 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, true); 152 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low); 153 154 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, 155 sizeof(struct smu_metrics)); 156 if (!dev->smu_virt_addr) 157 return -ENOMEM; 158 } 159 160 memset_io(dev->smu_virt_addr, 0, sizeof(struct smu_metrics)); 161 162 /* Start the logging */ 163 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, false); 164 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, false); 165 166 return 0; 167 } 168 169 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table) 170 { 171 int rc; 172 173 if (!pdev->smu_virt_addr) { 174 rc = amd_pmc_setup_smu_logging(pdev); 175 if (rc) 176 return rc; 177 } 178 179 if (pdev->cpu_id == AMD_CPU_ID_PCO) 180 return -ENODEV; 181 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics)); 182 return 0; 183 } 184 185 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev) 186 { 187 struct smu_metrics table; 188 189 if (get_metrics_table(pdev, &table)) 190 return; 191 192 if (!table.s0i3_last_entry_status) 193 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n"); 194 pm_report_hw_sleep_time(table.s0i3_last_entry_status ? 195 table.timein_s0i3_lastcapture : 0); 196 } 197 198 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev) 199 { 200 int rc; 201 u32 val; 202 203 if (dev->cpu_id == AMD_CPU_ID_PCO) 204 return -ENODEV; 205 206 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, true); 207 if (rc) 208 return rc; 209 210 dev->smu_program = (val >> 24) & GENMASK(7, 0); 211 dev->major = (val >> 16) & GENMASK(7, 0); 212 dev->minor = (val >> 8) & GENMASK(7, 0); 213 dev->rev = (val >> 0) & GENMASK(7, 0); 214 215 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n", 216 dev->smu_program, dev->major, dev->minor, dev->rev); 217 218 return 0; 219 } 220 221 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr, 222 char *buf) 223 { 224 struct amd_pmc_dev *dev = dev_get_drvdata(d); 225 int rc; 226 227 if (!dev->major) { 228 rc = amd_pmc_get_smu_version(dev); 229 if (rc) 230 return rc; 231 } 232 return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev); 233 } 234 235 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr, 236 char *buf) 237 { 238 struct amd_pmc_dev *dev = dev_get_drvdata(d); 239 int rc; 240 241 if (!dev->major) { 242 rc = amd_pmc_get_smu_version(dev); 243 if (rc) 244 return rc; 245 } 246 return sysfs_emit(buf, "%u\n", dev->smu_program); 247 } 248 249 static DEVICE_ATTR_RO(smu_fw_version); 250 static DEVICE_ATTR_RO(smu_program); 251 252 static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 253 { 254 struct device *dev = kobj_to_dev(kobj); 255 struct amd_pmc_dev *pdev = dev_get_drvdata(dev); 256 257 if (pdev->cpu_id == AMD_CPU_ID_PCO) 258 return 0; 259 return 0444; 260 } 261 262 static struct attribute *pmc_attrs[] = { 263 &dev_attr_smu_fw_version.attr, 264 &dev_attr_smu_program.attr, 265 NULL, 266 }; 267 268 static struct attribute_group pmc_attr_group = { 269 .attrs = pmc_attrs, 270 .is_visible = pmc_attr_is_visible, 271 }; 272 273 static const struct attribute_group *pmc_groups[] = { 274 &pmc_attr_group, 275 NULL, 276 }; 277 278 static int smu_fw_info_show(struct seq_file *s, void *unused) 279 { 280 struct amd_pmc_dev *dev = s->private; 281 struct smu_metrics table; 282 int idx; 283 284 if (get_metrics_table(dev, &table)) 285 return -EINVAL; 286 287 seq_puts(s, "\n=== SMU Statistics ===\n"); 288 seq_printf(s, "Table Version: %d\n", table.table_version); 289 seq_printf(s, "Hint Count: %d\n", table.hint_count); 290 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" : 291 "Unknown/Fail"); 292 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture); 293 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture); 294 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n", 295 table.timeto_resume_to_os_lastcapture); 296 297 seq_puts(s, "\n=== Active time (in us) ===\n"); 298 for (idx = 0 ; idx < dev->num_ips ; idx++) { 299 if (dev->ips_ptr[idx].bit_mask & dev->active_ips) 300 seq_printf(s, "%-8s : %lld\n", dev->ips_ptr[idx].name, 301 table.timecondition_notmet_lastcapture[idx]); 302 } 303 304 return 0; 305 } 306 DEFINE_SHOW_ATTRIBUTE(smu_fw_info); 307 308 static int s0ix_stats_show(struct seq_file *s, void *unused) 309 { 310 struct amd_pmc_dev *dev = s->private; 311 u64 entry_time, exit_time, residency; 312 313 /* Use FCH registers to get the S0ix stats */ 314 if (!dev->fch_virt_addr) { 315 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW; 316 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH; 317 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo); 318 319 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE); 320 if (!dev->fch_virt_addr) 321 return -ENOMEM; 322 } 323 324 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET); 325 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET); 326 327 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET); 328 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET); 329 330 /* It's in 48MHz. We need to convert it */ 331 residency = exit_time - entry_time; 332 do_div(residency, 48); 333 334 seq_puts(s, "=== S0ix statistics ===\n"); 335 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time); 336 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time); 337 seq_printf(s, "Residency Time: %lld\n", residency); 338 339 return 0; 340 } 341 DEFINE_SHOW_ATTRIBUTE(s0ix_stats); 342 343 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev, 344 struct seq_file *s) 345 { 346 u32 val; 347 int rc; 348 349 switch (pdev->cpu_id) { 350 case AMD_CPU_ID_CZN: 351 /* we haven't yet read SMU version */ 352 if (!pdev->major) { 353 rc = amd_pmc_get_smu_version(pdev); 354 if (rc) 355 return rc; 356 } 357 if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37)) 358 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN); 359 else 360 return -EINVAL; 361 break; 362 case AMD_CPU_ID_YC: 363 case AMD_CPU_ID_CB: 364 case AMD_CPU_ID_PS: 365 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC); 366 break; 367 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: 368 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: 369 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_1AH); 370 break; 371 default: 372 return -EINVAL; 373 } 374 375 if (dev) 376 pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val); 377 378 if (s) 379 seq_printf(s, "SMU idlemask : 0x%x\n", val); 380 381 return 0; 382 } 383 384 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused) 385 { 386 return amd_pmc_idlemask_read(s->private, NULL, s); 387 } 388 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask); 389 390 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev) 391 { 392 debugfs_remove_recursive(dev->dbgfs_dir); 393 } 394 395 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) 396 { 397 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL); 398 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev, 399 &smu_fw_info_fops); 400 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev, 401 &s0ix_stats_fops); 402 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev, 403 &amd_pmc_idlemask_fops); 404 } 405 406 static char *amd_pmc_get_msg_port(struct amd_pmc_dev *dev) 407 { 408 switch (dev->msg_port) { 409 case MSG_PORT_PMC: 410 return "PMC"; 411 case MSG_PORT_S2D: 412 return "S2D"; 413 default: 414 return "Invalid message port"; 415 } 416 } 417 418 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev) 419 { 420 u32 value, message, argument, response; 421 422 if (dev->msg_port == MSG_PORT_S2D) { 423 message = dev->stb_arg.msg; 424 argument = dev->stb_arg.arg; 425 response = dev->stb_arg.resp; 426 } else { 427 message = dev->smu_msg; 428 argument = AMD_PMC_REGISTER_ARGUMENT; 429 response = AMD_PMC_REGISTER_RESPONSE; 430 } 431 432 value = amd_pmc_reg_read(dev, response); 433 dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", amd_pmc_get_msg_port(dev), value); 434 435 value = amd_pmc_reg_read(dev, argument); 436 dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", amd_pmc_get_msg_port(dev), value); 437 438 value = amd_pmc_reg_read(dev, message); 439 dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", amd_pmc_get_msg_port(dev), value); 440 } 441 442 int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret) 443 { 444 int rc; 445 u32 val, message, argument, response; 446 447 guard(mutex)(&dev->lock); 448 449 if (dev->msg_port == MSG_PORT_S2D) { 450 message = dev->stb_arg.msg; 451 argument = dev->stb_arg.arg; 452 response = dev->stb_arg.resp; 453 } else { 454 message = dev->smu_msg; 455 argument = AMD_PMC_REGISTER_ARGUMENT; 456 response = AMD_PMC_REGISTER_RESPONSE; 457 } 458 459 /* Wait until we get a valid response */ 460 rc = readx_poll_timeout(ioread32, dev->regbase + response, 461 val, val != 0, PMC_MSG_DELAY_MIN_US, 462 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 463 if (rc) { 464 dev_err(dev->dev, "failed to talk to SMU\n"); 465 return rc; 466 } 467 468 /* Write zero to response register */ 469 amd_pmc_reg_write(dev, response, 0); 470 471 /* Write argument into response register */ 472 amd_pmc_reg_write(dev, argument, arg); 473 474 /* Write message ID to message ID register */ 475 amd_pmc_reg_write(dev, message, msg); 476 477 /* Wait until we get a valid response */ 478 rc = readx_poll_timeout(ioread32, dev->regbase + response, 479 val, val != 0, PMC_MSG_DELAY_MIN_US, 480 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 481 if (rc) { 482 dev_err(dev->dev, "SMU response timed out\n"); 483 return rc; 484 } 485 486 switch (val) { 487 case AMD_PMC_RESULT_OK: 488 if (ret) { 489 /* PMFW may take longer time to return back the data */ 490 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US); 491 *data = amd_pmc_reg_read(dev, argument); 492 } 493 break; 494 case AMD_PMC_RESULT_CMD_REJECT_BUSY: 495 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val); 496 rc = -EBUSY; 497 break; 498 case AMD_PMC_RESULT_CMD_UNKNOWN: 499 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val); 500 rc = -EINVAL; 501 break; 502 case AMD_PMC_RESULT_CMD_REJECT_PREREQ: 503 case AMD_PMC_RESULT_FAILED: 504 default: 505 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val); 506 rc = -EIO; 507 break; 508 } 509 510 amd_pmc_dump_registers(dev); 511 return rc; 512 } 513 514 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev) 515 { 516 switch (dev->cpu_id) { 517 case AMD_CPU_ID_PCO: 518 return MSG_OS_HINT_PCO; 519 case AMD_CPU_ID_RN: 520 case AMD_CPU_ID_YC: 521 case AMD_CPU_ID_CB: 522 case AMD_CPU_ID_PS: 523 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: 524 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: 525 return MSG_OS_HINT_RN; 526 } 527 return -EINVAL; 528 } 529 530 static int amd_pmc_wa_irq1(struct amd_pmc_dev *pdev) 531 { 532 struct device *d; 533 534 d = bus_find_device_by_name(&serio_bus, NULL, "serio0"); 535 if (!d) 536 return 0; 537 if (device_may_wakeup(d)) { 538 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n"); 539 disable_irq_wake(1); 540 device_set_wakeup_enable(d, false); 541 } 542 put_device(d); 543 544 return 0; 545 } 546 547 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg) 548 { 549 struct rtc_device *rtc_device; 550 time64_t then, now, duration; 551 struct rtc_wkalrm alarm; 552 struct rtc_time tm; 553 int rc; 554 555 /* we haven't yet read SMU version */ 556 if (!pdev->major) { 557 rc = amd_pmc_get_smu_version(pdev); 558 if (rc) 559 return rc; 560 } 561 562 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53)) 563 return 0; 564 565 rtc_device = rtc_class_open("rtc0"); 566 if (!rtc_device) 567 return 0; 568 rc = rtc_read_alarm(rtc_device, &alarm); 569 if (rc) 570 return rc; 571 if (!alarm.enabled) { 572 dev_dbg(pdev->dev, "alarm not enabled\n"); 573 return 0; 574 } 575 rc = rtc_read_time(rtc_device, &tm); 576 if (rc) 577 return rc; 578 then = rtc_tm_to_time64(&alarm.time); 579 now = rtc_tm_to_time64(&tm); 580 duration = then-now; 581 582 /* in the past */ 583 if (then < now) 584 return 0; 585 586 /* will be stored in upper 16 bits of s0i3 hint argument, 587 * so timer wakeup from s0i3 is limited to ~18 hours or less 588 */ 589 if (duration <= 4 || duration > U16_MAX) 590 return -EINVAL; 591 592 *arg |= (duration << 16); 593 rc = rtc_alarm_irq_enable(rtc_device, 0); 594 pm_pr_dbg("wakeup timer programmed for %lld seconds\n", duration); 595 596 return rc; 597 } 598 599 static void amd_pmc_s2idle_prepare(void) 600 { 601 struct amd_pmc_dev *pdev = &pmc; 602 int rc; 603 u8 msg; 604 u32 arg = 1; 605 606 /* Reset and Start SMU logging - to monitor the s0i3 stats */ 607 amd_pmc_setup_smu_logging(pdev); 608 609 /* Activate CZN specific platform bug workarounds */ 610 if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) { 611 rc = amd_pmc_verify_czn_rtc(pdev, &arg); 612 if (rc) { 613 dev_err(pdev->dev, "failed to set RTC: %d\n", rc); 614 return; 615 } 616 } 617 618 msg = amd_pmc_get_os_hint(pdev); 619 rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, false); 620 if (rc) { 621 dev_err(pdev->dev, "suspend failed: %d\n", rc); 622 return; 623 } 624 625 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_PREPARE); 626 if (rc) 627 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 628 } 629 630 static void amd_pmc_s2idle_check(void) 631 { 632 struct amd_pmc_dev *pdev = &pmc; 633 struct smu_metrics table; 634 int rc; 635 636 /* Avoid triggering OVP */ 637 if (!get_metrics_table(pdev, &table) && table.s0i3_last_entry_status) 638 msleep(2500); 639 640 /* Dump the IdleMask before we add to the STB */ 641 amd_pmc_idlemask_read(pdev, pdev->dev, NULL); 642 643 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_CHECK); 644 if (rc) 645 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 646 } 647 648 static int amd_pmc_dump_data(struct amd_pmc_dev *pdev) 649 { 650 if (pdev->cpu_id == AMD_CPU_ID_PCO) 651 return -ENODEV; 652 653 return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, false); 654 } 655 656 static void amd_pmc_s2idle_restore(void) 657 { 658 struct amd_pmc_dev *pdev = &pmc; 659 int rc; 660 u8 msg; 661 662 msg = amd_pmc_get_os_hint(pdev); 663 rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, false); 664 if (rc) 665 dev_err(pdev->dev, "resume failed: %d\n", rc); 666 667 /* Let SMU know that we are looking for stats */ 668 amd_pmc_dump_data(pdev); 669 670 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_RESTORE); 671 if (rc) 672 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 673 674 /* Notify on failed entry */ 675 amd_pmc_validate_deepest(pdev); 676 677 amd_pmc_process_restore_quirks(pdev); 678 } 679 680 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = { 681 .prepare = amd_pmc_s2idle_prepare, 682 .check = amd_pmc_s2idle_check, 683 .restore = amd_pmc_s2idle_restore, 684 }; 685 686 static int amd_pmc_suspend_handler(struct device *dev) 687 { 688 struct amd_pmc_dev *pdev = dev_get_drvdata(dev); 689 int rc; 690 691 /* 692 * Must be called only from the same set of dev_pm_ops handlers 693 * as i8042_pm_suspend() is called: currently just from .suspend. 694 */ 695 if (pdev->disable_8042_wakeup && !disable_workarounds) { 696 rc = amd_pmc_wa_irq1(pdev); 697 if (rc) { 698 dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc); 699 return rc; 700 } 701 } 702 703 return 0; 704 } 705 706 static const struct dev_pm_ops amd_pmc_pm = { 707 .suspend = amd_pmc_suspend_handler, 708 }; 709 710 static const struct pci_device_id pmc_pci_ids[] = { 711 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) }, 712 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) }, 713 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) }, 714 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) }, 715 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) }, 716 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) }, 717 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) }, 718 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) }, 719 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) }, 720 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) }, 721 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) }, 722 { } 723 }; 724 725 static int amd_pmc_probe(struct platform_device *pdev) 726 { 727 struct amd_pmc_dev *dev = &pmc; 728 struct pci_dev *rdev; 729 u32 base_addr_lo, base_addr_hi; 730 u64 base_addr; 731 int err; 732 u32 val; 733 734 dev->dev = &pdev->dev; 735 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); 736 if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) { 737 err = -ENODEV; 738 goto err_pci_dev_put; 739 } 740 741 dev->cpu_id = rdev->device; 742 if (dev->cpu_id == AMD_CPU_ID_SP || dev->cpu_id == AMD_CPU_ID_SHP) { 743 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n"); 744 err = -ENODEV; 745 goto err_pci_dev_put; 746 } 747 748 dev->rdev = rdev; 749 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val); 750 if (err) { 751 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO); 752 err = pcibios_err_to_errno(err); 753 goto err_pci_dev_put; 754 } 755 756 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK; 757 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val); 758 if (err) { 759 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI); 760 err = pcibios_err_to_errno(err); 761 goto err_pci_dev_put; 762 } 763 764 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK; 765 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo); 766 767 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET, 768 AMD_PMC_MAPPING_SIZE); 769 if (!dev->regbase) { 770 err = -ENOMEM; 771 goto err_pci_dev_put; 772 } 773 774 err = devm_mutex_init(dev->dev, &dev->lock); 775 if (err) 776 goto err_pci_dev_put; 777 778 /* Get num of IP blocks within the SoC */ 779 amd_pmc_get_ip_info(dev); 780 781 platform_set_drvdata(pdev, dev); 782 if (IS_ENABLED(CONFIG_SUSPEND)) { 783 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops); 784 if (err) 785 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n"); 786 if (!disable_workarounds) 787 amd_pmc_quirks_init(dev); 788 } 789 790 amd_pmc_dbgfs_register(dev); 791 err = amd_stb_s2d_init(dev); 792 if (err) 793 goto err_pci_dev_put; 794 795 if (IS_ENABLED(CONFIG_AMD_MP2_STB)) 796 amd_mp2_stb_init(dev); 797 pm_report_max_hw_sleep(U64_MAX); 798 return 0; 799 800 err_pci_dev_put: 801 pci_dev_put(rdev); 802 return err; 803 } 804 805 static void amd_pmc_remove(struct platform_device *pdev) 806 { 807 struct amd_pmc_dev *dev = platform_get_drvdata(pdev); 808 809 if (IS_ENABLED(CONFIG_SUSPEND)) 810 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops); 811 amd_pmc_dbgfs_unregister(dev); 812 pci_dev_put(dev->rdev); 813 if (IS_ENABLED(CONFIG_AMD_MP2_STB)) 814 amd_mp2_stb_deinit(dev); 815 } 816 817 static const struct acpi_device_id amd_pmc_acpi_ids[] = { 818 {"AMDI0005", 0}, 819 {"AMDI0006", 0}, 820 {"AMDI0007", 0}, 821 {"AMDI0008", 0}, 822 {"AMDI0009", 0}, 823 {"AMDI000A", 0}, 824 {"AMDI000B", 0}, 825 {"AMD0004", 0}, 826 {"AMD0005", 0}, 827 { } 828 }; 829 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids); 830 831 static struct platform_driver amd_pmc_driver = { 832 .driver = { 833 .name = "amd_pmc", 834 .acpi_match_table = amd_pmc_acpi_ids, 835 .dev_groups = pmc_groups, 836 .pm = pm_sleep_ptr(&amd_pmc_pm), 837 }, 838 .probe = amd_pmc_probe, 839 .remove = amd_pmc_remove, 840 }; 841 module_platform_driver(amd_pmc_driver); 842 843 MODULE_LICENSE("GPL v2"); 844 MODULE_DESCRIPTION("AMD PMC Driver"); 845