1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * AMD SoC Power Management Controller Driver 4 * 5 * Copyright (c) 2020, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/acpi.h> 14 #include <linux/array_size.h> 15 #include <linux/bitfield.h> 16 #include <linux/bits.h> 17 #include <linux/debugfs.h> 18 #include <linux/delay.h> 19 #include <linux/dmi.h> 20 #include <linux/io.h> 21 #include <linux/iopoll.h> 22 #include <linux/limits.h> 23 #include <linux/module.h> 24 #include <linux/pci.h> 25 #include <linux/platform_device.h> 26 #include <linux/rtc.h> 27 #include <linux/serio.h> 28 #include <linux/suspend.h> 29 #include <linux/seq_file.h> 30 #include <linux/uaccess.h> 31 32 #include <asm/amd/node.h> 33 34 #include "pmc.h" 35 36 static const struct amd_pmc_bit_map soc15_ip_blk_v3[] = { 37 {"VDDCR", BIT(0)}, 38 {"VDDCR_LP", BIT(1)}, 39 {"LSOCV", BIT(2)}, 40 {"DISPLAY", BIT(3)}, 41 {"VCN", BIT(4)}, 42 {"JPEG", BIT(5)}, 43 {"UMSCH", BIT(6)}, 44 {"VPE", BIT(7)}, 45 {"MPM", BIT(8)}, 46 {"NPU", BIT(9)}, 47 {"USB_HC0", BIT(10)}, 48 {"eUSB_HC0", BIT(11)}, 49 {"RT0_ADP_HC1", BIT(12)}, 50 {"RT1_ADP_HC1", BIT(13)}, 51 {"RT2_ADP_HC2", BIT(14)}, 52 {"USB4_RT0", BIT(15)}, 53 {"USB4_RT1", BIT(16)}, 54 {"USB4-RT2", BIT(17)}, 55 {"LAPIC", BIT(18)}, 56 }; 57 58 static const struct amd_pmc_bit_map soc15_ip_blk_v2[] = { 59 {"DISPLAY", BIT(0)}, 60 {"CPU", BIT(1)}, 61 {"GFX", BIT(2)}, 62 {"VDD", BIT(3)}, 63 {"VDD_CCX", BIT(4)}, 64 {"ACP", BIT(5)}, 65 {"VCN_0", BIT(6)}, 66 {"VCN_1", BIT(7)}, 67 {"ISP", BIT(8)}, 68 {"NBIO", BIT(9)}, 69 {"DF", BIT(10)}, 70 {"USB3_0", BIT(11)}, 71 {"USB3_1", BIT(12)}, 72 {"LAPIC", BIT(13)}, 73 {"USB3_2", BIT(14)}, 74 {"USB4_RT0", BIT(15)}, 75 {"USB4_RT1", BIT(16)}, 76 {"USB4_0", BIT(17)}, 77 {"USB4_1", BIT(18)}, 78 {"MPM", BIT(19)}, 79 {"JPEG_0", BIT(20)}, 80 {"JPEG_1", BIT(21)}, 81 {"IPU", BIT(22)}, 82 {"UMSCH", BIT(23)}, 83 {"VPE", BIT(24)}, 84 }; 85 86 static const struct amd_pmc_bit_map soc15_ip_blk[] = { 87 {"DISPLAY", BIT(0)}, 88 {"CPU", BIT(1)}, 89 {"GFX", BIT(2)}, 90 {"VDD", BIT(3)}, 91 {"ACP", BIT(4)}, 92 {"VCN", BIT(5)}, 93 {"ISP", BIT(6)}, 94 {"NBIO", BIT(7)}, 95 {"DF", BIT(8)}, 96 {"USB3_0", BIT(9)}, 97 {"USB3_1", BIT(10)}, 98 {"LAPIC", BIT(11)}, 99 {"USB3_2", BIT(12)}, 100 {"USB3_3", BIT(13)}, 101 {"USB3_4", BIT(14)}, 102 {"USB4_0", BIT(15)}, 103 {"USB4_1", BIT(16)}, 104 {"MPM", BIT(17)}, 105 {"JPEG", BIT(18)}, 106 {"IPU", BIT(19)}, 107 {"UMSCH", BIT(20)}, 108 {"VPE", BIT(21)}, 109 }; 110 111 /* CPU info structures for different SoC variants */ 112 static const struct amd_pmc_cpu_info amd_pco_cpu_info = { 113 .smu_msg = AMD_PMC_REGISTER_MESSAGE, 114 .smu_arg = AMD_PMC_REGISTER_ARGUMENT, 115 .smu_rsp = AMD_PMC_REGISTER_RESPONSE, 116 .num_ips = 12, 117 .ips_ptr = soc15_ip_blk, 118 .os_hint = MSG_OS_HINT_PCO, 119 }; 120 121 static const struct amd_pmc_cpu_info amd_czn_cpu_info = { 122 .smu_msg = AMD_PMC_REGISTER_MESSAGE, 123 .smu_arg = AMD_PMC_REGISTER_ARGUMENT, 124 .smu_rsp = AMD_PMC_REGISTER_RESPONSE, 125 .num_ips = 12, 126 .scratch_reg = AMD_PMC_SCRATCH_REG_CZN, 127 .ips_ptr = soc15_ip_blk, 128 .os_hint = MSG_OS_HINT_RN, 129 }; 130 131 static const struct amd_pmc_cpu_info amd_vg_cpu_info = { 132 .smu_msg = AMD_PMC_REGISTER_MESSAGE, 133 .smu_arg = AMD_PMC_REGISTER_ARGUMENT, 134 .smu_rsp = AMD_PMC_REGISTER_RESPONSE, 135 .num_ips = 12, 136 .ips_ptr = soc15_ip_blk, 137 .os_hint = MSG_OS_HINT_RN, 138 }; 139 140 static const struct amd_pmc_cpu_info amd_yc_cpu_info = { 141 .smu_msg = AMD_PMC_REGISTER_MESSAGE, 142 .smu_arg = AMD_PMC_REGISTER_ARGUMENT, 143 .smu_rsp = AMD_PMC_REGISTER_RESPONSE, 144 .num_ips = 12, 145 .scratch_reg = AMD_PMC_SCRATCH_REG_YC, 146 .ips_ptr = soc15_ip_blk, 147 .os_hint = MSG_OS_HINT_RN, 148 }; 149 150 static const struct amd_pmc_cpu_info amd_ps_cpu_info = { 151 .smu_msg = AMD_PMC_REGISTER_MESSAGE, 152 .smu_arg = AMD_PMC_REGISTER_ARGUMENT, 153 .smu_rsp = AMD_PMC_REGISTER_RESPONSE, 154 .num_ips = 21, 155 .scratch_reg = AMD_PMC_SCRATCH_REG_YC, 156 .ips_ptr = soc15_ip_blk, 157 .os_hint = MSG_OS_HINT_RN, 158 }; 159 160 static const struct amd_pmc_cpu_info amd_1ah_cpu_info = { 161 .smu_msg = AMD_PMC_REGISTER_MSG_1AH_20H, 162 .smu_arg = AMD_PMC_REGISTER_ARGUMENT, 163 .smu_rsp = AMD_PMC_REGISTER_RESPONSE, 164 .num_ips = ARRAY_SIZE(soc15_ip_blk), 165 .scratch_reg = AMD_PMC_SCRATCH_REG_1AH, 166 .ips_ptr = soc15_ip_blk, 167 .os_hint = MSG_OS_HINT_RN, 168 }; 169 170 static const struct amd_pmc_cpu_info amd_1ah_m70_cpu_info = { 171 .smu_msg = AMD_PMC_REGISTER_MSG_1AH_20H, 172 .smu_arg = AMD_PMC_REGISTER_ARGUMENT, 173 .smu_rsp = AMD_PMC_REGISTER_RESPONSE, 174 .num_ips = ARRAY_SIZE(soc15_ip_blk_v2), 175 .scratch_reg = AMD_PMC_SCRATCH_REG_1AH, 176 .ips_ptr = soc15_ip_blk_v2, 177 .os_hint = MSG_OS_HINT_RN, 178 }; 179 180 static const struct amd_pmc_cpu_info amd_1ah_m80_cpu_info = { 181 .smu_msg = AMD_PMC_REGISTER_MSG_1AH_80H, 182 .smu_arg = AMD_PMC_REGISTER_ARG_1AH_80H, 183 .smu_rsp = AMD_PMC_REGISTER_RSP_1AH_80H, 184 .num_ips = ARRAY_SIZE(soc15_ip_blk_v3), 185 .scratch_reg = AMD_PMC_SCRATCH_REG_1AH, 186 .ips_ptr = soc15_ip_blk_v3, 187 .os_hint = MSG_OS_HINT_RN, 188 }; 189 190 static const struct pci_device_id pmc_pci_ids[] = { 191 { PCI_DEVICE_DATA(AMD, CPU_ID_PCO, &amd_pco_cpu_info) }, 192 { PCI_DEVICE_DATA(AMD, CPU_ID_CZN, &amd_czn_cpu_info) }, 193 { PCI_DEVICE_DATA(AMD, CPU_ID_VG, &amd_vg_cpu_info) }, 194 { PCI_DEVICE_DATA(AMD, CPU_ID_YC, &amd_yc_cpu_info) }, 195 { PCI_DEVICE_DATA(AMD, CPU_ID_CB, &amd_yc_cpu_info) }, 196 { PCI_DEVICE_DATA(AMD, CPU_ID_PS, &amd_ps_cpu_info) }, 197 { PCI_DEVICE_DATA(AMD, CPU_ID_SP, NULL) }, 198 { PCI_DEVICE_DATA(AMD, CPU_ID_SHP, NULL) }, 199 { PCI_DEVICE_DATA(AMD, 1AH_M20H_ROOT, NULL) }, 200 { PCI_DEVICE_DATA(AMD, 1AH_M60H_ROOT, NULL) }, 201 { PCI_DEVICE_DATA(AMD, 1AH_M80H_ROOT, &amd_1ah_m80_cpu_info) }, 202 { } 203 }; 204 205 static bool disable_workarounds; 206 module_param(disable_workarounds, bool, 0644); 207 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs"); 208 209 static int delay_suspend = -1; 210 module_param(delay_suspend, int, 0644); 211 MODULE_PARM_DESC(delay_suspend, 212 "Delays s2idle by 2.5 seconds to work around buggy ECs, often causing keyboard issues after suspend. 0: don't delay, 1: do delay, -1 (default): let amd_pmc decide. If you need this please report this to: platform-driver-x86@vger.kernel.org"); 213 214 static struct amd_pmc_dev pmc; 215 216 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset) 217 { 218 return ioread32(dev->regbase + reg_offset); 219 } 220 221 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val) 222 { 223 iowrite32(val, dev->regbase + reg_offset); 224 } 225 226 static int amd_pmc_set_cpu_info(struct amd_pmc_dev *dev, struct pci_dev *rdev) 227 { 228 const struct pci_device_id *id; 229 230 id = pci_match_id(pmc_pci_ids, rdev); 231 if (!id) 232 return -ENODEV; 233 234 dev->cpu_id = rdev->device; 235 236 if (id->driver_data) { 237 dev->cpu_info = (const struct amd_pmc_cpu_info *)id->driver_data; 238 return 0; 239 } 240 241 /* Special case: 1Ah M20H/M60H needs x86_model detection */ 242 switch (dev->cpu_id) { 243 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: 244 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: 245 if (boot_cpu_data.x86_model == 0x70) 246 dev->cpu_info = &amd_1ah_m70_cpu_info; 247 else 248 dev->cpu_info = &amd_1ah_cpu_info; 249 break; 250 case AMD_CPU_ID_SP: 251 case AMD_CPU_ID_SHP: 252 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n"); 253 return -ENODEV; 254 default: 255 dev_err(dev->dev, "Unknown CPU ID: 0x%x\n", dev->cpu_id); 256 return -ENODEV; 257 } 258 259 return 0; 260 } 261 262 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev) 263 { 264 if (dev->cpu_id == AMD_CPU_ID_PCO) { 265 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n"); 266 return -EINVAL; 267 } 268 269 /* Get Active devices list from SMU */ 270 if (!dev->active_ips) 271 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, true); 272 273 /* Get dram address */ 274 if (!dev->smu_virt_addr) { 275 u32 phys_addr_low, phys_addr_hi; 276 u64 smu_phys_addr; 277 278 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, true); 279 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, true); 280 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low); 281 282 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, 283 sizeof(struct smu_metrics)); 284 if (!dev->smu_virt_addr) 285 return -ENOMEM; 286 } 287 288 memset_io(dev->smu_virt_addr, 0, sizeof(struct smu_metrics)); 289 290 /* Start the logging */ 291 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, false); 292 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, false); 293 294 return 0; 295 } 296 297 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table) 298 { 299 int rc; 300 301 if (!pdev->smu_virt_addr) { 302 rc = amd_pmc_setup_smu_logging(pdev); 303 if (rc) 304 return rc; 305 } 306 307 if (pdev->cpu_id == AMD_CPU_ID_PCO) 308 return -ENODEV; 309 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics)); 310 return 0; 311 } 312 313 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev) 314 { 315 struct smu_metrics table; 316 317 if (get_metrics_table(pdev, &table)) 318 return; 319 320 if (!table.s0i3_last_entry_status) 321 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n"); 322 pm_report_hw_sleep_time(table.s0i3_last_entry_status ? 323 table.timein_s0i3_lastcapture : 0); 324 } 325 326 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev) 327 { 328 int rc; 329 u32 val; 330 331 if (dev->cpu_id == AMD_CPU_ID_PCO) 332 return -ENODEV; 333 334 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, true); 335 if (rc) 336 return rc; 337 338 dev->smu_program = (val >> 24) & GENMASK(7, 0); 339 dev->major = (val >> 16) & GENMASK(7, 0); 340 dev->minor = (val >> 8) & GENMASK(7, 0); 341 dev->rev = (val >> 0) & GENMASK(7, 0); 342 343 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n", 344 dev->smu_program, dev->major, dev->minor, dev->rev); 345 346 return 0; 347 } 348 349 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr, 350 char *buf) 351 { 352 struct amd_pmc_dev *dev = dev_get_drvdata(d); 353 int rc; 354 355 if (!dev->major) { 356 rc = amd_pmc_get_smu_version(dev); 357 if (rc) 358 return rc; 359 } 360 return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev); 361 } 362 363 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr, 364 char *buf) 365 { 366 struct amd_pmc_dev *dev = dev_get_drvdata(d); 367 int rc; 368 369 if (!dev->major) { 370 rc = amd_pmc_get_smu_version(dev); 371 if (rc) 372 return rc; 373 } 374 return sysfs_emit(buf, "%u\n", dev->smu_program); 375 } 376 377 static DEVICE_ATTR_RO(smu_fw_version); 378 static DEVICE_ATTR_RO(smu_program); 379 380 static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 381 { 382 struct device *dev = kobj_to_dev(kobj); 383 struct amd_pmc_dev *pdev = dev_get_drvdata(dev); 384 385 if (pdev->cpu_id == AMD_CPU_ID_PCO) 386 return 0; 387 return 0444; 388 } 389 390 static struct attribute *pmc_attrs[] = { 391 &dev_attr_smu_fw_version.attr, 392 &dev_attr_smu_program.attr, 393 NULL, 394 }; 395 396 static struct attribute_group pmc_attr_group = { 397 .attrs = pmc_attrs, 398 .is_visible = pmc_attr_is_visible, 399 }; 400 401 static const struct attribute_group *pmc_groups[] = { 402 &pmc_attr_group, 403 NULL, 404 }; 405 406 static int smu_fw_info_show(struct seq_file *s, void *unused) 407 { 408 struct amd_pmc_dev *dev = s->private; 409 struct smu_metrics table; 410 int idx; 411 412 if (get_metrics_table(dev, &table)) 413 return -EINVAL; 414 415 seq_puts(s, "\n=== SMU Statistics ===\n"); 416 seq_printf(s, "Table Version: %d\n", table.table_version); 417 seq_printf(s, "Hint Count: %d\n", table.hint_count); 418 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" : 419 "Unknown/Fail"); 420 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture); 421 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture); 422 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n", 423 table.timeto_resume_to_os_lastcapture); 424 425 seq_puts(s, "\n=== Active time (in us) ===\n"); 426 for (idx = 0 ; idx < dev->cpu_info->num_ips ; idx++) { 427 if (dev->cpu_info->ips_ptr[idx].bit_mask & dev->active_ips) 428 seq_printf(s, "%-8s : %lld\n", dev->cpu_info->ips_ptr[idx].name, 429 table.timecondition_notmet_lastcapture[idx]); 430 } 431 432 return 0; 433 } 434 DEFINE_SHOW_ATTRIBUTE(smu_fw_info); 435 436 static int s0ix_stats_show(struct seq_file *s, void *unused) 437 { 438 struct amd_pmc_dev *dev = s->private; 439 u64 entry_time, exit_time, residency; 440 441 /* Use FCH registers to get the S0ix stats */ 442 if (!dev->fch_virt_addr) { 443 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW; 444 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH; 445 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo); 446 447 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE); 448 if (!dev->fch_virt_addr) 449 return -ENOMEM; 450 } 451 452 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET); 453 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET); 454 455 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET); 456 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET); 457 458 /* It's in 48MHz. We need to convert it */ 459 residency = exit_time - entry_time; 460 do_div(residency, 48); 461 462 seq_puts(s, "=== S0ix statistics ===\n"); 463 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time); 464 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time); 465 seq_printf(s, "Residency Time: %lld\n", residency); 466 467 return 0; 468 } 469 DEFINE_SHOW_ATTRIBUTE(s0ix_stats); 470 471 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev, 472 struct seq_file *s) 473 { 474 u32 val; 475 int rc; 476 477 /* we haven't yet read SMU version */ 478 if (pdev->cpu_id == AMD_CPU_ID_CZN) { 479 if (!pdev->major) { 480 rc = amd_pmc_get_smu_version(pdev); 481 if (rc) 482 return rc; 483 } 484 if (!(pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37))) 485 return -EINVAL; 486 } 487 488 if (!pdev->cpu_info->scratch_reg) 489 return -EINVAL; 490 491 val = amd_pmc_reg_read(pdev, pdev->cpu_info->scratch_reg); 492 493 if (dev) 494 pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val); 495 496 if (s) 497 seq_printf(s, "SMU idlemask : 0x%x\n", val); 498 499 return 0; 500 } 501 502 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused) 503 { 504 return amd_pmc_idlemask_read(s->private, NULL, s); 505 } 506 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask); 507 508 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev) 509 { 510 debugfs_remove_recursive(dev->dbgfs_dir); 511 } 512 513 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) 514 { 515 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL); 516 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev, 517 &smu_fw_info_fops); 518 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev, 519 &s0ix_stats_fops); 520 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev, 521 &amd_pmc_idlemask_fops); 522 } 523 524 static char *amd_pmc_get_msg_port(struct amd_pmc_dev *dev) 525 { 526 switch (dev->msg_port) { 527 case MSG_PORT_PMC: 528 return "PMC"; 529 case MSG_PORT_S2D: 530 return "S2D"; 531 default: 532 return "Invalid message port"; 533 } 534 } 535 536 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev) 537 { 538 u32 value, message, argument, response; 539 540 if (dev->msg_port == MSG_PORT_S2D) { 541 message = dev->stb_arg.msg; 542 argument = dev->stb_arg.arg; 543 response = dev->stb_arg.resp; 544 } else { 545 message = dev->cpu_info->smu_msg; 546 argument = dev->cpu_info->smu_arg; 547 response = dev->cpu_info->smu_rsp; 548 } 549 550 value = amd_pmc_reg_read(dev, response); 551 dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", amd_pmc_get_msg_port(dev), value); 552 553 value = amd_pmc_reg_read(dev, argument); 554 dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", amd_pmc_get_msg_port(dev), value); 555 556 value = amd_pmc_reg_read(dev, message); 557 dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", amd_pmc_get_msg_port(dev), value); 558 } 559 560 int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret) 561 { 562 int rc; 563 u32 val, message, argument, response; 564 565 guard(mutex)(&dev->lock); 566 567 if (dev->msg_port == MSG_PORT_S2D) { 568 message = dev->stb_arg.msg; 569 argument = dev->stb_arg.arg; 570 response = dev->stb_arg.resp; 571 } else { 572 message = dev->cpu_info->smu_msg; 573 argument = dev->cpu_info->smu_arg; 574 response = dev->cpu_info->smu_rsp; 575 } 576 577 /* Wait until we get a valid response */ 578 rc = readx_poll_timeout(ioread32, dev->regbase + response, 579 val, val != 0, PMC_MSG_DELAY_MIN_US, 580 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 581 if (rc) { 582 dev_err(dev->dev, "failed to talk to SMU\n"); 583 return rc; 584 } 585 586 /* Write zero to response register */ 587 amd_pmc_reg_write(dev, response, 0); 588 589 /* Write argument into response register */ 590 amd_pmc_reg_write(dev, argument, arg); 591 592 /* Write message ID to message ID register */ 593 amd_pmc_reg_write(dev, message, msg); 594 595 /* Wait until we get a valid response */ 596 rc = readx_poll_timeout(ioread32, dev->regbase + response, 597 val, val != 0, PMC_MSG_DELAY_MIN_US, 598 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); 599 if (rc) { 600 dev_err(dev->dev, "SMU response timed out\n"); 601 return rc; 602 } 603 604 switch (val) { 605 case AMD_PMC_RESULT_OK: 606 if (ret) { 607 /* PMFW may take longer time to return back the data */ 608 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US); 609 *data = amd_pmc_reg_read(dev, argument); 610 } 611 break; 612 case AMD_PMC_RESULT_CMD_REJECT_BUSY: 613 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val); 614 rc = -EBUSY; 615 break; 616 case AMD_PMC_RESULT_CMD_UNKNOWN: 617 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val); 618 rc = -EINVAL; 619 break; 620 case AMD_PMC_RESULT_CMD_REJECT_PREREQ: 621 case AMD_PMC_RESULT_FAILED: 622 default: 623 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val); 624 rc = -EIO; 625 break; 626 } 627 628 amd_pmc_dump_registers(dev); 629 return rc; 630 } 631 632 static int amd_pmc_wa_irq1(struct amd_pmc_dev *pdev) 633 { 634 struct device *d; 635 636 d = bus_find_device_by_name(&serio_bus, NULL, "serio0"); 637 if (!d) 638 return 0; 639 if (device_may_wakeup(d)) { 640 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n"); 641 disable_irq_wake(1); 642 device_set_wakeup_enable(d, false); 643 } 644 put_device(d); 645 646 return 0; 647 } 648 649 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg) 650 { 651 struct rtc_device *rtc_device; 652 time64_t then, now, duration; 653 struct rtc_wkalrm alarm; 654 struct rtc_time tm; 655 int rc; 656 657 /* we haven't yet read SMU version */ 658 if (!pdev->major) { 659 rc = amd_pmc_get_smu_version(pdev); 660 if (rc) 661 return rc; 662 } 663 664 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53)) 665 return 0; 666 667 rtc_device = rtc_class_open("rtc0"); 668 if (!rtc_device) 669 return 0; 670 rc = rtc_read_next_alarm(rtc_device, &alarm); 671 if (rc) { 672 if (rc == -ENOENT) 673 dev_dbg(pdev->dev, "no alarm pending\n"); 674 return rc == -ENOENT ? 0 : rc; 675 } 676 if (!alarm.enabled) { 677 dev_dbg(pdev->dev, "alarm not enabled\n"); 678 return 0; 679 } 680 rc = rtc_read_time(rtc_device, &tm); 681 if (rc) 682 return rc; 683 then = rtc_tm_to_time64(&alarm.time); 684 now = rtc_tm_to_time64(&tm); 685 duration = then-now; 686 687 /* in the past */ 688 if (then < now) 689 return 0; 690 691 /* will be stored in upper 16 bits of s0i3 hint argument, 692 * so timer wakeup from s0i3 is limited to ~18 hours or less 693 */ 694 if (duration <= 4 || duration > U16_MAX) 695 return -EINVAL; 696 697 *arg |= (duration << 16); 698 rc = rtc_alarm_irq_enable(rtc_device, 0); 699 pm_pr_dbg("wakeup timer programmed for %lld seconds\n", duration); 700 701 return rc; 702 } 703 704 static bool amd_pmc_intermediate_wakeup_need_delay(struct amd_pmc_dev *pdev) 705 { 706 /* 707 * Starting a new HW sleep cycle right after waking from one 708 * can cause electrical problems triggering the over voltage protection. 709 * That is avoided by delaying the next suspend a bit, see also 710 * https://lore.kernel.org/all/20250414162446.3853194-1-superm1@kernel.org/ 711 */ 712 struct smu_metrics table; 713 714 return get_metrics_table(pdev, &table) == 0 && table.s0i3_last_entry_status; 715 } 716 717 static bool amd_pmc_want_suspend_delay(struct amd_pmc_dev *pdev) 718 { 719 /* 720 * intermediate_wakeup implies that the machine didn't get to deepest sleep 721 * state before - otherwise this function isn't called in amd_pmc_s2idle_check() 722 * because amd_pmc_intermediate_wakeup_need_delay() returns true first. 723 * On some IdeaPads that happens when charging, because the EC seems 724 * to send lots of messages then that wake the machine. 725 * 726 * But even in that case, the sleep here is necessary (on those IdeaPads), 727 * otherwise they wake up completely (resume) after a few seconds. 728 * So this variable is only used to avoid spamming dmesg on each 729 * intermediate wakeup. 730 */ 731 bool intermediate_wakeup = !pdev->is_first_check_after_suspend; 732 733 /* 734 * Some Lenovo Laptops (like different IdeaPad 3 Slims) need some 735 * me-time before sleeping or they get uncooperative after waking 736 * up and don't send events for keyboard and lid switch anymore. 737 * 738 * Unfortunately this doesn't entirely fix the problem: It can still 739 * happen when resuming with a timer (wakealarm), but at least the 740 * more common usecases (wakeup by opening lid or pressing a key) 741 * work fine with this workaround. 742 * 743 * See https://bugzilla.kernel.org/show_bug.cgi?id=221383 744 */ 745 if (amd_pmc_quirk_need_suspend_delay(pdev)) { 746 /* 747 * delay_suspend=1 force-enables this, otherwise it can be 748 * disabled with disable_workarounds or delay_suspend=0 749 */ 750 if (delay_suspend == 1 || (delay_suspend == -1 && !disable_workarounds)) { 751 if (!intermediate_wakeup) 752 dev_info(pdev->dev, "Delaying suspend by 2.5s to avoid platform bug\n"); 753 return true; 754 } 755 if (!intermediate_wakeup) 756 dev_info(pdev->dev, "Not delaying suspend because of module parameter, even though your device is assumed to need it!\n"); 757 } else if (delay_suspend == 1) { 758 if (!intermediate_wakeup) 759 dev_info(pdev->dev, "Delaying suspend by 2.5s because delay_suspend=1. If this solves problems on your machine, please report this whole line to: platform-driver-x86@vger.kernel.org so it can be automatically detected as affected in the future. System Vendor: \"%s\" Product Name: \"%s\" Product Family: \"%s\" Board Vendor: \"%s\" Board Name: \"%s\"\n", 760 dmi_get_system_info(DMI_SYS_VENDOR) ?: "(Unknown)", 761 dmi_get_system_info(DMI_PRODUCT_NAME) ?: "(Unknown)", 762 dmi_get_system_info(DMI_PRODUCT_FAMILY) ?: "(Unknown)", 763 dmi_get_system_info(DMI_BOARD_VENDOR) ?: "(Unknown)", 764 dmi_get_system_info(DMI_BOARD_NAME) ?: "(Unknown)"); 765 return true; 766 } 767 return false; 768 } 769 770 static void amd_pmc_s2idle_prepare(void) 771 { 772 struct amd_pmc_dev *pdev = &pmc; 773 int rc; 774 u32 arg = 1; 775 776 /* Reset this variable because this is a fresh suspend */ 777 pdev->is_first_check_after_suspend = true; 778 779 /* Reset and Start SMU logging - to monitor the s0i3 stats */ 780 amd_pmc_setup_smu_logging(pdev); 781 782 /* Activate CZN specific platform bug workarounds */ 783 if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) { 784 rc = amd_pmc_verify_czn_rtc(pdev, &arg); 785 if (rc) { 786 dev_err(pdev->dev, "failed to set RTC: %d\n", rc); 787 return; 788 } 789 } 790 791 rc = amd_pmc_send_cmd(pdev, arg, NULL, pdev->cpu_info->os_hint, false); 792 if (rc) { 793 dev_err(pdev->dev, "suspend failed: %d\n", rc); 794 return; 795 } 796 797 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_PREPARE); 798 if (rc) 799 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 800 } 801 802 static void amd_pmc_s2idle_check(void) 803 { 804 struct amd_pmc_dev *pdev = &pmc; 805 int rc; 806 807 if (amd_pmc_intermediate_wakeup_need_delay(pdev) || 808 amd_pmc_want_suspend_delay(pdev)) 809 msleep(2500); 810 811 /* Dump the IdleMask before we add to the STB */ 812 amd_pmc_idlemask_read(pdev, pdev->dev, NULL); 813 814 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_CHECK); 815 if (rc) 816 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 817 818 /* remember that first check after suspend is done (until next prepare) */ 819 pdev->is_first_check_after_suspend = false; 820 } 821 822 static int amd_pmc_dump_data(struct amd_pmc_dev *pdev) 823 { 824 if (pdev->cpu_id == AMD_CPU_ID_PCO) 825 return -ENODEV; 826 827 return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, false); 828 } 829 830 static void amd_pmc_s2idle_restore(void) 831 { 832 struct amd_pmc_dev *pdev = &pmc; 833 int rc; 834 835 rc = amd_pmc_send_cmd(pdev, 0, NULL, pdev->cpu_info->os_hint, false); 836 if (rc) 837 dev_err(pdev->dev, "resume failed: %d\n", rc); 838 839 /* Let SMU know that we are looking for stats */ 840 amd_pmc_dump_data(pdev); 841 842 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_RESTORE); 843 if (rc) 844 dev_err(pdev->dev, "error writing to STB: %d\n", rc); 845 846 /* Notify on failed entry */ 847 amd_pmc_validate_deepest(pdev); 848 849 amd_pmc_process_restore_quirks(pdev); 850 } 851 852 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = { 853 .prepare = amd_pmc_s2idle_prepare, 854 .check = amd_pmc_s2idle_check, 855 .restore = amd_pmc_s2idle_restore, 856 }; 857 858 static int amd_pmc_suspend_handler(struct device *dev) 859 { 860 struct amd_pmc_dev *pdev = dev_get_drvdata(dev); 861 int rc; 862 863 /* 864 * Must be called only from the same set of dev_pm_ops handlers 865 * as i8042_pm_suspend() is called: currently just from .suspend. 866 */ 867 if (pdev->disable_8042_wakeup && !disable_workarounds) { 868 rc = amd_pmc_wa_irq1(pdev); 869 if (rc) { 870 dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc); 871 return rc; 872 } 873 } 874 875 return 0; 876 } 877 878 static const struct dev_pm_ops amd_pmc_pm = { 879 .suspend = amd_pmc_suspend_handler, 880 }; 881 882 static int amd_pmc_probe(struct platform_device *pdev) 883 { 884 struct amd_pmc_dev *dev = &pmc; 885 struct pci_dev *rdev; 886 u32 base_addr_lo, base_addr_hi; 887 u64 base_addr; 888 int err; 889 u32 val; 890 891 dev->dev = &pdev->dev; 892 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); 893 if (!rdev) { 894 err = -ENODEV; 895 goto err_pci_dev_put; 896 } 897 898 err = amd_pmc_set_cpu_info(dev, rdev); 899 if (err) 900 goto err_pci_dev_put; 901 902 dev->rdev = rdev; 903 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val); 904 if (err) { 905 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO); 906 err = pcibios_err_to_errno(err); 907 goto err_pci_dev_put; 908 } 909 910 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK; 911 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val); 912 if (err) { 913 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI); 914 err = pcibios_err_to_errno(err); 915 goto err_pci_dev_put; 916 } 917 918 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK; 919 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo); 920 921 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET, 922 AMD_PMC_MAPPING_SIZE); 923 if (!dev->regbase) { 924 err = -ENOMEM; 925 goto err_pci_dev_put; 926 } 927 928 err = devm_mutex_init(dev->dev, &dev->lock); 929 if (err) 930 goto err_pci_dev_put; 931 932 platform_set_drvdata(pdev, dev); 933 if (IS_ENABLED(CONFIG_SUSPEND)) { 934 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops); 935 if (err) 936 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n"); 937 if (!disable_workarounds) 938 amd_pmc_quirks_init(dev); 939 } 940 941 amd_pmc_dbgfs_register(dev); 942 943 /* 944 * STB is an optional debug facility (enable_stb); a failure to set it 945 * up must not stop the rest of the driver - most importantly the s0i3 946 * LPS0 handler - from working, so treat it as non-fatal. 947 */ 948 err = amd_stb_s2d_init(dev); 949 if (err) 950 dev_warn(dev->dev, "STB initialization failed (%d), continuing without STB support\n", 951 err); 952 953 if (IS_ENABLED(CONFIG_AMD_MP2_STB)) 954 amd_mp2_stb_init(dev); 955 pm_report_max_hw_sleep(U64_MAX); 956 return 0; 957 958 err_pci_dev_put: 959 pci_dev_put(rdev); 960 return err; 961 } 962 963 static void amd_pmc_remove(struct platform_device *pdev) 964 { 965 struct amd_pmc_dev *dev = platform_get_drvdata(pdev); 966 967 if (IS_ENABLED(CONFIG_SUSPEND)) 968 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops); 969 amd_pmc_dbgfs_unregister(dev); 970 pci_dev_put(dev->rdev); 971 if (IS_ENABLED(CONFIG_AMD_MP2_STB)) 972 amd_mp2_stb_deinit(dev); 973 } 974 975 static const struct acpi_device_id amd_pmc_acpi_ids[] = { 976 {"AMDI0005", 0}, 977 {"AMDI0006", 0}, 978 {"AMDI0007", 0}, 979 {"AMDI0008", 0}, 980 {"AMDI0009", 0}, 981 {"AMDI000A", 0}, 982 {"AMDI000B", 0}, 983 {"AMDI000C", 0}, 984 {"AMD0004", 0}, 985 {"AMD0005", 0}, 986 { } 987 }; 988 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids); 989 990 static struct platform_driver amd_pmc_driver = { 991 .driver = { 992 .name = "amd_pmc", 993 .acpi_match_table = amd_pmc_acpi_ids, 994 .dev_groups = pmc_groups, 995 .pm = pm_sleep_ptr(&amd_pmc_pm), 996 }, 997 .probe = amd_pmc_probe, 998 .remove = amd_pmc_remove, 999 }; 1000 module_platform_driver(amd_pmc_driver); 1001 1002 MODULE_LICENSE("GPL v2"); 1003 MODULE_DESCRIPTION("AMD PMC Driver"); 1004