1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* 3 * Mellanox platform driver 4 * 5 * Copyright (C) 2016-2018 Mellanox Technologies 6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com> 7 */ 8 9 #include <linux/array_size.h> 10 #include <linux/bits.h> 11 #include <linux/device.h> 12 #include <linux/dmi.h> 13 #include <linux/i2c.h> 14 #include <linux/i2c-mux.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/pci.h> 18 #include <linux/platform_device.h> 19 #include <linux/platform_data/i2c-mux-reg.h> 20 #include <linux/platform_data/mlxreg.h> 21 #include <linux/reboot.h> 22 #include <linux/regmap.h> 23 24 #define MLX_PLAT_DEVICE_NAME "mlxplat" 25 26 /* LPC bus IO offsets */ 27 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000 28 #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500 29 #define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00 30 #define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01 31 #define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02 32 #define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03 33 #define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0x04 34 #define MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET 0x05 35 #define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06 36 #define MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET 0x07 37 #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08 38 #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET 0x09 39 #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a 40 #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b 41 #define MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET 0x17 42 #define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET 0x19 43 #define MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET 0x1b 44 #define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c 45 #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d 46 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e 47 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f 48 #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20 49 #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21 50 #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22 51 #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23 52 #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24 53 #define MLXPLAT_CPLD_LPC_REG_LED6_OFFSET 0x25 54 #define MLXPLAT_CPLD_LPC_REG_LED7_OFFSET 0x26 55 #define MLXPLAT_CPLD_LPC_REG_LED8_OFFSET 0x27 56 #define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a 57 #define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b 58 #define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0x2d 59 #define MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET 0x2c 60 #define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e 61 #define MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET 0x2f 62 #define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30 63 #define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31 64 #define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32 65 #define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33 66 #define MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE 0x34 67 #define MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET 0x35 68 #define MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET 0x36 69 #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 70 #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a 71 #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b 72 #define MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET 0x3c 73 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 74 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 75 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42 76 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43 77 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44 78 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45 79 #define MLXPLAT_CPLD_LPC_REG_GP3_OFFSET 0x46 80 #define MLXPLAT_CPLD_LPC_REG_BRD_OFFSET 0x47 81 #define MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET 0x48 82 #define MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET 0x49 83 #define MLXPLAT_CPLD_LPC_REG_GWP_OFFSET 0x4a 84 #define MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET 0x4b 85 #define MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET 0x4c 86 #define MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET 0x4e 87 #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 88 #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 89 #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 90 #define MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET 0x53 91 #define MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET 0x54 92 #define MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET 0x55 93 #define MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET 0x56 94 #define MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET 0x57 95 #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 96 #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59 97 #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a 98 #define MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET 0x5e 99 #define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64 100 #define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65 101 #define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66 102 #define MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET 0x6a 103 #define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0x70 104 #define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0x71 105 #define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0x72 106 #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 107 #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 108 #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a 109 #define MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET 0x8b 110 #define MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET 0x8c 111 #define MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET 0x8d 112 #define MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET 0x8e 113 #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET 0x8f 114 #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET 0x90 115 #define MLXPLAT_CPLD_LPC_REG_EROT_OFFSET 0x91 116 #define MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET 0x92 117 #define MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET 0x93 118 #define MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET 0x94 119 #define MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET 0x95 120 #define MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET 0x96 121 #define MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET 0x97 122 #define MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET 0x98 123 #define MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET 0x99 124 #define MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET 0x9a 125 #define MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET 0x9b 126 #define MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET 0x9c 127 #define MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET 0x9d 128 #define MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET 0x9e 129 #define MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET 0x9f 130 #define MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET 0xa0 131 #define MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET 0xa1 132 #define MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET 0xa2 133 #define MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET 0xa3 134 #define MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET 0xa4 135 #define MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET 0xa5 136 #define MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET 0xa6 137 #define MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET 0xa7 138 #define MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET 0xa8 139 #define MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET 0xa9 140 #define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa 141 #define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab 142 #define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2 143 #define MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET 0xb4 144 #define MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET 0xb5 145 #define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0xb6 146 #define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0xb7 147 #define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0xb8 148 #define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0xb9 149 #define MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET 0xba 150 #define MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET 0xbb 151 #define MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET 0xc1 152 #define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2 153 #define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3 154 #define MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET 0xc4 155 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7 156 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8 157 #define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9 158 #define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb 159 #define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd 160 #define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce 161 #define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf 162 #define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1 163 #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 164 #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 165 #define MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET 0xd9 166 #define MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET 0xdb 167 #define MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET 0xda 168 #define MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET 0xdc 169 #define MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET 0xdd 170 #define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde 171 #define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf 172 #define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0 173 #define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0xe1 174 #define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET 0xe2 175 #define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3 176 #define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4 177 #define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5 178 #define MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET 0xe6 179 #define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7 180 #define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8 181 #define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9 182 #define MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET 0xea 183 #define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xeb 184 #define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xec 185 #define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xed 186 #define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee 187 #define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef 188 #define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0 189 #define MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET 0xf1 190 #define MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET 0xf2 191 #define MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET 0xf3 192 #define MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET 0xf4 193 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5 194 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6 195 #define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7 196 #define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8 197 #define MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET 0xf9 198 #define MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET 0xfa 199 #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb 200 #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc 201 #define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd 202 #define MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET 0xfe 203 #define MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET 0xff 204 205 #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 206 207 #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL 208 #define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 209 MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET) | \ 210 MLXPLAT_CPLD_LPC_PIO_OFFSET) 211 #define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 212 MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET) | \ 213 MLXPLAT_CPLD_LPC_PIO_OFFSET) 214 #define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 215 MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET) | \ 216 MLXPLAT_CPLD_LPC_PIO_OFFSET) 217 #define MLXPLAT_CPLD_LPC_REG4 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 218 MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET) | \ 219 MLXPLAT_CPLD_LPC_PIO_OFFSET) 220 221 /* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */ 222 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04 223 #define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08 224 #define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08 225 #define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40 226 #define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 227 MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \ 228 MLXPLAT_CPLD_AGGR_FAN_MASK_DEF) 229 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01 230 #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04 231 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0) 232 #define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3) 233 #define MLXPLAT_CPLD_AGGR_MASK_DPU_BRD BIT(4) 234 #define MLXPLAT_CPLD_AGGR_MASK_DPU_CORE BIT(5) 235 #define MLXPLAT_CPLD_AGGR_MASK_MODULAR (MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \ 236 MLXPLAT_CPLD_AGGR_MASK_COMEX | \ 237 MLXPLAT_CPLD_AGGR_MASK_LC) 238 #define MLXPLAT_CPLD_AGGR_MASK_SMART_SW (MLXPLAT_CPLD_AGGR_MASK_COMEX | \ 239 MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \ 240 MLXPLAT_CPLD_AGGR_MASK_DPU_BRD | \ 241 MLXPLAT_CPLD_AGGR_MASK_DPU_CORE) 242 #define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0) 243 #define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1) 244 #define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2) 245 #define MLXPLAT_CPLD_AGGR_MASK_LC_SCRD BIT(3) 246 #define MLXPLAT_CPLD_AGGR_MASK_LC_SYNC BIT(4) 247 #define MLXPLAT_CPLD_AGGR_MASK_LC_ACT BIT(5) 248 #define MLXPLAT_CPLD_AGGR_MASK_LC_SDWN BIT(6) 249 #define MLXPLAT_CPLD_AGGR_MASK_LC_LOW (MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT | \ 250 MLXPLAT_CPLD_AGGR_MASK_LC_RDY | \ 251 MLXPLAT_CPLD_AGGR_MASK_LC_PG | \ 252 MLXPLAT_CPLD_AGGR_MASK_LC_SCRD | \ 253 MLXPLAT_CPLD_AGGR_MASK_LC_SYNC | \ 254 MLXPLAT_CPLD_AGGR_MASK_LC_ACT | \ 255 MLXPLAT_CPLD_AGGR_MASK_LC_SDWN) 256 #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 257 #define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2) 258 #define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT GENMASK(5, 4) 259 #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) 260 #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) 261 #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) 262 #define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0) 263 #define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0) 264 #define MLXPLAT_CPLD_PSU_XDR_MASK GENMASK(7, 0) 265 #define MLXPLAT_CPLD_PWR_XDR_MASK GENMASK(7, 0) 266 #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0) 267 #define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0) 268 #define MLXPLAT_CPLD_ASIC_XDR_MASK GENMASK(3, 0) 269 #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6, 0) 270 #define MLXPLAT_CPLD_FAN_XDR_MASK GENMASK(7, 0) 271 #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4) 272 #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) 273 #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) 274 #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) 275 #define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) 276 #define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0) 277 #define MLXPLAT_CPLD_BIOS_STATUS_MASK GENMASK(3, 1) 278 #define MLXPLAT_CPLD_DPU_MASK GENMASK(3, 0) 279 #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) 280 #define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6) 281 #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3) 282 #define MLXPLAT_CPLD_THERMAL2_PDB_MASK BIT(4) 283 #define MLXPLAT_CPLD_INTRUSION_MASK BIT(6) 284 #define MLXPLAT_CPLD_PWM_PG_MASK BIT(7) 285 #define MLXPLAT_CPLD_L1_CHA_HEALTH_MASK (MLXPLAT_CPLD_THERMAL1_PDB_MASK | \ 286 MLXPLAT_CPLD_THERMAL2_PDB_MASK | \ 287 MLXPLAT_CPLD_INTRUSION_MASK |\ 288 MLXPLAT_CPLD_PWM_PG_MASK) 289 #define MLXPLAT_CPLD_I2C_CAP_BIT 0x04 290 #define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT) 291 #define MLXPLAT_CPLD_SYS_RESET_MASK BIT(0) 292 293 /* Masks for aggregation for comex carriers */ 294 #define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1) 295 #define MLXPLAT_CPLD_AGGR_MASK_CARR_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 296 MLXPLAT_CPLD_AGGR_MASK_CARRIER) 297 #define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0xc1 298 299 /* Masks for aggregation for modular systems */ 300 #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0) 301 302 /* Masks for aggregation for smart switch systems */ 303 #define MLXPLAT_CPLD_LPC_SM_SW_MASK GENMASK(7, 0) 304 305 #define MLXPLAT_CPLD_HALT_MASK BIT(3) 306 #define MLXPLAT_CPLD_RESET_MASK GENMASK(7, 1) 307 308 /* Default I2C parent bus number */ 309 #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 310 311 /* Maximum number of possible physical buses equipped on system */ 312 #define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 313 #define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24 314 315 /* Number of channels in group */ 316 #define MLXPLAT_CPLD_GRP_CHNL_NUM 8 317 318 /* Start channel numbers */ 319 #define MLXPLAT_CPLD_CH1 2 320 #define MLXPLAT_CPLD_CH2 10 321 #define MLXPLAT_CPLD_CH3 18 322 #define MLXPLAT_CPLD_CH2_ETH_MODULAR 3 323 #define MLXPLAT_CPLD_CH3_ETH_MODULAR 43 324 #define MLXPLAT_CPLD_CH4_ETH_MODULAR 51 325 #define MLXPLAT_CPLD_CH2_RACK_SWITCH 18 326 #define MLXPLAT_CPLD_CH2_NG800 34 327 328 /* Number of LPC attached MUX platform devices */ 329 #define MLXPLAT_CPLD_LPC_MUX_DEVS 4 330 331 /* Hotplug devices adapter numbers */ 332 #define MLXPLAT_CPLD_NR_NONE -1 333 #define MLXPLAT_CPLD_PSU_DEFAULT_NR 10 334 #define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4 335 #define MLXPLAT_CPLD_PSU_XDR_NR 3 336 #define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11 337 #define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12 338 #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13 339 #define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14 340 #define MLXPLAT_CPLD_NR_ASIC 3 341 #define MLXPLAT_CPLD_NR_LC_BASE 34 342 #define MLXPLAT_CPLD_NR_DPU_BASE 18 343 344 #define MLXPLAT_CPLD_NR_LC_SET(nr) (MLXPLAT_CPLD_NR_LC_BASE + (nr)) 345 #define MLXPLAT_CPLD_LC_ADDR 0x32 346 #define MLXPLAT_CPLD_DPU_ADDR 0x68 347 348 /* Masks and default values for watchdogs */ 349 #define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1) 350 #define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1)) 351 352 #define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4) 353 #define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0 354 #define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1) 355 #define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4)) 356 #define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7)) 357 #define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6)) 358 #define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30 359 #define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600 360 #define MLXPLAT_CPLD_WD_MAX_DEVS 2 361 #define MLXPLAT_CPLD_DPU_MAX_DEVS 4 362 363 #define MLXPLAT_CPLD_LPC_SYSIRQ 17 364 365 /* Minimum power required for turning on Ethernet modular system (WATT) */ 366 #define MLXPLAT_CPLD_ETH_MODULAR_PWR_MIN 50 367 368 /* Default value for PWM control register for rack switch system */ 369 #define MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT 0xf4 370 371 #define MLXPLAT_I2C_MAIN_BUS_NOTIFIED 0x01 372 #define MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED 0x02 373 374 /* Lattice FPGA PCI configuration */ 375 #define PCI_VENDOR_ID_LATTICE 0x1204 376 #define PCI_DEVICE_ID_LATTICE_I2C_BRIDGE 0x9c2f 377 #define PCI_DEVICE_ID_LATTICE_JTAG_BRIDGE 0x9c30 378 #define PCI_DEVICE_ID_LATTICE_LPC_BRIDGE 0x9c32 379 380 /* mlxplat_priv - platform private data 381 * @pdev_i2c - i2c controller platform device 382 * @pdev_mux - array of mux platform devices 383 * @pdev_hotplug - hotplug platform devices 384 * @pdev_led - led platform devices 385 * @pdev_io_regs - register access platform devices 386 * @pdev_fan - FAN platform devices 387 * @pdev_wd - array of watchdog platform devices 388 * pdev_dpu - array of Data Processor Unit platform devices 389 * @regmap: device register map 390 * @hotplug_resources: system hotplug resources 391 * @hotplug_resources_size: size of system hotplug resources 392 * @hi2c_main_init_status: init status of I2C main bus 393 * @irq_fpga: FPGA IRQ number 394 */ 395 struct mlxplat_priv { 396 struct platform_device *pdev_i2c; 397 struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS]; 398 struct platform_device *pdev_hotplug; 399 struct platform_device *pdev_led; 400 struct platform_device *pdev_io_regs; 401 struct platform_device *pdev_fan; 402 struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS]; 403 struct platform_device *pdev_dpu[MLXPLAT_CPLD_DPU_MAX_DEVS]; 404 void *regmap; 405 struct resource *hotplug_resources; 406 unsigned int hotplug_resources_size; 407 u8 i2c_main_init_status; 408 int irq_fpga; 409 }; 410 411 static struct platform_device *mlxplat_dev; 412 static int mlxplat_i2c_main_completion_notify(void *handle, int id); 413 static void __iomem *i2c_bridge_addr, *jtag_bridge_addr; 414 415 /* Regions for LPC I2C controller and LPC base register space */ 416 static const struct resource mlxplat_lpc_resources[] = { 417 [0] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR, 418 MLXPLAT_CPLD_LPC_IO_RANGE, 419 "mlxplat_cpld_lpc_i2c_ctrl", IORESOURCE_IO), 420 [1] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_REG_BASE_ADRR, 421 MLXPLAT_CPLD_LPC_IO_RANGE, 422 "mlxplat_cpld_lpc_regs", 423 IORESOURCE_IO), 424 }; 425 426 /* Platform systems default i2c data */ 427 static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_default_data = { 428 .completion_notify = mlxplat_i2c_main_completion_notify, 429 }; 430 431 /* Platform i2c next generation systems data */ 432 static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = { 433 { 434 .reg = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 435 .mask = MLXPLAT_CPLD_I2C_CAP_MASK, 436 .bit = MLXPLAT_CPLD_I2C_CAP_BIT, 437 }, 438 }; 439 440 static struct mlxreg_core_item mlxplat_mlxcpld_i2c_ng_items[] = { 441 { 442 .data = mlxplat_mlxcpld_i2c_ng_items_data, 443 }, 444 }; 445 446 /* Platform next generation systems i2c data */ 447 static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = { 448 .items = mlxplat_mlxcpld_i2c_ng_items, 449 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 450 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, 451 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET, 452 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_I2C, 453 .completion_notify = mlxplat_i2c_main_completion_notify, 454 }; 455 456 /* Platform default channels */ 457 static const int mlxplat_default_channels[][MLXPLAT_CPLD_GRP_CHNL_NUM] = { 458 { 459 MLXPLAT_CPLD_CH1, MLXPLAT_CPLD_CH1 + 1, MLXPLAT_CPLD_CH1 + 2, 460 MLXPLAT_CPLD_CH1 + 3, MLXPLAT_CPLD_CH1 + 4, MLXPLAT_CPLD_CH1 + 461 5, MLXPLAT_CPLD_CH1 + 6, MLXPLAT_CPLD_CH1 + 7 462 }, 463 { 464 MLXPLAT_CPLD_CH2, MLXPLAT_CPLD_CH2 + 1, MLXPLAT_CPLD_CH2 + 2, 465 MLXPLAT_CPLD_CH2 + 3, MLXPLAT_CPLD_CH2 + 4, MLXPLAT_CPLD_CH2 + 466 5, MLXPLAT_CPLD_CH2 + 6, MLXPLAT_CPLD_CH2 + 7 467 }, 468 }; 469 470 /* Platform channels for MSN21xx system family */ 471 static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 }; 472 473 /* Platform mux data */ 474 static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { 475 { 476 .parent = 1, 477 .base_nr = MLXPLAT_CPLD_CH1, 478 .write_only = 1, 479 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 480 .reg_size = 1, 481 .idle_in_use = 1, 482 }, 483 { 484 .parent = 1, 485 .base_nr = MLXPLAT_CPLD_CH2, 486 .write_only = 1, 487 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 488 .reg_size = 1, 489 .idle_in_use = 1, 490 }, 491 492 }; 493 494 /* Platform mux configuration variables */ 495 static int mlxplat_max_adap_num; 496 static int mlxplat_mux_num; 497 static struct i2c_mux_reg_platform_data *mlxplat_mux_data; 498 static struct notifier_block *mlxplat_reboot_nb; 499 500 /* Platform extended mux data */ 501 static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = { 502 { 503 .parent = 1, 504 .base_nr = MLXPLAT_CPLD_CH1, 505 .write_only = 1, 506 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 507 .reg_size = 1, 508 .idle_in_use = 1, 509 }, 510 { 511 .parent = 1, 512 .base_nr = MLXPLAT_CPLD_CH2, 513 .write_only = 1, 514 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, 515 .reg_size = 1, 516 .idle_in_use = 1, 517 }, 518 { 519 .parent = 1, 520 .base_nr = MLXPLAT_CPLD_CH3, 521 .write_only = 1, 522 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 523 .reg_size = 1, 524 .idle_in_use = 1, 525 }, 526 527 }; 528 529 /* Platform channels for modular system family */ 530 static const int mlxplat_modular_upper_channel[] = { 1 }; 531 static const int mlxplat_modular_channels[] = { 532 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 533 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 534 38, 39, 40 535 }; 536 537 /* Platform modular mux data */ 538 static struct i2c_mux_reg_platform_data mlxplat_modular_mux_data[] = { 539 { 540 .parent = 1, 541 .base_nr = MLXPLAT_CPLD_CH1, 542 .write_only = 1, 543 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG4, 544 .reg_size = 1, 545 .idle_in_use = 1, 546 .values = mlxplat_modular_upper_channel, 547 .n_values = ARRAY_SIZE(mlxplat_modular_upper_channel), 548 }, 549 { 550 .parent = 1, 551 .base_nr = MLXPLAT_CPLD_CH2_ETH_MODULAR, 552 .write_only = 1, 553 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 554 .reg_size = 1, 555 .idle_in_use = 1, 556 .values = mlxplat_modular_channels, 557 .n_values = ARRAY_SIZE(mlxplat_modular_channels), 558 }, 559 { 560 .parent = MLXPLAT_CPLD_CH1, 561 .base_nr = MLXPLAT_CPLD_CH3_ETH_MODULAR, 562 .write_only = 1, 563 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, 564 .reg_size = 1, 565 .idle_in_use = 1, 566 .values = mlxplat_msn21xx_channels, 567 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 568 }, 569 { 570 .parent = 1, 571 .base_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR, 572 .write_only = 1, 573 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 574 .reg_size = 1, 575 .idle_in_use = 1, 576 .values = mlxplat_msn21xx_channels, 577 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 578 }, 579 }; 580 581 /* Platform channels for rack switch system family */ 582 static const int mlxplat_rack_switch_channels[] = { 583 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 584 }; 585 586 /* Platform rack switch mux data */ 587 static struct i2c_mux_reg_platform_data mlxplat_rack_switch_mux_data[] = { 588 { 589 .parent = 1, 590 .base_nr = MLXPLAT_CPLD_CH1, 591 .write_only = 1, 592 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 593 .reg_size = 1, 594 .idle_in_use = 1, 595 .values = mlxplat_rack_switch_channels, 596 .n_values = ARRAY_SIZE(mlxplat_rack_switch_channels), 597 }, 598 { 599 .parent = 1, 600 .base_nr = MLXPLAT_CPLD_CH2_RACK_SWITCH, 601 .write_only = 1, 602 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 603 .reg_size = 1, 604 .idle_in_use = 1, 605 .values = mlxplat_msn21xx_channels, 606 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 607 }, 608 609 }; 610 611 /* Platform channels for ng800 system family */ 612 static const int mlxplat_ng800_channels[] = { 613 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 614 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 615 }; 616 617 /* Platform ng800 mux data */ 618 static struct i2c_mux_reg_platform_data mlxplat_ng800_mux_data[] = { 619 { 620 .parent = 1, 621 .base_nr = MLXPLAT_CPLD_CH1, 622 .write_only = 1, 623 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 624 .reg_size = 1, 625 .idle_in_use = 1, 626 .values = mlxplat_ng800_channels, 627 .n_values = ARRAY_SIZE(mlxplat_ng800_channels), 628 }, 629 { 630 .parent = 1, 631 .base_nr = MLXPLAT_CPLD_CH2_NG800, 632 .write_only = 1, 633 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 634 .reg_size = 1, 635 .idle_in_use = 1, 636 .values = mlxplat_msn21xx_channels, 637 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 638 }, 639 640 }; 641 642 /* Platform hotplug devices */ 643 static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { 644 { 645 I2C_BOARD_INFO("dps460", 0x59), 646 }, 647 { 648 I2C_BOARD_INFO("dps460", 0x58), 649 }, 650 }; 651 652 static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = { 653 { 654 I2C_BOARD_INFO("dps460", 0x5b), 655 }, 656 { 657 I2C_BOARD_INFO("dps460", 0x5a), 658 }, 659 }; 660 661 static struct i2c_board_info mlxplat_mlxcpld_pwr_ng800[] = { 662 { 663 I2C_BOARD_INFO("dps460", 0x59), 664 }, 665 { 666 I2C_BOARD_INFO("dps460", 0x5a), 667 }, 668 }; 669 670 static struct i2c_board_info mlxplat_mlxcpld_xdr_pwr[] = { 671 { 672 I2C_BOARD_INFO("dps460", 0x5d), 673 }, 674 { 675 I2C_BOARD_INFO("dps460", 0x5c), 676 }, 677 { 678 I2C_BOARD_INFO("dps460", 0x5e), 679 }, 680 { 681 I2C_BOARD_INFO("dps460", 0x5f), 682 }, 683 }; 684 685 static struct i2c_board_info mlxplat_mlxcpld_fan[] = { 686 { 687 I2C_BOARD_INFO("24c32", 0x50), 688 }, 689 { 690 I2C_BOARD_INFO("24c32", 0x50), 691 }, 692 { 693 I2C_BOARD_INFO("24c32", 0x50), 694 }, 695 { 696 I2C_BOARD_INFO("24c32", 0x50), 697 }, 698 }; 699 700 /* Platform hotplug comex carrier system family data */ 701 static struct mlxreg_core_data mlxplat_mlxcpld_comex_psu_items_data[] = { 702 { 703 .label = "psu1", 704 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 705 .mask = BIT(0), 706 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 707 }, 708 { 709 .label = "psu2", 710 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 711 .mask = BIT(1), 712 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 713 }, 714 }; 715 716 /* Platform hotplug default data */ 717 static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = { 718 { 719 .label = "psu1", 720 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 721 .mask = BIT(0), 722 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 723 }, 724 { 725 .label = "psu2", 726 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 727 .mask = BIT(1), 728 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 729 }, 730 }; 731 732 /* Platform hotplug dgx data */ 733 static struct mlxreg_core_data mlxplat_mlxcpld_dgx_pdb_items_data[] = { 734 { 735 .label = "pdb1", 736 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 737 .mask = BIT(0), 738 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 739 }, 740 }; 741 742 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = { 743 { 744 .label = "pwr1", 745 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 746 .mask = BIT(0), 747 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 748 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 749 }, 750 { 751 .label = "pwr2", 752 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 753 .mask = BIT(1), 754 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 755 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 756 }, 757 }; 758 759 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_wc_items_data[] = { 760 { 761 .label = "pwr1", 762 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 763 .mask = BIT(0), 764 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 765 }, 766 { 767 .label = "pwr2", 768 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 769 .mask = BIT(1), 770 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 771 }, 772 }; 773 774 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_ng800_items_data[] = { 775 { 776 .label = "pwr1", 777 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 778 .mask = BIT(0), 779 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[0], 780 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 781 }, 782 { 783 .label = "pwr2", 784 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 785 .mask = BIT(1), 786 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[1], 787 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 788 }, 789 }; 790 791 static struct mlxreg_core_data mlxplat_mlxcpld_dgx_pwr_items_data[] = { 792 { 793 .label = "pwr1", 794 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 795 .mask = BIT(0), 796 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 797 }, 798 }; 799 800 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = { 801 { 802 .label = "fan1", 803 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 804 .mask = BIT(0), 805 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[0], 806 .hpdev.nr = MLXPLAT_CPLD_FAN1_DEFAULT_NR, 807 }, 808 { 809 .label = "fan2", 810 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 811 .mask = BIT(1), 812 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[1], 813 .hpdev.nr = MLXPLAT_CPLD_FAN2_DEFAULT_NR, 814 }, 815 { 816 .label = "fan3", 817 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 818 .mask = BIT(2), 819 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[2], 820 .hpdev.nr = MLXPLAT_CPLD_FAN3_DEFAULT_NR, 821 }, 822 { 823 .label = "fan4", 824 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 825 .mask = BIT(3), 826 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[3], 827 .hpdev.nr = MLXPLAT_CPLD_FAN4_DEFAULT_NR, 828 }, 829 }; 830 831 static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = { 832 { 833 .label = "asic1", 834 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 835 .mask = MLXPLAT_CPLD_ASIC_MASK, 836 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 837 }, 838 }; 839 840 static struct mlxreg_core_data mlxplat_mlxcpld_default_asic2_items_data[] = { 841 { 842 .label = "asic2", 843 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, 844 .mask = MLXPLAT_CPLD_ASIC_MASK, 845 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 846 }, 847 }; 848 849 static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = { 850 { 851 .data = mlxplat_mlxcpld_default_psu_items_data, 852 .aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF, 853 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 854 .mask = MLXPLAT_CPLD_PSU_MASK, 855 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 856 .inversed = 1, 857 .health = false, 858 }, 859 { 860 .data = mlxplat_mlxcpld_default_pwr_items_data, 861 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 862 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 863 .mask = MLXPLAT_CPLD_PWR_MASK, 864 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 865 .inversed = 0, 866 .health = false, 867 }, 868 { 869 .data = mlxplat_mlxcpld_default_fan_items_data, 870 .aggr_mask = MLXPLAT_CPLD_AGGR_FAN_MASK_DEF, 871 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 872 .mask = MLXPLAT_CPLD_FAN_MASK, 873 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data), 874 .inversed = 1, 875 .health = false, 876 }, 877 { 878 .data = mlxplat_mlxcpld_default_asic_items_data, 879 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 880 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 881 .mask = MLXPLAT_CPLD_ASIC_MASK, 882 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 883 .inversed = 0, 884 .health = true, 885 }, 886 }; 887 888 static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = { 889 { 890 .data = mlxplat_mlxcpld_comex_psu_items_data, 891 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 892 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 893 .mask = MLXPLAT_CPLD_PSU_MASK, 894 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 895 .inversed = 1, 896 .health = false, 897 }, 898 { 899 .data = mlxplat_mlxcpld_default_pwr_items_data, 900 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 901 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 902 .mask = MLXPLAT_CPLD_PWR_MASK, 903 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 904 .inversed = 0, 905 .health = false, 906 }, 907 { 908 .data = mlxplat_mlxcpld_default_fan_items_data, 909 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 910 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 911 .mask = MLXPLAT_CPLD_FAN_MASK, 912 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data), 913 .inversed = 1, 914 .health = false, 915 }, 916 { 917 .data = mlxplat_mlxcpld_default_asic_items_data, 918 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 919 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 920 .mask = MLXPLAT_CPLD_ASIC_MASK, 921 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 922 .inversed = 0, 923 .health = true, 924 }, 925 }; 926 927 static 928 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = { 929 .items = mlxplat_mlxcpld_default_items, 930 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_items), 931 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 932 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 933 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 934 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 935 }; 936 937 static struct mlxreg_core_item mlxplat_mlxcpld_default_wc_items[] = { 938 { 939 .data = mlxplat_mlxcpld_comex_psu_items_data, 940 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 941 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 942 .mask = MLXPLAT_CPLD_PSU_MASK, 943 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 944 .inversed = 1, 945 .health = false, 946 }, 947 { 948 .data = mlxplat_mlxcpld_default_pwr_wc_items_data, 949 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 950 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 951 .mask = MLXPLAT_CPLD_PWR_MASK, 952 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 953 .inversed = 0, 954 .health = false, 955 }, 956 { 957 .data = mlxplat_mlxcpld_default_asic_items_data, 958 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 959 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 960 .mask = MLXPLAT_CPLD_ASIC_MASK, 961 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 962 .inversed = 0, 963 .health = true, 964 }, 965 }; 966 967 static 968 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_wc_data = { 969 .items = mlxplat_mlxcpld_default_wc_items, 970 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_wc_items), 971 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 972 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 973 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 974 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 975 }; 976 977 static 978 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = { 979 .items = mlxplat_mlxcpld_comex_items, 980 .count = ARRAY_SIZE(mlxplat_mlxcpld_comex_items), 981 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 982 .mask = MLXPLAT_CPLD_AGGR_MASK_CARR_DEF, 983 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET, 984 .mask_low = MLXPLAT_CPLD_LOW_AGGRCX_MASK, 985 }; 986 987 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = { 988 { 989 .label = "pwr1", 990 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 991 .mask = BIT(0), 992 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 993 }, 994 { 995 .label = "pwr2", 996 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 997 .mask = BIT(1), 998 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 999 }, 1000 }; 1001 1002 /* Platform hotplug MSN21xx system family data */ 1003 static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = { 1004 { 1005 .data = mlxplat_mlxcpld_msn21xx_pwr_items_data, 1006 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 1007 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1008 .mask = MLXPLAT_CPLD_PWR_MASK, 1009 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_pwr_items_data), 1010 .inversed = 0, 1011 .health = false, 1012 }, 1013 { 1014 .data = mlxplat_mlxcpld_default_asic_items_data, 1015 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 1016 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1017 .mask = MLXPLAT_CPLD_ASIC_MASK, 1018 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1019 .inversed = 0, 1020 .health = true, 1021 }, 1022 }; 1023 1024 static 1025 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = { 1026 .items = mlxplat_mlxcpld_msn21xx_items, 1027 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items), 1028 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1029 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 1030 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1031 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1032 }; 1033 1034 /* Platform hotplug msn274x system family data */ 1035 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_psu_items_data[] = { 1036 { 1037 .label = "psu1", 1038 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1039 .mask = BIT(0), 1040 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1041 }, 1042 { 1043 .label = "psu2", 1044 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1045 .mask = BIT(1), 1046 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1047 }, 1048 }; 1049 1050 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_pwr_items_data[] = { 1051 { 1052 .label = "pwr1", 1053 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1054 .mask = BIT(0), 1055 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 1056 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1057 }, 1058 { 1059 .label = "pwr2", 1060 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1061 .mask = BIT(1), 1062 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 1063 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1064 }, 1065 }; 1066 1067 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_fan_items_data[] = { 1068 { 1069 .label = "fan1", 1070 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1071 .mask = BIT(0), 1072 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1073 }, 1074 { 1075 .label = "fan2", 1076 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1077 .mask = BIT(1), 1078 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1079 }, 1080 { 1081 .label = "fan3", 1082 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1083 .mask = BIT(2), 1084 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1085 }, 1086 { 1087 .label = "fan4", 1088 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1089 .mask = BIT(3), 1090 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1091 }, 1092 }; 1093 1094 static struct mlxreg_core_item mlxplat_mlxcpld_msn274x_items[] = { 1095 { 1096 .data = mlxplat_mlxcpld_msn274x_psu_items_data, 1097 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1098 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1099 .mask = MLXPLAT_CPLD_PSU_MASK, 1100 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_psu_items_data), 1101 .inversed = 1, 1102 .health = false, 1103 }, 1104 { 1105 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 1106 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1107 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1108 .mask = MLXPLAT_CPLD_PWR_MASK, 1109 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 1110 .inversed = 0, 1111 .health = false, 1112 }, 1113 { 1114 .data = mlxplat_mlxcpld_msn274x_fan_items_data, 1115 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1116 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1117 .mask = MLXPLAT_CPLD_FAN_MASK, 1118 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_fan_items_data), 1119 .inversed = 1, 1120 .health = false, 1121 }, 1122 { 1123 .data = mlxplat_mlxcpld_default_asic_items_data, 1124 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1125 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1126 .mask = MLXPLAT_CPLD_ASIC_MASK, 1127 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1128 .inversed = 0, 1129 .health = true, 1130 }, 1131 }; 1132 1133 static 1134 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn274x_data = { 1135 .items = mlxplat_mlxcpld_msn274x_items, 1136 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_items), 1137 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1138 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1139 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1140 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1141 }; 1142 1143 /* Platform hotplug MSN201x system family data */ 1144 static struct mlxreg_core_data mlxplat_mlxcpld_msn201x_pwr_items_data[] = { 1145 { 1146 .label = "pwr1", 1147 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1148 .mask = BIT(0), 1149 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1150 }, 1151 { 1152 .label = "pwr2", 1153 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1154 .mask = BIT(1), 1155 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1156 }, 1157 }; 1158 1159 static struct mlxreg_core_item mlxplat_mlxcpld_msn201x_items[] = { 1160 { 1161 .data = mlxplat_mlxcpld_msn201x_pwr_items_data, 1162 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 1163 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1164 .mask = MLXPLAT_CPLD_PWR_MASK, 1165 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_pwr_items_data), 1166 .inversed = 0, 1167 .health = false, 1168 }, 1169 { 1170 .data = mlxplat_mlxcpld_default_asic_items_data, 1171 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 1172 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1173 .mask = MLXPLAT_CPLD_ASIC_MASK, 1174 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1175 .inversed = 0, 1176 .health = true, 1177 }, 1178 }; 1179 1180 static 1181 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn201x_data = { 1182 .items = mlxplat_mlxcpld_msn201x_items, 1183 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_items), 1184 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1185 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 1186 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1187 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1188 }; 1189 1190 /* Platform hotplug next generation system family data */ 1191 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = { 1192 { 1193 .label = "psu1", 1194 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1195 .mask = BIT(0), 1196 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1197 }, 1198 { 1199 .label = "psu2", 1200 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1201 .mask = BIT(1), 1202 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1203 }, 1204 }; 1205 1206 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = { 1207 { 1208 .label = "fan1", 1209 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1210 .mask = BIT(0), 1211 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1212 .bit = BIT(0), 1213 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1214 }, 1215 { 1216 .label = "fan2", 1217 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1218 .mask = BIT(1), 1219 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1220 .bit = BIT(1), 1221 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1222 }, 1223 { 1224 .label = "fan3", 1225 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1226 .mask = BIT(2), 1227 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1228 .bit = BIT(2), 1229 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1230 }, 1231 { 1232 .label = "fan4", 1233 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1234 .mask = BIT(3), 1235 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1236 .bit = BIT(3), 1237 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1238 }, 1239 { 1240 .label = "fan5", 1241 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1242 .mask = BIT(4), 1243 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1244 .bit = BIT(4), 1245 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1246 }, 1247 { 1248 .label = "fan6", 1249 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1250 .mask = BIT(5), 1251 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1252 .bit = BIT(5), 1253 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1254 }, 1255 { 1256 .label = "fan7", 1257 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1258 .mask = BIT(6), 1259 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1260 .bit = BIT(6), 1261 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1262 }, 1263 }; 1264 1265 static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = { 1266 { 1267 .data = mlxplat_mlxcpld_default_ng_psu_items_data, 1268 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1269 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1270 .mask = MLXPLAT_CPLD_PSU_MASK, 1271 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data), 1272 .inversed = 1, 1273 .health = false, 1274 }, 1275 { 1276 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 1277 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1278 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1279 .mask = MLXPLAT_CPLD_PWR_MASK, 1280 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 1281 .inversed = 0, 1282 .health = false, 1283 }, 1284 { 1285 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1286 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1287 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1288 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1289 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1290 .inversed = 1, 1291 .health = false, 1292 }, 1293 { 1294 .data = mlxplat_mlxcpld_default_asic_items_data, 1295 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1296 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1297 .mask = MLXPLAT_CPLD_ASIC_MASK, 1298 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1299 .inversed = 0, 1300 .health = true, 1301 }, 1302 }; 1303 1304 static 1305 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = { 1306 .items = mlxplat_mlxcpld_default_ng_items, 1307 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items), 1308 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1309 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1310 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1311 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1312 }; 1313 1314 /* Platform hotplug extended system family data */ 1315 static struct mlxreg_core_data mlxplat_mlxcpld_ext_psu_items_data[] = { 1316 { 1317 .label = "psu1", 1318 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1319 .mask = BIT(0), 1320 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1321 }, 1322 { 1323 .label = "psu2", 1324 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1325 .mask = BIT(1), 1326 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1327 }, 1328 { 1329 .label = "psu3", 1330 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1331 .mask = BIT(2), 1332 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1333 }, 1334 { 1335 .label = "psu4", 1336 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1337 .mask = BIT(3), 1338 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1339 }, 1340 }; 1341 1342 static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = { 1343 { 1344 .label = "pwr1", 1345 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1346 .mask = BIT(0), 1347 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 1348 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1349 }, 1350 { 1351 .label = "pwr2", 1352 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1353 .mask = BIT(1), 1354 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 1355 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1356 }, 1357 { 1358 .label = "pwr3", 1359 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1360 .mask = BIT(2), 1361 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 1362 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1363 }, 1364 { 1365 .label = "pwr4", 1366 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1367 .mask = BIT(3), 1368 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 1369 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1370 }, 1371 }; 1372 1373 static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { 1374 { 1375 .data = mlxplat_mlxcpld_ext_psu_items_data, 1376 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1377 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1378 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 1379 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1380 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 1381 .inversed = 1, 1382 .health = false, 1383 }, 1384 { 1385 .data = mlxplat_mlxcpld_ext_pwr_items_data, 1386 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1387 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1388 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 1389 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1390 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 1391 .inversed = 0, 1392 .health = false, 1393 }, 1394 { 1395 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1396 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1397 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1398 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1399 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1400 .inversed = 1, 1401 .health = false, 1402 }, 1403 { 1404 .data = mlxplat_mlxcpld_default_asic_items_data, 1405 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1406 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1407 .mask = MLXPLAT_CPLD_ASIC_MASK, 1408 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1409 .inversed = 0, 1410 .health = true, 1411 }, 1412 { 1413 .data = mlxplat_mlxcpld_default_asic2_items_data, 1414 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1415 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, 1416 .mask = MLXPLAT_CPLD_ASIC_MASK, 1417 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic2_items_data), 1418 .inversed = 0, 1419 .health = true, 1420 } 1421 }; 1422 1423 static struct mlxreg_core_item mlxplat_mlxcpld_ext_dgx_items[] = { 1424 { 1425 .data = mlxplat_mlxcpld_dgx_pdb_items_data, 1426 .aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF, 1427 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1428 .mask = MLXPLAT_CPLD_PSU_MASK, 1429 .count = ARRAY_SIZE(mlxplat_mlxcpld_dgx_pdb_items_data), 1430 .inversed = 1, 1431 .health = false, 1432 }, 1433 { 1434 .data = mlxplat_mlxcpld_dgx_pwr_items_data, 1435 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 1436 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1437 .mask = MLXPLAT_CPLD_PWR_MASK, 1438 .count = ARRAY_SIZE(mlxplat_mlxcpld_dgx_pwr_items_data), 1439 .inversed = 0, 1440 .health = false, 1441 }, 1442 { 1443 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1444 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1445 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1446 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1447 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1448 .inversed = 1, 1449 .health = false, 1450 }, 1451 { 1452 .data = mlxplat_mlxcpld_default_asic_items_data, 1453 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1454 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1455 .mask = MLXPLAT_CPLD_ASIC_MASK, 1456 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1457 .inversed = 0, 1458 .health = true, 1459 }, 1460 }; 1461 1462 static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = { 1463 { 1464 .data = mlxplat_mlxcpld_default_ng_psu_items_data, 1465 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1466 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1467 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 1468 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1469 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data), 1470 .inversed = 1, 1471 .health = false, 1472 }, 1473 { 1474 .data = mlxplat_mlxcpld_default_pwr_ng800_items_data, 1475 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1476 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1477 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 1478 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1479 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_ng800_items_data), 1480 .inversed = 0, 1481 .health = false, 1482 }, 1483 { 1484 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1485 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1486 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1487 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1488 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1489 .inversed = 1, 1490 .health = false, 1491 }, 1492 { 1493 .data = mlxplat_mlxcpld_default_asic_items_data, 1494 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1495 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1496 .mask = MLXPLAT_CPLD_ASIC_MASK, 1497 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1498 .inversed = 0, 1499 .health = true, 1500 }, 1501 }; 1502 1503 static 1504 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { 1505 .items = mlxplat_mlxcpld_ext_items, 1506 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_items), 1507 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1508 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1509 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1510 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, 1511 }; 1512 1513 static 1514 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_dgx_ext_data = { 1515 .items = mlxplat_mlxcpld_ext_dgx_items, 1516 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_dgx_items), 1517 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1518 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1519 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1520 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, 1521 }; 1522 1523 static 1524 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_data = { 1525 .items = mlxplat_mlxcpld_ng800_items, 1526 .count = ARRAY_SIZE(mlxplat_mlxcpld_ng800_items), 1527 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1528 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1529 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1530 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, 1531 }; 1532 1533 static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { 1534 { 1535 .label = "pwr1", 1536 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1537 .mask = BIT(0), 1538 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 1539 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1540 }, 1541 { 1542 .label = "pwr2", 1543 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1544 .mask = BIT(1), 1545 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 1546 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1547 }, 1548 { 1549 .label = "pwr3", 1550 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1551 .mask = BIT(2), 1552 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 1553 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1554 }, 1555 { 1556 .label = "pwr4", 1557 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1558 .mask = BIT(3), 1559 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 1560 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1561 }, 1562 }; 1563 1564 static 1565 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_lc_act = { 1566 .irq = MLXPLAT_CPLD_LPC_SYSIRQ, 1567 }; 1568 1569 static struct mlxreg_core_data mlxplat_mlxcpld_modular_asic_items_data[] = { 1570 { 1571 .label = "asic1", 1572 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1573 .mask = MLXPLAT_CPLD_ASIC_MASK, 1574 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1575 }, 1576 }; 1577 1578 static struct i2c_board_info mlxplat_mlxcpld_lc_i2c_dev[] = { 1579 { 1580 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1581 .platform_data = &mlxplat_mlxcpld_lc_act, 1582 }, 1583 { 1584 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1585 .platform_data = &mlxplat_mlxcpld_lc_act, 1586 }, 1587 { 1588 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1589 .platform_data = &mlxplat_mlxcpld_lc_act, 1590 }, 1591 { 1592 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1593 .platform_data = &mlxplat_mlxcpld_lc_act, 1594 }, 1595 { 1596 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1597 .platform_data = &mlxplat_mlxcpld_lc_act, 1598 }, 1599 { 1600 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1601 .platform_data = &mlxplat_mlxcpld_lc_act, 1602 }, 1603 { 1604 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1605 .platform_data = &mlxplat_mlxcpld_lc_act, 1606 }, 1607 { 1608 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1609 .platform_data = &mlxplat_mlxcpld_lc_act, 1610 }, 1611 }; 1612 1613 static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_modular_lc_notifier[] = { 1614 { 1615 .identity = "lc1", 1616 }, 1617 { 1618 .identity = "lc2", 1619 }, 1620 { 1621 .identity = "lc3", 1622 }, 1623 { 1624 .identity = "lc4", 1625 }, 1626 { 1627 .identity = "lc5", 1628 }, 1629 { 1630 .identity = "lc6", 1631 }, 1632 { 1633 .identity = "lc7", 1634 }, 1635 { 1636 .identity = "lc8", 1637 }, 1638 }; 1639 1640 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { 1641 { 1642 .label = "lc1_present", 1643 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1644 .mask = BIT(0), 1645 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1646 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1647 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1648 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1649 .slot = 1, 1650 }, 1651 { 1652 .label = "lc2_present", 1653 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1654 .mask = BIT(1), 1655 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1656 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1657 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1658 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1659 .slot = 2, 1660 }, 1661 { 1662 .label = "lc3_present", 1663 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1664 .mask = BIT(2), 1665 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1666 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1667 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1668 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1669 .slot = 3, 1670 }, 1671 { 1672 .label = "lc4_present", 1673 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1674 .mask = BIT(3), 1675 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1676 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1677 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1678 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1679 .slot = 4, 1680 }, 1681 { 1682 .label = "lc5_present", 1683 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1684 .mask = BIT(4), 1685 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1686 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1687 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1688 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1689 .slot = 5, 1690 }, 1691 { 1692 .label = "lc6_present", 1693 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1694 .mask = BIT(5), 1695 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1696 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1697 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1698 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1699 .slot = 6, 1700 }, 1701 { 1702 .label = "lc7_present", 1703 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1704 .mask = BIT(6), 1705 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1706 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1707 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1708 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1709 .slot = 7, 1710 }, 1711 { 1712 .label = "lc8_present", 1713 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1714 .mask = BIT(7), 1715 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1716 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1717 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1718 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1719 .slot = 8, 1720 }, 1721 }; 1722 1723 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = { 1724 { 1725 .label = "lc1_verified", 1726 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1727 .mask = BIT(0), 1728 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1729 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1730 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1731 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1732 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1733 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1734 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1735 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1736 .slot = 1, 1737 }, 1738 { 1739 .label = "lc2_verified", 1740 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1741 .mask = BIT(1), 1742 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1743 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1744 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1745 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1746 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1747 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1748 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1749 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1750 .slot = 2, 1751 }, 1752 { 1753 .label = "lc3_verified", 1754 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1755 .mask = BIT(2), 1756 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1757 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1758 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1759 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1760 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1761 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1762 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1763 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1764 .slot = 3, 1765 }, 1766 { 1767 .label = "lc4_verified", 1768 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1769 .mask = BIT(3), 1770 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1771 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1772 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1773 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1774 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1775 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1776 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1777 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1778 .slot = 4, 1779 }, 1780 { 1781 .label = "lc5_verified", 1782 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1783 .mask = BIT(4), 1784 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1785 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1786 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1787 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1788 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1789 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1790 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1791 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1792 .slot = 5, 1793 }, 1794 { 1795 .label = "lc6_verified", 1796 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1797 .mask = BIT(5), 1798 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1799 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1800 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1801 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1802 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1803 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1804 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1805 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1806 .slot = 6, 1807 }, 1808 { 1809 .label = "lc7_verified", 1810 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1811 .mask = BIT(6), 1812 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1813 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1814 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1815 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1816 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1817 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1818 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1819 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1820 .slot = 7, 1821 }, 1822 { 1823 .label = "lc8_verified", 1824 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1825 .mask = BIT(7), 1826 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1827 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1828 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1829 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1830 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1831 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1832 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1833 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1834 .slot = 8, 1835 }, 1836 }; 1837 1838 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = { 1839 { 1840 .label = "lc1_powered", 1841 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1842 .mask = BIT(0), 1843 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1844 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1845 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1846 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1847 .slot = 1, 1848 }, 1849 { 1850 .label = "lc2_powered", 1851 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1852 .mask = BIT(1), 1853 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1854 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1855 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1856 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1857 .slot = 2, 1858 }, 1859 { 1860 .label = "lc3_powered", 1861 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1862 .mask = BIT(2), 1863 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1864 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1865 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1866 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1867 .slot = 3, 1868 }, 1869 { 1870 .label = "lc4_powered", 1871 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1872 .mask = BIT(3), 1873 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1874 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1875 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1876 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1877 .slot = 4, 1878 }, 1879 { 1880 .label = "lc5_powered", 1881 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1882 .mask = BIT(4), 1883 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1884 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1885 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1886 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1887 .slot = 5, 1888 }, 1889 { 1890 .label = "lc6_powered", 1891 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1892 .mask = BIT(5), 1893 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1894 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1895 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1896 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1897 .slot = 6, 1898 }, 1899 { 1900 .label = "lc7_powered", 1901 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1902 .mask = BIT(6), 1903 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1904 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1905 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1906 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1907 .slot = 7, 1908 }, 1909 { 1910 .label = "lc8_powered", 1911 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1912 .mask = BIT(7), 1913 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1914 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1915 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1916 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1917 .slot = 8, 1918 }, 1919 }; 1920 1921 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = { 1922 { 1923 .label = "lc1_ready", 1924 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1925 .mask = BIT(0), 1926 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1927 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1928 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1929 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1930 .slot = 1, 1931 }, 1932 { 1933 .label = "lc2_ready", 1934 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1935 .mask = BIT(1), 1936 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1937 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1938 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1939 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1940 .slot = 2, 1941 }, 1942 { 1943 .label = "lc3_ready", 1944 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1945 .mask = BIT(2), 1946 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1947 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1948 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1949 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1950 .slot = 3, 1951 }, 1952 { 1953 .label = "lc4_ready", 1954 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1955 .mask = BIT(3), 1956 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1957 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1958 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1959 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1960 .slot = 4, 1961 }, 1962 { 1963 .label = "lc5_ready", 1964 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1965 .mask = BIT(4), 1966 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1967 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1968 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1969 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1970 .slot = 5, 1971 }, 1972 { 1973 .label = "lc6_ready", 1974 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1975 .mask = BIT(5), 1976 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1977 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1978 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1979 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1980 .slot = 6, 1981 }, 1982 { 1983 .label = "lc7_ready", 1984 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1985 .mask = BIT(6), 1986 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1987 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1988 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1989 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1990 .slot = 7, 1991 }, 1992 { 1993 .label = "lc8_ready", 1994 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1995 .mask = BIT(7), 1996 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1997 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1998 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1999 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 2000 .slot = 8, 2001 }, 2002 }; 2003 2004 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = { 2005 { 2006 .label = "lc1_synced", 2007 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2008 .mask = BIT(0), 2009 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 2010 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 2011 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2012 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 2013 .slot = 1, 2014 }, 2015 { 2016 .label = "lc2_synced", 2017 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2018 .mask = BIT(1), 2019 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 2020 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 2021 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2022 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 2023 .slot = 2, 2024 }, 2025 { 2026 .label = "lc3_synced", 2027 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2028 .mask = BIT(2), 2029 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 2030 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 2031 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2032 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 2033 .slot = 3, 2034 }, 2035 { 2036 .label = "lc4_synced", 2037 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2038 .mask = BIT(3), 2039 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 2040 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 2041 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2042 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 2043 .slot = 4, 2044 }, 2045 { 2046 .label = "lc5_synced", 2047 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2048 .mask = BIT(4), 2049 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 2050 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 2051 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2052 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 2053 .slot = 5, 2054 }, 2055 { 2056 .label = "lc6_synced", 2057 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2058 .mask = BIT(5), 2059 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 2060 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 2061 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2062 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 2063 .slot = 6, 2064 }, 2065 { 2066 .label = "lc7_synced", 2067 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2068 .mask = BIT(6), 2069 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 2070 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 2071 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2072 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 2073 .slot = 7, 2074 }, 2075 { 2076 .label = "lc8_synced", 2077 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2078 .mask = BIT(7), 2079 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 2080 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 2081 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2082 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 2083 .slot = 8, 2084 }, 2085 }; 2086 2087 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = { 2088 { 2089 .label = "lc1_active", 2090 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2091 .mask = BIT(0), 2092 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 2093 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 2094 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2095 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 2096 .slot = 1, 2097 }, 2098 { 2099 .label = "lc2_active", 2100 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2101 .mask = BIT(1), 2102 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 2103 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 2104 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2105 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 2106 .slot = 2, 2107 }, 2108 { 2109 .label = "lc3_active", 2110 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2111 .mask = BIT(2), 2112 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 2113 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 2114 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2115 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 2116 .slot = 3, 2117 }, 2118 { 2119 .label = "lc4_active", 2120 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2121 .mask = BIT(3), 2122 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 2123 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 2124 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2125 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 2126 .slot = 4, 2127 }, 2128 { 2129 .label = "lc5_active", 2130 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2131 .mask = BIT(4), 2132 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 2133 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 2134 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2135 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 2136 .slot = 5, 2137 }, 2138 { 2139 .label = "lc6_active", 2140 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2141 .mask = BIT(5), 2142 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 2143 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 2144 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2145 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 2146 .slot = 6, 2147 }, 2148 { 2149 .label = "lc7_active", 2150 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2151 .mask = BIT(6), 2152 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 2153 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 2154 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2155 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 2156 .slot = 7, 2157 }, 2158 { 2159 .label = "lc8_active", 2160 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2161 .mask = BIT(7), 2162 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 2163 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 2164 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2165 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 2166 .slot = 8, 2167 }, 2168 }; 2169 2170 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = { 2171 { 2172 .label = "lc1_shutdown", 2173 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2174 .mask = BIT(0), 2175 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 2176 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 2177 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2178 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 2179 .slot = 1, 2180 }, 2181 { 2182 .label = "lc2_shutdown", 2183 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2184 .mask = BIT(1), 2185 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 2186 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 2187 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2188 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 2189 .slot = 2, 2190 }, 2191 { 2192 .label = "lc3_shutdown", 2193 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2194 .mask = BIT(2), 2195 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 2196 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 2197 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2198 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 2199 .slot = 3, 2200 }, 2201 { 2202 .label = "lc4_shutdown", 2203 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2204 .mask = BIT(3), 2205 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 2206 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 2207 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2208 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 2209 .slot = 4, 2210 }, 2211 { 2212 .label = "lc5_shutdown", 2213 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2214 .mask = BIT(4), 2215 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 2216 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 2217 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2218 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 2219 .slot = 5, 2220 }, 2221 { 2222 .label = "lc6_shutdown", 2223 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2224 .mask = BIT(5), 2225 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 2226 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 2227 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2228 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 2229 .slot = 6, 2230 }, 2231 { 2232 .label = "lc7_shutdown", 2233 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2234 .mask = BIT(6), 2235 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 2236 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 2237 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2238 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 2239 .slot = 7, 2240 }, 2241 { 2242 .label = "lc8_shutdown", 2243 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2244 .mask = BIT(7), 2245 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 2246 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 2247 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2248 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 2249 .slot = 8, 2250 }, 2251 }; 2252 2253 static struct mlxreg_core_item mlxplat_mlxcpld_modular_items[] = { 2254 { 2255 .data = mlxplat_mlxcpld_ext_psu_items_data, 2256 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2257 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2258 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 2259 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2260 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 2261 .inversed = 1, 2262 .health = false, 2263 }, 2264 { 2265 .data = mlxplat_mlxcpld_modular_pwr_items_data, 2266 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2267 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2268 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 2269 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2270 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 2271 .inversed = 0, 2272 .health = false, 2273 }, 2274 { 2275 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 2276 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2277 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2278 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 2279 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 2280 .inversed = 1, 2281 .health = false, 2282 }, 2283 { 2284 .data = mlxplat_mlxcpld_modular_asic_items_data, 2285 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2286 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 2287 .mask = MLXPLAT_CPLD_ASIC_MASK, 2288 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_asic_items_data), 2289 .inversed = 0, 2290 .health = true, 2291 }, 2292 { 2293 .data = mlxplat_mlxcpld_modular_lc_pr_items_data, 2294 .kind = MLXREG_HOTPLUG_LC_PRESENT, 2295 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2296 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 2297 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2298 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pr_items_data), 2299 .inversed = 1, 2300 .health = false, 2301 }, 2302 { 2303 .data = mlxplat_mlxcpld_modular_lc_ver_items_data, 2304 .kind = MLXREG_HOTPLUG_LC_VERIFIED, 2305 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2306 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 2307 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2308 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ver_items_data), 2309 .inversed = 0, 2310 .health = false, 2311 }, 2312 { 2313 .data = mlxplat_mlxcpld_modular_lc_pg_data, 2314 .kind = MLXREG_HOTPLUG_LC_POWERED, 2315 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2316 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 2317 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2318 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pg_data), 2319 .inversed = 0, 2320 .health = false, 2321 }, 2322 { 2323 .data = mlxplat_mlxcpld_modular_lc_ready_data, 2324 .kind = MLXREG_HOTPLUG_LC_READY, 2325 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2326 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 2327 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2328 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ready_data), 2329 .inversed = 0, 2330 .health = false, 2331 }, 2332 { 2333 .data = mlxplat_mlxcpld_modular_lc_synced_data, 2334 .kind = MLXREG_HOTPLUG_LC_SYNCED, 2335 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2336 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2337 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2338 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_synced_data), 2339 .inversed = 0, 2340 .health = false, 2341 }, 2342 { 2343 .data = mlxplat_mlxcpld_modular_lc_act_data, 2344 .kind = MLXREG_HOTPLUG_LC_ACTIVE, 2345 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2346 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2347 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2348 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_act_data), 2349 .inversed = 0, 2350 .health = false, 2351 }, 2352 { 2353 .data = mlxplat_mlxcpld_modular_lc_sd_data, 2354 .kind = MLXREG_HOTPLUG_LC_THERMAL, 2355 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2356 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2357 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2358 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_sd_data), 2359 .inversed = 0, 2360 .health = false, 2361 }, 2362 }; 2363 2364 static 2365 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = { 2366 .items = mlxplat_mlxcpld_modular_items, 2367 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_items), 2368 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2369 .mask = MLXPLAT_CPLD_AGGR_MASK_MODULAR, 2370 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2371 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2372 }; 2373 2374 /* Platform hotplug for NVLink blade systems family data */ 2375 static struct mlxreg_core_data mlxplat_mlxcpld_global_wp_items_data[] = { 2376 { 2377 .label = "global_wp_grant", 2378 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, 2379 .mask = MLXPLAT_CPLD_GWP_MASK, 2380 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2381 }, 2382 }; 2383 2384 static struct mlxreg_core_item mlxplat_mlxcpld_chassis_blade_items[] = { 2385 { 2386 .data = mlxplat_mlxcpld_global_wp_items_data, 2387 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2388 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, 2389 .mask = MLXPLAT_CPLD_GWP_MASK, 2390 .count = ARRAY_SIZE(mlxplat_mlxcpld_global_wp_items_data), 2391 .inversed = 0, 2392 .health = false, 2393 }, 2394 }; 2395 2396 static 2397 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_chassis_blade_data = { 2398 .items = mlxplat_mlxcpld_chassis_blade_items, 2399 .count = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_items), 2400 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2401 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, 2402 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2403 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2404 }; 2405 2406 /* Platform hotplug for switch systems family data */ 2407 static struct mlxreg_core_data mlxplat_mlxcpld_erot_ap_items_data[] = { 2408 { 2409 .label = "erot1_ap", 2410 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 2411 .mask = BIT(0), 2412 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2413 }, 2414 { 2415 .label = "erot2_ap", 2416 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 2417 .mask = BIT(1), 2418 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2419 }, 2420 }; 2421 2422 static struct mlxreg_core_data mlxplat_mlxcpld_erot_error_items_data[] = { 2423 { 2424 .label = "erot1_error", 2425 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 2426 .mask = BIT(0), 2427 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2428 }, 2429 { 2430 .label = "erot2_error", 2431 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 2432 .mask = BIT(1), 2433 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2434 }, 2435 }; 2436 2437 static struct mlxreg_core_item mlxplat_mlxcpld_rack_switch_items[] = { 2438 { 2439 .data = mlxplat_mlxcpld_ext_psu_items_data, 2440 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2441 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2442 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 2443 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2444 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 2445 .inversed = 1, 2446 .health = false, 2447 }, 2448 { 2449 .data = mlxplat_mlxcpld_ext_pwr_items_data, 2450 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2451 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2452 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 2453 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2454 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 2455 .inversed = 0, 2456 .health = false, 2457 }, 2458 { 2459 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 2460 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2461 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2462 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 2463 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 2464 .inversed = 1, 2465 .health = false, 2466 }, 2467 { 2468 .data = mlxplat_mlxcpld_erot_ap_items_data, 2469 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2470 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 2471 .mask = MLXPLAT_CPLD_EROT_MASK, 2472 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data), 2473 .inversed = 1, 2474 .health = false, 2475 }, 2476 { 2477 .data = mlxplat_mlxcpld_erot_error_items_data, 2478 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2479 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 2480 .mask = MLXPLAT_CPLD_EROT_MASK, 2481 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data), 2482 .inversed = 1, 2483 .health = false, 2484 }, 2485 }; 2486 2487 static 2488 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = { 2489 .items = mlxplat_mlxcpld_rack_switch_items, 2490 .count = ARRAY_SIZE(mlxplat_mlxcpld_rack_switch_items), 2491 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2492 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 2493 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2494 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2495 }; 2496 2497 /* Platform hotplug XDR and smart switch system family data */ 2498 static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = { 2499 { 2500 .label = "psu1", 2501 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2502 .mask = BIT(0), 2503 .slot = 1, 2504 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2505 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2506 }, 2507 { 2508 .label = "psu2", 2509 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2510 .mask = BIT(1), 2511 .slot = 2, 2512 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2513 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2514 }, 2515 { 2516 .label = "psu3", 2517 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2518 .mask = BIT(2), 2519 .slot = 3, 2520 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2521 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2522 }, 2523 { 2524 .label = "psu4", 2525 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2526 .mask = BIT(3), 2527 .slot = 4, 2528 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2529 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2530 }, 2531 { 2532 .label = "psu5", 2533 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2534 .mask = BIT(4), 2535 .slot = 5, 2536 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2537 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2538 }, 2539 { 2540 .label = "psu6", 2541 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2542 .mask = BIT(5), 2543 .slot = 6, 2544 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2545 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2546 }, 2547 { 2548 .label = "psu7", 2549 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2550 .mask = BIT(6), 2551 .slot = 7, 2552 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2553 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2554 }, 2555 { 2556 .label = "psu8", 2557 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2558 .mask = BIT(7), 2559 .slot = 8, 2560 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2561 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2562 }, 2563 }; 2564 2565 static struct mlxreg_core_data mlxplat_mlxcpld_xdr_pwr_items_data[] = { 2566 { 2567 .label = "pwr1", 2568 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2569 .mask = BIT(0), 2570 .slot = 1, 2571 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2572 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 2573 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 2574 }, 2575 { 2576 .label = "pwr2", 2577 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2578 .mask = BIT(1), 2579 .slot = 2, 2580 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2581 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 2582 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 2583 }, 2584 { 2585 .label = "pwr3", 2586 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2587 .mask = BIT(2), 2588 .slot = 3, 2589 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2590 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 2591 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 2592 }, 2593 { 2594 .label = "pwr4", 2595 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2596 .mask = BIT(3), 2597 .slot = 4, 2598 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2599 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 2600 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 2601 }, 2602 { 2603 .label = "pwr5", 2604 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2605 .mask = BIT(4), 2606 .slot = 5, 2607 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2608 .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[0], 2609 .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, 2610 }, 2611 { 2612 .label = "pwr6", 2613 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2614 .mask = BIT(5), 2615 .slot = 6, 2616 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2617 .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[1], 2618 .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, 2619 }, 2620 { 2621 .label = "pwr7", 2622 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2623 .mask = BIT(6), 2624 .slot = 7, 2625 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2626 .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[2], 2627 .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, 2628 }, 2629 { 2630 .label = "pwr8", 2631 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2632 .mask = BIT(7), 2633 .slot = 8, 2634 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2635 .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[3], 2636 .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, 2637 }, 2638 }; 2639 2640 static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = { 2641 { 2642 .label = "fan1", 2643 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2644 .mask = BIT(0), 2645 .slot = 1, 2646 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2647 .bit = BIT(0), 2648 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2649 }, 2650 { 2651 .label = "fan2", 2652 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2653 .mask = BIT(1), 2654 .slot = 2, 2655 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2656 .bit = BIT(1), 2657 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2658 }, 2659 { 2660 .label = "fan3", 2661 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2662 .mask = BIT(2), 2663 .slot = 3, 2664 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2665 .bit = BIT(2), 2666 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2667 }, 2668 { 2669 .label = "fan4", 2670 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2671 .mask = BIT(3), 2672 .slot = 4, 2673 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2674 .bit = BIT(3), 2675 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2676 }, 2677 { 2678 .label = "fan5", 2679 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2680 .mask = BIT(4), 2681 .slot = 5, 2682 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2683 .bit = BIT(4), 2684 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2685 }, 2686 { 2687 .label = "fan6", 2688 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2689 .mask = BIT(5), 2690 .slot = 6, 2691 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2692 .bit = BIT(5), 2693 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2694 }, 2695 { 2696 .label = "fan7", 2697 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2698 .mask = BIT(6), 2699 .slot = 7, 2700 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2701 .bit = BIT(6), 2702 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2703 }, 2704 { 2705 .label = "fan8", 2706 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2707 .mask = BIT(7), 2708 .slot = 8, 2709 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2710 .bit = BIT(7), 2711 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2712 }, 2713 }; 2714 2715 static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic1_items_data[] = { 2716 { 2717 .label = "asic1", 2718 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 2719 .mask = MLXPLAT_CPLD_ASIC_MASK, 2720 .slot = 1, 2721 .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, 2722 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2723 } 2724 }; 2725 2726 /* Platform hotplug for smart switch systems families data */ 2727 static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_ready_data[] = { 2728 { 2729 .label = "dpu1_ready", 2730 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 2731 .mask = BIT(0), 2732 .slot = 1, 2733 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2734 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2735 }, 2736 { 2737 .label = "dpu2_ready", 2738 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 2739 .mask = BIT(1), 2740 .slot = 2, 2741 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2742 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2743 }, 2744 { 2745 .label = "dpu3_ready", 2746 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 2747 .mask = BIT(2), 2748 .slot = 3, 2749 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2750 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2751 }, 2752 { 2753 .label = "dpu4_ready", 2754 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 2755 .mask = BIT(3), 2756 .slot = 4, 2757 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2758 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2759 }, 2760 }; 2761 2762 static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data[] = { 2763 { 2764 .label = "dpu1_shtdn_ready", 2765 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2766 .mask = BIT(0), 2767 .slot = 1, 2768 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2769 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2770 }, 2771 { 2772 .label = "dpu2_shtdn_ready", 2773 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2774 .mask = BIT(1), 2775 .slot = 2, 2776 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2777 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2778 }, 2779 { 2780 .label = "dpu3_shtdn_ready", 2781 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2782 .mask = BIT(2), 2783 .slot = 3, 2784 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2785 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2786 }, 2787 { 2788 .label = "dpu4_shtdn_ready", 2789 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2790 .mask = BIT(3), 2791 .slot = 4, 2792 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2793 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2794 }, 2795 }; 2796 2797 static struct mlxreg_core_item mlxplat_mlxcpld_smart_switch_items[] = { 2798 { 2799 .data = mlxplat_mlxcpld_xdr_psu_items_data, 2800 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2801 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2802 .mask = MLXPLAT_CPLD_PSU_XDR_MASK, 2803 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2804 .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_psu_items_data), 2805 .inversed = 1, 2806 .health = false, 2807 }, 2808 { 2809 .data = mlxplat_mlxcpld_xdr_pwr_items_data, 2810 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2811 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2812 .mask = MLXPLAT_CPLD_PWR_XDR_MASK, 2813 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2814 .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_pwr_items_data), 2815 .inversed = 0, 2816 .health = false, 2817 }, 2818 { 2819 .data = mlxplat_mlxcpld_xdr_fan_items_data, 2820 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2821 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2822 .mask = MLXPLAT_CPLD_FAN_XDR_MASK, 2823 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2824 .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data), 2825 .inversed = 1, 2826 .health = false, 2827 }, 2828 { 2829 .data = mlxplat_mlxcpld_xdr_asic1_items_data, 2830 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2831 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 2832 .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, 2833 .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, 2834 .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic1_items_data), 2835 .inversed = 0, 2836 .health = true, 2837 }, 2838 { 2839 .data = mlxplat_mlxcpld_smart_switch_dpu_ready_data, 2840 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_DPU_CORE, 2841 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 2842 .mask = MLXPLAT_CPLD_DPU_MASK, 2843 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2844 .count = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_ready_data), 2845 .inversed = 1, 2846 .health = false, 2847 }, 2848 { 2849 .data = mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data, 2850 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_DPU_CORE, 2851 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2852 .mask = MLXPLAT_CPLD_DPU_MASK, 2853 .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, 2854 .count = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data), 2855 .inversed = 1, 2856 .health = false, 2857 }, 2858 }; 2859 2860 static 2861 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_smart_switch_data = { 2862 .items = mlxplat_mlxcpld_smart_switch_items, 2863 .count = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_items), 2864 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2865 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX | 2866 MLXPLAT_CPLD_AGGR_MASK_DPU_BRD | MLXPLAT_CPLD_AGGR_MASK_DPU_CORE, 2867 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2868 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2869 }; 2870 2871 /* Smart switch data processor units data */ 2872 static struct i2c_board_info mlxplat_mlxcpld_smart_switch_dpu_devs[] = { 2873 { 2874 I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), 2875 .irq = MLXPLAT_CPLD_LPC_SYSIRQ, 2876 }, 2877 { 2878 I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), 2879 .irq = MLXPLAT_CPLD_LPC_SYSIRQ, 2880 }, 2881 { 2882 I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), 2883 .irq = MLXPLAT_CPLD_LPC_SYSIRQ, 2884 }, 2885 { 2886 I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), 2887 .irq = MLXPLAT_CPLD_LPC_SYSIRQ, 2888 }, 2889 }; 2890 2891 static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_data[] = { 2892 { 2893 .label = "dpu1", 2894 .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[0], 2895 .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE, 2896 .slot = 1, 2897 }, 2898 { 2899 .label = "dpu2", 2900 .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[1], 2901 .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 1, 2902 .slot = 2, 2903 }, 2904 { 2905 .label = "dpu3", 2906 .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[2], 2907 .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 2, 2908 .slot = 3, 2909 }, 2910 { 2911 .label = "dpu4", 2912 .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[3], 2913 .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 3, 2914 .slot = 4, 2915 }, 2916 }; 2917 2918 /* Callback performs graceful shutdown after notification about power button event */ 2919 static int 2920 mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_kind kind, 2921 u8 action) 2922 { 2923 if (action) { 2924 dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); 2925 kernel_power_off(); 2926 } 2927 2928 return 0; 2929 } 2930 2931 static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_pwr_events_notifier = { 2932 .user_handler = mlxplat_mlxcpld_l1_switch_pwr_events_handler, 2933 }; 2934 2935 /* Platform hotplug for l1 switch systems family data */ 2936 static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] = { 2937 { 2938 .label = "power_button", 2939 .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, 2940 .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, 2941 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2942 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2943 .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_pwr_events_notifier, 2944 }, 2945 }; 2946 2947 /* Callback activates latch reset flow after notification about intrusion event */ 2948 static int 2949 mlxplat_mlxcpld_l1_switch_intrusion_events_handler(void *handle, enum mlxreg_hotplug_kind kind, 2950 u8 action) 2951 { 2952 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 2953 u32 regval; 2954 int err; 2955 2956 err = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ®val); 2957 if (err) 2958 goto fail_regmap_read; 2959 2960 if (action) { 2961 dev_info(&mlxplat_dev->dev, "Detected intrusion - system latch is opened"); 2962 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2963 regval | MLXPLAT_CPLD_LATCH_RST_MASK); 2964 } else { 2965 dev_info(&mlxplat_dev->dev, "System latch is properly closed"); 2966 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2967 regval & ~MLXPLAT_CPLD_LATCH_RST_MASK); 2968 } 2969 2970 if (err) 2971 goto fail_regmap_write; 2972 2973 return 0; 2974 2975 fail_regmap_read: 2976 fail_regmap_write: 2977 dev_err(&mlxplat_dev->dev, "Register access failed"); 2978 return err; 2979 } 2980 2981 static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_intrusion_events_notifier = { 2982 .user_handler = mlxplat_mlxcpld_l1_switch_intrusion_events_handler, 2983 }; 2984 2985 static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_health_events_items_data[] = { 2986 { 2987 .label = "thermal1_pdb", 2988 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2989 .mask = MLXPLAT_CPLD_THERMAL1_PDB_MASK, 2990 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2991 }, 2992 { 2993 .label = "thermal2_pdb", 2994 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2995 .mask = MLXPLAT_CPLD_THERMAL2_PDB_MASK, 2996 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2997 }, 2998 { 2999 .label = "intrusion", 3000 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 3001 .mask = MLXPLAT_CPLD_INTRUSION_MASK, 3002 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 3003 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 3004 .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_intrusion_events_notifier, 3005 }, 3006 { 3007 .label = "pwm_pg", 3008 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 3009 .mask = MLXPLAT_CPLD_PWM_PG_MASK, 3010 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 3011 }, 3012 }; 3013 3014 static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { 3015 { 3016 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 3017 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 3018 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3019 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 3020 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 3021 .inversed = 1, 3022 .health = false, 3023 }, 3024 { 3025 .data = mlxplat_mlxcpld_erot_ap_items_data, 3026 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 3027 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 3028 .mask = MLXPLAT_CPLD_EROT_MASK, 3029 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data), 3030 .inversed = 1, 3031 .health = false, 3032 }, 3033 { 3034 .data = mlxplat_mlxcpld_erot_error_items_data, 3035 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 3036 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 3037 .mask = MLXPLAT_CPLD_EROT_MASK, 3038 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data), 3039 .inversed = 1, 3040 .health = false, 3041 }, 3042 { 3043 .data = mlxplat_mlxcpld_l1_switch_pwr_events_items_data, 3044 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 3045 .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, 3046 .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, 3047 .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_pwr_events_items_data), 3048 .inversed = 1, 3049 .health = false, 3050 }, 3051 { 3052 .data = mlxplat_mlxcpld_l1_switch_health_events_items_data, 3053 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 3054 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 3055 .mask = MLXPLAT_CPLD_L1_CHA_HEALTH_MASK, 3056 .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_health_events_items_data), 3057 .inversed = 1, 3058 .health = false, 3059 .ind = 8, 3060 }, 3061 }; 3062 3063 static 3064 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { 3065 .items = mlxplat_mlxcpld_l1_switch_events_items, 3066 .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_events_items), 3067 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 3068 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 3069 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 3070 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT, 3071 }; 3072 3073 /* Platform hotplug for 800G systems family data */ 3074 static struct mlxreg_core_item mlxplat_mlxcpld_ng800_hi171_items[] = { 3075 { 3076 .data = mlxplat_mlxcpld_ext_psu_items_data, 3077 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 3078 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 3079 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 3080 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 3081 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 3082 .inversed = 1, 3083 .health = false, 3084 }, 3085 { 3086 .data = mlxplat_mlxcpld_modular_pwr_items_data, 3087 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 3088 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 3089 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 3090 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 3091 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 3092 .inversed = 0, 3093 .health = false, 3094 }, 3095 { 3096 .data = mlxplat_mlxcpld_xdr_fan_items_data, 3097 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 3098 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3099 .mask = MLXPLAT_CPLD_FAN_XDR_MASK, 3100 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3101 .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data), 3102 .inversed = 1, 3103 .health = false, 3104 }, 3105 { 3106 .data = mlxplat_mlxcpld_default_asic_items_data, 3107 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 3108 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 3109 .mask = MLXPLAT_CPLD_ASIC_MASK, 3110 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 3111 .inversed = 0, 3112 .health = true, 3113 }, 3114 }; 3115 3116 static 3117 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_hi171_data = { 3118 .items = mlxplat_mlxcpld_ng800_hi171_items, 3119 .count = ARRAY_SIZE(mlxplat_mlxcpld_ng800_hi171_items), 3120 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 3121 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 3122 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 3123 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, 3124 }; 3125 3126 /* Platform led default data */ 3127 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { 3128 { 3129 .label = "status:green", 3130 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3131 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3132 }, 3133 { 3134 .label = "status:red", 3135 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3136 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3137 }, 3138 { 3139 .label = "psu:green", 3140 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3141 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3142 }, 3143 { 3144 .label = "psu:red", 3145 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3146 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3147 }, 3148 { 3149 .label = "fan1:green", 3150 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3151 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3152 }, 3153 { 3154 .label = "fan1:red", 3155 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3156 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3157 }, 3158 { 3159 .label = "fan2:green", 3160 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3161 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3162 }, 3163 { 3164 .label = "fan2:red", 3165 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3166 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3167 }, 3168 { 3169 .label = "fan3:green", 3170 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3171 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3172 }, 3173 { 3174 .label = "fan3:red", 3175 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3176 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3177 }, 3178 { 3179 .label = "fan4:green", 3180 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3181 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3182 }, 3183 { 3184 .label = "fan4:red", 3185 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3186 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3187 }, 3188 }; 3189 3190 static struct mlxreg_core_platform_data mlxplat_default_led_data = { 3191 .data = mlxplat_mlxcpld_default_led_data, 3192 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data), 3193 }; 3194 3195 /* Platform led default data for water cooling */ 3196 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_wc_data[] = { 3197 { 3198 .label = "status:green", 3199 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3200 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3201 }, 3202 { 3203 .label = "status:red", 3204 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3205 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3206 }, 3207 { 3208 .label = "psu:green", 3209 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3210 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3211 }, 3212 { 3213 .label = "psu:red", 3214 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3215 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3216 }, 3217 }; 3218 3219 static struct mlxreg_core_platform_data mlxplat_default_led_wc_data = { 3220 .data = mlxplat_mlxcpld_default_led_wc_data, 3221 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_wc_data), 3222 }; 3223 3224 /* Platform led default data for water cooling Ethernet switch blade */ 3225 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_eth_wc_blade_data[] = { 3226 { 3227 .label = "status:green", 3228 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3229 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3230 }, 3231 { 3232 .label = "status:red", 3233 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3234 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3235 }, 3236 }; 3237 3238 static struct mlxreg_core_platform_data mlxplat_default_led_eth_wc_blade_data = { 3239 .data = mlxplat_mlxcpld_default_led_eth_wc_blade_data, 3240 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_eth_wc_blade_data), 3241 }; 3242 3243 /* Platform led MSN21xx system family data */ 3244 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = { 3245 { 3246 .label = "status:green", 3247 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3248 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3249 }, 3250 { 3251 .label = "status:red", 3252 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3253 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3254 }, 3255 { 3256 .label = "fan:green", 3257 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3258 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3259 }, 3260 { 3261 .label = "fan:red", 3262 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3263 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3264 }, 3265 { 3266 .label = "psu1:green", 3267 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3268 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3269 }, 3270 { 3271 .label = "psu1:red", 3272 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3273 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3274 }, 3275 { 3276 .label = "psu2:green", 3277 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3278 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3279 }, 3280 { 3281 .label = "psu2:red", 3282 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3283 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3284 }, 3285 { 3286 .label = "uid:blue", 3287 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3288 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3289 }, 3290 }; 3291 3292 static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = { 3293 .data = mlxplat_mlxcpld_msn21xx_led_data, 3294 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data), 3295 }; 3296 3297 /* Platform led for default data for 200GbE systems */ 3298 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = { 3299 { 3300 .label = "status:green", 3301 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3302 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3303 }, 3304 { 3305 .label = "status:orange", 3306 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3307 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3308 }, 3309 { 3310 .label = "psu:green", 3311 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3312 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3313 }, 3314 { 3315 .label = "psu:orange", 3316 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3317 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3318 }, 3319 { 3320 .label = "fan1:green", 3321 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3322 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3323 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3324 .bit = BIT(0), 3325 }, 3326 { 3327 .label = "fan1:orange", 3328 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3329 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3330 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3331 .bit = BIT(0), 3332 }, 3333 { 3334 .label = "fan2:green", 3335 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3336 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3337 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3338 .bit = BIT(1), 3339 }, 3340 { 3341 .label = "fan2:orange", 3342 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3343 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3344 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3345 .bit = BIT(1), 3346 }, 3347 { 3348 .label = "fan3:green", 3349 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3350 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3351 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3352 .bit = BIT(2), 3353 }, 3354 { 3355 .label = "fan3:orange", 3356 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3357 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3358 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3359 .bit = BIT(2), 3360 }, 3361 { 3362 .label = "fan4:green", 3363 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3364 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3365 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3366 .bit = BIT(3), 3367 }, 3368 { 3369 .label = "fan4:orange", 3370 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3371 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3372 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3373 .bit = BIT(3), 3374 }, 3375 { 3376 .label = "fan5:green", 3377 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3378 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3379 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3380 .bit = BIT(4), 3381 }, 3382 { 3383 .label = "fan5:orange", 3384 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3385 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3386 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3387 .bit = BIT(4), 3388 }, 3389 { 3390 .label = "fan6:green", 3391 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3392 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3393 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3394 .bit = BIT(5), 3395 }, 3396 { 3397 .label = "fan6:orange", 3398 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3399 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3400 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3401 .bit = BIT(5), 3402 }, 3403 { 3404 .label = "fan7:green", 3405 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3406 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3407 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3408 .bit = BIT(6), 3409 }, 3410 { 3411 .label = "fan7:orange", 3412 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3413 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3414 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3415 .bit = BIT(6), 3416 }, 3417 { 3418 .label = "uid:blue", 3419 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3420 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3421 }, 3422 }; 3423 3424 static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = { 3425 .data = mlxplat_mlxcpld_default_ng_led_data, 3426 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data), 3427 }; 3428 3429 /* Platform led for Comex based 100GbE systems */ 3430 static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = { 3431 { 3432 .label = "status:green", 3433 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3434 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3435 }, 3436 { 3437 .label = "status:red", 3438 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3439 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3440 }, 3441 { 3442 .label = "psu:green", 3443 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3444 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3445 }, 3446 { 3447 .label = "psu:red", 3448 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3449 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3450 }, 3451 { 3452 .label = "fan1:green", 3453 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3454 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3455 }, 3456 { 3457 .label = "fan1:red", 3458 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3459 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3460 }, 3461 { 3462 .label = "fan2:green", 3463 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3464 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3465 }, 3466 { 3467 .label = "fan2:red", 3468 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3469 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3470 }, 3471 { 3472 .label = "fan3:green", 3473 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3474 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3475 }, 3476 { 3477 .label = "fan3:red", 3478 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3479 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3480 }, 3481 { 3482 .label = "fan4:green", 3483 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3484 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3485 }, 3486 { 3487 .label = "fan4:red", 3488 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3489 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3490 }, 3491 { 3492 .label = "uid:blue", 3493 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3494 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3495 }, 3496 }; 3497 3498 static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = { 3499 .data = mlxplat_mlxcpld_comex_100G_led_data, 3500 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data), 3501 }; 3502 3503 /* Platform led for data for modular systems */ 3504 static struct mlxreg_core_data mlxplat_mlxcpld_modular_led_data[] = { 3505 { 3506 .label = "status:green", 3507 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3508 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3509 }, 3510 { 3511 .label = "status:orange", 3512 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3513 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3514 }, 3515 { 3516 .label = "psu:green", 3517 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3518 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3519 }, 3520 { 3521 .label = "psu:orange", 3522 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3523 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3524 }, 3525 { 3526 .label = "fan1:green", 3527 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3528 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3529 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3530 .bit = BIT(0), 3531 }, 3532 { 3533 .label = "fan1:orange", 3534 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3535 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3536 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3537 .bit = BIT(0), 3538 }, 3539 { 3540 .label = "fan2:green", 3541 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3542 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3543 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3544 .bit = BIT(1), 3545 }, 3546 { 3547 .label = "fan2:orange", 3548 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3549 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3550 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3551 .bit = BIT(1), 3552 }, 3553 { 3554 .label = "fan3:green", 3555 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3556 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3557 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3558 .bit = BIT(2), 3559 }, 3560 { 3561 .label = "fan3:orange", 3562 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3563 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3564 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3565 .bit = BIT(2), 3566 }, 3567 { 3568 .label = "fan4:green", 3569 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3570 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3571 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3572 .bit = BIT(3), 3573 }, 3574 { 3575 .label = "fan4:orange", 3576 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3577 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3578 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3579 .bit = BIT(3), 3580 }, 3581 { 3582 .label = "fan5:green", 3583 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3584 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3585 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3586 .bit = BIT(4), 3587 }, 3588 { 3589 .label = "fan5:orange", 3590 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3591 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3592 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3593 .bit = BIT(4), 3594 }, 3595 { 3596 .label = "fan6:green", 3597 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3598 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3599 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3600 .bit = BIT(5), 3601 }, 3602 { 3603 .label = "fan6:orange", 3604 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3605 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3606 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3607 .bit = BIT(5), 3608 }, 3609 { 3610 .label = "fan7:green", 3611 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3612 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3613 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3614 .bit = BIT(6), 3615 }, 3616 { 3617 .label = "fan7:orange", 3618 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3619 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3620 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3621 .bit = BIT(6), 3622 }, 3623 { 3624 .label = "uid:blue", 3625 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3626 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3627 }, 3628 { 3629 .label = "fan_front:green", 3630 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3631 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3632 }, 3633 { 3634 .label = "fan_front:orange", 3635 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3636 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3637 }, 3638 { 3639 .label = "mgmt:green", 3640 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3641 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3642 }, 3643 { 3644 .label = "mgmt:orange", 3645 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3646 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3647 }, 3648 }; 3649 3650 static struct mlxreg_core_platform_data mlxplat_modular_led_data = { 3651 .data = mlxplat_mlxcpld_modular_led_data, 3652 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_led_data), 3653 }; 3654 3655 /* Platform led data for chassis system */ 3656 static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { 3657 { 3658 .label = "status:green", 3659 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3660 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3661 }, 3662 { 3663 .label = "status:orange", 3664 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3665 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3666 }, 3667 { 3668 .label = "fan1:green", 3669 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3670 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3671 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3672 .bit = BIT(0), 3673 }, 3674 { 3675 .label = "fan1:orange", 3676 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3677 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3678 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3679 .bit = BIT(0), 3680 }, 3681 { 3682 .label = "fan2:green", 3683 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3684 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3685 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3686 .bit = BIT(1), 3687 }, 3688 { 3689 .label = "fan2:orange", 3690 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3691 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3692 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3693 .bit = BIT(1), 3694 }, 3695 { 3696 .label = "fan3:green", 3697 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3698 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3699 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3700 .bit = BIT(2), 3701 }, 3702 { 3703 .label = "fan3:orange", 3704 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3705 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3706 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3707 .bit = BIT(2), 3708 }, 3709 { 3710 .label = "fan4:green", 3711 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3712 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3713 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3714 .bit = BIT(3), 3715 }, 3716 { 3717 .label = "fan4:orange", 3718 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3719 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3720 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3721 .bit = BIT(3), 3722 }, 3723 { 3724 .label = "fan5:green", 3725 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3726 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3727 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3728 .bit = BIT(4), 3729 }, 3730 { 3731 .label = "fan5:orange", 3732 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3733 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3734 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3735 .bit = BIT(4), 3736 }, 3737 { 3738 .label = "fan6:green", 3739 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3740 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3741 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3742 .bit = BIT(5), 3743 }, 3744 { 3745 .label = "fan6:orange", 3746 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3747 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3748 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3749 .bit = BIT(5), 3750 }, 3751 { 3752 .label = "uid:blue", 3753 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3754 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3755 }, 3756 }; 3757 3758 static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = { 3759 .data = mlxplat_mlxcpld_l1_switch_led_data, 3760 .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data), 3761 }; 3762 3763 /* Platform led data for XDR and smart switch systems */ 3764 static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { 3765 { 3766 .label = "status:green", 3767 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3768 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3769 }, 3770 { 3771 .label = "status:orange", 3772 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3773 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3774 }, 3775 { 3776 .label = "psu:green", 3777 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3778 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3779 }, 3780 { 3781 .label = "psu:orange", 3782 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3783 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3784 }, 3785 { 3786 .label = "fan1:green", 3787 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3788 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3789 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3790 .slot = 1, 3791 }, 3792 { 3793 .label = "fan1:orange", 3794 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3795 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3796 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3797 .slot = 1, 3798 }, 3799 { 3800 .label = "fan2:green", 3801 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3802 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3803 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3804 .slot = 2, 3805 }, 3806 { 3807 .label = "fan2:orange", 3808 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3809 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3810 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3811 .slot = 2, 3812 }, 3813 { 3814 .label = "fan3:green", 3815 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3816 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3817 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3818 .slot = 3, 3819 }, 3820 { 3821 .label = "fan3:orange", 3822 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3823 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3824 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3825 .slot = 3, 3826 }, 3827 { 3828 .label = "fan4:green", 3829 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3830 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3831 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3832 .slot = 4, 3833 }, 3834 { 3835 .label = "fan4:orange", 3836 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3837 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3838 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3839 .slot = 4, 3840 }, 3841 { 3842 .label = "fan5:green", 3843 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3844 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3845 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3846 .slot = 5, 3847 }, 3848 { 3849 .label = "fan5:orange", 3850 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3851 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3852 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3853 .slot = 5, 3854 }, 3855 { 3856 .label = "fan6:green", 3857 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3858 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3859 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3860 .slot = 6, 3861 }, 3862 { 3863 .label = "fan6:orange", 3864 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3865 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3866 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3867 .slot = 6, 3868 }, 3869 { 3870 .label = "fan7:green", 3871 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3872 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3873 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3874 .slot = 7, 3875 }, 3876 { 3877 .label = "fan7:orange", 3878 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3879 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3880 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3881 .slot = 7, 3882 }, 3883 { 3884 .label = "fan8:green", 3885 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3886 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3887 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3888 .slot = 8, 3889 }, 3890 { 3891 .label = "fan8:orange", 3892 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3893 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3894 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3895 .slot = 8, 3896 }, 3897 { 3898 .label = "fan9:green", 3899 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3900 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3901 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3902 .slot = 9, 3903 }, 3904 { 3905 .label = "fan9:orange", 3906 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3907 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3908 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3909 .slot = 9, 3910 }, 3911 { 3912 .label = "fan10:green", 3913 .reg = MLXPLAT_CPLD_LPC_REG_LED8_OFFSET, 3914 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3915 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3916 .slot = 10, 3917 }, 3918 { 3919 .label = "fan10:orange", 3920 .reg = MLXPLAT_CPLD_LPC_REG_LED8_OFFSET, 3921 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3922 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3923 .slot = 10, 3924 }, 3925 { 3926 .label = "uid:blue", 3927 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3928 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3929 }, 3930 }; 3931 3932 static struct mlxreg_core_platform_data mlxplat_xdr_led_data = { 3933 .data = mlxplat_mlxcpld_xdr_led_data, 3934 .counter = ARRAY_SIZE(mlxplat_mlxcpld_xdr_led_data), 3935 }; 3936 3937 /* Platform register access default */ 3938 static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { 3939 { 3940 .label = "cpld1_version", 3941 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 3942 .bit = GENMASK(7, 0), 3943 .mode = 0444, 3944 }, 3945 { 3946 .label = "cpld2_version", 3947 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 3948 .bit = GENMASK(7, 0), 3949 .mode = 0444, 3950 }, 3951 { 3952 .label = "cpld1_pn", 3953 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 3954 .bit = GENMASK(15, 0), 3955 .mode = 0444, 3956 .regnum = 2, 3957 }, 3958 { 3959 .label = "cpld2_pn", 3960 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 3961 .bit = GENMASK(15, 0), 3962 .mode = 0444, 3963 .regnum = 2, 3964 }, 3965 { 3966 .label = "cpld1_version_min", 3967 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 3968 .bit = GENMASK(7, 0), 3969 .mode = 0444, 3970 }, 3971 { 3972 .label = "cpld2_version_min", 3973 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 3974 .bit = GENMASK(7, 0), 3975 .mode = 0444, 3976 }, 3977 { 3978 .label = "reset_long_pb", 3979 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3980 .mask = GENMASK(7, 0) & ~BIT(0), 3981 .mode = 0444, 3982 }, 3983 { 3984 .label = "reset_short_pb", 3985 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3986 .mask = GENMASK(7, 0) & ~BIT(1), 3987 .mode = 0444, 3988 }, 3989 { 3990 .label = "reset_aux_pwr_or_ref", 3991 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3992 .mask = GENMASK(7, 0) & ~BIT(2), 3993 .mode = 0444, 3994 }, 3995 { 3996 .label = "reset_main_pwr_fail", 3997 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3998 .mask = GENMASK(7, 0) & ~BIT(3), 3999 .mode = 0444, 4000 }, 4001 { 4002 .label = "reset_sw_reset", 4003 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4004 .mask = GENMASK(7, 0) & ~BIT(4), 4005 .mode = 0444, 4006 }, 4007 { 4008 .label = "reset_fw_reset", 4009 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4010 .mask = GENMASK(7, 0) & ~BIT(5), 4011 .mode = 0444, 4012 }, 4013 { 4014 .label = "reset_hotswap_or_wd", 4015 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4016 .mask = GENMASK(7, 0) & ~BIT(6), 4017 .mode = 0444, 4018 }, 4019 { 4020 .label = "reset_asic_thermal", 4021 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4022 .mask = GENMASK(7, 0) & ~BIT(7), 4023 .mode = 0444, 4024 }, 4025 { 4026 .label = "psu1_on", 4027 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4028 .mask = GENMASK(7, 0) & ~BIT(0), 4029 .mode = 0200, 4030 }, 4031 { 4032 .label = "psu2_on", 4033 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4034 .mask = GENMASK(7, 0) & ~BIT(1), 4035 .mode = 0200, 4036 }, 4037 { 4038 .label = "pwr_cycle", 4039 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4040 .mask = GENMASK(7, 0) & ~BIT(2), 4041 .mode = 0200, 4042 }, 4043 { 4044 .label = "pwr_down", 4045 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4046 .mask = GENMASK(7, 0) & ~BIT(3), 4047 .mode = 0200, 4048 }, 4049 { 4050 .label = "select_iio", 4051 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 4052 .mask = GENMASK(7, 0) & ~BIT(6), 4053 .mode = 0644, 4054 }, 4055 { 4056 .label = "asic_health", 4057 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 4058 .mask = MLXPLAT_CPLD_ASIC_MASK, 4059 .bit = 1, 4060 .mode = 0444, 4061 }, 4062 }; 4063 4064 static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = { 4065 .data = mlxplat_mlxcpld_default_regs_io_data, 4066 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data), 4067 }; 4068 4069 /* Platform register access MSN21xx, MSN201x, MSN274x systems families data */ 4070 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { 4071 { 4072 .label = "cpld1_version", 4073 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 4074 .bit = GENMASK(7, 0), 4075 .mode = 0444, 4076 }, 4077 { 4078 .label = "cpld2_version", 4079 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 4080 .bit = GENMASK(7, 0), 4081 .mode = 0444, 4082 }, 4083 { 4084 .label = "cpld1_pn", 4085 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 4086 .bit = GENMASK(15, 0), 4087 .mode = 0444, 4088 .regnum = 2, 4089 }, 4090 { 4091 .label = "cpld2_pn", 4092 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 4093 .bit = GENMASK(15, 0), 4094 .mode = 0444, 4095 .regnum = 2, 4096 }, 4097 { 4098 .label = "cpld1_version_min", 4099 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 4100 .bit = GENMASK(7, 0), 4101 .mode = 0444, 4102 }, 4103 { 4104 .label = "cpld2_version_min", 4105 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 4106 .bit = GENMASK(7, 0), 4107 .mode = 0444, 4108 }, 4109 { 4110 .label = "reset_long_pb", 4111 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4112 .mask = GENMASK(7, 0) & ~BIT(0), 4113 .mode = 0444, 4114 }, 4115 { 4116 .label = "reset_short_pb", 4117 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4118 .mask = GENMASK(7, 0) & ~BIT(1), 4119 .mode = 0444, 4120 }, 4121 { 4122 .label = "reset_aux_pwr_or_ref", 4123 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4124 .mask = GENMASK(7, 0) & ~BIT(2), 4125 .mode = 0444, 4126 }, 4127 { 4128 .label = "reset_sw_reset", 4129 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4130 .mask = GENMASK(7, 0) & ~BIT(3), 4131 .mode = 0444, 4132 }, 4133 { 4134 .label = "reset_main_pwr_fail", 4135 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4136 .mask = GENMASK(7, 0) & ~BIT(4), 4137 .mode = 0444, 4138 }, 4139 { 4140 .label = "reset_asic_thermal", 4141 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4142 .mask = GENMASK(7, 0) & ~BIT(5), 4143 .mode = 0444, 4144 }, 4145 { 4146 .label = "reset_hotswap_or_halt", 4147 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4148 .mask = GENMASK(7, 0) & ~BIT(6), 4149 .mode = 0444, 4150 }, 4151 { 4152 .label = "reset_sff_wd", 4153 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4154 .mask = GENMASK(7, 0) & ~BIT(6), 4155 .mode = 0444, 4156 }, 4157 { 4158 .label = "psu1_on", 4159 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4160 .mask = GENMASK(7, 0) & ~BIT(0), 4161 .mode = 0200, 4162 }, 4163 { 4164 .label = "psu2_on", 4165 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4166 .mask = GENMASK(7, 0) & ~BIT(1), 4167 .mode = 0200, 4168 }, 4169 { 4170 .label = "pwr_cycle", 4171 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4172 .mask = GENMASK(7, 0) & ~BIT(2), 4173 .mode = 0200, 4174 }, 4175 { 4176 .label = "pwr_down", 4177 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4178 .mask = GENMASK(7, 0) & ~BIT(3), 4179 .mode = 0200, 4180 }, 4181 { 4182 .label = "select_iio", 4183 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 4184 .mask = GENMASK(7, 0) & ~BIT(6), 4185 .mode = 0644, 4186 }, 4187 { 4188 .label = "asic_health", 4189 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 4190 .mask = MLXPLAT_CPLD_ASIC_MASK, 4191 .bit = 1, 4192 .mode = 0444, 4193 }, 4194 }; 4195 4196 static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = { 4197 .data = mlxplat_mlxcpld_msn21xx_regs_io_data, 4198 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data), 4199 }; 4200 4201 /* Platform register access for next generation systems families data */ 4202 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { 4203 { 4204 .label = "cpld1_version", 4205 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 4206 .bit = GENMASK(7, 0), 4207 .mode = 0444, 4208 }, 4209 { 4210 .label = "cpld2_version", 4211 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 4212 .bit = GENMASK(7, 0), 4213 .mode = 0444, 4214 }, 4215 { 4216 .label = "cpld3_version", 4217 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 4218 .bit = GENMASK(7, 0), 4219 .mode = 0444, 4220 }, 4221 { 4222 .label = "cpld4_version", 4223 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 4224 .bit = GENMASK(7, 0), 4225 .mode = 0444, 4226 }, 4227 { 4228 .label = "cpld5_version", 4229 .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET, 4230 .bit = GENMASK(7, 0), 4231 .mode = 0444, 4232 }, 4233 { 4234 .label = "cpld1_pn", 4235 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 4236 .bit = GENMASK(15, 0), 4237 .mode = 0444, 4238 .regnum = 2, 4239 }, 4240 { 4241 .label = "cpld2_pn", 4242 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 4243 .bit = GENMASK(15, 0), 4244 .mode = 0444, 4245 .regnum = 2, 4246 }, 4247 { 4248 .label = "cpld3_pn", 4249 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 4250 .bit = GENMASK(15, 0), 4251 .mode = 0444, 4252 .regnum = 2, 4253 }, 4254 { 4255 .label = "cpld4_pn", 4256 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 4257 .bit = GENMASK(15, 0), 4258 .mode = 0444, 4259 .regnum = 2, 4260 }, 4261 { 4262 .label = "cpld5_pn", 4263 .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET, 4264 .bit = GENMASK(15, 0), 4265 .mode = 0444, 4266 .regnum = 2, 4267 }, 4268 { 4269 .label = "cpld1_version_min", 4270 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 4271 .bit = GENMASK(7, 0), 4272 .mode = 0444, 4273 }, 4274 { 4275 .label = "cpld2_version_min", 4276 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 4277 .bit = GENMASK(7, 0), 4278 .mode = 0444, 4279 }, 4280 { 4281 .label = "cpld3_version_min", 4282 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 4283 .bit = GENMASK(7, 0), 4284 .mode = 0444, 4285 }, 4286 { 4287 .label = "cpld4_version_min", 4288 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 4289 .bit = GENMASK(7, 0), 4290 .mode = 0444, 4291 }, 4292 { 4293 .label = "cpld5_version_min", 4294 .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET, 4295 .bit = GENMASK(7, 0), 4296 .mode = 0444, 4297 }, 4298 { 4299 .label = "asic_reset", 4300 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 4301 .mask = GENMASK(7, 0) & ~BIT(3), 4302 .mode = 0200, 4303 }, 4304 { 4305 .label = "asic2_reset", 4306 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 4307 .mask = GENMASK(7, 0) & ~BIT(2), 4308 .mode = 0200, 4309 }, 4310 { 4311 .label = "erot1_reset", 4312 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 4313 .mask = GENMASK(7, 0) & ~BIT(6), 4314 .mode = 0644, 4315 }, 4316 { 4317 .label = "erot2_reset", 4318 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 4319 .mask = GENMASK(7, 0) & ~BIT(7), 4320 .mode = 0644, 4321 }, 4322 { 4323 .label = "clk_brd_prog_en", 4324 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 4325 .mask = GENMASK(7, 0) & ~BIT(1), 4326 .mode = 0644, 4327 .secured = 1, 4328 }, 4329 { 4330 .label = "erot1_recovery", 4331 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 4332 .mask = GENMASK(7, 0) & ~BIT(6), 4333 .mode = 0644, 4334 }, 4335 { 4336 .label = "erot2_recovery", 4337 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 4338 .mask = GENMASK(7, 0) & ~BIT(7), 4339 .mode = 0644, 4340 }, 4341 { 4342 .label = "erot1_wp", 4343 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 4344 .mask = GENMASK(7, 0) & ~BIT(4), 4345 .mode = 0644, 4346 .secured = 1, 4347 }, 4348 { 4349 .label = "erot2_wp", 4350 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 4351 .mask = GENMASK(7, 0) & ~BIT(5), 4352 .mode = 0644, 4353 .secured = 1, 4354 }, 4355 { 4356 .label = "reset_long_pb", 4357 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4358 .mask = GENMASK(7, 0) & ~BIT(0), 4359 .mode = 0444, 4360 }, 4361 { 4362 .label = "reset_short_pb", 4363 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4364 .mask = GENMASK(7, 0) & ~BIT(1), 4365 .mode = 0444, 4366 }, 4367 { 4368 .label = "reset_aux_pwr_or_ref", 4369 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4370 .mask = GENMASK(7, 0) & ~BIT(2), 4371 .mode = 0444, 4372 }, 4373 { 4374 .label = "reset_swb_dc_dc_pwr_fail", 4375 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4376 .mask = GENMASK(7, 0) & ~BIT(3), 4377 .mode = 0444, 4378 }, 4379 { 4380 .label = "reset_from_asic", 4381 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4382 .mask = GENMASK(7, 0) & ~BIT(5), 4383 .mode = 0444, 4384 }, 4385 { 4386 .label = "reset_swb_wd", 4387 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4388 .mask = GENMASK(7, 0) & ~BIT(6), 4389 .mode = 0444, 4390 }, 4391 { 4392 .label = "reset_asic_thermal", 4393 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4394 .mask = GENMASK(7, 0) & ~BIT(7), 4395 .mode = 0444, 4396 }, 4397 { 4398 .label = "reset_sw_reset", 4399 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4400 .mask = GENMASK(7, 0) & ~BIT(0), 4401 .mode = 0444, 4402 }, 4403 { 4404 .label = "reset_comex_pwr_fail", 4405 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4406 .mask = GENMASK(7, 0) & ~BIT(3), 4407 .mode = 0444, 4408 }, 4409 { 4410 .label = "reset_platform", 4411 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4412 .mask = GENMASK(7, 0) & ~BIT(4), 4413 .mode = 0444, 4414 }, 4415 { 4416 .label = "reset_soc", 4417 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4418 .mask = GENMASK(7, 0) & ~BIT(5), 4419 .mode = 0444, 4420 }, 4421 { 4422 .label = "reset_comex_wd", 4423 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4424 .mask = GENMASK(7, 0) & ~BIT(6), 4425 .mode = 0444, 4426 }, 4427 { 4428 .label = "reset_pwr_converter_fail", 4429 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4430 .mask = GENMASK(7, 0) & ~BIT(0), 4431 .mode = 0444, 4432 }, 4433 { 4434 .label = "reset_system", 4435 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4436 .mask = GENMASK(7, 0) & ~BIT(1), 4437 .mode = 0444, 4438 }, 4439 { 4440 .label = "reset_sw_pwr_off", 4441 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4442 .mask = GENMASK(7, 0) & ~BIT(2), 4443 .mode = 0444, 4444 }, 4445 { 4446 .label = "reset_comex_thermal", 4447 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4448 .mask = GENMASK(7, 0) & ~BIT(3), 4449 .mode = 0444, 4450 }, 4451 { 4452 .label = "reset_reload_bios", 4453 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4454 .mask = GENMASK(7, 0) & ~BIT(5), 4455 .mode = 0444, 4456 }, 4457 { 4458 .label = "reset_ac_pwr_fail", 4459 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4460 .mask = GENMASK(7, 0) & ~BIT(6), 4461 .mode = 0444, 4462 }, 4463 { 4464 .label = "reset_ac_ok_fail", 4465 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4466 .mask = GENMASK(7, 0) & ~BIT(7), 4467 .mode = 0444, 4468 }, 4469 { 4470 .label = "psu1_on", 4471 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4472 .mask = GENMASK(7, 0) & ~BIT(0), 4473 .mode = 0200, 4474 }, 4475 { 4476 .label = "psu2_on", 4477 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4478 .mask = GENMASK(7, 0) & ~BIT(1), 4479 .mode = 0200, 4480 }, 4481 { 4482 .label = "pwr_cycle", 4483 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4484 .mask = GENMASK(7, 0) & ~BIT(2), 4485 .mode = 0200, 4486 }, 4487 { 4488 .label = "pwr_down", 4489 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4490 .mask = GENMASK(7, 0) & ~BIT(3), 4491 .mode = 0200, 4492 }, 4493 { 4494 .label = "deep_pwr_cycle", 4495 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4496 .mask = GENMASK(7, 0) & ~BIT(5), 4497 .mode = 0200, 4498 }, 4499 { 4500 .label = "latch_reset", 4501 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4502 .mask = GENMASK(7, 0) & ~BIT(6), 4503 .mode = 0200, 4504 }, 4505 { 4506 .label = "jtag_cap", 4507 .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET, 4508 .mask = MLXPLAT_CPLD_FU_CAP_MASK, 4509 .bit = 1, 4510 .mode = 0444, 4511 }, 4512 { 4513 .label = "jtag_enable", 4514 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 4515 .mask = GENMASK(7, 0) & ~BIT(4), 4516 .mode = 0644, 4517 }, 4518 { 4519 .label = "dbg1", 4520 .reg = MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET, 4521 .bit = GENMASK(7, 0), 4522 .mode = 0644, 4523 }, 4524 { 4525 .label = "dbg2", 4526 .reg = MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET, 4527 .bit = GENMASK(7, 0), 4528 .mode = 0644, 4529 }, 4530 { 4531 .label = "dbg3", 4532 .reg = MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET, 4533 .bit = GENMASK(7, 0), 4534 .mode = 0644, 4535 }, 4536 { 4537 .label = "dbg4", 4538 .reg = MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET, 4539 .bit = GENMASK(7, 0), 4540 .mode = 0644, 4541 }, 4542 { 4543 .label = "asic_health", 4544 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 4545 .mask = MLXPLAT_CPLD_ASIC_MASK, 4546 .bit = 1, 4547 .mode = 0444, 4548 }, 4549 { 4550 .label = "asic2_health", 4551 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, 4552 .mask = MLXPLAT_CPLD_ASIC_MASK, 4553 .bit = 1, 4554 .mode = 0444, 4555 }, 4556 { 4557 .label = "fan_dir", 4558 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 4559 .bit = GENMASK(7, 0), 4560 .mode = 0444, 4561 }, 4562 { 4563 .label = "bios_safe_mode", 4564 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4565 .mask = GENMASK(7, 0) & ~BIT(4), 4566 .mode = 0444, 4567 }, 4568 { 4569 .label = "bios_active_image", 4570 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4571 .mask = GENMASK(7, 0) & ~BIT(5), 4572 .mode = 0444, 4573 }, 4574 { 4575 .label = "bios_auth_fail", 4576 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4577 .mask = GENMASK(7, 0) & ~BIT(6), 4578 .mode = 0444, 4579 }, 4580 { 4581 .label = "bios_upgrade_fail", 4582 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4583 .mask = GENMASK(7, 0) & ~BIT(7), 4584 .mode = 0444, 4585 }, 4586 { 4587 .label = "voltreg_update_status", 4588 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 4589 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 4590 .bit = 5, 4591 .mode = 0444, 4592 }, 4593 { 4594 .label = "pwr_converter_prog_en", 4595 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4596 .mask = GENMASK(7, 0) & ~BIT(0), 4597 .mode = 0644, 4598 .secured = 1, 4599 }, 4600 { 4601 .label = "vpd_wp", 4602 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4603 .mask = GENMASK(7, 0) & ~BIT(3), 4604 .mode = 0644, 4605 }, 4606 { 4607 .label = "pcie_asic_reset_dis", 4608 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4609 .mask = GENMASK(7, 0) & ~BIT(4), 4610 .mode = 0644, 4611 }, 4612 { 4613 .label = "shutdown_unlock", 4614 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4615 .mask = GENMASK(7, 0) & ~BIT(5), 4616 .mode = 0644, 4617 }, 4618 { 4619 .label = "erot1_ap_reset", 4620 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 4621 .mask = GENMASK(7, 0) & ~BIT(0), 4622 .mode = 0444, 4623 }, 4624 { 4625 .label = "erot2_ap_reset", 4626 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 4627 .mask = GENMASK(7, 0) & ~BIT(1), 4628 .mode = 0444, 4629 }, 4630 { 4631 .label = "lid_open", 4632 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 4633 .mask = GENMASK(7, 0) & ~BIT(2), 4634 .mode = 0444, 4635 }, 4636 { 4637 .label = "clk_brd1_boot_fail", 4638 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 4639 .mask = GENMASK(7, 0) & ~BIT(4), 4640 .mode = 0444, 4641 }, 4642 { 4643 .label = "clk_brd2_boot_fail", 4644 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 4645 .mask = GENMASK(7, 0) & ~BIT(5), 4646 .mode = 0444, 4647 }, 4648 { 4649 .label = "clk_brd_fail", 4650 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 4651 .mask = GENMASK(7, 0) & ~BIT(6), 4652 .mode = 0444, 4653 }, 4654 { 4655 .label = "asic_pg_fail", 4656 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 4657 .mask = GENMASK(7, 0) & ~BIT(7), 4658 .mode = 0444, 4659 }, 4660 { 4661 .label = "spi_chnl_select", 4662 .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT, 4663 .mask = GENMASK(7, 0), 4664 .bit = 1, 4665 .mode = 0644, 4666 }, 4667 { 4668 .label = "config1", 4669 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 4670 .bit = GENMASK(7, 0), 4671 .mode = 0444, 4672 }, 4673 { 4674 .label = "config2", 4675 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 4676 .bit = GENMASK(7, 0), 4677 .mode = 0444, 4678 }, 4679 { 4680 .label = "config3", 4681 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 4682 .bit = GENMASK(7, 0), 4683 .mode = 0444, 4684 }, 4685 { 4686 .label = "ufm_version", 4687 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 4688 .bit = GENMASK(7, 0), 4689 .mode = 0444, 4690 }, 4691 }; 4692 4693 static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { 4694 .data = mlxplat_mlxcpld_default_ng_regs_io_data, 4695 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data), 4696 }; 4697 4698 /* Platform register access for next generation systems families data */ 4699 static struct mlxreg_core_data mlxplat_mlxcpld_dgx_ng_regs_io_data[] = { 4700 { 4701 .label = "cpld1_version", 4702 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 4703 .bit = GENMASK(7, 0), 4704 .mode = 0444, 4705 }, 4706 { 4707 .label = "cpld2_version", 4708 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 4709 .bit = GENMASK(7, 0), 4710 .mode = 0444, 4711 }, 4712 { 4713 .label = "cpld3_version", 4714 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 4715 .bit = GENMASK(7, 0), 4716 .mode = 0444, 4717 }, 4718 { 4719 .label = "cpld4_version", 4720 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 4721 .bit = GENMASK(7, 0), 4722 .mode = 0444, 4723 }, 4724 { 4725 .label = "cpld1_pn", 4726 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 4727 .bit = GENMASK(15, 0), 4728 .mode = 0444, 4729 .regnum = 2, 4730 }, 4731 { 4732 .label = "cpld2_pn", 4733 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 4734 .bit = GENMASK(15, 0), 4735 .mode = 0444, 4736 .regnum = 2, 4737 }, 4738 { 4739 .label = "cpld3_pn", 4740 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 4741 .bit = GENMASK(15, 0), 4742 .mode = 0444, 4743 .regnum = 2, 4744 }, 4745 { 4746 .label = "cpld4_pn", 4747 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 4748 .bit = GENMASK(15, 0), 4749 .mode = 0444, 4750 .regnum = 2, 4751 }, 4752 { 4753 .label = "cpld1_version_min", 4754 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 4755 .bit = GENMASK(7, 0), 4756 .mode = 0444, 4757 }, 4758 { 4759 .label = "cpld2_version_min", 4760 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 4761 .bit = GENMASK(7, 0), 4762 .mode = 0444, 4763 }, 4764 { 4765 .label = "cpld3_version_min", 4766 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 4767 .bit = GENMASK(7, 0), 4768 .mode = 0444, 4769 }, 4770 { 4771 .label = "cpld4_version_min", 4772 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 4773 .bit = GENMASK(7, 0), 4774 .mode = 0444, 4775 }, 4776 { 4777 .label = "asic_reset", 4778 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 4779 .mask = GENMASK(7, 0) & ~BIT(3), 4780 .mode = 0200, 4781 }, 4782 { 4783 .label = "reset_long_pb", 4784 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4785 .mask = GENMASK(7, 0) & ~BIT(0), 4786 .mode = 0444, 4787 }, 4788 { 4789 .label = "reset_short_pb", 4790 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4791 .mask = GENMASK(7, 0) & ~BIT(1), 4792 .mode = 0444, 4793 }, 4794 { 4795 .label = "reset_aux_pwr_or_ref", 4796 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4797 .mask = GENMASK(7, 0) & ~BIT(2), 4798 .mode = 0444, 4799 }, 4800 { 4801 .label = "reset_swb_dc_dc_pwr_fail", 4802 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4803 .mask = GENMASK(7, 0) & ~BIT(3), 4804 .mode = 0444, 4805 }, 4806 { 4807 .label = "reset_from_asic", 4808 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4809 .mask = GENMASK(7, 0) & ~BIT(5), 4810 .mode = 0444, 4811 }, 4812 { 4813 .label = "reset_swb_wd", 4814 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4815 .mask = GENMASK(7, 0) & ~BIT(6), 4816 .mode = 0444, 4817 }, 4818 { 4819 .label = "reset_asic_thermal", 4820 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4821 .mask = GENMASK(7, 0) & ~BIT(7), 4822 .mode = 0444, 4823 }, 4824 { 4825 .label = "reset_sw_reset", 4826 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4827 .mask = GENMASK(7, 0) & ~BIT(0), 4828 .mode = 0444, 4829 }, 4830 { 4831 .label = "reset_comex_pwr_fail", 4832 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4833 .mask = GENMASK(7, 0) & ~BIT(3), 4834 .mode = 0444, 4835 }, 4836 { 4837 .label = "reset_platform", 4838 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4839 .mask = GENMASK(7, 0) & ~BIT(4), 4840 .mode = 0444, 4841 }, 4842 { 4843 .label = "reset_soc", 4844 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4845 .mask = GENMASK(7, 0) & ~BIT(5), 4846 .mode = 0444, 4847 }, 4848 { 4849 .label = "reset_comex_wd", 4850 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4851 .mask = GENMASK(7, 0) & ~BIT(6), 4852 .mode = 0444, 4853 }, 4854 { 4855 .label = "reset_system", 4856 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4857 .mask = GENMASK(7, 0) & ~BIT(1), 4858 .mode = 0444, 4859 }, 4860 { 4861 .label = "reset_sw_pwr_off", 4862 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4863 .mask = GENMASK(7, 0) & ~BIT(2), 4864 .mode = 0444, 4865 }, 4866 { 4867 .label = "reset_comex_thermal", 4868 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4869 .mask = GENMASK(7, 0) & ~BIT(3), 4870 .mode = 0444, 4871 }, 4872 { 4873 .label = "reset_reload_bios", 4874 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4875 .mask = GENMASK(7, 0) & ~BIT(5), 4876 .mode = 0444, 4877 }, 4878 { 4879 .label = "reset_pdb_pwr_fail", 4880 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4881 .mask = GENMASK(7, 0) & ~BIT(6), 4882 .mode = 0444, 4883 }, 4884 { 4885 .label = "pdb_reset_stby", 4886 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4887 .mask = GENMASK(7, 0) & ~BIT(0), 4888 .mode = 0200, 4889 }, 4890 { 4891 .label = "pwr_cycle", 4892 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4893 .mask = GENMASK(7, 0) & ~BIT(2), 4894 .mode = 0200, 4895 }, 4896 { 4897 .label = "pwr_down", 4898 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4899 .mask = GENMASK(7, 0) & ~BIT(3), 4900 .mode = 0200, 4901 }, 4902 { 4903 .label = "deep_pwr_cycle", 4904 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4905 .mask = GENMASK(7, 0) & ~BIT(5), 4906 .mode = 0200, 4907 }, 4908 { 4909 .label = "latch_reset", 4910 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4911 .mask = GENMASK(7, 0) & ~BIT(6), 4912 .mode = 0200, 4913 }, 4914 { 4915 .label = "jtag_cap", 4916 .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET, 4917 .mask = MLXPLAT_CPLD_FU_CAP_MASK, 4918 .bit = 1, 4919 .mode = 0444, 4920 }, 4921 { 4922 .label = "jtag_enable", 4923 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 4924 .mask = GENMASK(7, 0) & ~BIT(4), 4925 .mode = 0644, 4926 }, 4927 { 4928 .label = "dbg1", 4929 .reg = MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET, 4930 .bit = GENMASK(7, 0), 4931 .mode = 0644, 4932 }, 4933 { 4934 .label = "dbg2", 4935 .reg = MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET, 4936 .bit = GENMASK(7, 0), 4937 .mode = 0644, 4938 }, 4939 { 4940 .label = "dbg3", 4941 .reg = MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET, 4942 .bit = GENMASK(7, 0), 4943 .mode = 0644, 4944 }, 4945 { 4946 .label = "dbg4", 4947 .reg = MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET, 4948 .bit = GENMASK(7, 0), 4949 .mode = 0644, 4950 }, 4951 { 4952 .label = "asic_health", 4953 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 4954 .mask = MLXPLAT_CPLD_ASIC_MASK, 4955 .bit = 1, 4956 .mode = 0444, 4957 }, 4958 { 4959 .label = "fan_dir", 4960 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 4961 .bit = GENMASK(7, 0), 4962 .mode = 0444, 4963 }, 4964 { 4965 .label = "bios_safe_mode", 4966 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4967 .mask = GENMASK(7, 0) & ~BIT(4), 4968 .mode = 0444, 4969 }, 4970 { 4971 .label = "bios_active_image", 4972 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4973 .mask = GENMASK(7, 0) & ~BIT(5), 4974 .mode = 0444, 4975 }, 4976 { 4977 .label = "bios_auth_fail", 4978 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4979 .mask = GENMASK(7, 0) & ~BIT(6), 4980 .mode = 0444, 4981 }, 4982 { 4983 .label = "bios_upgrade_fail", 4984 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4985 .mask = GENMASK(7, 0) & ~BIT(7), 4986 .mode = 0444, 4987 }, 4988 { 4989 .label = "voltreg_update_status", 4990 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 4991 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 4992 .bit = 5, 4993 .mode = 0444, 4994 }, 4995 { 4996 .label = "pwr_converter_prog_en", 4997 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4998 .mask = GENMASK(7, 0) & ~BIT(0), 4999 .mode = 0644, 5000 .secured = 1, 5001 }, 5002 { 5003 .label = "vpd_wp", 5004 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 5005 .mask = GENMASK(7, 0) & ~BIT(3), 5006 .mode = 0644, 5007 }, 5008 { 5009 .label = "pcie_asic_reset_dis", 5010 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 5011 .mask = GENMASK(7, 0) & ~BIT(4), 5012 .mode = 0644, 5013 }, 5014 { 5015 .label = "shutdown_unlock", 5016 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 5017 .mask = GENMASK(7, 0) & ~BIT(5), 5018 .mode = 0644, 5019 }, 5020 { 5021 .label = "config1", 5022 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 5023 .bit = GENMASK(7, 0), 5024 .mode = 0444, 5025 }, 5026 { 5027 .label = "config2", 5028 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 5029 .bit = GENMASK(7, 0), 5030 .mode = 0444, 5031 }, 5032 { 5033 .label = "config3", 5034 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 5035 .bit = GENMASK(7, 0), 5036 .mode = 0444, 5037 }, 5038 { 5039 .label = "ufm_version", 5040 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 5041 .bit = GENMASK(7, 0), 5042 .mode = 0444, 5043 }, 5044 }; 5045 5046 static struct mlxreg_core_platform_data mlxplat_dgx_ng_regs_io_data = { 5047 .data = mlxplat_mlxcpld_dgx_ng_regs_io_data, 5048 .counter = ARRAY_SIZE(mlxplat_mlxcpld_dgx_ng_regs_io_data), 5049 }; 5050 5051 /* Platform register access for modular systems families data */ 5052 static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { 5053 { 5054 .label = "cpld1_version", 5055 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 5056 .bit = GENMASK(7, 0), 5057 .mode = 0444, 5058 }, 5059 { 5060 .label = "cpld2_version", 5061 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 5062 .bit = GENMASK(7, 0), 5063 .mode = 0444, 5064 }, 5065 { 5066 .label = "cpld3_version", 5067 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 5068 .bit = GENMASK(7, 0), 5069 .mode = 0444, 5070 }, 5071 { 5072 .label = "cpld4_version", 5073 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 5074 .bit = GENMASK(7, 0), 5075 .mode = 0444, 5076 }, 5077 { 5078 .label = "cpld1_pn", 5079 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 5080 .bit = GENMASK(15, 0), 5081 .mode = 0444, 5082 .regnum = 2, 5083 }, 5084 { 5085 .label = "cpld2_pn", 5086 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 5087 .bit = GENMASK(15, 0), 5088 .mode = 0444, 5089 .regnum = 2, 5090 }, 5091 { 5092 .label = "cpld3_pn", 5093 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 5094 .bit = GENMASK(15, 0), 5095 .mode = 0444, 5096 .regnum = 2, 5097 }, 5098 { 5099 .label = "cpld4_pn", 5100 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 5101 .bit = GENMASK(15, 0), 5102 .mode = 0444, 5103 .regnum = 2, 5104 }, 5105 { 5106 .label = "cpld1_version_min", 5107 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 5108 .bit = GENMASK(7, 0), 5109 .mode = 0444, 5110 }, 5111 { 5112 .label = "cpld2_version_min", 5113 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 5114 .bit = GENMASK(7, 0), 5115 .mode = 0444, 5116 }, 5117 { 5118 .label = "cpld3_version_min", 5119 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 5120 .bit = GENMASK(7, 0), 5121 .mode = 0444, 5122 }, 5123 { 5124 .label = "cpld4_version_min", 5125 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 5126 .bit = GENMASK(7, 0), 5127 .mode = 0444, 5128 }, 5129 { 5130 .label = "lc1_enable", 5131 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5132 .mask = GENMASK(7, 0) & ~BIT(0), 5133 .mode = 0644, 5134 }, 5135 { 5136 .label = "lc2_enable", 5137 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5138 .mask = GENMASK(7, 0) & ~BIT(1), 5139 .mode = 0644, 5140 }, 5141 { 5142 .label = "lc3_enable", 5143 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5144 .mask = GENMASK(7, 0) & ~BIT(2), 5145 .mode = 0644, 5146 }, 5147 { 5148 .label = "lc4_enable", 5149 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5150 .mask = GENMASK(7, 0) & ~BIT(3), 5151 .mode = 0644, 5152 }, 5153 { 5154 .label = "lc5_enable", 5155 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5156 .mask = GENMASK(7, 0) & ~BIT(4), 5157 .mode = 0644, 5158 }, 5159 { 5160 .label = "lc6_enable", 5161 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5162 .mask = GENMASK(7, 0) & ~BIT(5), 5163 .mode = 0644, 5164 }, 5165 { 5166 .label = "lc7_enable", 5167 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5168 .mask = GENMASK(7, 0) & ~BIT(6), 5169 .mode = 0644, 5170 }, 5171 { 5172 .label = "lc8_enable", 5173 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5174 .mask = GENMASK(7, 0) & ~BIT(7), 5175 .mode = 0644, 5176 }, 5177 { 5178 .label = "reset_long_pb", 5179 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5180 .mask = GENMASK(7, 0) & ~BIT(0), 5181 .mode = 0444, 5182 }, 5183 { 5184 .label = "reset_short_pb", 5185 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5186 .mask = GENMASK(7, 0) & ~BIT(1), 5187 .mode = 0444, 5188 }, 5189 { 5190 .label = "reset_aux_pwr_or_fu", 5191 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5192 .mask = GENMASK(7, 0) & ~BIT(2), 5193 .mode = 0444, 5194 }, 5195 { 5196 .label = "reset_mgmt_dc_dc_pwr_fail", 5197 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5198 .mask = GENMASK(7, 0) & ~BIT(3), 5199 .mode = 0444, 5200 }, 5201 { 5202 .label = "reset_sys_comex_bios", 5203 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5204 .mask = GENMASK(7, 0) & ~BIT(5), 5205 .mode = 0444, 5206 }, 5207 { 5208 .label = "reset_sw_reset", 5209 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5210 .mask = GENMASK(7, 0) & ~BIT(0), 5211 .mode = 0444, 5212 }, 5213 { 5214 .label = "reset_aux_pwr_or_reload", 5215 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5216 .mask = GENMASK(7, 0) & ~BIT(2), 5217 .mode = 0444, 5218 }, 5219 { 5220 .label = "reset_comex_pwr_fail", 5221 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5222 .mask = GENMASK(7, 0) & ~BIT(3), 5223 .mode = 0444, 5224 }, 5225 { 5226 .label = "reset_platform", 5227 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5228 .mask = GENMASK(7, 0) & ~BIT(4), 5229 .mode = 0444, 5230 }, 5231 { 5232 .label = "reset_soc", 5233 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5234 .mask = GENMASK(7, 0) & ~BIT(5), 5235 .mode = 0444, 5236 }, 5237 { 5238 .label = "reset_pwr_off_from_carrier", 5239 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5240 .mask = GENMASK(7, 0) & ~BIT(7), 5241 .mode = 0444, 5242 }, 5243 { 5244 .label = "reset_swb_wd", 5245 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5246 .mask = GENMASK(7, 0) & ~BIT(0), 5247 .mode = 0444, 5248 }, 5249 { 5250 .label = "reset_swb_aux_pwr_or_fu", 5251 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5252 .mask = GENMASK(7, 0) & ~BIT(2), 5253 .mode = 0444, 5254 }, 5255 { 5256 .label = "reset_swb_dc_dc_pwr_fail", 5257 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5258 .mask = GENMASK(7, 0) & ~BIT(3), 5259 .mode = 0444, 5260 }, 5261 { 5262 .label = "reset_swb_12v_fail", 5263 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5264 .mask = GENMASK(7, 0) & ~BIT(4), 5265 .mode = 0444, 5266 }, 5267 { 5268 .label = "reset_system", 5269 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5270 .mask = GENMASK(7, 0) & ~BIT(5), 5271 .mode = 0444, 5272 }, 5273 { 5274 .label = "reset_thermal_spc_or_pciesw", 5275 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5276 .mask = GENMASK(7, 0) & ~BIT(7), 5277 .mode = 0444, 5278 }, 5279 { 5280 .label = "bios_safe_mode", 5281 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5282 .mask = GENMASK(7, 0) & ~BIT(4), 5283 .mode = 0444, 5284 }, 5285 { 5286 .label = "bios_active_image", 5287 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5288 .mask = GENMASK(7, 0) & ~BIT(5), 5289 .mode = 0444, 5290 }, 5291 { 5292 .label = "bios_auth_fail", 5293 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5294 .mask = GENMASK(7, 0) & ~BIT(6), 5295 .mode = 0444, 5296 }, 5297 { 5298 .label = "bios_upgrade_fail", 5299 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5300 .mask = GENMASK(7, 0) & ~BIT(7), 5301 .mode = 0444, 5302 }, 5303 { 5304 .label = "voltreg_update_status", 5305 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 5306 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 5307 .bit = 5, 5308 .mode = 0444, 5309 }, 5310 { 5311 .label = "vpd_wp", 5312 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 5313 .mask = GENMASK(7, 0) & ~BIT(3), 5314 .mode = 0644, 5315 }, 5316 { 5317 .label = "pcie_asic_reset_dis", 5318 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 5319 .mask = GENMASK(7, 0) & ~BIT(4), 5320 .mode = 0644, 5321 }, 5322 { 5323 .label = "shutdown_unlock", 5324 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 5325 .mask = GENMASK(7, 0) & ~BIT(5), 5326 .mode = 0644, 5327 }, 5328 { 5329 .label = "lc1_rst_mask", 5330 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 5331 .mask = GENMASK(7, 0) & ~BIT(0), 5332 .mode = 0200, 5333 }, 5334 { 5335 .label = "lc2_rst_mask", 5336 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 5337 .mask = GENMASK(7, 0) & ~BIT(1), 5338 .mode = 0200, 5339 }, 5340 { 5341 .label = "lc3_rst_mask", 5342 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 5343 .mask = GENMASK(7, 0) & ~BIT(2), 5344 .mode = 0200, 5345 }, 5346 { 5347 .label = "lc4_rst_mask", 5348 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 5349 .mask = GENMASK(7, 0) & ~BIT(3), 5350 .mode = 0200, 5351 }, 5352 { 5353 .label = "lc5_rst_mask", 5354 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 5355 .mask = GENMASK(7, 0) & ~BIT(4), 5356 .mode = 0200, 5357 }, 5358 { 5359 .label = "lc6_rst_mask", 5360 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 5361 .mask = GENMASK(7, 0) & ~BIT(5), 5362 .mode = 0200, 5363 }, 5364 { 5365 .label = "lc7_rst_mask", 5366 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 5367 .mask = GENMASK(7, 0) & ~BIT(6), 5368 .mode = 0200, 5369 }, 5370 { 5371 .label = "lc8_rst_mask", 5372 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 5373 .mask = GENMASK(7, 0) & ~BIT(7), 5374 .mode = 0200, 5375 }, 5376 { 5377 .label = "psu1_on", 5378 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5379 .mask = GENMASK(7, 0) & ~BIT(0), 5380 .mode = 0200, 5381 }, 5382 { 5383 .label = "psu2_on", 5384 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5385 .mask = GENMASK(7, 0) & ~BIT(1), 5386 .mode = 0200, 5387 }, 5388 { 5389 .label = "pwr_cycle", 5390 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5391 .mask = GENMASK(7, 0) & ~BIT(2), 5392 .mode = 0200, 5393 }, 5394 { 5395 .label = "pwr_down", 5396 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5397 .mask = GENMASK(7, 0) & ~BIT(3), 5398 .mode = 0200, 5399 }, 5400 { 5401 .label = "psu3_on", 5402 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5403 .mask = GENMASK(7, 0) & ~BIT(4), 5404 .mode = 0200, 5405 }, 5406 { 5407 .label = "psu4_on", 5408 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5409 .mask = GENMASK(7, 0) & ~BIT(5), 5410 .mode = 0200, 5411 }, 5412 { 5413 .label = "auto_power_mode", 5414 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5415 .mask = GENMASK(7, 0) & ~BIT(6), 5416 .mode = 0644, 5417 }, 5418 { 5419 .label = "pm_mgmt_en", 5420 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5421 .mask = GENMASK(7, 0) & ~BIT(7), 5422 .mode = 0644, 5423 }, 5424 { 5425 .label = "jtag_enable", 5426 .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE, 5427 .mask = GENMASK(3, 0), 5428 .bit = 1, 5429 .mode = 0644, 5430 }, 5431 { 5432 .label = "safe_bios_dis", 5433 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, 5434 .mask = GENMASK(7, 0) & ~BIT(5), 5435 .mode = 0644, 5436 }, 5437 { 5438 .label = "safe_bios_dis_wp", 5439 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET, 5440 .mask = GENMASK(7, 0) & ~BIT(5), 5441 .mode = 0644, 5442 }, 5443 { 5444 .label = "asic_health", 5445 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 5446 .mask = MLXPLAT_CPLD_ASIC_MASK, 5447 .bit = 1, 5448 .mode = 0444, 5449 }, 5450 { 5451 .label = "fan_dir", 5452 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 5453 .bit = GENMASK(7, 0), 5454 .mode = 0444, 5455 }, 5456 { 5457 .label = "lc1_pwr", 5458 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5459 .mask = GENMASK(7, 0) & ~BIT(0), 5460 .mode = 0644, 5461 }, 5462 { 5463 .label = "lc2_pwr", 5464 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5465 .mask = GENMASK(7, 0) & ~BIT(1), 5466 .mode = 0644, 5467 }, 5468 { 5469 .label = "lc3_pwr", 5470 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5471 .mask = GENMASK(7, 0) & ~BIT(2), 5472 .mode = 0644, 5473 }, 5474 { 5475 .label = "lc4_pwr", 5476 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5477 .mask = GENMASK(7, 0) & ~BIT(3), 5478 .mode = 0644, 5479 }, 5480 { 5481 .label = "lc5_pwr", 5482 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5483 .mask = GENMASK(7, 0) & ~BIT(4), 5484 .mode = 0644, 5485 }, 5486 { 5487 .label = "lc6_pwr", 5488 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5489 .mask = GENMASK(7, 0) & ~BIT(5), 5490 .mode = 0644, 5491 }, 5492 { 5493 .label = "lc7_pwr", 5494 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5495 .mask = GENMASK(7, 0) & ~BIT(6), 5496 .mode = 0644, 5497 }, 5498 { 5499 .label = "lc8_pwr", 5500 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 5501 .mask = GENMASK(7, 0) & ~BIT(7), 5502 .mode = 0644, 5503 }, 5504 { 5505 .label = "config1", 5506 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 5507 .bit = GENMASK(7, 0), 5508 .mode = 0444, 5509 }, 5510 { 5511 .label = "config2", 5512 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 5513 .bit = GENMASK(7, 0), 5514 .mode = 0444, 5515 }, 5516 { 5517 .label = "config3", 5518 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 5519 .bit = GENMASK(7, 0), 5520 .mode = 0444, 5521 }, 5522 { 5523 .label = "ufm_version", 5524 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 5525 .bit = GENMASK(7, 0), 5526 .mode = 0444, 5527 }, 5528 }; 5529 5530 static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = { 5531 .data = mlxplat_mlxcpld_modular_regs_io_data, 5532 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data), 5533 }; 5534 5535 /* Platform register access for chassis blade systems family data */ 5536 static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { 5537 { 5538 .label = "cpld1_version", 5539 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 5540 .bit = GENMASK(7, 0), 5541 .mode = 0444, 5542 }, 5543 { 5544 .label = "cpld1_pn", 5545 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 5546 .bit = GENMASK(15, 0), 5547 .mode = 0444, 5548 .regnum = 2, 5549 }, 5550 { 5551 .label = "cpld1_version_min", 5552 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 5553 .bit = GENMASK(7, 0), 5554 .mode = 0444, 5555 }, 5556 { 5557 .label = "reset_aux_pwr_or_ref", 5558 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5559 .mask = GENMASK(7, 0) & ~BIT(2), 5560 .mode = 0444, 5561 }, 5562 { 5563 .label = "reset_from_comex", 5564 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5565 .mask = GENMASK(7, 0) & ~BIT(4), 5566 .mode = 0444, 5567 }, 5568 { 5569 .label = "reset_comex_pwr_fail", 5570 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5571 .mask = GENMASK(7, 0) & ~BIT(3), 5572 .mode = 0444, 5573 }, 5574 { 5575 .label = "reset_platform", 5576 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5577 .mask = GENMASK(7, 0) & ~BIT(4), 5578 .mode = 0444, 5579 }, 5580 { 5581 .label = "reset_soc", 5582 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5583 .mask = GENMASK(7, 0) & ~BIT(5), 5584 .mode = 0444, 5585 }, 5586 { 5587 .label = "reset_comex_wd", 5588 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5589 .mask = GENMASK(7, 0) & ~BIT(6), 5590 .mode = 0444, 5591 }, 5592 { 5593 .label = "reset_voltmon_upgrade_fail", 5594 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5595 .mask = GENMASK(7, 0) & ~BIT(0), 5596 .mode = 0444, 5597 }, 5598 { 5599 .label = "reset_system", 5600 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5601 .mask = GENMASK(7, 0) & ~BIT(1), 5602 .mode = 0444, 5603 }, 5604 { 5605 .label = "reset_sw_pwr_off", 5606 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5607 .mask = GENMASK(7, 0) & ~BIT(2), 5608 .mode = 0444, 5609 }, 5610 { 5611 .label = "reset_comex_thermal", 5612 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5613 .mask = GENMASK(7, 0) & ~BIT(3), 5614 .mode = 0444, 5615 }, 5616 { 5617 .label = "reset_reload_bios", 5618 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5619 .mask = GENMASK(7, 0) & ~BIT(5), 5620 .mode = 0444, 5621 }, 5622 { 5623 .label = "reset_ac_pwr_fail", 5624 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5625 .mask = GENMASK(7, 0) & ~BIT(6), 5626 .mode = 0444, 5627 }, 5628 { 5629 .label = "reset_long_pwr_pb", 5630 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5631 .mask = GENMASK(7, 0) & ~BIT(7), 5632 .mode = 0444, 5633 }, 5634 { 5635 .label = "pwr_cycle", 5636 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5637 .mask = GENMASK(7, 0) & ~BIT(2), 5638 .mode = 0200, 5639 }, 5640 { 5641 .label = "pwr_down", 5642 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 5643 .mask = GENMASK(7, 0) & ~BIT(3), 5644 .mode = 0200, 5645 }, 5646 { 5647 .label = "global_wp_request", 5648 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 5649 .mask = GENMASK(7, 0) & ~BIT(0), 5650 .mode = 0644, 5651 }, 5652 { 5653 .label = "jtag_enable", 5654 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 5655 .mask = GENMASK(7, 0) & ~BIT(4), 5656 .mode = 0644, 5657 }, 5658 { 5659 .label = "comm_chnl_ready", 5660 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 5661 .mask = GENMASK(7, 0) & ~BIT(6), 5662 .mode = 0200, 5663 }, 5664 { 5665 .label = "bios_safe_mode", 5666 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5667 .mask = GENMASK(7, 0) & ~BIT(4), 5668 .mode = 0444, 5669 }, 5670 { 5671 .label = "bios_active_image", 5672 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5673 .mask = GENMASK(7, 0) & ~BIT(5), 5674 .mode = 0444, 5675 }, 5676 { 5677 .label = "bios_auth_fail", 5678 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5679 .mask = GENMASK(7, 0) & ~BIT(6), 5680 .mode = 0444, 5681 }, 5682 { 5683 .label = "bios_upgrade_fail", 5684 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5685 .mask = GENMASK(7, 0) & ~BIT(7), 5686 .mode = 0444, 5687 }, 5688 { 5689 .label = "voltreg_update_status", 5690 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 5691 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 5692 .bit = 5, 5693 .mode = 0444, 5694 }, 5695 { 5696 .label = "vpd_wp", 5697 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 5698 .mask = GENMASK(7, 0) & ~BIT(3), 5699 .mode = 0644, 5700 }, 5701 { 5702 .label = "pcie_asic_reset_dis", 5703 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 5704 .mask = GENMASK(7, 0) & ~BIT(4), 5705 .mode = 0644, 5706 }, 5707 { 5708 .label = "global_wp_response", 5709 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, 5710 .mask = GENMASK(7, 0) & ~BIT(0), 5711 .mode = 0444, 5712 }, 5713 { 5714 .label = "config1", 5715 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 5716 .bit = GENMASK(7, 0), 5717 .mode = 0444, 5718 }, 5719 { 5720 .label = "config2", 5721 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 5722 .bit = GENMASK(7, 0), 5723 .mode = 0444, 5724 }, 5725 { 5726 .label = "config3", 5727 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 5728 .bit = GENMASK(7, 0), 5729 .mode = 0444, 5730 }, 5731 { 5732 .label = "ufm_version", 5733 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 5734 .bit = GENMASK(7, 0), 5735 .mode = 0444, 5736 }, 5737 }; 5738 5739 static struct mlxreg_core_platform_data mlxplat_chassis_blade_regs_io_data = { 5740 .data = mlxplat_mlxcpld_chassis_blade_regs_io_data, 5741 .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_regs_io_data), 5742 }; 5743 5744 /* Platform register access for smart switch systems families data */ 5745 static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_regs_io_data[] = { 5746 { 5747 .label = "cpld1_version", 5748 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 5749 .bit = GENMASK(7, 0), 5750 .mode = 0444, 5751 }, 5752 { 5753 .label = "cpld2_version", 5754 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 5755 .bit = GENMASK(7, 0), 5756 .mode = 0444, 5757 }, 5758 { 5759 .label = "cpld3_version", 5760 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 5761 .bit = GENMASK(7, 0), 5762 .mode = 0444, 5763 }, 5764 { 5765 .label = "cpld1_pn", 5766 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 5767 .bit = GENMASK(15, 0), 5768 .mode = 0444, 5769 .regnum = 2, 5770 }, 5771 { 5772 .label = "cpld2_pn", 5773 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 5774 .bit = GENMASK(15, 0), 5775 .mode = 0444, 5776 .regnum = 2, 5777 }, 5778 { 5779 .label = "cpld3_pn", 5780 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 5781 .bit = GENMASK(15, 0), 5782 .mode = 0444, 5783 .regnum = 2, 5784 }, 5785 { 5786 .label = "cpld1_version_min", 5787 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 5788 .bit = GENMASK(7, 0), 5789 .mode = 0444, 5790 }, 5791 { 5792 .label = "cpld2_version_min", 5793 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 5794 .bit = GENMASK(7, 0), 5795 .mode = 0444, 5796 }, 5797 { 5798 .label = "cpld3_version_min", 5799 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 5800 .bit = GENMASK(7, 0), 5801 .mode = 0444, 5802 }, 5803 { 5804 .label = "kexec_activated", 5805 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, 5806 .mask = GENMASK(7, 0) & ~BIT(1), 5807 .mode = 0644, 5808 }, 5809 { 5810 .label = "asic_reset", 5811 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 5812 .mask = GENMASK(7, 0) & ~BIT(3), 5813 .mode = 0644, 5814 }, 5815 { 5816 .label = "eth_switch_reset", 5817 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 5818 .mask = GENMASK(7, 0) & ~BIT(4), 5819 .mode = 0644, 5820 }, 5821 { 5822 .label = "dpu1_rst", 5823 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, 5824 .mask = GENMASK(7, 0) & ~BIT(0), 5825 .mode = 0200, 5826 }, 5827 { 5828 .label = "dpu2_rst", 5829 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, 5830 .mask = GENMASK(7, 0) & ~BIT(1), 5831 .mode = 0200, 5832 }, 5833 { 5834 .label = "dpu3_rst", 5835 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, 5836 .mask = GENMASK(7, 0) & ~BIT(2), 5837 .mode = 0200, 5838 }, 5839 { 5840 .label = "dpu4_rst", 5841 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, 5842 .mask = GENMASK(7, 0) & ~BIT(3), 5843 .mode = 0200, 5844 }, 5845 { 5846 .label = "dpu1_pwr", 5847 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5848 .mask = GENMASK(7, 0) & ~BIT(0), 5849 .mode = 0200, 5850 }, 5851 { 5852 .label = "dpu2_pwr", 5853 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5854 .mask = GENMASK(7, 0) & ~BIT(1), 5855 .mode = 0200, 5856 }, 5857 { 5858 .label = "dpu3_pwr", 5859 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5860 .mask = GENMASK(7, 0) & ~BIT(2), 5861 .mode = 0200, 5862 }, 5863 { 5864 .label = "dpu4_pwr", 5865 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 5866 .mask = GENMASK(7, 0) & ~BIT(3), 5867 .mode = 0200, 5868 }, 5869 { 5870 .label = "reset_long_pb", 5871 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5872 .mask = GENMASK(7, 0) & ~BIT(0), 5873 .mode = 0444, 5874 }, 5875 { 5876 .label = "reset_short_pb", 5877 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5878 .mask = GENMASK(7, 0) & ~BIT(1), 5879 .mode = 0444, 5880 }, 5881 { 5882 .label = "reset_aux_pwr_or_ref", 5883 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5884 .mask = GENMASK(7, 0) & ~BIT(2), 5885 .mode = 0444, 5886 }, 5887 { 5888 .label = "reset_swb_dc_dc_pwr_fail", 5889 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5890 .mask = GENMASK(7, 0) & ~BIT(3), 5891 .mode = 0444, 5892 }, 5893 { 5894 .label = "reset_swb_wd", 5895 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5896 .mask = GENMASK(7, 0) & ~BIT(6), 5897 .mode = 0444, 5898 }, 5899 { 5900 .label = "reset_asic_thermal", 5901 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 5902 .mask = GENMASK(7, 0) & ~BIT(7), 5903 .mode = 0444, 5904 }, 5905 { 5906 .label = "reset_sw_reset", 5907 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5908 .mask = GENMASK(7, 0) & ~BIT(0), 5909 .mode = 0444, 5910 }, 5911 { 5912 .label = "reset_aux_pwr_or_reload", 5913 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5914 .mask = GENMASK(7, 0) & ~BIT(2), 5915 .mode = 0444, 5916 }, 5917 { 5918 .label = "reset_comex_pwr_fail", 5919 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5920 .mask = GENMASK(7, 0) & ~BIT(3), 5921 .mode = 0444, 5922 }, 5923 { 5924 .label = "reset_platform", 5925 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5926 .mask = GENMASK(7, 0) & ~BIT(4), 5927 .mode = 0444, 5928 }, 5929 { 5930 .label = "reset_soc", 5931 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5932 .mask = GENMASK(7, 0) & ~BIT(5), 5933 .mode = 0444, 5934 }, 5935 { 5936 .label = "reset_pwr", 5937 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 5938 .mask = GENMASK(7, 0) & ~BIT(7), 5939 .mode = 0444, 5940 }, 5941 { 5942 .label = "reset_pwr_converter_fail", 5943 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5944 .mask = GENMASK(7, 0) & ~BIT(0), 5945 .mode = 0444, 5946 }, 5947 { 5948 .label = "reset_system", 5949 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5950 .mask = GENMASK(7, 0) & ~BIT(1), 5951 .mode = 0444, 5952 }, 5953 { 5954 .label = "reset_sw_pwr_off", 5955 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5956 .mask = GENMASK(7, 0) & ~BIT(2), 5957 .mode = 0444, 5958 }, 5959 { 5960 .label = "reset_comex_thermal", 5961 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5962 .mask = GENMASK(7, 0) & ~BIT(3), 5963 .mode = 0444, 5964 }, 5965 { 5966 .label = "reset_ac_pwr_fail", 5967 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 5968 .mask = GENMASK(7, 0) & ~BIT(6), 5969 .mode = 0444, 5970 }, 5971 { 5972 .label = "voltreg_update_status", 5973 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 5974 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 5975 .bit = 5, 5976 .mode = 0444, 5977 }, 5978 { 5979 .label = "port80", 5980 .reg = MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET, 5981 .bit = GENMASK(7, 0), 5982 .mode = 0444, 5983 }, 5984 { 5985 .label = "bios_status", 5986 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5987 .mask = MLXPLAT_CPLD_BIOS_STATUS_MASK, 5988 .bit = 2, 5989 .mode = 0444, 5990 }, 5991 { 5992 .label = "bios_start_retry", 5993 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 5994 .mask = GENMASK(7, 0) & ~BIT(4), 5995 .mode = 0444, 5996 }, 5997 { 5998 .label = "bios_active_image", 5999 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 6000 .mask = GENMASK(7, 0) & ~BIT(5), 6001 .mode = 0444, 6002 }, 6003 { 6004 .label = "vpd_wp", 6005 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 6006 .mask = GENMASK(7, 0) & ~BIT(3), 6007 .mode = 0644, 6008 }, 6009 { 6010 .label = "pcie_asic_reset_dis", 6011 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 6012 .mask = GENMASK(7, 0) & ~BIT(4), 6013 .mode = 0644, 6014 }, 6015 { 6016 .label = "shutdown_unlock", 6017 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 6018 .mask = GENMASK(7, 0) & ~BIT(5), 6019 .mode = 0644, 6020 }, 6021 { 6022 .label = "fan_dir", 6023 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 6024 .bit = GENMASK(7, 0), 6025 .mode = 0444, 6026 }, 6027 { 6028 .label = "dpu1_rst_en", 6029 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 6030 .mask = GENMASK(7, 0) & ~BIT(0), 6031 .mode = 0200, 6032 }, 6033 { 6034 .label = "dpu2_rst_en", 6035 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 6036 .mask = GENMASK(7, 0) & ~BIT(1), 6037 .mode = 0200, 6038 }, 6039 { 6040 .label = "dpu3_rst_en", 6041 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 6042 .mask = GENMASK(7, 0) & ~BIT(2), 6043 .mode = 0200, 6044 }, 6045 { 6046 .label = "dpu4_rst_en", 6047 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 6048 .mask = GENMASK(7, 0) & ~BIT(3), 6049 .mode = 0200, 6050 }, 6051 { 6052 .label = "psu1_on", 6053 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 6054 .mask = GENMASK(7, 0) & ~BIT(0), 6055 .mode = 0200, 6056 }, 6057 { 6058 .label = "psu2_on", 6059 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 6060 .mask = GENMASK(7, 0) & ~BIT(1), 6061 .mode = 0200, 6062 }, 6063 { 6064 .label = "pwr_cycle", 6065 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 6066 .mask = GENMASK(7, 0) & ~BIT(2), 6067 .mode = 0200, 6068 }, 6069 { 6070 .label = "pwr_down", 6071 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 6072 .mask = GENMASK(7, 0) & ~BIT(3), 6073 .mode = 0200, 6074 }, 6075 { 6076 .label = "jtag_cap", 6077 .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET, 6078 .mask = MLXPLAT_CPLD_FU_CAP_MASK, 6079 .bit = 1, 6080 .mode = 0444, 6081 }, 6082 { 6083 .label = "jtag_enable", 6084 .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE, 6085 .mask = GENMASK(1, 0), 6086 .bit = 1, 6087 .mode = 0644, 6088 }, 6089 { 6090 .label = "non_active_bios_select", 6091 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, 6092 .mask = GENMASK(7, 0) & ~BIT(4), 6093 .mode = 0644, 6094 }, 6095 { 6096 .label = "bios_upgrade_fail", 6097 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, 6098 .mask = GENMASK(7, 0) & ~BIT(5), 6099 .mode = 0444, 6100 }, 6101 { 6102 .label = "bios_image_invert", 6103 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, 6104 .mask = GENMASK(7, 0) & ~BIT(6), 6105 .mode = 0644, 6106 }, 6107 { 6108 .label = "me_reboot", 6109 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, 6110 .mask = GENMASK(7, 0) & ~BIT(7), 6111 .mode = 0644, 6112 }, 6113 { 6114 .label = "dpu1_pwr_force", 6115 .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, 6116 .mask = GENMASK(7, 0) & ~BIT(0), 6117 .mode = 0200, 6118 }, 6119 { 6120 .label = "dpu2_pwr_force", 6121 .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, 6122 .mask = GENMASK(7, 0) & ~BIT(1), 6123 .mode = 0200, 6124 }, 6125 { 6126 .label = "dpu3_pwr_force", 6127 .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, 6128 .mask = GENMASK(7, 0) & ~BIT(2), 6129 .mode = 0200, 6130 }, 6131 { 6132 .label = "dpu4_pwr_force", 6133 .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, 6134 .mask = GENMASK(7, 0) & ~BIT(3), 6135 .mode = 0200, 6136 }, 6137 { 6138 .label = "ufm_done", 6139 .reg = MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET, 6140 .bit = GENMASK(7, 0), 6141 .mode = 0444, 6142 }, 6143 { 6144 .label = "asic_health", 6145 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 6146 .mask = MLXPLAT_CPLD_ASIC_MASK, 6147 .bit = 1, 6148 .mode = 0444, 6149 }, 6150 { 6151 .label = "psu1_ac_ok", 6152 .reg = MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET, 6153 .mask = GENMASK(7, 0) & ~BIT(0), 6154 .mode = 0644, 6155 }, 6156 { 6157 .label = "psu2_ac_ok", 6158 .reg = MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET, 6159 .mask = GENMASK(7, 0) & ~BIT(1), 6160 .mode = 0644, 6161 }, 6162 { 6163 .label = "psu1_no_alert", 6164 .reg = MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET, 6165 .mask = GENMASK(7, 0) & ~BIT(0), 6166 .mode = 0644, 6167 }, 6168 { 6169 .label = "psu2_no_alert", 6170 .reg = MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET, 6171 .mask = GENMASK(7, 0) & ~BIT(1), 6172 .mode = 0644, 6173 }, 6174 { 6175 .label = "asic_pg_fail", 6176 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 6177 .mask = GENMASK(7, 0) & ~BIT(7), 6178 .mode = 0444, 6179 }, 6180 { 6181 .label = "spi_chnl_select", 6182 .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT, 6183 .mask = GENMASK(7, 0), 6184 .bit = 1, 6185 .mode = 0644, 6186 }, 6187 { 6188 .label = "config1", 6189 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 6190 .bit = GENMASK(7, 0), 6191 .mode = 0444, 6192 }, 6193 { 6194 .label = "config2", 6195 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 6196 .bit = GENMASK(7, 0), 6197 .mode = 0444, 6198 }, 6199 { 6200 .label = "config3", 6201 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 6202 .bit = GENMASK(7, 0), 6203 .mode = 0444, 6204 }, 6205 { 6206 .label = "ufm_version", 6207 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 6208 .bit = GENMASK(7, 0), 6209 .mode = 0444, 6210 }, 6211 }; 6212 6213 static struct mlxreg_core_platform_data mlxplat_smart_switch_regs_io_data = { 6214 .data = mlxplat_mlxcpld_smart_switch_regs_io_data, 6215 .counter = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_regs_io_data), 6216 }; 6217 6218 /* Platform FAN default */ 6219 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { 6220 { 6221 .label = "pwm1", 6222 .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, 6223 }, 6224 { 6225 .label = "pwm2", 6226 .reg = MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, 6227 }, 6228 { 6229 .label = "pwm3", 6230 .reg = MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, 6231 }, 6232 { 6233 .label = "pwm4", 6234 .reg = MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, 6235 }, 6236 { 6237 .label = "tacho1", 6238 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, 6239 .mask = GENMASK(7, 0), 6240 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6241 .bit = BIT(0), 6242 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6243 6244 }, 6245 { 6246 .label = "tacho2", 6247 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, 6248 .mask = GENMASK(7, 0), 6249 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6250 .bit = BIT(1), 6251 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6252 }, 6253 { 6254 .label = "tacho3", 6255 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, 6256 .mask = GENMASK(7, 0), 6257 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6258 .bit = BIT(2), 6259 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6260 }, 6261 { 6262 .label = "tacho4", 6263 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, 6264 .mask = GENMASK(7, 0), 6265 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6266 .bit = BIT(3), 6267 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6268 }, 6269 { 6270 .label = "tacho5", 6271 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, 6272 .mask = GENMASK(7, 0), 6273 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6274 .bit = BIT(4), 6275 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6276 }, 6277 { 6278 .label = "tacho6", 6279 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, 6280 .mask = GENMASK(7, 0), 6281 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6282 .bit = BIT(5), 6283 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6284 }, 6285 { 6286 .label = "tacho7", 6287 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, 6288 .mask = GENMASK(7, 0), 6289 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6290 .bit = BIT(6), 6291 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6292 }, 6293 { 6294 .label = "tacho8", 6295 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, 6296 .mask = GENMASK(7, 0), 6297 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6298 .bit = BIT(7), 6299 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6300 }, 6301 { 6302 .label = "tacho9", 6303 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, 6304 .mask = GENMASK(7, 0), 6305 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 6306 .bit = BIT(0), 6307 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6308 }, 6309 { 6310 .label = "tacho10", 6311 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, 6312 .mask = GENMASK(7, 0), 6313 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 6314 .bit = BIT(1), 6315 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6316 }, 6317 { 6318 .label = "tacho11", 6319 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, 6320 .mask = GENMASK(7, 0), 6321 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 6322 .bit = BIT(2), 6323 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6324 }, 6325 { 6326 .label = "tacho12", 6327 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, 6328 .mask = GENMASK(7, 0), 6329 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 6330 .bit = BIT(3), 6331 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6332 }, 6333 { 6334 .label = "tacho13", 6335 .reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET, 6336 .mask = GENMASK(7, 0), 6337 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 6338 .bit = BIT(4), 6339 }, 6340 { 6341 .label = "tacho14", 6342 .reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET, 6343 .mask = GENMASK(7, 0), 6344 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 6345 .bit = BIT(5), 6346 }, 6347 { 6348 .label = "conf", 6349 .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET, 6350 }, 6351 }; 6352 6353 static struct mlxreg_core_platform_data mlxplat_default_fan_data = { 6354 .data = mlxplat_mlxcpld_default_fan_data, 6355 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data), 6356 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 6357 }; 6358 6359 /* XDR and smart switch platform fan data */ 6360 static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_data[] = { 6361 { 6362 .label = "pwm1", 6363 .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, 6364 }, 6365 { 6366 .label = "tacho1", 6367 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, 6368 .mask = GENMASK(7, 0), 6369 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6370 .slot = 1, 6371 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6372 }, 6373 { 6374 .label = "tacho2", 6375 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, 6376 .mask = GENMASK(7, 0), 6377 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6378 .slot = 2, 6379 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6380 }, 6381 { 6382 .label = "tacho3", 6383 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, 6384 .mask = GENMASK(7, 0), 6385 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6386 .slot = 3, 6387 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6388 }, 6389 { 6390 .label = "tacho4", 6391 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, 6392 .mask = GENMASK(7, 0), 6393 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6394 .slot = 4, 6395 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6396 }, 6397 { 6398 .label = "tacho5", 6399 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, 6400 .mask = GENMASK(7, 0), 6401 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6402 .slot = 5, 6403 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6404 }, 6405 { 6406 .label = "tacho6", 6407 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, 6408 .mask = GENMASK(7, 0), 6409 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6410 .slot = 6, 6411 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6412 }, 6413 { 6414 .label = "tacho7", 6415 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, 6416 .mask = GENMASK(7, 0), 6417 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6418 .slot = 7, 6419 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6420 }, 6421 { 6422 .label = "tacho8", 6423 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, 6424 .mask = GENMASK(7, 0), 6425 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6426 .slot = 8, 6427 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6428 }, 6429 { 6430 .label = "tacho9", 6431 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, 6432 .mask = GENMASK(7, 0), 6433 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6434 .slot = 9, 6435 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6436 }, 6437 { 6438 .label = "tacho10", 6439 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, 6440 .mask = GENMASK(7, 0), 6441 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6442 .slot = 10, 6443 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6444 }, 6445 { 6446 .label = "tacho11", 6447 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, 6448 .mask = GENMASK(7, 0), 6449 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6450 .slot = 11, 6451 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6452 }, 6453 { 6454 .label = "tacho12", 6455 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, 6456 .mask = GENMASK(7, 0), 6457 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6458 .slot = 12, 6459 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6460 }, 6461 { 6462 .label = "tacho13", 6463 .reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET, 6464 .mask = GENMASK(7, 0), 6465 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6466 .slot = 13, 6467 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6468 }, 6469 { 6470 .label = "tacho14", 6471 .reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET, 6472 .mask = GENMASK(7, 0), 6473 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6474 .slot = 14, 6475 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6476 }, 6477 { 6478 .label = "tacho15", 6479 .reg = MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET, 6480 .mask = GENMASK(7, 0), 6481 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6482 .slot = 15, 6483 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6484 }, 6485 { 6486 .label = "tacho16", 6487 .reg = MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET, 6488 .mask = GENMASK(7, 0), 6489 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6490 .slot = 16, 6491 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 6492 }, 6493 { 6494 .label = "tacho17", 6495 .reg = MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET, 6496 .mask = GENMASK(7, 0), 6497 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6498 .slot = 17, 6499 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, 6500 }, 6501 { 6502 .label = "tacho18", 6503 .reg = MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET, 6504 .mask = GENMASK(7, 0), 6505 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6506 .slot = 18, 6507 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, 6508 }, 6509 { 6510 .label = "tacho19", 6511 .reg = MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET, 6512 .mask = GENMASK(7, 0), 6513 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6514 .slot = 19, 6515 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, 6516 }, 6517 { 6518 .label = "tacho20", 6519 .reg = MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET, 6520 .mask = GENMASK(7, 0), 6521 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 6522 .slot = 20, 6523 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, 6524 }, 6525 { 6526 .label = "conf", 6527 .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET, 6528 }, 6529 }; 6530 6531 static struct mlxreg_core_platform_data mlxplat_xdr_fan_data = { 6532 .data = mlxplat_mlxcpld_xdr_fan_data, 6533 .counter = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_data), 6534 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 6535 .version = 1, 6536 }; 6537 6538 /* Watchdog type1: hardware implementation version1 6539 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems). 6540 */ 6541 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = { 6542 { 6543 .label = "action", 6544 .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 6545 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 6546 .bit = 0, 6547 }, 6548 { 6549 .label = "timeout", 6550 .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET, 6551 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 6552 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 6553 }, 6554 { 6555 .label = "ping", 6556 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 6557 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 6558 .bit = 0, 6559 }, 6560 { 6561 .label = "reset", 6562 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 6563 .mask = GENMASK(7, 0) & ~BIT(6), 6564 .bit = 6, 6565 }, 6566 }; 6567 6568 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = { 6569 { 6570 .label = "action", 6571 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 6572 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 6573 .bit = 4, 6574 }, 6575 { 6576 .label = "timeout", 6577 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 6578 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 6579 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 6580 }, 6581 { 6582 .label = "ping", 6583 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 6584 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 6585 .bit = 1, 6586 }, 6587 }; 6588 6589 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = { 6590 { 6591 .data = mlxplat_mlxcpld_wd_main_regs_type1, 6592 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1), 6593 .version = MLX_WDT_TYPE1, 6594 .identity = "mlx-wdt-main", 6595 }, 6596 { 6597 .data = mlxplat_mlxcpld_wd_aux_regs_type1, 6598 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1), 6599 .version = MLX_WDT_TYPE1, 6600 .identity = "mlx-wdt-aux", 6601 }, 6602 }; 6603 6604 /* Watchdog type2: hardware implementation version 2 6605 * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140). 6606 */ 6607 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = { 6608 { 6609 .label = "action", 6610 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 6611 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 6612 .bit = 0, 6613 }, 6614 { 6615 .label = "timeout", 6616 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 6617 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6618 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 6619 }, 6620 { 6621 .label = "timeleft", 6622 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET, 6623 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6624 }, 6625 { 6626 .label = "ping", 6627 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 6628 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 6629 .bit = 0, 6630 }, 6631 { 6632 .label = "reset", 6633 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 6634 .mask = GENMASK(7, 0) & ~BIT(6), 6635 .bit = 6, 6636 }, 6637 }; 6638 6639 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = { 6640 { 6641 .label = "action", 6642 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 6643 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 6644 .bit = 4, 6645 }, 6646 { 6647 .label = "timeout", 6648 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 6649 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6650 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 6651 }, 6652 { 6653 .label = "timeleft", 6654 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET, 6655 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6656 }, 6657 { 6658 .label = "ping", 6659 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 6660 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 6661 .bit = 4, 6662 }, 6663 }; 6664 6665 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = { 6666 { 6667 .data = mlxplat_mlxcpld_wd_main_regs_type2, 6668 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2), 6669 .version = MLX_WDT_TYPE2, 6670 .identity = "mlx-wdt-main", 6671 }, 6672 { 6673 .data = mlxplat_mlxcpld_wd_aux_regs_type2, 6674 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2), 6675 .version = MLX_WDT_TYPE2, 6676 .identity = "mlx-wdt-aux", 6677 }, 6678 }; 6679 6680 /* Watchdog type3: hardware implementation version 3 6681 * Can be on all systems. It's differentiated by WD capability bit. 6682 * Old systems (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140) 6683 * still have only one main watchdog. 6684 */ 6685 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type3[] = { 6686 { 6687 .label = "action", 6688 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 6689 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 6690 .bit = 0, 6691 }, 6692 { 6693 .label = "timeout", 6694 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 6695 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6696 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 6697 }, 6698 { 6699 .label = "timeleft", 6700 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 6701 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6702 }, 6703 { 6704 .label = "ping", 6705 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 6706 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 6707 .bit = 0, 6708 }, 6709 { 6710 .label = "reset", 6711 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 6712 .mask = GENMASK(7, 0) & ~BIT(6), 6713 .bit = 6, 6714 }, 6715 }; 6716 6717 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type3[] = { 6718 { 6719 .label = "action", 6720 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 6721 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 6722 .bit = 4, 6723 }, 6724 { 6725 .label = "timeout", 6726 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 6727 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6728 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 6729 }, 6730 { 6731 .label = "timeleft", 6732 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 6733 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 6734 }, 6735 { 6736 .label = "ping", 6737 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 6738 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 6739 .bit = 4, 6740 }, 6741 }; 6742 6743 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = { 6744 { 6745 .data = mlxplat_mlxcpld_wd_main_regs_type3, 6746 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type3), 6747 .version = MLX_WDT_TYPE3, 6748 .identity = "mlx-wdt-main", 6749 }, 6750 { 6751 .data = mlxplat_mlxcpld_wd_aux_regs_type3, 6752 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type3), 6753 .version = MLX_WDT_TYPE3, 6754 .identity = "mlx-wdt-aux", 6755 }, 6756 }; 6757 6758 static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) 6759 { 6760 switch (reg) { 6761 case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: 6762 case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: 6763 case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: 6764 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 6765 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 6766 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 6767 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 6768 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 6769 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 6770 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 6771 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 6772 case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: 6773 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 6774 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 6775 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 6776 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 6777 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 6778 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 6779 case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET: 6780 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 6781 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 6782 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 6783 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 6784 case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET: 6785 case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: 6786 case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: 6787 case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: 6788 case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: 6789 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 6790 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 6791 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 6792 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: 6793 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: 6794 case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: 6795 case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: 6796 case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: 6797 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 6798 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 6799 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: 6800 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: 6801 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 6802 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 6803 case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: 6804 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 6805 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 6806 case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET: 6807 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 6808 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 6809 case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET: 6810 case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET: 6811 case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: 6812 case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: 6813 case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: 6814 case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: 6815 case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: 6816 case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: 6817 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 6818 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 6819 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 6820 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 6821 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 6822 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 6823 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 6824 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 6825 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 6826 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 6827 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 6828 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 6829 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 6830 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 6831 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 6832 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 6833 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 6834 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: 6835 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 6836 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 6837 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 6838 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 6839 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 6840 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 6841 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 6842 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 6843 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 6844 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 6845 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: 6846 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: 6847 case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: 6848 case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: 6849 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 6850 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 6851 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 6852 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 6853 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 6854 return true; 6855 } 6856 return false; 6857 } 6858 6859 static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) 6860 { 6861 switch (reg) { 6862 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 6863 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 6864 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 6865 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 6866 case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: 6867 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 6868 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: 6869 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 6870 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET: 6871 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 6872 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: 6873 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 6874 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: 6875 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: 6876 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: 6877 case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: 6878 case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: 6879 case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: 6880 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 6881 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 6882 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 6883 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 6884 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 6885 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 6886 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 6887 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 6888 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 6889 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 6890 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 6891 case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: 6892 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 6893 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 6894 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: 6895 case MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET: 6896 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 6897 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 6898 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 6899 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 6900 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 6901 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 6902 case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET: 6903 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 6904 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 6905 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 6906 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 6907 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 6908 case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET: 6909 case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: 6910 case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: 6911 case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: 6912 case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: 6913 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 6914 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 6915 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 6916 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 6917 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 6918 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 6919 case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: 6920 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: 6921 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: 6922 case MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET: 6923 case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: 6924 case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: 6925 case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: 6926 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 6927 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 6928 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 6929 case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: 6930 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: 6931 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: 6932 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 6933 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 6934 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 6935 case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: 6936 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 6937 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 6938 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 6939 case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET: 6940 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 6941 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 6942 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 6943 case MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET: 6944 case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET: 6945 case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET: 6946 case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: 6947 case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: 6948 case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: 6949 case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET: 6950 case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: 6951 case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: 6952 case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET: 6953 case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: 6954 case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: 6955 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: 6956 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 6957 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: 6958 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 6959 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 6960 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET: 6961 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 6962 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 6963 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 6964 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 6965 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 6966 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET: 6967 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 6968 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 6969 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET: 6970 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 6971 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 6972 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET: 6973 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 6974 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 6975 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: 6976 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 6977 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 6978 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 6979 case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET: 6980 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: 6981 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 6982 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 6983 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 6984 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 6985 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 6986 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 6987 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 6988 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 6989 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 6990 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 6991 case MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET: 6992 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: 6993 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: 6994 case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: 6995 case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: 6996 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 6997 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 6998 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 6999 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 7000 case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET: 7001 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 7002 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 7003 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 7004 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 7005 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 7006 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 7007 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 7008 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 7009 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 7010 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 7011 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 7012 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 7013 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 7014 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 7015 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 7016 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 7017 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: 7018 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: 7019 case MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET: 7020 case MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET: 7021 case MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET: 7022 case MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET: 7023 case MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET: 7024 case MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET: 7025 case MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET: 7026 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 7027 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 7028 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 7029 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 7030 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 7031 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 7032 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: 7033 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 7034 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 7035 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: 7036 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 7037 return true; 7038 } 7039 return false; 7040 } 7041 7042 static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) 7043 { 7044 switch (reg) { 7045 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 7046 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 7047 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 7048 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 7049 case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: 7050 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 7051 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: 7052 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 7053 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET: 7054 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 7055 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: 7056 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 7057 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: 7058 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: 7059 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: 7060 case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: 7061 case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: 7062 case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: 7063 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 7064 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 7065 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 7066 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 7067 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 7068 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 7069 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 7070 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 7071 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 7072 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 7073 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 7074 case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: 7075 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 7076 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 7077 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: 7078 case MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET: 7079 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 7080 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 7081 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 7082 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 7083 case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET: 7084 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 7085 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 7086 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 7087 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 7088 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 7089 case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET: 7090 case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: 7091 case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: 7092 case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: 7093 case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: 7094 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 7095 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 7096 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 7097 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 7098 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 7099 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 7100 case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: 7101 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: 7102 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: 7103 case MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET: 7104 case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: 7105 case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: 7106 case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: 7107 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 7108 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 7109 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 7110 case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: 7111 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: 7112 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: 7113 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 7114 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 7115 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 7116 case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: 7117 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 7118 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 7119 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 7120 case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET: 7121 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 7122 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 7123 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 7124 case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: 7125 case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: 7126 case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: 7127 case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET: 7128 case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: 7129 case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: 7130 case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET: 7131 case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: 7132 case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: 7133 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: 7134 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 7135 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: 7136 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 7137 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 7138 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET: 7139 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 7140 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 7141 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 7142 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 7143 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 7144 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET: 7145 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 7146 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 7147 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET: 7148 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 7149 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 7150 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET: 7151 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 7152 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 7153 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: 7154 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 7155 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 7156 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 7157 case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET: 7158 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: 7159 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 7160 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 7161 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 7162 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 7163 case MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET: 7164 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: 7165 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: 7166 case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: 7167 case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: 7168 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 7169 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 7170 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 7171 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 7172 case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET: 7173 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 7174 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 7175 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 7176 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 7177 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 7178 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 7179 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 7180 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 7181 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 7182 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 7183 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 7184 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 7185 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 7186 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 7187 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 7188 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 7189 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: 7190 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: 7191 case MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET: 7192 case MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET: 7193 case MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET: 7194 case MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET: 7195 case MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET: 7196 case MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET: 7197 case MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET: 7198 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 7199 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 7200 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 7201 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 7202 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 7203 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 7204 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: 7205 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 7206 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 7207 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: 7208 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 7209 return true; 7210 } 7211 return false; 7212 } 7213 7214 static const struct reg_default mlxplat_mlxcpld_regmap_default[] = { 7215 { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 }, 7216 { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 }, 7217 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 7218 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 7219 }; 7220 7221 static const struct reg_default mlxplat_mlxcpld_regmap_ng[] = { 7222 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 7223 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 7224 }; 7225 7226 static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = { 7227 { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, 7228 MLXPLAT_CPLD_LOW_AGGRCX_MASK }, 7229 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 7230 }; 7231 7232 static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { 7233 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 7234 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 7235 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 7236 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 7237 }; 7238 7239 static const struct reg_default mlxplat_mlxcpld_regmap_rack_switch[] = { 7240 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT }, 7241 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 7242 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 7243 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 7244 }; 7245 7246 static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = { 7247 { MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 0x61 }, 7248 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 7249 { MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, 0x00 }, 7250 { MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, 0x00 }, 7251 { MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, 0x00 }, 7252 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 7253 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 7254 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 7255 { MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET, 7256 MLXPLAT_CPLD_AGGR_MASK_LC_LOW }, 7257 }; 7258 7259 static const struct reg_default mlxplat_mlxcpld_regmap_smart_switch[] = { 7260 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 7261 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 7262 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 7263 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 7264 { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, MLXPLAT_CPLD_LPC_SM_SW_MASK }, 7265 }; 7266 7267 struct mlxplat_mlxcpld_regmap_context { 7268 void __iomem *base; 7269 }; 7270 7271 static struct mlxplat_mlxcpld_regmap_context mlxplat_mlxcpld_regmap_ctx; 7272 7273 static int 7274 mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val) 7275 { 7276 struct mlxplat_mlxcpld_regmap_context *ctx = context; 7277 7278 *val = ioread8(ctx->base + reg); 7279 return 0; 7280 } 7281 7282 static int 7283 mlxplat_mlxcpld_reg_write(void *context, unsigned int reg, unsigned int val) 7284 { 7285 struct mlxplat_mlxcpld_regmap_context *ctx = context; 7286 7287 iowrite8(val, ctx->base + reg); 7288 return 0; 7289 } 7290 7291 static const struct regmap_config mlxplat_mlxcpld_regmap_config = { 7292 .reg_bits = 8, 7293 .val_bits = 8, 7294 .max_register = 255, 7295 .cache_type = REGCACHE_FLAT, 7296 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 7297 .readable_reg = mlxplat_mlxcpld_readable_reg, 7298 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 7299 .reg_defaults = mlxplat_mlxcpld_regmap_default, 7300 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_default), 7301 .reg_read = mlxplat_mlxcpld_reg_read, 7302 .reg_write = mlxplat_mlxcpld_reg_write, 7303 }; 7304 7305 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng = { 7306 .reg_bits = 8, 7307 .val_bits = 8, 7308 .max_register = 255, 7309 .cache_type = REGCACHE_FLAT, 7310 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 7311 .readable_reg = mlxplat_mlxcpld_readable_reg, 7312 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 7313 .reg_defaults = mlxplat_mlxcpld_regmap_ng, 7314 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng), 7315 .reg_read = mlxplat_mlxcpld_reg_read, 7316 .reg_write = mlxplat_mlxcpld_reg_write, 7317 }; 7318 7319 static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = { 7320 .reg_bits = 8, 7321 .val_bits = 8, 7322 .max_register = 255, 7323 .cache_type = REGCACHE_FLAT, 7324 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 7325 .readable_reg = mlxplat_mlxcpld_readable_reg, 7326 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 7327 .reg_defaults = mlxplat_mlxcpld_regmap_comex_default, 7328 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_comex_default), 7329 .reg_read = mlxplat_mlxcpld_reg_read, 7330 .reg_write = mlxplat_mlxcpld_reg_write, 7331 }; 7332 7333 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = { 7334 .reg_bits = 8, 7335 .val_bits = 8, 7336 .max_register = 255, 7337 .cache_type = REGCACHE_FLAT, 7338 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 7339 .readable_reg = mlxplat_mlxcpld_readable_reg, 7340 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 7341 .reg_defaults = mlxplat_mlxcpld_regmap_ng400, 7342 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng400), 7343 .reg_read = mlxplat_mlxcpld_reg_read, 7344 .reg_write = mlxplat_mlxcpld_reg_write, 7345 }; 7346 7347 static const struct regmap_config mlxplat_mlxcpld_regmap_config_rack_switch = { 7348 .reg_bits = 8, 7349 .val_bits = 8, 7350 .max_register = 255, 7351 .cache_type = REGCACHE_FLAT, 7352 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 7353 .readable_reg = mlxplat_mlxcpld_readable_reg, 7354 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 7355 .reg_defaults = mlxplat_mlxcpld_regmap_rack_switch, 7356 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_rack_switch), 7357 .reg_read = mlxplat_mlxcpld_reg_read, 7358 .reg_write = mlxplat_mlxcpld_reg_write, 7359 }; 7360 7361 static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = { 7362 .reg_bits = 8, 7363 .val_bits = 8, 7364 .max_register = 255, 7365 .cache_type = REGCACHE_FLAT, 7366 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 7367 .readable_reg = mlxplat_mlxcpld_readable_reg, 7368 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 7369 .reg_defaults = mlxplat_mlxcpld_regmap_eth_modular, 7370 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_eth_modular), 7371 .reg_read = mlxplat_mlxcpld_reg_read, 7372 .reg_write = mlxplat_mlxcpld_reg_write, 7373 }; 7374 7375 static const struct regmap_config mlxplat_mlxcpld_regmap_config_smart_switch = { 7376 .reg_bits = 8, 7377 .val_bits = 8, 7378 .max_register = 255, 7379 .cache_type = REGCACHE_FLAT, 7380 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 7381 .readable_reg = mlxplat_mlxcpld_readable_reg, 7382 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 7383 .reg_defaults = mlxplat_mlxcpld_regmap_smart_switch, 7384 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_smart_switch), 7385 .reg_read = mlxplat_mlxcpld_reg_read, 7386 .reg_write = mlxplat_mlxcpld_reg_write, 7387 }; 7388 7389 static struct resource mlxplat_mlxcpld_resources[] = { 7390 [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), 7391 }; 7392 7393 static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c; 7394 static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug; 7395 static struct mlxreg_core_platform_data *mlxplat_led; 7396 static struct mlxreg_core_platform_data *mlxplat_regs_io; 7397 static struct mlxreg_core_platform_data *mlxplat_fan; 7398 static struct mlxreg_core_platform_data 7399 *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; 7400 static struct mlxreg_core_data *mlxplat_dpu_data[MLXPLAT_CPLD_DPU_MAX_DEVS]; 7401 static const struct regmap_config *mlxplat_regmap_config; 7402 static struct pci_dev *lpc_bridge; 7403 static struct pci_dev *i2c_bridge; 7404 static struct pci_dev *jtag_bridge; 7405 7406 /* Platform default reset function */ 7407 static int mlxplat_reboot_notifier(struct notifier_block *nb, unsigned long action, void *unused) 7408 { 7409 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 7410 u32 regval; 7411 int ret; 7412 7413 ret = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, ®val); 7414 7415 if (action == SYS_RESTART && !ret && regval & MLXPLAT_CPLD_SYS_RESET_MASK) 7416 regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, 7417 MLXPLAT_CPLD_RESET_MASK); 7418 7419 return NOTIFY_DONE; 7420 } 7421 7422 static struct notifier_block mlxplat_reboot_default_nb = { 7423 .notifier_call = mlxplat_reboot_notifier, 7424 }; 7425 7426 /* Platform default poweroff function */ 7427 static void mlxplat_poweroff(void) 7428 { 7429 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 7430 7431 if (mlxplat_reboot_nb) 7432 unregister_reboot_notifier(mlxplat_reboot_nb); 7433 regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, MLXPLAT_CPLD_HALT_MASK); 7434 kernel_halt(); 7435 } 7436 7437 static int __init mlxplat_register_platform_device(void) 7438 { 7439 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1, 7440 mlxplat_lpc_resources, 7441 ARRAY_SIZE(mlxplat_lpc_resources)); 7442 if (IS_ERR(mlxplat_dev)) 7443 return PTR_ERR(mlxplat_dev); 7444 else 7445 return 1; 7446 } 7447 7448 static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) 7449 { 7450 int i; 7451 7452 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7453 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7454 mlxplat_mux_data = mlxplat_default_mux_data; 7455 for (i = 0; i < mlxplat_mux_num; i++) { 7456 mlxplat_mux_data[i].values = mlxplat_default_channels[i]; 7457 mlxplat_mux_data[i].n_values = 7458 ARRAY_SIZE(mlxplat_default_channels[i]); 7459 } 7460 mlxplat_hotplug = &mlxplat_mlxcpld_default_data; 7461 mlxplat_hotplug->deferred_nr = 7462 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7463 mlxplat_led = &mlxplat_default_led_data; 7464 mlxplat_regs_io = &mlxplat_default_regs_io_data; 7465 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 7466 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 7467 7468 return mlxplat_register_platform_device(); 7469 } 7470 7471 static int __init mlxplat_dmi_default_wc_matched(const struct dmi_system_id *dmi) 7472 { 7473 int i; 7474 7475 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7476 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7477 mlxplat_mux_data = mlxplat_default_mux_data; 7478 for (i = 0; i < mlxplat_mux_num; i++) { 7479 mlxplat_mux_data[i].values = mlxplat_default_channels[i]; 7480 mlxplat_mux_data[i].n_values = 7481 ARRAY_SIZE(mlxplat_default_channels[i]); 7482 } 7483 mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data; 7484 mlxplat_hotplug->deferred_nr = 7485 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7486 mlxplat_led = &mlxplat_default_led_wc_data; 7487 mlxplat_regs_io = &mlxplat_default_regs_io_data; 7488 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 7489 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 7490 7491 return mlxplat_register_platform_device(); 7492 } 7493 7494 static int __init mlxplat_dmi_default_eth_wc_blade_matched(const struct dmi_system_id *dmi) 7495 { 7496 int i; 7497 7498 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7499 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7500 mlxplat_mux_data = mlxplat_default_mux_data; 7501 for (i = 0; i < mlxplat_mux_num; i++) { 7502 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7503 mlxplat_mux_data[i].n_values = 7504 ARRAY_SIZE(mlxplat_msn21xx_channels); 7505 } 7506 mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data; 7507 mlxplat_hotplug->deferred_nr = 7508 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7509 mlxplat_led = &mlxplat_default_led_eth_wc_blade_data; 7510 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7511 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7512 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7513 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7514 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; 7515 7516 return mlxplat_register_platform_device(); 7517 } 7518 7519 static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) 7520 { 7521 int i; 7522 7523 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7524 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7525 mlxplat_mux_data = mlxplat_default_mux_data; 7526 for (i = 0; i < mlxplat_mux_num; i++) { 7527 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7528 mlxplat_mux_data[i].n_values = 7529 ARRAY_SIZE(mlxplat_msn21xx_channels); 7530 } 7531 mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data; 7532 mlxplat_hotplug->deferred_nr = 7533 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7534 mlxplat_led = &mlxplat_msn21xx_led_data; 7535 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 7536 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 7537 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 7538 7539 return mlxplat_register_platform_device(); 7540 } 7541 7542 static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi) 7543 { 7544 int i; 7545 7546 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7547 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7548 mlxplat_mux_data = mlxplat_default_mux_data; 7549 for (i = 0; i < mlxplat_mux_num; i++) { 7550 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7551 mlxplat_mux_data[i].n_values = 7552 ARRAY_SIZE(mlxplat_msn21xx_channels); 7553 } 7554 mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data; 7555 mlxplat_hotplug->deferred_nr = 7556 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7557 mlxplat_led = &mlxplat_default_led_data; 7558 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 7559 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 7560 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 7561 7562 return mlxplat_register_platform_device(); 7563 } 7564 7565 static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi) 7566 { 7567 int i; 7568 7569 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7570 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7571 mlxplat_mux_data = mlxplat_default_mux_data; 7572 for (i = 0; i < mlxplat_mux_num; i++) { 7573 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7574 mlxplat_mux_data[i].n_values = 7575 ARRAY_SIZE(mlxplat_msn21xx_channels); 7576 } 7577 mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data; 7578 mlxplat_hotplug->deferred_nr = 7579 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7580 mlxplat_led = &mlxplat_msn21xx_led_data; 7581 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 7582 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 7583 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 7584 7585 return mlxplat_register_platform_device(); 7586 } 7587 7588 static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi) 7589 { 7590 int i; 7591 7592 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7593 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7594 mlxplat_mux_data = mlxplat_default_mux_data; 7595 for (i = 0; i < mlxplat_mux_num; i++) { 7596 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7597 mlxplat_mux_data[i].n_values = 7598 ARRAY_SIZE(mlxplat_msn21xx_channels); 7599 } 7600 mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data; 7601 mlxplat_hotplug->deferred_nr = 7602 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7603 mlxplat_led = &mlxplat_default_ng_led_data; 7604 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7605 mlxplat_fan = &mlxplat_default_fan_data; 7606 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7607 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7608 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7609 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; 7610 7611 return mlxplat_register_platform_device(); 7612 } 7613 7614 static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi) 7615 { 7616 int i; 7617 7618 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 7619 mlxplat_mux_num = ARRAY_SIZE(mlxplat_extended_mux_data); 7620 mlxplat_mux_data = mlxplat_extended_mux_data; 7621 for (i = 0; i < mlxplat_mux_num; i++) { 7622 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7623 mlxplat_mux_data[i].n_values = 7624 ARRAY_SIZE(mlxplat_msn21xx_channels); 7625 } 7626 mlxplat_hotplug = &mlxplat_mlxcpld_comex_data; 7627 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 7628 mlxplat_led = &mlxplat_comex_100G_led_data; 7629 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7630 mlxplat_fan = &mlxplat_default_fan_data; 7631 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7632 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7633 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 7634 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex; 7635 7636 return mlxplat_register_platform_device(); 7637 } 7638 7639 static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) 7640 { 7641 int i; 7642 7643 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7644 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7645 mlxplat_mux_data = mlxplat_default_mux_data; 7646 for (i = 0; i < mlxplat_mux_num; i++) { 7647 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7648 mlxplat_mux_data[i].n_values = 7649 ARRAY_SIZE(mlxplat_msn21xx_channels); 7650 } 7651 mlxplat_hotplug = &mlxplat_mlxcpld_ext_data; 7652 mlxplat_hotplug->deferred_nr = 7653 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7654 mlxplat_led = &mlxplat_default_ng_led_data; 7655 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7656 mlxplat_fan = &mlxplat_default_fan_data; 7657 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7658 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7659 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7660 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 7661 7662 return mlxplat_register_platform_device(); 7663 } 7664 7665 static int __init mlxplat_dmi_ng400_dgx_matched(const struct dmi_system_id *dmi) 7666 { 7667 int i; 7668 7669 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7670 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7671 mlxplat_mux_data = mlxplat_default_mux_data; 7672 for (i = 0; i < mlxplat_mux_num; i++) { 7673 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7674 mlxplat_mux_data[i].n_values = 7675 ARRAY_SIZE(mlxplat_msn21xx_channels); 7676 } 7677 mlxplat_hotplug = &mlxplat_mlxcpld_dgx_ext_data; 7678 mlxplat_hotplug->deferred_nr = 7679 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7680 mlxplat_led = &mlxplat_default_ng_led_data; 7681 mlxplat_regs_io = &mlxplat_dgx_ng_regs_io_data; 7682 mlxplat_fan = &mlxplat_default_fan_data; 7683 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7684 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7685 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7686 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 7687 7688 return mlxplat_register_platform_device(); 7689 } 7690 7691 static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi) 7692 { 7693 int i; 7694 7695 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7696 mlxplat_mux_num = ARRAY_SIZE(mlxplat_modular_mux_data); 7697 mlxplat_mux_data = mlxplat_modular_mux_data; 7698 mlxplat_hotplug = &mlxplat_mlxcpld_modular_data; 7699 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR; 7700 mlxplat_led = &mlxplat_modular_led_data; 7701 mlxplat_regs_io = &mlxplat_modular_regs_io_data; 7702 mlxplat_fan = &mlxplat_default_fan_data; 7703 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7704 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7705 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7706 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_eth_modular; 7707 7708 return mlxplat_register_platform_device(); 7709 } 7710 7711 static int __init mlxplat_dmi_chassis_blade_matched(const struct dmi_system_id *dmi) 7712 { 7713 int i; 7714 7715 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7716 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 7717 mlxplat_mux_data = mlxplat_default_mux_data; 7718 mlxplat_hotplug = &mlxplat_mlxcpld_chassis_blade_data; 7719 mlxplat_hotplug->deferred_nr = 7720 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7721 for (i = 0; i < mlxplat_mux_num; i++) { 7722 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 7723 mlxplat_mux_data[i].n_values = 7724 ARRAY_SIZE(mlxplat_msn21xx_channels); 7725 } 7726 mlxplat_regs_io = &mlxplat_chassis_blade_regs_io_data; 7727 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7728 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 7729 7730 return mlxplat_register_platform_device(); 7731 } 7732 7733 static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dmi) 7734 { 7735 int i; 7736 7737 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7738 mlxplat_mux_num = ARRAY_SIZE(mlxplat_rack_switch_mux_data); 7739 mlxplat_mux_data = mlxplat_rack_switch_mux_data; 7740 mlxplat_hotplug = &mlxplat_mlxcpld_rack_switch_data; 7741 mlxplat_hotplug->deferred_nr = 7742 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7743 mlxplat_led = &mlxplat_default_ng_led_data; 7744 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7745 mlxplat_fan = &mlxplat_default_fan_data; 7746 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7747 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7748 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7749 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; 7750 7751 return mlxplat_register_platform_device(); 7752 } 7753 7754 static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi) 7755 { 7756 int i; 7757 7758 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7759 mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); 7760 mlxplat_mux_data = mlxplat_ng800_mux_data; 7761 mlxplat_hotplug = &mlxplat_mlxcpld_ng800_data; 7762 mlxplat_hotplug->deferred_nr = 7763 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7764 mlxplat_led = &mlxplat_default_ng_led_data; 7765 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7766 mlxplat_fan = &mlxplat_default_fan_data; 7767 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7768 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7769 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7770 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 7771 7772 return mlxplat_register_platform_device(); 7773 } 7774 7775 static int __init mlxplat_dmi_ng800_dgx_matched(const struct dmi_system_id *dmi) 7776 { 7777 int i; 7778 7779 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7780 mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); 7781 mlxplat_mux_data = mlxplat_ng800_mux_data; 7782 mlxplat_hotplug = &mlxplat_mlxcpld_dgx_ext_data; 7783 mlxplat_hotplug->deferred_nr = 7784 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7785 mlxplat_led = &mlxplat_default_ng_led_data; 7786 mlxplat_regs_io = &mlxplat_dgx_ng_regs_io_data; 7787 mlxplat_fan = &mlxplat_default_fan_data; 7788 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7789 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7790 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7791 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 7792 7793 return mlxplat_register_platform_device(); 7794 } 7795 7796 static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) 7797 { 7798 int i; 7799 7800 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7801 mlxplat_mux_num = ARRAY_SIZE(mlxplat_rack_switch_mux_data); 7802 mlxplat_mux_data = mlxplat_rack_switch_mux_data; 7803 mlxplat_hotplug = &mlxplat_mlxcpld_l1_switch_data; 7804 mlxplat_hotplug->deferred_nr = 7805 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7806 mlxplat_led = &mlxplat_l1_switch_led_data; 7807 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7808 mlxplat_fan = &mlxplat_default_fan_data; 7809 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7810 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7811 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7812 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; 7813 pm_power_off = mlxplat_poweroff; 7814 mlxplat_reboot_nb = &mlxplat_reboot_default_nb; 7815 7816 return mlxplat_register_platform_device(); 7817 } 7818 7819 static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *dmi) 7820 { 7821 int i; 7822 7823 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7824 mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); 7825 mlxplat_mux_data = mlxplat_ng800_mux_data; 7826 mlxplat_hotplug = &mlxplat_mlxcpld_smart_switch_data; 7827 mlxplat_hotplug->deferred_nr = 7828 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7829 mlxplat_led = &mlxplat_xdr_led_data; 7830 mlxplat_regs_io = &mlxplat_smart_switch_regs_io_data; 7831 mlxplat_fan = &mlxplat_xdr_fan_data; 7832 7833 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 7834 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 7835 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_data); i++) 7836 mlxplat_dpu_data[i] = &mlxplat_mlxcpld_smart_switch_dpu_data[i]; 7837 7838 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7839 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_smart_switch; 7840 7841 return mlxplat_register_platform_device(); 7842 } 7843 7844 static int __init mlxplat_dmi_ng400_hi171_matched(const struct dmi_system_id *dmi) 7845 { 7846 unsigned int i; 7847 7848 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 7849 mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); 7850 mlxplat_mux_data = mlxplat_ng800_mux_data; 7851 mlxplat_hotplug = &mlxplat_mlxcpld_ng800_hi171_data; 7852 mlxplat_hotplug->deferred_nr = 7853 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 7854 mlxplat_led = &mlxplat_xdr_led_data; 7855 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 7856 mlxplat_fan = &mlxplat_xdr_fan_data; 7857 7858 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) 7859 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type3[i]; 7860 7861 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 7862 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 7863 7864 return mlxplat_register_platform_device(); 7865 } 7866 7867 static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { 7868 { 7869 .callback = mlxplat_dmi_default_wc_matched, 7870 .matches = { 7871 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 7872 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI138"), 7873 }, 7874 }, 7875 { 7876 .callback = mlxplat_dmi_default_matched, 7877 .matches = { 7878 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 7879 }, 7880 }, 7881 { 7882 .callback = mlxplat_dmi_msn21xx_matched, 7883 .matches = { 7884 DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"), 7885 }, 7886 }, 7887 { 7888 .callback = mlxplat_dmi_msn274x_matched, 7889 .matches = { 7890 DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"), 7891 }, 7892 }, 7893 { 7894 .callback = mlxplat_dmi_msn201x_matched, 7895 .matches = { 7896 DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"), 7897 }, 7898 }, 7899 { 7900 .callback = mlxplat_dmi_default_eth_wc_blade_matched, 7901 .matches = { 7902 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), 7903 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI139"), 7904 }, 7905 }, 7906 { 7907 .callback = mlxplat_dmi_qmb7xx_matched, 7908 .matches = { 7909 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), 7910 }, 7911 }, 7912 { 7913 .callback = mlxplat_dmi_qmb7xx_matched, 7914 .matches = { 7915 DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"), 7916 }, 7917 }, 7918 { 7919 .callback = mlxplat_dmi_comex_matched, 7920 .matches = { 7921 DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"), 7922 }, 7923 }, 7924 { 7925 .callback = mlxplat_dmi_rack_switch_matched, 7926 .matches = { 7927 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), 7928 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI142"), 7929 }, 7930 }, 7931 { 7932 .callback = mlxplat_dmi_ng400_dgx_matched, 7933 .matches = { 7934 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), 7935 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI173"), 7936 }, 7937 }, 7938 { 7939 .callback = mlxplat_dmi_ng400_matched, 7940 .matches = { 7941 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), 7942 }, 7943 }, 7944 { 7945 .callback = mlxplat_dmi_modular_matched, 7946 .matches = { 7947 DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"), 7948 }, 7949 }, 7950 { 7951 .callback = mlxplat_dmi_ng800_dgx_matched, 7952 .matches = { 7953 DMI_MATCH(DMI_BOARD_NAME, "VMOD0013"), 7954 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI174"), 7955 }, 7956 }, 7957 { 7958 .callback = mlxplat_dmi_ng800_matched, 7959 .matches = { 7960 DMI_MATCH(DMI_BOARD_NAME, "VMOD0013"), 7961 }, 7962 }, 7963 { 7964 .callback = mlxplat_dmi_chassis_blade_matched, 7965 .matches = { 7966 DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"), 7967 }, 7968 }, 7969 { 7970 .callback = mlxplat_dmi_l1_switch_matched, 7971 .matches = { 7972 DMI_MATCH(DMI_BOARD_NAME, "VMOD0017"), 7973 }, 7974 }, 7975 { 7976 .callback = mlxplat_dmi_smart_switch_matched, 7977 .matches = { 7978 DMI_MATCH(DMI_BOARD_NAME, "VMOD0019"), 7979 }, 7980 }, 7981 { 7982 .callback = mlxplat_dmi_ng400_hi171_matched, 7983 .matches = { 7984 DMI_MATCH(DMI_BOARD_NAME, "VMOD0022"), 7985 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI171"), 7986 }, 7987 }, 7988 { 7989 .callback = mlxplat_dmi_ng400_hi171_matched, 7990 .matches = { 7991 DMI_MATCH(DMI_BOARD_NAME, "VMOD0022"), 7992 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI172"), 7993 }, 7994 }, 7995 { 7996 .callback = mlxplat_dmi_msn274x_matched, 7997 .matches = { 7998 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 7999 DMI_MATCH(DMI_PRODUCT_NAME, "MSN274"), 8000 }, 8001 }, 8002 { 8003 .callback = mlxplat_dmi_default_matched, 8004 .matches = { 8005 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 8006 DMI_MATCH(DMI_PRODUCT_NAME, "MSN24"), 8007 }, 8008 }, 8009 { 8010 .callback = mlxplat_dmi_default_matched, 8011 .matches = { 8012 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 8013 DMI_MATCH(DMI_PRODUCT_NAME, "MSN27"), 8014 }, 8015 }, 8016 { 8017 .callback = mlxplat_dmi_default_matched, 8018 .matches = { 8019 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 8020 DMI_MATCH(DMI_PRODUCT_NAME, "MSB"), 8021 }, 8022 }, 8023 { 8024 .callback = mlxplat_dmi_default_matched, 8025 .matches = { 8026 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 8027 DMI_MATCH(DMI_PRODUCT_NAME, "MSX"), 8028 }, 8029 }, 8030 { 8031 .callback = mlxplat_dmi_msn21xx_matched, 8032 .matches = { 8033 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 8034 DMI_MATCH(DMI_PRODUCT_NAME, "MSN21"), 8035 }, 8036 }, 8037 { 8038 .callback = mlxplat_dmi_msn201x_matched, 8039 .matches = { 8040 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 8041 DMI_MATCH(DMI_PRODUCT_NAME, "MSN201"), 8042 }, 8043 }, 8044 { 8045 .callback = mlxplat_dmi_qmb7xx_matched, 8046 .matches = { 8047 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 8048 DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"), 8049 }, 8050 }, 8051 { 8052 .callback = mlxplat_dmi_qmb7xx_matched, 8053 .matches = { 8054 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 8055 DMI_MATCH(DMI_PRODUCT_NAME, "MSN37"), 8056 }, 8057 }, 8058 { 8059 .callback = mlxplat_dmi_qmb7xx_matched, 8060 .matches = { 8061 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 8062 DMI_MATCH(DMI_PRODUCT_NAME, "MSN34"), 8063 }, 8064 }, 8065 { 8066 .callback = mlxplat_dmi_qmb7xx_matched, 8067 .matches = { 8068 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 8069 DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"), 8070 }, 8071 }, 8072 { } 8073 }; 8074 8075 MODULE_DEVICE_TABLE(dmi, mlxplat_dmi_table); 8076 8077 static int mlxplat_mlxcpld_verify_bus_topology(int *nr) 8078 { 8079 struct i2c_adapter *search_adap; 8080 int i, shift = 0; 8081 8082 /* Scan adapters from expected id to verify it is free. */ 8083 *nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; 8084 for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i < 8085 mlxplat_max_adap_num; i++) { 8086 search_adap = i2c_get_adapter(i); 8087 if (search_adap) { 8088 i2c_put_adapter(search_adap); 8089 continue; 8090 } 8091 8092 /* Return if expected parent adapter is free. */ 8093 if (i == MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR) 8094 return 0; 8095 break; 8096 } 8097 8098 /* Return with error if free id for adapter is not found. */ 8099 if (i == mlxplat_max_adap_num) 8100 return -ENODEV; 8101 8102 /* Shift adapter ids, since expected parent adapter is not free. */ 8103 *nr = i; 8104 for (i = 0; i < mlxplat_mux_num; i++) { 8105 shift = *nr - mlxplat_mux_data[i].parent; 8106 mlxplat_mux_data[i].parent = *nr; 8107 mlxplat_mux_data[i].base_nr += shift; 8108 } 8109 8110 if (shift > 0) 8111 mlxplat_hotplug->shift_nr = shift; 8112 8113 return 0; 8114 } 8115 8116 static int mlxplat_mlxcpld_check_wd_capability(void *regmap) 8117 { 8118 u32 regval; 8119 int i, rc; 8120 8121 rc = regmap_read(regmap, MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 8122 ®val); 8123 if (rc) 8124 return rc; 8125 8126 if (!(regval & ~MLXPLAT_CPLD_WD_CPBLTY_MASK)) { 8127 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) { 8128 if (mlxplat_wd_data[i]) 8129 mlxplat_wd_data[i] = 8130 &mlxplat_mlxcpld_wd_set_type3[i]; 8131 } 8132 } 8133 8134 return 0; 8135 } 8136 8137 static int mlxplat_lpc_cpld_device_init(struct resource **hotplug_resources, 8138 unsigned int *hotplug_resources_size) 8139 { 8140 int err; 8141 8142 mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, 8143 mlxplat_lpc_resources[1].start, 1); 8144 if (!mlxplat_mlxcpld_regmap_ctx.base) { 8145 err = -ENOMEM; 8146 goto fail_devm_ioport_map; 8147 } 8148 8149 *hotplug_resources = mlxplat_mlxcpld_resources; 8150 *hotplug_resources_size = ARRAY_SIZE(mlxplat_mlxcpld_resources); 8151 8152 return 0; 8153 8154 fail_devm_ioport_map: 8155 return err; 8156 } 8157 8158 static void mlxplat_lpc_cpld_device_exit(void) 8159 { 8160 } 8161 8162 static int 8163 mlxplat_pci_fpga_device_init(unsigned int device, const char *res_name, struct pci_dev **pci_bridge, 8164 void __iomem **pci_bridge_addr) 8165 { 8166 void __iomem *pci_mem_addr; 8167 struct pci_dev *pci_dev; 8168 int err; 8169 8170 pci_dev = pci_get_device(PCI_VENDOR_ID_LATTICE, device, NULL); 8171 if (!pci_dev) 8172 return -ENODEV; 8173 8174 err = pci_enable_device(pci_dev); 8175 if (err) { 8176 dev_err(&pci_dev->dev, "pci_enable_device failed with error %d\n", err); 8177 goto fail_pci_enable_device; 8178 } 8179 8180 err = pci_request_region(pci_dev, 0, res_name); 8181 if (err) { 8182 dev_err(&pci_dev->dev, "pci_request_regions failed with error %d\n", err); 8183 goto fail_pci_request_regions; 8184 } 8185 8186 err = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(64)); 8187 if (err) { 8188 err = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32)); 8189 if (err) { 8190 dev_err(&pci_dev->dev, "dma_set_mask failed with error %d\n", err); 8191 goto fail_pci_set_dma_mask; 8192 } 8193 } 8194 8195 pci_set_master(pci_dev); 8196 8197 pci_mem_addr = devm_ioremap(&pci_dev->dev, pci_resource_start(pci_dev, 0), 8198 pci_resource_len(pci_dev, 0)); 8199 if (!pci_mem_addr) { 8200 dev_err(&mlxplat_dev->dev, "ioremap failed\n"); 8201 err = -EIO; 8202 goto fail_ioremap; 8203 } 8204 8205 *pci_bridge = pci_dev; 8206 *pci_bridge_addr = pci_mem_addr; 8207 8208 return 0; 8209 8210 fail_ioremap: 8211 fail_pci_set_dma_mask: 8212 pci_release_regions(pci_dev); 8213 fail_pci_request_regions: 8214 pci_disable_device(pci_dev); 8215 fail_pci_enable_device: 8216 pci_dev_put(pci_dev); 8217 return err; 8218 } 8219 8220 static void 8221 mlxplat_pci_fpga_device_exit(struct pci_dev *pci_bridge, 8222 void __iomem *pci_bridge_addr) 8223 { 8224 iounmap(pci_bridge_addr); 8225 pci_release_regions(pci_bridge); 8226 pci_disable_device(pci_bridge); 8227 pci_dev_put(pci_bridge); 8228 } 8229 8230 static int 8231 mlxplat_pci_fpga_devices_init(struct resource **hotplug_resources, 8232 unsigned int *hotplug_resources_size) 8233 { 8234 int err; 8235 8236 err = mlxplat_pci_fpga_device_init(PCI_DEVICE_ID_LATTICE_LPC_BRIDGE, 8237 "mlxplat_lpc_bridge", &lpc_bridge, 8238 &mlxplat_mlxcpld_regmap_ctx.base); 8239 if (err) 8240 goto mlxplat_pci_fpga_device_init_lpc_fail; 8241 8242 err = mlxplat_pci_fpga_device_init(PCI_DEVICE_ID_LATTICE_I2C_BRIDGE, 8243 "mlxplat_i2c_bridge", &i2c_bridge, 8244 &i2c_bridge_addr); 8245 if (err) 8246 goto mlxplat_pci_fpga_device_init_i2c_fail; 8247 8248 err = mlxplat_pci_fpga_device_init(PCI_DEVICE_ID_LATTICE_JTAG_BRIDGE, 8249 "mlxplat_jtag_bridge", &jtag_bridge, 8250 &jtag_bridge_addr); 8251 if (err) 8252 goto mlxplat_pci_fpga_device_init_jtag_fail; 8253 8254 return 0; 8255 8256 mlxplat_pci_fpga_device_init_jtag_fail: 8257 mlxplat_pci_fpga_device_exit(i2c_bridge, i2c_bridge_addr); 8258 mlxplat_pci_fpga_device_init_i2c_fail: 8259 mlxplat_pci_fpga_device_exit(lpc_bridge, mlxplat_mlxcpld_regmap_ctx.base); 8260 mlxplat_pci_fpga_device_init_lpc_fail: 8261 return err; 8262 } 8263 8264 static void mlxplat_pci_fpga_devices_exit(void) 8265 { 8266 mlxplat_pci_fpga_device_exit(jtag_bridge, jtag_bridge_addr); 8267 mlxplat_pci_fpga_device_exit(i2c_bridge, i2c_bridge_addr); 8268 mlxplat_pci_fpga_device_exit(lpc_bridge, mlxplat_mlxcpld_regmap_ctx.base); 8269 } 8270 8271 static int 8272 mlxplat_logicdev_init(struct resource **hotplug_resources, unsigned int *hotplug_resources_size) 8273 { 8274 int err; 8275 8276 err = mlxplat_pci_fpga_devices_init(hotplug_resources, hotplug_resources_size); 8277 if (err == -ENODEV) 8278 return mlxplat_lpc_cpld_device_init(hotplug_resources, hotplug_resources_size); 8279 8280 return err; 8281 } 8282 8283 static void mlxplat_logicdev_exit(void) 8284 { 8285 if (lpc_bridge) 8286 mlxplat_pci_fpga_devices_exit(); 8287 else 8288 mlxplat_lpc_cpld_device_exit(); 8289 } 8290 8291 static int mlxplat_platdevs_init(struct mlxplat_priv *priv) 8292 { 8293 int i = 0, err; 8294 8295 /* Add hotplug driver */ 8296 if (mlxplat_hotplug) { 8297 mlxplat_hotplug->regmap = priv->regmap; 8298 if (priv->irq_fpga) 8299 mlxplat_hotplug->irq = priv->irq_fpga; 8300 priv->pdev_hotplug = 8301 platform_device_register_resndata(&mlxplat_dev->dev, 8302 "mlxreg-hotplug", PLATFORM_DEVID_NONE, 8303 priv->hotplug_resources, 8304 priv->hotplug_resources_size, 8305 mlxplat_hotplug, sizeof(*mlxplat_hotplug)); 8306 if (IS_ERR(priv->pdev_hotplug)) { 8307 err = PTR_ERR(priv->pdev_hotplug); 8308 goto fail_platform_hotplug_register; 8309 } 8310 } 8311 8312 /* Add LED driver. */ 8313 if (mlxplat_led) { 8314 mlxplat_led->regmap = priv->regmap; 8315 priv->pdev_led = 8316 platform_device_register_resndata(&mlxplat_dev->dev, "leds-mlxreg", 8317 PLATFORM_DEVID_NONE, NULL, 0, mlxplat_led, 8318 sizeof(*mlxplat_led)); 8319 if (IS_ERR(priv->pdev_led)) { 8320 err = PTR_ERR(priv->pdev_led); 8321 goto fail_platform_leds_register; 8322 } 8323 } 8324 8325 /* Add registers io access driver. */ 8326 if (mlxplat_regs_io) { 8327 mlxplat_regs_io->regmap = priv->regmap; 8328 priv->pdev_io_regs = platform_device_register_resndata(&mlxplat_dev->dev, 8329 "mlxreg-io", 8330 PLATFORM_DEVID_NONE, NULL, 8331 0, mlxplat_regs_io, 8332 sizeof(*mlxplat_regs_io)); 8333 if (IS_ERR(priv->pdev_io_regs)) { 8334 err = PTR_ERR(priv->pdev_io_regs); 8335 goto fail_platform_io_register; 8336 } 8337 } 8338 8339 /* Add FAN driver. */ 8340 if (mlxplat_fan) { 8341 mlxplat_fan->regmap = priv->regmap; 8342 priv->pdev_fan = platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-fan", 8343 PLATFORM_DEVID_NONE, NULL, 0, 8344 mlxplat_fan, 8345 sizeof(*mlxplat_fan)); 8346 if (IS_ERR(priv->pdev_fan)) { 8347 err = PTR_ERR(priv->pdev_fan); 8348 goto fail_platform_fan_register; 8349 } 8350 } 8351 8352 /* Add WD drivers. */ 8353 err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); 8354 if (err) 8355 goto fail_platform_wd_register; 8356 for (i = 0; i < MLXPLAT_CPLD_WD_MAX_DEVS; i++) { 8357 if (mlxplat_wd_data[i]) { 8358 mlxplat_wd_data[i]->regmap = priv->regmap; 8359 priv->pdev_wd[i] = 8360 platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", i, 8361 NULL, 0, mlxplat_wd_data[i], 8362 sizeof(*mlxplat_wd_data[i])); 8363 if (IS_ERR(priv->pdev_wd[i])) { 8364 err = PTR_ERR(priv->pdev_wd[i]); 8365 goto fail_platform_wd_register; 8366 } 8367 } 8368 } 8369 8370 /* Add DPU drivers. */ 8371 for (i = 0; i < MLXPLAT_CPLD_DPU_MAX_DEVS; i++) { 8372 if (!mlxplat_dpu_data[i]) 8373 continue; 8374 priv->pdev_dpu[i] = 8375 platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-dpu", 8376 i, NULL, 0, mlxplat_dpu_data[i], 8377 sizeof(*mlxplat_dpu_data[i])); 8378 if (IS_ERR(priv->pdev_dpu[i])) { 8379 err = PTR_ERR(priv->pdev_dpu[i]); 8380 goto fail_platform_dpu_register; 8381 } 8382 } 8383 8384 return 0; 8385 8386 fail_platform_dpu_register: 8387 while (i--) 8388 platform_device_unregister(priv->pdev_dpu[i]); 8389 fail_platform_wd_register: 8390 while (i--) 8391 platform_device_unregister(priv->pdev_wd[i]); 8392 fail_platform_fan_register: 8393 if (mlxplat_regs_io) 8394 platform_device_unregister(priv->pdev_io_regs); 8395 fail_platform_io_register: 8396 if (mlxplat_led) 8397 platform_device_unregister(priv->pdev_led); 8398 fail_platform_leds_register: 8399 if (mlxplat_hotplug) 8400 platform_device_unregister(priv->pdev_hotplug); 8401 fail_platform_hotplug_register: 8402 return err; 8403 } 8404 8405 static void mlxplat_platdevs_exit(struct mlxplat_priv *priv) 8406 { 8407 int i; 8408 8409 for (i = MLXPLAT_CPLD_DPU_MAX_DEVS - 1; i >= 0; i--) 8410 platform_device_unregister(priv->pdev_dpu[i]); 8411 for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0; i--) 8412 platform_device_unregister(priv->pdev_wd[i]); 8413 if (priv->pdev_fan) 8414 platform_device_unregister(priv->pdev_fan); 8415 if (priv->pdev_io_regs) 8416 platform_device_unregister(priv->pdev_io_regs); 8417 if (priv->pdev_led) 8418 platform_device_unregister(priv->pdev_led); 8419 if (priv->pdev_hotplug) 8420 platform_device_unregister(priv->pdev_hotplug); 8421 } 8422 8423 static int 8424 mlxplat_i2c_mux_complition_notify(void *handle, struct i2c_adapter *parent, 8425 struct i2c_adapter *adapters[]) 8426 { 8427 struct mlxplat_priv *priv = handle; 8428 8429 return mlxplat_platdevs_init(priv); 8430 } 8431 8432 static int mlxplat_i2c_mux_topology_init(struct mlxplat_priv *priv) 8433 { 8434 int i, err; 8435 8436 if (!priv->pdev_i2c) { 8437 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_NOTIFIED; 8438 return 0; 8439 } 8440 8441 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED; 8442 for (i = 0; i < mlxplat_mux_num; i++) { 8443 priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev, 8444 "i2c-mux-reg", i, NULL, 0, 8445 &mlxplat_mux_data[i], 8446 sizeof(mlxplat_mux_data[i])); 8447 if (IS_ERR(priv->pdev_mux[i])) { 8448 err = PTR_ERR(priv->pdev_mux[i]); 8449 goto fail_platform_mux_register; 8450 } 8451 } 8452 8453 return mlxplat_i2c_mux_complition_notify(priv, NULL, NULL); 8454 8455 fail_platform_mux_register: 8456 while (i--) 8457 platform_device_unregister(priv->pdev_mux[i]); 8458 return err; 8459 } 8460 8461 static void mlxplat_i2c_mux_topology_exit(struct mlxplat_priv *priv) 8462 { 8463 int i; 8464 8465 for (i = mlxplat_mux_num - 1; i >= 0; i--) { 8466 if (priv->pdev_mux[i]) 8467 platform_device_unregister(priv->pdev_mux[i]); 8468 } 8469 } 8470 8471 static int mlxplat_i2c_main_completion_notify(void *handle, int id) 8472 { 8473 struct mlxplat_priv *priv = handle; 8474 8475 return mlxplat_i2c_mux_topology_init(priv); 8476 } 8477 8478 static int mlxplat_i2c_main_init(struct mlxplat_priv *priv) 8479 { 8480 int nr, err; 8481 8482 if (!mlxplat_i2c) 8483 return 0; 8484 8485 err = mlxplat_mlxcpld_verify_bus_topology(&nr); 8486 if (nr < 0) 8487 goto fail_mlxplat_mlxcpld_verify_bus_topology; 8488 8489 nr = (nr == mlxplat_max_adap_num) ? -1 : nr; 8490 mlxplat_i2c->regmap = priv->regmap; 8491 mlxplat_i2c->handle = priv; 8492 8493 /* Set mapped base address of I2C-LPC bridge over PCIe */ 8494 if (lpc_bridge) 8495 mlxplat_i2c->addr = i2c_bridge_addr; 8496 priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", 8497 nr, priv->hotplug_resources, 8498 priv->hotplug_resources_size, 8499 mlxplat_i2c, sizeof(*mlxplat_i2c)); 8500 if (IS_ERR(priv->pdev_i2c)) { 8501 err = PTR_ERR(priv->pdev_i2c); 8502 goto fail_platform_i2c_register; 8503 } 8504 8505 if (priv->i2c_main_init_status == MLXPLAT_I2C_MAIN_BUS_NOTIFIED) { 8506 err = mlxplat_i2c_mux_topology_init(priv); 8507 if (err) 8508 goto fail_mlxplat_i2c_mux_topology_init; 8509 } 8510 8511 return 0; 8512 8513 fail_mlxplat_i2c_mux_topology_init: 8514 platform_device_unregister(priv->pdev_i2c); 8515 fail_platform_i2c_register: 8516 fail_mlxplat_mlxcpld_verify_bus_topology: 8517 return err; 8518 } 8519 8520 static void mlxplat_i2c_main_exit(struct mlxplat_priv *priv) 8521 { 8522 mlxplat_platdevs_exit(priv); 8523 mlxplat_i2c_mux_topology_exit(priv); 8524 if (priv->pdev_i2c) 8525 platform_device_unregister(priv->pdev_i2c); 8526 } 8527 8528 static int mlxplat_probe(struct platform_device *pdev) 8529 { 8530 unsigned int hotplug_resources_size = 0; 8531 struct resource *hotplug_resources = NULL; 8532 struct acpi_device *acpi_dev; 8533 struct mlxplat_priv *priv; 8534 int irq_fpga = 0, i, err; 8535 8536 acpi_dev = ACPI_COMPANION(&pdev->dev); 8537 if (acpi_dev) { 8538 irq_fpga = acpi_dev_gpio_irq_get(acpi_dev, 0); 8539 if (irq_fpga < 0) 8540 return -ENODEV; 8541 mlxplat_dev = pdev; 8542 } 8543 8544 err = mlxplat_logicdev_init(&hotplug_resources, &hotplug_resources_size); 8545 if (err) 8546 return err; 8547 8548 priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), 8549 GFP_KERNEL); 8550 if (!priv) { 8551 err = -ENOMEM; 8552 goto fail_alloc; 8553 } 8554 platform_set_drvdata(mlxplat_dev, priv); 8555 priv->hotplug_resources = hotplug_resources; 8556 priv->hotplug_resources_size = hotplug_resources_size; 8557 priv->irq_fpga = irq_fpga; 8558 8559 if (!mlxplat_regmap_config) 8560 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; 8561 8562 priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, 8563 &mlxplat_mlxcpld_regmap_ctx, 8564 mlxplat_regmap_config); 8565 if (IS_ERR(priv->regmap)) { 8566 err = PTR_ERR(priv->regmap); 8567 goto fail_alloc; 8568 } 8569 8570 /* Set default registers. */ 8571 for (i = 0; i < mlxplat_regmap_config->num_reg_defaults; i++) { 8572 err = regmap_write(priv->regmap, 8573 mlxplat_regmap_config->reg_defaults[i].reg, 8574 mlxplat_regmap_config->reg_defaults[i].def); 8575 if (err) 8576 goto fail_regmap_write; 8577 } 8578 8579 err = mlxplat_i2c_main_init(priv); 8580 if (err) 8581 goto fail_mlxplat_i2c_main_init; 8582 8583 /* Sync registers with hardware. */ 8584 regcache_mark_dirty(priv->regmap); 8585 err = regcache_sync(priv->regmap); 8586 if (err) 8587 goto fail_regcache_sync; 8588 8589 if (mlxplat_reboot_nb) { 8590 err = register_reboot_notifier(mlxplat_reboot_nb); 8591 if (err) 8592 goto fail_register_reboot_notifier; 8593 } 8594 8595 return 0; 8596 8597 fail_register_reboot_notifier: 8598 fail_regcache_sync: 8599 mlxplat_i2c_main_exit(priv); 8600 fail_mlxplat_i2c_main_init: 8601 fail_regmap_write: 8602 fail_alloc: 8603 mlxplat_logicdev_exit(); 8604 8605 return err; 8606 } 8607 8608 static void mlxplat_remove(struct platform_device *pdev) 8609 { 8610 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 8611 8612 if (pm_power_off) 8613 pm_power_off = NULL; 8614 if (mlxplat_reboot_nb) 8615 unregister_reboot_notifier(mlxplat_reboot_nb); 8616 mlxplat_i2c_main_exit(priv); 8617 mlxplat_logicdev_exit(); 8618 } 8619 8620 static const struct acpi_device_id mlxplat_acpi_table[] = { 8621 { "MLNXBF49", 0 }, 8622 {} 8623 }; 8624 MODULE_DEVICE_TABLE(acpi, mlxplat_acpi_table); 8625 8626 static struct platform_driver mlxplat_driver = { 8627 .driver = { 8628 .name = "mlxplat", 8629 .acpi_match_table = mlxplat_acpi_table, 8630 .probe_type = PROBE_FORCE_SYNCHRONOUS, 8631 }, 8632 .probe = mlxplat_probe, 8633 .remove = mlxplat_remove, 8634 }; 8635 8636 static int __init mlxplat_init(void) 8637 { 8638 int err; 8639 8640 if (!dmi_check_system(mlxplat_dmi_table)) 8641 return -ENODEV; 8642 8643 err = platform_driver_register(&mlxplat_driver); 8644 if (err) 8645 return err; 8646 return 0; 8647 } 8648 module_init(mlxplat_init); 8649 8650 static void __exit mlxplat_exit(void) 8651 { 8652 if (mlxplat_dev) 8653 platform_device_unregister(mlxplat_dev); 8654 8655 platform_driver_unregister(&mlxplat_driver); 8656 } 8657 module_exit(mlxplat_exit); 8658 8659 MODULE_AUTHOR("Vadim Pasternak <vadimp@mellanox.com>"); 8660 MODULE_DESCRIPTION("Mellanox platform driver"); 8661 MODULE_LICENSE("Dual BSD/GPL"); 8662