1 // SPDX-License-Identifier: GPL-2.0 2 // LPC interface for ChromeOS Embedded Controller 3 // 4 // Copyright (C) 2012-2015 Google, Inc 5 // 6 // This driver uses the ChromeOS EC byte-level message-based protocol for 7 // communicating the keyboard state (which keys are pressed) from a keyboard EC 8 // to the AP over some bus (such as i2c, lpc, spi). The EC does debouncing, 9 // but everything else (including deghosting) is done here. The main 10 // motivation for this is to keep the EC firmware as simple as possible, since 11 // it cannot be easily upgraded and EC flash/IRAM space is relatively 12 // expensive. 13 14 #include <linux/acpi.h> 15 #include <linux/dmi.h> 16 #include <linux/delay.h> 17 #include <linux/io.h> 18 #include <linux/interrupt.h> 19 #include <linux/kobject.h> 20 #include <linux/module.h> 21 #include <linux/platform_data/cros_ec_commands.h> 22 #include <linux/platform_data/cros_ec_proto.h> 23 #include <linux/platform_device.h> 24 #include <linux/printk.h> 25 #include <linux/reboot.h> 26 #include <linux/suspend.h> 27 28 #include "cros_ec.h" 29 #include "cros_ec_lpc_mec.h" 30 31 #define DRV_NAME "cros_ec_lpcs" 32 #define ACPI_DRV_NAME "GOOG0004" 33 34 /* True if ACPI device is present */ 35 static bool cros_ec_lpc_acpi_device_found; 36 37 /* 38 * Indicates that lpc_driver_data.quirk_mmio_memory_base should 39 * be used as the base port for EC mapped memory. 40 */ 41 #define CROS_EC_LPC_QUIRK_REMAP_MEMORY BIT(0) 42 /* 43 * Indicates that lpc_driver_data.quirk_acpi_id should be used to find 44 * the ACPI device. 45 */ 46 #define CROS_EC_LPC_QUIRK_ACPI_ID BIT(1) 47 /* 48 * Indicates that lpc_driver_data.quirk_aml_mutex_name should be used 49 * to find an AML mutex to protect access to Microchip EC. 50 */ 51 #define CROS_EC_LPC_QUIRK_AML_MUTEX BIT(2) 52 53 /** 54 * struct lpc_driver_data - driver data attached to a DMI device ID to indicate 55 * hardware quirks. 56 * @quirks: a bitfield composed of quirks from CROS_EC_LPC_QUIRK_* 57 * @quirk_mmio_memory_base: The first I/O port addressing EC mapped memory (used 58 * when quirk ...REMAP_MEMORY is set.) 59 * @quirk_acpi_id: An ACPI HID to be used to find the ACPI device. 60 * @quirk_aml_mutex_name: The name of an AML mutex to be used to protect access 61 * to Microchip EC. 62 */ 63 struct lpc_driver_data { 64 u32 quirks; 65 u16 quirk_mmio_memory_base; 66 const char *quirk_acpi_id; 67 const char *quirk_aml_mutex_name; 68 }; 69 70 /** 71 * struct cros_ec_lpc - LPC device-specific data 72 * @mmio_memory_base: The first I/O port addressing EC mapped memory. 73 * @base: For EC supporting memory mapping, base address of the mapped region. 74 * @mem32: Information about the memory mapped register region, if present. 75 * @read: Copy length bytes from EC address offset into buffer dest. 76 * Returns a negative error code on error, or the 8-bit checksum 77 * of all bytes read. 78 * @write: Copy length bytes from buffer msg into EC address offset. 79 * Returns a negative error code on error, or the 8-bit checksum 80 * of all bytes written. 81 */ 82 struct cros_ec_lpc { 83 u16 mmio_memory_base; 84 void __iomem *base; 85 struct acpi_resource_fixed_memory32 mem32; 86 int (*read)(struct cros_ec_lpc *ec_lpc, unsigned int offset, 87 unsigned int length, u8 *dest); 88 int (*write)(struct cros_ec_lpc *ec_lpc, unsigned int offset, 89 unsigned int length, const u8 *msg); 90 }; 91 92 /* 93 * A generic instance of the read function of struct lpc_driver_ops, used for 94 * the LPC EC. 95 */ 96 static int cros_ec_lpc_read_bytes(struct cros_ec_lpc *_, unsigned int offset, unsigned int length, 97 u8 *dest) 98 { 99 u8 sum = 0; 100 int i; 101 102 for (i = 0; i < length; ++i) { 103 dest[i] = inb(offset + i); 104 sum += dest[i]; 105 } 106 107 /* Return checksum of all bytes read */ 108 return sum; 109 } 110 111 /* 112 * A generic instance of the write function of struct lpc_driver_ops, used for 113 * the LPC EC. 114 */ 115 static int cros_ec_lpc_write_bytes(struct cros_ec_lpc *_, unsigned int offset, unsigned int length, 116 const u8 *msg) 117 { 118 u8 sum = 0; 119 int i; 120 121 for (i = 0; i < length; ++i) { 122 outb(msg[i], offset + i); 123 sum += msg[i]; 124 } 125 126 /* Return checksum of all bytes written */ 127 return sum; 128 } 129 130 /* 131 * An instance of the read function of struct lpc_driver_ops, used for the 132 * MEC variant of LPC EC. 133 */ 134 static int cros_ec_lpc_mec_read_bytes(struct cros_ec_lpc *ec_lpc, unsigned int offset, 135 unsigned int length, u8 *dest) 136 { 137 int in_range = cros_ec_lpc_mec_in_range(offset, length); 138 139 if (in_range < 0) 140 return in_range; 141 142 return in_range ? 143 cros_ec_lpc_io_bytes_mec(MEC_IO_READ, 144 offset - EC_HOST_CMD_REGION0, 145 length, dest) : 146 cros_ec_lpc_read_bytes(ec_lpc, offset, length, dest); 147 } 148 149 /* 150 * An instance of the write function of struct lpc_driver_ops, used for the 151 * MEC variant of LPC EC. 152 */ 153 static int cros_ec_lpc_mec_write_bytes(struct cros_ec_lpc *ec_lpc, unsigned int offset, 154 unsigned int length, const u8 *msg) 155 { 156 int in_range = cros_ec_lpc_mec_in_range(offset, length); 157 158 if (in_range < 0) 159 return in_range; 160 161 return in_range ? 162 cros_ec_lpc_io_bytes_mec(MEC_IO_WRITE, 163 offset - EC_HOST_CMD_REGION0, 164 length, (u8 *)msg) : 165 cros_ec_lpc_write_bytes(ec_lpc, offset, length, msg); 166 } 167 168 static int cros_ec_lpc_direct_read(struct cros_ec_lpc *ec_lpc, unsigned int offset, 169 unsigned int length, u8 *dest) 170 { 171 int sum = 0; 172 int i; 173 174 if (offset < EC_HOST_CMD_REGION0 || offset > EC_LPC_ADDR_MEMMAP + 175 EC_MEMMAP_SIZE) { 176 return cros_ec_lpc_read_bytes(ec_lpc, offset, length, dest); 177 } 178 179 for (i = 0; i < length; ++i) { 180 dest[i] = readb(ec_lpc->base + offset - EC_HOST_CMD_REGION0 + i); 181 sum += dest[i]; 182 } 183 184 /* Return checksum of all bytes read */ 185 return sum; 186 } 187 188 static int cros_ec_lpc_direct_write(struct cros_ec_lpc *ec_lpc, unsigned int offset, 189 unsigned int length, const u8 *msg) 190 { 191 int sum = 0; 192 int i; 193 194 if (offset < EC_HOST_CMD_REGION0 || offset > EC_LPC_ADDR_MEMMAP + 195 EC_MEMMAP_SIZE) { 196 return cros_ec_lpc_write_bytes(ec_lpc, offset, length, msg); 197 } 198 199 for (i = 0; i < length; ++i) { 200 writeb(msg[i], ec_lpc->base + offset - EC_HOST_CMD_REGION0 + i); 201 sum += msg[i]; 202 } 203 204 /* Return checksum of all bytes written */ 205 return sum; 206 } 207 208 static int ec_response_timed_out(struct cros_ec_lpc *ec_lpc) 209 { 210 unsigned long one_second = jiffies + HZ; 211 u8 data; 212 int ret; 213 214 usleep_range(200, 300); 215 do { 216 ret = ec_lpc->read(ec_lpc, EC_LPC_ADDR_HOST_CMD, 1, &data); 217 if (ret < 0) 218 return ret; 219 if (!(data & EC_LPC_STATUS_BUSY_MASK)) 220 return 0; 221 usleep_range(100, 200); 222 } while (time_before(jiffies, one_second)); 223 224 return 1; 225 } 226 227 static int cros_ec_pkt_xfer_lpc(struct cros_ec_device *ec, 228 struct cros_ec_command *msg) 229 { 230 struct cros_ec_lpc *ec_lpc = ec->priv; 231 struct ec_host_response response; 232 u8 sum; 233 int ret = 0; 234 u8 *dout; 235 236 ret = cros_ec_prepare_tx(ec, msg); 237 if (ret < 0) 238 goto done; 239 240 /* Write buffer */ 241 ret = ec_lpc->write(ec_lpc, EC_LPC_ADDR_HOST_PACKET, ret, ec->dout); 242 if (ret < 0) 243 goto done; 244 245 /* Here we go */ 246 sum = EC_COMMAND_PROTOCOL_3; 247 ret = ec_lpc->write(ec_lpc, EC_LPC_ADDR_HOST_CMD, 1, &sum); 248 if (ret < 0) 249 goto done; 250 251 ret = ec_response_timed_out(ec_lpc); 252 if (ret < 0) 253 goto done; 254 if (ret) { 255 dev_warn(ec->dev, "EC response timed out\n"); 256 ret = -EIO; 257 goto done; 258 } 259 260 /* Check result */ 261 ret = ec_lpc->read(ec_lpc, EC_LPC_ADDR_HOST_DATA, 1, &sum); 262 if (ret < 0) 263 goto done; 264 msg->result = ret; 265 ret = cros_ec_check_result(ec, msg); 266 if (ret) 267 goto done; 268 269 /* Read back response */ 270 dout = (u8 *)&response; 271 ret = ec_lpc->read(ec_lpc, EC_LPC_ADDR_HOST_PACKET, sizeof(response), 272 dout); 273 if (ret < 0) 274 goto done; 275 sum = ret; 276 277 msg->result = response.result; 278 279 if (response.data_len > msg->insize) { 280 dev_err(ec->dev, 281 "packet too long (%d bytes, expected %d)", 282 response.data_len, msg->insize); 283 ret = -EMSGSIZE; 284 goto done; 285 } 286 287 /* Read response and process checksum */ 288 ret = ec_lpc->read(ec_lpc, EC_LPC_ADDR_HOST_PACKET + 289 sizeof(response), response.data_len, 290 msg->data); 291 if (ret < 0) 292 goto done; 293 sum += ret; 294 295 if (sum) { 296 dev_err(ec->dev, 297 "bad packet checksum %02x\n", 298 response.checksum); 299 ret = -EBADMSG; 300 goto done; 301 } 302 303 /* Return actual amount of data received */ 304 ret = response.data_len; 305 done: 306 return ret; 307 } 308 309 static int cros_ec_cmd_xfer_lpc(struct cros_ec_device *ec, 310 struct cros_ec_command *msg) 311 { 312 struct cros_ec_lpc *ec_lpc = ec->priv; 313 struct ec_lpc_host_args args; 314 u8 sum; 315 int ret = 0; 316 317 if (msg->outsize > EC_PROTO2_MAX_PARAM_SIZE || 318 msg->insize > EC_PROTO2_MAX_PARAM_SIZE) { 319 dev_err(ec->dev, 320 "invalid buffer sizes (out %d, in %d)\n", 321 msg->outsize, msg->insize); 322 return -EINVAL; 323 } 324 325 /* Now actually send the command to the EC and get the result */ 326 args.flags = EC_HOST_ARGS_FLAG_FROM_HOST; 327 args.command_version = msg->version; 328 args.data_size = msg->outsize; 329 330 /* Initialize checksum */ 331 sum = msg->command + args.flags + args.command_version + args.data_size; 332 333 /* Copy data and update checksum */ 334 ret = ec_lpc->write(ec_lpc, EC_LPC_ADDR_HOST_PARAM, msg->outsize, 335 msg->data); 336 if (ret < 0) 337 goto done; 338 sum += ret; 339 340 /* Finalize checksum and write args */ 341 args.checksum = sum; 342 ret = ec_lpc->write(ec_lpc, EC_LPC_ADDR_HOST_ARGS, sizeof(args), 343 (u8 *)&args); 344 if (ret < 0) 345 goto done; 346 347 /* Here we go */ 348 sum = msg->command; 349 ret = ec_lpc->write(ec_lpc, EC_LPC_ADDR_HOST_CMD, 1, &sum); 350 if (ret < 0) 351 goto done; 352 353 ret = ec_response_timed_out(ec_lpc); 354 if (ret < 0) 355 goto done; 356 if (ret) { 357 dev_warn(ec->dev, "EC response timed out\n"); 358 ret = -EIO; 359 goto done; 360 } 361 362 /* Check result */ 363 ret = ec_lpc->read(ec_lpc, EC_LPC_ADDR_HOST_DATA, 1, &sum); 364 if (ret < 0) 365 goto done; 366 msg->result = ret; 367 ret = cros_ec_check_result(ec, msg); 368 if (ret) 369 goto done; 370 371 /* Read back args */ 372 ret = ec_lpc->read(ec_lpc, EC_LPC_ADDR_HOST_ARGS, sizeof(args), (u8 *)&args); 373 if (ret < 0) 374 goto done; 375 376 if (args.data_size > msg->insize) { 377 dev_err(ec->dev, 378 "packet too long (%d bytes, expected %d)", 379 args.data_size, msg->insize); 380 ret = -ENOSPC; 381 goto done; 382 } 383 384 /* Start calculating response checksum */ 385 sum = msg->command + args.flags + args.command_version + args.data_size; 386 387 /* Read response and update checksum */ 388 ret = ec_lpc->read(ec_lpc, EC_LPC_ADDR_HOST_PARAM, args.data_size, 389 msg->data); 390 if (ret < 0) 391 goto done; 392 sum += ret; 393 394 /* Verify checksum */ 395 if (args.checksum != sum) { 396 dev_err(ec->dev, 397 "bad packet checksum, expected %02x, got %02x\n", 398 args.checksum, sum); 399 ret = -EBADMSG; 400 goto done; 401 } 402 403 /* Return actual amount of data received */ 404 ret = args.data_size; 405 done: 406 return ret; 407 } 408 409 /* Returns num bytes read, or negative on error. Doesn't need locking. */ 410 static int cros_ec_lpc_readmem(struct cros_ec_device *ec, unsigned int offset, 411 unsigned int bytes, void *dest) 412 { 413 struct cros_ec_lpc *ec_lpc = ec->priv; 414 int i = offset; 415 char *s = dest; 416 int cnt = 0; 417 int ret; 418 419 if (offset >= EC_MEMMAP_SIZE - bytes) 420 return -EINVAL; 421 422 /* fixed length */ 423 if (bytes) { 424 ret = ec_lpc->read(ec_lpc, ec_lpc->mmio_memory_base + offset, bytes, s); 425 if (ret < 0) 426 return ret; 427 return bytes; 428 } 429 430 /* string */ 431 for (; i < EC_MEMMAP_SIZE; i++, s++) { 432 ret = ec_lpc->read(ec_lpc, ec_lpc->mmio_memory_base + i, 1, s); 433 if (ret < 0) 434 return ret; 435 cnt++; 436 if (!*s) 437 break; 438 } 439 440 return cnt; 441 } 442 443 static void cros_ec_lpc_acpi_notify(acpi_handle device, u32 value, void *data) 444 { 445 static const char *env[] = { "ERROR=PANIC", NULL }; 446 struct cros_ec_device *ec_dev = data; 447 bool ec_has_more_events; 448 int ret; 449 450 ec_dev->last_event_time = cros_ec_get_time_ns(); 451 452 if (value == ACPI_NOTIFY_CROS_EC_PANIC) { 453 dev_emerg(ec_dev->dev, "CrOS EC Panic Reported. Shutdown is imminent!"); 454 blocking_notifier_call_chain(&ec_dev->panic_notifier, 0, ec_dev); 455 kobject_uevent_env(&ec_dev->dev->kobj, KOBJ_CHANGE, (char **)env); 456 /* Begin orderly shutdown. EC will force reset after a short period. */ 457 hw_protection_shutdown("CrOS EC Panic", -1); 458 /* Do not query for other events after a panic is reported */ 459 return; 460 } 461 462 if (value == ACPI_NOTIFY_CROS_EC_MKBP && ec_dev->mkbp_event_supported) 463 do { 464 ret = cros_ec_get_next_event(ec_dev, NULL, 465 &ec_has_more_events); 466 if (ret > 0) 467 blocking_notifier_call_chain( 468 &ec_dev->event_notifier, 0, 469 ec_dev); 470 } while (ec_has_more_events); 471 472 if (value == ACPI_NOTIFY_DEVICE_WAKE) 473 pm_system_wakeup(); 474 } 475 476 static acpi_status cros_ec_lpc_parse_device(acpi_handle handle, u32 level, 477 void *context, void **retval) 478 { 479 *(struct acpi_device **)context = acpi_fetch_acpi_dev(handle); 480 return AE_CTRL_TERMINATE; 481 } 482 483 static struct acpi_device *cros_ec_lpc_get_device(const char *id) 484 { 485 struct acpi_device *adev = NULL; 486 acpi_status status = acpi_get_devices(id, cros_ec_lpc_parse_device, 487 &adev, NULL); 488 if (ACPI_FAILURE(status)) { 489 pr_warn(DRV_NAME ": Looking for %s failed\n", id); 490 return NULL; 491 } 492 493 return adev; 494 } 495 496 static acpi_status cros_ec_lpc_resources(struct acpi_resource *res, void *data) 497 { 498 struct cros_ec_lpc *ec_lpc = data; 499 500 switch (res->type) { 501 case ACPI_RESOURCE_TYPE_FIXED_MEMORY32: 502 ec_lpc->mem32 = res->data.fixed_memory32; 503 break; 504 default: 505 break; 506 } 507 return AE_OK; 508 } 509 510 static int cros_ec_lpc_probe(struct platform_device *pdev) 511 { 512 struct device *dev = &pdev->dev; 513 struct acpi_device *adev; 514 acpi_status status; 515 struct cros_ec_device *ec_dev; 516 struct cros_ec_lpc *ec_lpc; 517 struct lpc_driver_data *driver_data; 518 u8 buf[2] = {}; 519 int irq, ret; 520 u32 quirks; 521 522 ec_lpc = devm_kzalloc(dev, sizeof(*ec_lpc), GFP_KERNEL); 523 if (!ec_lpc) 524 return -ENOMEM; 525 526 ec_lpc->mmio_memory_base = EC_LPC_ADDR_MEMMAP; 527 528 driver_data = platform_get_drvdata(pdev); 529 if (driver_data) { 530 quirks = driver_data->quirks; 531 532 if (quirks) 533 dev_info(dev, "loaded with quirks %8.08x\n", quirks); 534 535 if (quirks & CROS_EC_LPC_QUIRK_REMAP_MEMORY) 536 ec_lpc->mmio_memory_base = driver_data->quirk_mmio_memory_base; 537 538 if (quirks & CROS_EC_LPC_QUIRK_ACPI_ID) { 539 adev = cros_ec_lpc_get_device(driver_data->quirk_acpi_id); 540 if (!adev) { 541 dev_err(dev, "failed to get ACPI device '%s'", 542 driver_data->quirk_acpi_id); 543 return -ENODEV; 544 } 545 ACPI_COMPANION_SET(dev, adev); 546 } 547 548 if (quirks & CROS_EC_LPC_QUIRK_AML_MUTEX) { 549 const char *name = driver_data->quirk_aml_mutex_name; 550 ret = cros_ec_lpc_mec_acpi_mutex(ACPI_COMPANION(dev), name); 551 if (ret) { 552 dev_err(dev, "failed to get AML mutex '%s'", name); 553 return ret; 554 } 555 dev_info(dev, "got AML mutex '%s'", name); 556 } 557 } 558 adev = ACPI_COMPANION(dev); 559 if (adev) { 560 /* 561 * Retrieve the resource information in the CRS register, if available. 562 */ 563 status = acpi_walk_resources(adev->handle, METHOD_NAME__CRS, 564 cros_ec_lpc_resources, ec_lpc); 565 if (ACPI_SUCCESS(status) && ec_lpc->mem32.address_length) { 566 ec_lpc->base = devm_ioremap(dev, 567 ec_lpc->mem32.address, 568 ec_lpc->mem32.address_length); 569 if (!ec_lpc->base) 570 return -EINVAL; 571 572 ec_lpc->read = cros_ec_lpc_direct_read; 573 ec_lpc->write = cros_ec_lpc_direct_write; 574 } 575 } 576 if (!ec_lpc->read) { 577 /* 578 * The Framework Laptop (and possibly other non-ChromeOS devices) 579 * only exposes the eight I/O ports that are required for the Microchip EC. 580 * Requesting a larger reservation will fail. 581 */ 582 if (!devm_request_region(dev, EC_HOST_CMD_REGION0, 583 EC_HOST_CMD_MEC_REGION_SIZE, dev_name(dev))) { 584 dev_err(dev, "couldn't reserve MEC region\n"); 585 return -EBUSY; 586 } 587 588 cros_ec_lpc_mec_init(EC_HOST_CMD_REGION0, 589 EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE); 590 591 /* 592 * Read the mapped ID twice, the first one is assuming the 593 * EC is a Microchip Embedded Controller (MEC) variant, if the 594 * protocol fails, fallback to the non MEC variant and try to 595 * read again the ID. 596 */ 597 ec_lpc->read = cros_ec_lpc_mec_read_bytes; 598 ec_lpc->write = cros_ec_lpc_mec_write_bytes; 599 } 600 ret = ec_lpc->read(ec_lpc, EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID, 2, buf); 601 if (ret < 0) 602 return ret; 603 if (buf[0] != 'E' || buf[1] != 'C') { 604 if (!devm_request_region(dev, ec_lpc->mmio_memory_base, EC_MEMMAP_SIZE, 605 dev_name(dev))) { 606 dev_err(dev, "couldn't reserve memmap region\n"); 607 return -EBUSY; 608 } 609 610 /* Re-assign read/write operations for the non MEC variant */ 611 ec_lpc->read = cros_ec_lpc_read_bytes; 612 ec_lpc->write = cros_ec_lpc_write_bytes; 613 ret = ec_lpc->read(ec_lpc, ec_lpc->mmio_memory_base + EC_MEMMAP_ID, 2, 614 buf); 615 if (ret < 0) 616 return ret; 617 if (buf[0] != 'E' || buf[1] != 'C') { 618 dev_err(dev, "EC ID not detected\n"); 619 return -ENODEV; 620 } 621 622 /* Reserve the remaining I/O ports required by the non-MEC protocol. */ 623 if (!devm_request_region(dev, EC_HOST_CMD_REGION0 + EC_HOST_CMD_MEC_REGION_SIZE, 624 EC_HOST_CMD_REGION_SIZE - EC_HOST_CMD_MEC_REGION_SIZE, 625 dev_name(dev))) { 626 dev_err(dev, "couldn't reserve remainder of region0\n"); 627 return -EBUSY; 628 } 629 if (!devm_request_region(dev, EC_HOST_CMD_REGION1, 630 EC_HOST_CMD_REGION_SIZE, dev_name(dev))) { 631 dev_err(dev, "couldn't reserve region1\n"); 632 return -EBUSY; 633 } 634 } 635 636 ec_dev = devm_kzalloc(dev, sizeof(*ec_dev), GFP_KERNEL); 637 if (!ec_dev) 638 return -ENOMEM; 639 640 platform_set_drvdata(pdev, ec_dev); 641 ec_dev->dev = dev; 642 ec_dev->phys_name = dev_name(dev); 643 ec_dev->cmd_xfer = cros_ec_cmd_xfer_lpc; 644 ec_dev->pkt_xfer = cros_ec_pkt_xfer_lpc; 645 ec_dev->cmd_readmem = cros_ec_lpc_readmem; 646 ec_dev->din_size = sizeof(struct ec_host_response) + 647 sizeof(struct ec_response_get_protocol_info); 648 ec_dev->dout_size = sizeof(struct ec_host_request) + sizeof(struct ec_params_rwsig_action); 649 ec_dev->priv = ec_lpc; 650 651 /* 652 * Some boards do not have an IRQ allotted for cros_ec_lpc, 653 * which makes ENXIO an expected (and safe) scenario. 654 */ 655 irq = platform_get_irq_optional(pdev, 0); 656 if (irq > 0) 657 ec_dev->irq = irq; 658 else if (irq != -ENXIO) { 659 dev_err(dev, "couldn't retrieve IRQ number (%d)\n", irq); 660 return irq; 661 } 662 663 ret = cros_ec_register(ec_dev); 664 if (ret) { 665 dev_err(dev, "couldn't register ec_dev (%d)\n", ret); 666 return ret; 667 } 668 669 /* 670 * Connect a notify handler to process MKBP messages if we have a 671 * companion ACPI device. 672 */ 673 if (adev) { 674 status = acpi_install_notify_handler(adev->handle, 675 ACPI_ALL_NOTIFY, 676 cros_ec_lpc_acpi_notify, 677 ec_dev); 678 if (ACPI_FAILURE(status)) 679 dev_warn(dev, "Failed to register notifier %08x\n", 680 status); 681 } 682 683 return 0; 684 } 685 686 static void cros_ec_lpc_remove(struct platform_device *pdev) 687 { 688 struct cros_ec_device *ec_dev = platform_get_drvdata(pdev); 689 struct acpi_device *adev; 690 691 adev = ACPI_COMPANION(&pdev->dev); 692 if (adev) 693 acpi_remove_notify_handler(adev->handle, ACPI_ALL_NOTIFY, 694 cros_ec_lpc_acpi_notify); 695 696 cros_ec_unregister(ec_dev); 697 } 698 699 static const struct acpi_device_id cros_ec_lpc_acpi_device_ids[] = { 700 { ACPI_DRV_NAME, 0 }, 701 { } 702 }; 703 MODULE_DEVICE_TABLE(acpi, cros_ec_lpc_acpi_device_ids); 704 705 static const struct lpc_driver_data framework_laptop_npcx_lpc_driver_data __initconst = { 706 .quirks = CROS_EC_LPC_QUIRK_REMAP_MEMORY, 707 .quirk_mmio_memory_base = 0xE00, 708 }; 709 710 static const struct lpc_driver_data framework_laptop_mec_lpc_driver_data __initconst = { 711 .quirks = CROS_EC_LPC_QUIRK_ACPI_ID|CROS_EC_LPC_QUIRK_AML_MUTEX, 712 .quirk_acpi_id = "PNP0C09", 713 .quirk_aml_mutex_name = "ECMT", 714 }; 715 716 static const struct dmi_system_id cros_ec_lpc_dmi_table[] __initconst = { 717 { 718 /* 719 * Today all Chromebooks/boxes ship with Google_* as version and 720 * coreboot as bios vendor. No other systems with this 721 * combination are known to date. 722 */ 723 .matches = { 724 DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), 725 DMI_MATCH(DMI_BIOS_VERSION, "Google_"), 726 }, 727 }, 728 { 729 /* 730 * If the box is running custom coreboot firmware then the 731 * DMI BIOS version string will not be matched by "Google_", 732 * but the system vendor string will still be matched by 733 * "GOOGLE". 734 */ 735 .matches = { 736 DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), 737 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 738 }, 739 }, 740 { 741 /* x86-link, the Chromebook Pixel. */ 742 .matches = { 743 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 744 DMI_MATCH(DMI_PRODUCT_NAME, "Link"), 745 }, 746 }, 747 { 748 /* x86-samus, the Chromebook Pixel 2. */ 749 .matches = { 750 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 751 DMI_MATCH(DMI_PRODUCT_NAME, "Samus"), 752 }, 753 }, 754 { 755 /* x86-peppy, the Acer C720 Chromebook. */ 756 .matches = { 757 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 758 DMI_MATCH(DMI_PRODUCT_NAME, "Peppy"), 759 }, 760 }, 761 { 762 /* x86-glimmer, the Lenovo Thinkpad Yoga 11e. */ 763 .matches = { 764 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 765 DMI_MATCH(DMI_PRODUCT_NAME, "Glimmer"), 766 }, 767 }, 768 /* A small number of non-Chromebook/box machines also use the ChromeOS EC */ 769 { 770 /* Framework Laptop (11th Gen Intel Core) */ 771 .matches = { 772 DMI_MATCH(DMI_SYS_VENDOR, "Framework"), 773 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Laptop"), 774 }, 775 .driver_data = (void *)&framework_laptop_mec_lpc_driver_data, 776 }, 777 { 778 /* Framework Laptop (12th Gen Intel Core) */ 779 .matches = { 780 DMI_MATCH(DMI_SYS_VENDOR, "Framework"), 781 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Laptop (12th Gen Intel Core)"), 782 }, 783 .driver_data = (void *)&framework_laptop_mec_lpc_driver_data, 784 }, 785 { 786 /* Framework Laptop (13th Gen Intel Core) */ 787 .matches = { 788 DMI_MATCH(DMI_SYS_VENDOR, "Framework"), 789 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Laptop (13th Gen Intel Core)"), 790 }, 791 .driver_data = (void *)&framework_laptop_mec_lpc_driver_data, 792 }, 793 { 794 /* 795 * All remaining Framework Laptop models (13 AMD Ryzen, 16 AMD 796 * Ryzen, Intel Core Ultra) 797 */ 798 .matches = { 799 DMI_MATCH(DMI_SYS_VENDOR, "Framework"), 800 DMI_MATCH(DMI_PRODUCT_FAMILY, "Laptop"), 801 }, 802 .driver_data = (void *)&framework_laptop_npcx_lpc_driver_data, 803 }, 804 { /* sentinel */ } 805 }; 806 MODULE_DEVICE_TABLE(dmi, cros_ec_lpc_dmi_table); 807 808 #ifdef CONFIG_PM_SLEEP 809 static int cros_ec_lpc_prepare(struct device *dev) 810 { 811 struct cros_ec_device *ec_dev = dev_get_drvdata(dev); 812 return cros_ec_suspend_prepare(ec_dev); 813 } 814 815 static void cros_ec_lpc_complete(struct device *dev) 816 { 817 struct cros_ec_device *ec_dev = dev_get_drvdata(dev); 818 cros_ec_resume_complete(ec_dev); 819 } 820 821 static int cros_ec_lpc_suspend_late(struct device *dev) 822 { 823 struct cros_ec_device *ec_dev = dev_get_drvdata(dev); 824 825 return cros_ec_suspend_late(ec_dev); 826 } 827 828 static int cros_ec_lpc_resume_early(struct device *dev) 829 { 830 struct cros_ec_device *ec_dev = dev_get_drvdata(dev); 831 832 return cros_ec_resume_early(ec_dev); 833 } 834 #endif 835 836 static const struct dev_pm_ops cros_ec_lpc_pm_ops = { 837 #ifdef CONFIG_PM_SLEEP 838 .prepare = cros_ec_lpc_prepare, 839 .complete = cros_ec_lpc_complete, 840 #endif 841 SET_LATE_SYSTEM_SLEEP_PM_OPS(cros_ec_lpc_suspend_late, cros_ec_lpc_resume_early) 842 }; 843 844 static struct platform_driver cros_ec_lpc_driver = { 845 .driver = { 846 .name = DRV_NAME, 847 .acpi_match_table = cros_ec_lpc_acpi_device_ids, 848 .pm = &cros_ec_lpc_pm_ops, 849 /* 850 * ACPI child devices may probe before us, and they racily 851 * check our drvdata pointer. Force synchronous probe until 852 * those races are resolved. 853 */ 854 .probe_type = PROBE_FORCE_SYNCHRONOUS, 855 }, 856 .probe = cros_ec_lpc_probe, 857 .remove = cros_ec_lpc_remove, 858 }; 859 860 static struct platform_device cros_ec_lpc_device = { 861 .name = DRV_NAME 862 }; 863 864 static int __init cros_ec_lpc_init(void) 865 { 866 int ret; 867 const struct dmi_system_id *dmi_match; 868 869 cros_ec_lpc_acpi_device_found = !!cros_ec_lpc_get_device(ACPI_DRV_NAME); 870 871 dmi_match = dmi_first_match(cros_ec_lpc_dmi_table); 872 873 if (!cros_ec_lpc_acpi_device_found && !dmi_match) { 874 pr_err(DRV_NAME ": unsupported system.\n"); 875 return -ENODEV; 876 } 877 878 /* Register the driver */ 879 ret = platform_driver_register(&cros_ec_lpc_driver); 880 if (ret) { 881 pr_err(DRV_NAME ": can't register driver: %d\n", ret); 882 return ret; 883 } 884 885 if (!cros_ec_lpc_acpi_device_found) { 886 /* Pass the DMI match's driver data down to the platform device */ 887 platform_set_drvdata(&cros_ec_lpc_device, dmi_match->driver_data); 888 889 /* Register the device, and it'll get hooked up automatically */ 890 ret = platform_device_register(&cros_ec_lpc_device); 891 if (ret) { 892 pr_err(DRV_NAME ": can't register device: %d\n", ret); 893 platform_driver_unregister(&cros_ec_lpc_driver); 894 } 895 } 896 897 return ret; 898 } 899 900 static void __exit cros_ec_lpc_exit(void) 901 { 902 if (!cros_ec_lpc_acpi_device_found) 903 platform_device_unregister(&cros_ec_lpc_device); 904 platform_driver_unregister(&cros_ec_lpc_driver); 905 } 906 907 module_init(cros_ec_lpc_init); 908 module_exit(cros_ec_lpc_exit); 909 910 MODULE_LICENSE("GPL"); 911 MODULE_DESCRIPTION("ChromeOS EC LPC driver"); 912