1 // SPDX-License-Identifier: GPL-2.0 2 // LPC interface for ChromeOS Embedded Controller 3 // 4 // Copyright (C) 2012-2015 Google, Inc 5 // 6 // This driver uses the ChromeOS EC byte-level message-based protocol for 7 // communicating the keyboard state (which keys are pressed) from a keyboard EC 8 // to the AP over some bus (such as i2c, lpc, spi). The EC does debouncing, 9 // but everything else (including deghosting) is done here. The main 10 // motivation for this is to keep the EC firmware as simple as possible, since 11 // it cannot be easily upgraded and EC flash/IRAM space is relatively 12 // expensive. 13 14 #include <linux/acpi.h> 15 #include <linux/dmi.h> 16 #include <linux/delay.h> 17 #include <linux/io.h> 18 #include <linux/interrupt.h> 19 #include <linux/kobject.h> 20 #include <linux/module.h> 21 #include <linux/platform_data/cros_ec_commands.h> 22 #include <linux/platform_data/cros_ec_proto.h> 23 #include <linux/platform_device.h> 24 #include <linux/printk.h> 25 #include <linux/reboot.h> 26 #include <linux/suspend.h> 27 28 #include "cros_ec.h" 29 #include "cros_ec_lpc_mec.h" 30 31 #define DRV_NAME "cros_ec_lpcs" 32 #define ACPI_DRV_NAME "GOOG0004" 33 34 /* True if ACPI device is present */ 35 static bool cros_ec_lpc_acpi_device_found; 36 37 /* 38 * Indicates that lpc_driver_data.quirk_mmio_memory_base should 39 * be used as the base port for EC mapped memory. 40 */ 41 #define CROS_EC_LPC_QUIRK_REMAP_MEMORY BIT(0) 42 /* 43 * Indicates that lpc_driver_data.quirk_acpi_id should be used to find 44 * the ACPI device. 45 */ 46 #define CROS_EC_LPC_QUIRK_ACPI_ID BIT(1) 47 /* 48 * Indicates that lpc_driver_data.quirk_aml_mutex_name should be used 49 * to find an AML mutex to protect access to Microchip EC. 50 */ 51 #define CROS_EC_LPC_QUIRK_AML_MUTEX BIT(2) 52 53 /** 54 * struct lpc_driver_data - driver data attached to a DMI device ID to indicate 55 * hardware quirks. 56 * @quirks: a bitfield composed of quirks from CROS_EC_LPC_QUIRK_* 57 * @quirk_mmio_memory_base: The first I/O port addressing EC mapped memory (used 58 * when quirk ...REMAP_MEMORY is set.) 59 * @quirk_acpi_id: An ACPI HID to be used to find the ACPI device. 60 * @quirk_aml_mutex_name: The name of an AML mutex to be used to protect access 61 * to Microchip EC. 62 */ 63 struct lpc_driver_data { 64 u32 quirks; 65 u16 quirk_mmio_memory_base; 66 const char *quirk_acpi_id; 67 const char *quirk_aml_mutex_name; 68 }; 69 70 /** 71 * struct cros_ec_lpc - LPC device-specific data 72 * @mmio_memory_base: The first I/O port addressing EC mapped memory. 73 */ 74 struct cros_ec_lpc { 75 u16 mmio_memory_base; 76 }; 77 78 /** 79 * struct lpc_driver_ops - LPC driver operations 80 * @read: Copy length bytes from EC address offset into buffer dest. 81 * Returns a negative error code on error, or the 8-bit checksum 82 * of all bytes read. 83 * @write: Copy length bytes from buffer msg into EC address offset. 84 * Returns a negative error code on error, or the 8-bit checksum 85 * of all bytes written. 86 */ 87 struct lpc_driver_ops { 88 int (*read)(unsigned int offset, unsigned int length, u8 *dest); 89 int (*write)(unsigned int offset, unsigned int length, const u8 *msg); 90 }; 91 92 static struct lpc_driver_ops cros_ec_lpc_ops = { }; 93 94 /* 95 * A generic instance of the read function of struct lpc_driver_ops, used for 96 * the LPC EC. 97 */ 98 static int cros_ec_lpc_read_bytes(unsigned int offset, unsigned int length, 99 u8 *dest) 100 { 101 u8 sum = 0; 102 int i; 103 104 for (i = 0; i < length; ++i) { 105 dest[i] = inb(offset + i); 106 sum += dest[i]; 107 } 108 109 /* Return checksum of all bytes read */ 110 return sum; 111 } 112 113 /* 114 * A generic instance of the write function of struct lpc_driver_ops, used for 115 * the LPC EC. 116 */ 117 static int cros_ec_lpc_write_bytes(unsigned int offset, unsigned int length, 118 const u8 *msg) 119 { 120 u8 sum = 0; 121 int i; 122 123 for (i = 0; i < length; ++i) { 124 outb(msg[i], offset + i); 125 sum += msg[i]; 126 } 127 128 /* Return checksum of all bytes written */ 129 return sum; 130 } 131 132 /* 133 * An instance of the read function of struct lpc_driver_ops, used for the 134 * MEC variant of LPC EC. 135 */ 136 static int cros_ec_lpc_mec_read_bytes(unsigned int offset, unsigned int length, 137 u8 *dest) 138 { 139 int in_range = cros_ec_lpc_mec_in_range(offset, length); 140 141 if (in_range < 0) 142 return in_range; 143 144 return in_range ? 145 cros_ec_lpc_io_bytes_mec(MEC_IO_READ, 146 offset - EC_HOST_CMD_REGION0, 147 length, dest) : 148 cros_ec_lpc_read_bytes(offset, length, dest); 149 } 150 151 /* 152 * An instance of the write function of struct lpc_driver_ops, used for the 153 * MEC variant of LPC EC. 154 */ 155 static int cros_ec_lpc_mec_write_bytes(unsigned int offset, unsigned int length, 156 const u8 *msg) 157 { 158 int in_range = cros_ec_lpc_mec_in_range(offset, length); 159 160 if (in_range < 0) 161 return in_range; 162 163 return in_range ? 164 cros_ec_lpc_io_bytes_mec(MEC_IO_WRITE, 165 offset - EC_HOST_CMD_REGION0, 166 length, (u8 *)msg) : 167 cros_ec_lpc_write_bytes(offset, length, msg); 168 } 169 170 static int ec_response_timed_out(void) 171 { 172 unsigned long one_second = jiffies + HZ; 173 u8 data; 174 int ret; 175 176 usleep_range(200, 300); 177 do { 178 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_CMD, 1, &data); 179 if (ret < 0) 180 return ret; 181 if (!(data & EC_LPC_STATUS_BUSY_MASK)) 182 return 0; 183 usleep_range(100, 200); 184 } while (time_before(jiffies, one_second)); 185 186 return 1; 187 } 188 189 static int cros_ec_pkt_xfer_lpc(struct cros_ec_device *ec, 190 struct cros_ec_command *msg) 191 { 192 struct ec_host_response response; 193 u8 sum; 194 int ret = 0; 195 u8 *dout; 196 197 ret = cros_ec_prepare_tx(ec, msg); 198 if (ret < 0) 199 goto done; 200 201 /* Write buffer */ 202 ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_PACKET, ret, ec->dout); 203 if (ret < 0) 204 goto done; 205 206 /* Here we go */ 207 sum = EC_COMMAND_PROTOCOL_3; 208 ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_CMD, 1, &sum); 209 if (ret < 0) 210 goto done; 211 212 ret = ec_response_timed_out(); 213 if (ret < 0) 214 goto done; 215 if (ret) { 216 dev_warn(ec->dev, "EC response timed out\n"); 217 ret = -EIO; 218 goto done; 219 } 220 221 /* Check result */ 222 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_DATA, 1, &sum); 223 if (ret < 0) 224 goto done; 225 msg->result = ret; 226 ret = cros_ec_check_result(ec, msg); 227 if (ret) 228 goto done; 229 230 /* Read back response */ 231 dout = (u8 *)&response; 232 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PACKET, sizeof(response), 233 dout); 234 if (ret < 0) 235 goto done; 236 sum = ret; 237 238 msg->result = response.result; 239 240 if (response.data_len > msg->insize) { 241 dev_err(ec->dev, 242 "packet too long (%d bytes, expected %d)", 243 response.data_len, msg->insize); 244 ret = -EMSGSIZE; 245 goto done; 246 } 247 248 /* Read response and process checksum */ 249 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PACKET + 250 sizeof(response), response.data_len, 251 msg->data); 252 if (ret < 0) 253 goto done; 254 sum += ret; 255 256 if (sum) { 257 dev_err(ec->dev, 258 "bad packet checksum %02x\n", 259 response.checksum); 260 ret = -EBADMSG; 261 goto done; 262 } 263 264 /* Return actual amount of data received */ 265 ret = response.data_len; 266 done: 267 return ret; 268 } 269 270 static int cros_ec_cmd_xfer_lpc(struct cros_ec_device *ec, 271 struct cros_ec_command *msg) 272 { 273 struct ec_lpc_host_args args; 274 u8 sum; 275 int ret = 0; 276 277 if (msg->outsize > EC_PROTO2_MAX_PARAM_SIZE || 278 msg->insize > EC_PROTO2_MAX_PARAM_SIZE) { 279 dev_err(ec->dev, 280 "invalid buffer sizes (out %d, in %d)\n", 281 msg->outsize, msg->insize); 282 return -EINVAL; 283 } 284 285 /* Now actually send the command to the EC and get the result */ 286 args.flags = EC_HOST_ARGS_FLAG_FROM_HOST; 287 args.command_version = msg->version; 288 args.data_size = msg->outsize; 289 290 /* Initialize checksum */ 291 sum = msg->command + args.flags + args.command_version + args.data_size; 292 293 /* Copy data and update checksum */ 294 ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_PARAM, msg->outsize, 295 msg->data); 296 if (ret < 0) 297 goto done; 298 sum += ret; 299 300 /* Finalize checksum and write args */ 301 args.checksum = sum; 302 ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_ARGS, sizeof(args), 303 (u8 *)&args); 304 if (ret < 0) 305 goto done; 306 307 /* Here we go */ 308 sum = msg->command; 309 ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_CMD, 1, &sum); 310 if (ret < 0) 311 goto done; 312 313 ret = ec_response_timed_out(); 314 if (ret < 0) 315 goto done; 316 if (ret) { 317 dev_warn(ec->dev, "EC response timed out\n"); 318 ret = -EIO; 319 goto done; 320 } 321 322 /* Check result */ 323 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_DATA, 1, &sum); 324 if (ret < 0) 325 goto done; 326 msg->result = ret; 327 ret = cros_ec_check_result(ec, msg); 328 if (ret) 329 goto done; 330 331 /* Read back args */ 332 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_ARGS, sizeof(args), (u8 *)&args); 333 if (ret < 0) 334 goto done; 335 336 if (args.data_size > msg->insize) { 337 dev_err(ec->dev, 338 "packet too long (%d bytes, expected %d)", 339 args.data_size, msg->insize); 340 ret = -ENOSPC; 341 goto done; 342 } 343 344 /* Start calculating response checksum */ 345 sum = msg->command + args.flags + args.command_version + args.data_size; 346 347 /* Read response and update checksum */ 348 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PARAM, args.data_size, 349 msg->data); 350 if (ret < 0) 351 goto done; 352 sum += ret; 353 354 /* Verify checksum */ 355 if (args.checksum != sum) { 356 dev_err(ec->dev, 357 "bad packet checksum, expected %02x, got %02x\n", 358 args.checksum, sum); 359 ret = -EBADMSG; 360 goto done; 361 } 362 363 /* Return actual amount of data received */ 364 ret = args.data_size; 365 done: 366 return ret; 367 } 368 369 /* Returns num bytes read, or negative on error. Doesn't need locking. */ 370 static int cros_ec_lpc_readmem(struct cros_ec_device *ec, unsigned int offset, 371 unsigned int bytes, void *dest) 372 { 373 struct cros_ec_lpc *ec_lpc = ec->priv; 374 int i = offset; 375 char *s = dest; 376 int cnt = 0; 377 int ret; 378 379 if (offset >= EC_MEMMAP_SIZE - bytes) 380 return -EINVAL; 381 382 /* fixed length */ 383 if (bytes) { 384 ret = cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + offset, bytes, s); 385 if (ret < 0) 386 return ret; 387 return bytes; 388 } 389 390 /* string */ 391 for (; i < EC_MEMMAP_SIZE; i++, s++) { 392 ret = cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + i, 1, s); 393 if (ret < 0) 394 return ret; 395 cnt++; 396 if (!*s) 397 break; 398 } 399 400 return cnt; 401 } 402 403 static void cros_ec_lpc_acpi_notify(acpi_handle device, u32 value, void *data) 404 { 405 static const char *env[] = { "ERROR=PANIC", NULL }; 406 struct cros_ec_device *ec_dev = data; 407 bool ec_has_more_events; 408 int ret; 409 410 ec_dev->last_event_time = cros_ec_get_time_ns(); 411 412 if (value == ACPI_NOTIFY_CROS_EC_PANIC) { 413 dev_emerg(ec_dev->dev, "CrOS EC Panic Reported. Shutdown is imminent!"); 414 blocking_notifier_call_chain(&ec_dev->panic_notifier, 0, ec_dev); 415 kobject_uevent_env(&ec_dev->dev->kobj, KOBJ_CHANGE, (char **)env); 416 /* Begin orderly shutdown. EC will force reset after a short period. */ 417 hw_protection_shutdown("CrOS EC Panic", -1); 418 /* Do not query for other events after a panic is reported */ 419 return; 420 } 421 422 if (ec_dev->mkbp_event_supported) 423 do { 424 ret = cros_ec_get_next_event(ec_dev, NULL, 425 &ec_has_more_events); 426 if (ret > 0) 427 blocking_notifier_call_chain( 428 &ec_dev->event_notifier, 0, 429 ec_dev); 430 } while (ec_has_more_events); 431 432 if (value == ACPI_NOTIFY_DEVICE_WAKE) 433 pm_system_wakeup(); 434 } 435 436 static acpi_status cros_ec_lpc_parse_device(acpi_handle handle, u32 level, 437 void *context, void **retval) 438 { 439 *(struct acpi_device **)context = acpi_fetch_acpi_dev(handle); 440 return AE_CTRL_TERMINATE; 441 } 442 443 static struct acpi_device *cros_ec_lpc_get_device(const char *id) 444 { 445 struct acpi_device *adev = NULL; 446 acpi_status status = acpi_get_devices(id, cros_ec_lpc_parse_device, 447 &adev, NULL); 448 if (ACPI_FAILURE(status)) { 449 pr_warn(DRV_NAME ": Looking for %s failed\n", id); 450 return NULL; 451 } 452 453 return adev; 454 } 455 456 static int cros_ec_lpc_probe(struct platform_device *pdev) 457 { 458 struct device *dev = &pdev->dev; 459 struct acpi_device *adev; 460 acpi_status status; 461 struct cros_ec_device *ec_dev; 462 struct cros_ec_lpc *ec_lpc; 463 struct lpc_driver_data *driver_data; 464 u8 buf[2] = {}; 465 int irq, ret; 466 u32 quirks; 467 468 ec_lpc = devm_kzalloc(dev, sizeof(*ec_lpc), GFP_KERNEL); 469 if (!ec_lpc) 470 return -ENOMEM; 471 472 ec_lpc->mmio_memory_base = EC_LPC_ADDR_MEMMAP; 473 474 driver_data = platform_get_drvdata(pdev); 475 if (driver_data) { 476 quirks = driver_data->quirks; 477 478 if (quirks) 479 dev_info(dev, "loaded with quirks %8.08x\n", quirks); 480 481 if (quirks & CROS_EC_LPC_QUIRK_REMAP_MEMORY) 482 ec_lpc->mmio_memory_base = driver_data->quirk_mmio_memory_base; 483 484 if (quirks & CROS_EC_LPC_QUIRK_ACPI_ID) { 485 adev = cros_ec_lpc_get_device(driver_data->quirk_acpi_id); 486 if (!adev) { 487 dev_err(dev, "failed to get ACPI device '%s'", 488 driver_data->quirk_acpi_id); 489 return -ENODEV; 490 } 491 ACPI_COMPANION_SET(dev, adev); 492 } 493 494 if (quirks & CROS_EC_LPC_QUIRK_AML_MUTEX) { 495 const char *name 496 = driver_data->quirk_aml_mutex_name; 497 ret = cros_ec_lpc_mec_acpi_mutex(ACPI_COMPANION(dev), name); 498 if (ret) { 499 dev_err(dev, "failed to get AML mutex '%s'", name); 500 return ret; 501 } 502 dev_info(dev, "got AML mutex '%s'", name); 503 } 504 } 505 506 /* 507 * The Framework Laptop (and possibly other non-ChromeOS devices) 508 * only exposes the eight I/O ports that are required for the Microchip EC. 509 * Requesting a larger reservation will fail. 510 */ 511 if (!devm_request_region(dev, EC_HOST_CMD_REGION0, 512 EC_HOST_CMD_MEC_REGION_SIZE, dev_name(dev))) { 513 dev_err(dev, "couldn't reserve MEC region\n"); 514 return -EBUSY; 515 } 516 517 cros_ec_lpc_mec_init(EC_HOST_CMD_REGION0, 518 EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE); 519 520 /* 521 * Read the mapped ID twice, the first one is assuming the 522 * EC is a Microchip Embedded Controller (MEC) variant, if the 523 * protocol fails, fallback to the non MEC variant and try to 524 * read again the ID. 525 */ 526 cros_ec_lpc_ops.read = cros_ec_lpc_mec_read_bytes; 527 cros_ec_lpc_ops.write = cros_ec_lpc_mec_write_bytes; 528 ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID, 2, buf); 529 if (ret < 0) 530 return ret; 531 if (buf[0] != 'E' || buf[1] != 'C') { 532 if (!devm_request_region(dev, ec_lpc->mmio_memory_base, EC_MEMMAP_SIZE, 533 dev_name(dev))) { 534 dev_err(dev, "couldn't reserve memmap region\n"); 535 return -EBUSY; 536 } 537 538 /* Re-assign read/write operations for the non MEC variant */ 539 cros_ec_lpc_ops.read = cros_ec_lpc_read_bytes; 540 cros_ec_lpc_ops.write = cros_ec_lpc_write_bytes; 541 ret = cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + EC_MEMMAP_ID, 2, 542 buf); 543 if (ret < 0) 544 return ret; 545 if (buf[0] != 'E' || buf[1] != 'C') { 546 dev_err(dev, "EC ID not detected\n"); 547 return -ENODEV; 548 } 549 550 /* Reserve the remaining I/O ports required by the non-MEC protocol. */ 551 if (!devm_request_region(dev, EC_HOST_CMD_REGION0 + EC_HOST_CMD_MEC_REGION_SIZE, 552 EC_HOST_CMD_REGION_SIZE - EC_HOST_CMD_MEC_REGION_SIZE, 553 dev_name(dev))) { 554 dev_err(dev, "couldn't reserve remainder of region0\n"); 555 return -EBUSY; 556 } 557 if (!devm_request_region(dev, EC_HOST_CMD_REGION1, 558 EC_HOST_CMD_REGION_SIZE, dev_name(dev))) { 559 dev_err(dev, "couldn't reserve region1\n"); 560 return -EBUSY; 561 } 562 } 563 564 ec_dev = devm_kzalloc(dev, sizeof(*ec_dev), GFP_KERNEL); 565 if (!ec_dev) 566 return -ENOMEM; 567 568 platform_set_drvdata(pdev, ec_dev); 569 ec_dev->dev = dev; 570 ec_dev->phys_name = dev_name(dev); 571 ec_dev->cmd_xfer = cros_ec_cmd_xfer_lpc; 572 ec_dev->pkt_xfer = cros_ec_pkt_xfer_lpc; 573 ec_dev->cmd_readmem = cros_ec_lpc_readmem; 574 ec_dev->din_size = sizeof(struct ec_host_response) + 575 sizeof(struct ec_response_get_protocol_info); 576 ec_dev->dout_size = sizeof(struct ec_host_request); 577 ec_dev->priv = ec_lpc; 578 579 /* 580 * Some boards do not have an IRQ allotted for cros_ec_lpc, 581 * which makes ENXIO an expected (and safe) scenario. 582 */ 583 irq = platform_get_irq_optional(pdev, 0); 584 if (irq > 0) 585 ec_dev->irq = irq; 586 else if (irq != -ENXIO) { 587 dev_err(dev, "couldn't retrieve IRQ number (%d)\n", irq); 588 return irq; 589 } 590 591 ret = cros_ec_register(ec_dev); 592 if (ret) { 593 dev_err(dev, "couldn't register ec_dev (%d)\n", ret); 594 return ret; 595 } 596 597 /* 598 * Connect a notify handler to process MKBP messages if we have a 599 * companion ACPI device. 600 */ 601 adev = ACPI_COMPANION(dev); 602 if (adev) { 603 status = acpi_install_notify_handler(adev->handle, 604 ACPI_ALL_NOTIFY, 605 cros_ec_lpc_acpi_notify, 606 ec_dev); 607 if (ACPI_FAILURE(status)) 608 dev_warn(dev, "Failed to register notifier %08x\n", 609 status); 610 } 611 612 return 0; 613 } 614 615 static void cros_ec_lpc_remove(struct platform_device *pdev) 616 { 617 struct cros_ec_device *ec_dev = platform_get_drvdata(pdev); 618 struct acpi_device *adev; 619 620 adev = ACPI_COMPANION(&pdev->dev); 621 if (adev) 622 acpi_remove_notify_handler(adev->handle, ACPI_ALL_NOTIFY, 623 cros_ec_lpc_acpi_notify); 624 625 cros_ec_unregister(ec_dev); 626 } 627 628 static const struct acpi_device_id cros_ec_lpc_acpi_device_ids[] = { 629 { ACPI_DRV_NAME, 0 }, 630 { } 631 }; 632 MODULE_DEVICE_TABLE(acpi, cros_ec_lpc_acpi_device_ids); 633 634 static const struct lpc_driver_data framework_laptop_npcx_lpc_driver_data __initconst = { 635 .quirks = CROS_EC_LPC_QUIRK_REMAP_MEMORY, 636 .quirk_mmio_memory_base = 0xE00, 637 }; 638 639 static const struct lpc_driver_data framework_laptop_mec_lpc_driver_data __initconst = { 640 .quirks = CROS_EC_LPC_QUIRK_ACPI_ID|CROS_EC_LPC_QUIRK_AML_MUTEX, 641 .quirk_acpi_id = "PNP0C09", 642 .quirk_aml_mutex_name = "ECMT", 643 }; 644 645 static const struct dmi_system_id cros_ec_lpc_dmi_table[] __initconst = { 646 { 647 /* 648 * Today all Chromebooks/boxes ship with Google_* as version and 649 * coreboot as bios vendor. No other systems with this 650 * combination are known to date. 651 */ 652 .matches = { 653 DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), 654 DMI_MATCH(DMI_BIOS_VERSION, "Google_"), 655 }, 656 }, 657 { 658 /* 659 * If the box is running custom coreboot firmware then the 660 * DMI BIOS version string will not be matched by "Google_", 661 * but the system vendor string will still be matched by 662 * "GOOGLE". 663 */ 664 .matches = { 665 DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"), 666 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 667 }, 668 }, 669 { 670 /* x86-link, the Chromebook Pixel. */ 671 .matches = { 672 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 673 DMI_MATCH(DMI_PRODUCT_NAME, "Link"), 674 }, 675 }, 676 { 677 /* x86-samus, the Chromebook Pixel 2. */ 678 .matches = { 679 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 680 DMI_MATCH(DMI_PRODUCT_NAME, "Samus"), 681 }, 682 }, 683 { 684 /* x86-peppy, the Acer C720 Chromebook. */ 685 .matches = { 686 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 687 DMI_MATCH(DMI_PRODUCT_NAME, "Peppy"), 688 }, 689 }, 690 { 691 /* x86-glimmer, the Lenovo Thinkpad Yoga 11e. */ 692 .matches = { 693 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 694 DMI_MATCH(DMI_PRODUCT_NAME, "Glimmer"), 695 }, 696 }, 697 /* A small number of non-Chromebook/box machines also use the ChromeOS EC */ 698 { 699 /* Framework Laptop (11th Gen Intel Core) */ 700 .matches = { 701 DMI_MATCH(DMI_SYS_VENDOR, "Framework"), 702 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Laptop"), 703 }, 704 .driver_data = (void *)&framework_laptop_mec_lpc_driver_data, 705 }, 706 { 707 /* Framework Laptop (12th Gen Intel Core) */ 708 .matches = { 709 DMI_MATCH(DMI_SYS_VENDOR, "Framework"), 710 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "12th Gen Intel Core"), 711 }, 712 .driver_data = (void *)&framework_laptop_mec_lpc_driver_data, 713 }, 714 { 715 /* Framework Laptop (13th Gen Intel Core) */ 716 .matches = { 717 DMI_MATCH(DMI_SYS_VENDOR, "Framework"), 718 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "13th Gen Intel Core"), 719 }, 720 .driver_data = (void *)&framework_laptop_mec_lpc_driver_data, 721 }, 722 { 723 /* 724 * All remaining Framework Laptop models (13 AMD Ryzen, 16 AMD 725 * Ryzen, Intel Core Ultra) 726 */ 727 .matches = { 728 DMI_MATCH(DMI_SYS_VENDOR, "Framework"), 729 DMI_MATCH(DMI_PRODUCT_FAMILY, "Laptop"), 730 }, 731 .driver_data = (void *)&framework_laptop_npcx_lpc_driver_data, 732 }, 733 { /* sentinel */ } 734 }; 735 MODULE_DEVICE_TABLE(dmi, cros_ec_lpc_dmi_table); 736 737 #ifdef CONFIG_PM_SLEEP 738 static int cros_ec_lpc_prepare(struct device *dev) 739 { 740 struct cros_ec_device *ec_dev = dev_get_drvdata(dev); 741 return cros_ec_suspend_prepare(ec_dev); 742 } 743 744 static void cros_ec_lpc_complete(struct device *dev) 745 { 746 struct cros_ec_device *ec_dev = dev_get_drvdata(dev); 747 cros_ec_resume_complete(ec_dev); 748 } 749 750 static int cros_ec_lpc_suspend_late(struct device *dev) 751 { 752 struct cros_ec_device *ec_dev = dev_get_drvdata(dev); 753 754 return cros_ec_suspend_late(ec_dev); 755 } 756 757 static int cros_ec_lpc_resume_early(struct device *dev) 758 { 759 struct cros_ec_device *ec_dev = dev_get_drvdata(dev); 760 761 return cros_ec_resume_early(ec_dev); 762 } 763 #endif 764 765 static const struct dev_pm_ops cros_ec_lpc_pm_ops = { 766 #ifdef CONFIG_PM_SLEEP 767 .prepare = cros_ec_lpc_prepare, 768 .complete = cros_ec_lpc_complete, 769 #endif 770 SET_LATE_SYSTEM_SLEEP_PM_OPS(cros_ec_lpc_suspend_late, cros_ec_lpc_resume_early) 771 }; 772 773 static struct platform_driver cros_ec_lpc_driver = { 774 .driver = { 775 .name = DRV_NAME, 776 .acpi_match_table = cros_ec_lpc_acpi_device_ids, 777 .pm = &cros_ec_lpc_pm_ops, 778 /* 779 * ACPI child devices may probe before us, and they racily 780 * check our drvdata pointer. Force synchronous probe until 781 * those races are resolved. 782 */ 783 .probe_type = PROBE_FORCE_SYNCHRONOUS, 784 }, 785 .probe = cros_ec_lpc_probe, 786 .remove_new = cros_ec_lpc_remove, 787 }; 788 789 static struct platform_device cros_ec_lpc_device = { 790 .name = DRV_NAME 791 }; 792 793 static int __init cros_ec_lpc_init(void) 794 { 795 int ret; 796 const struct dmi_system_id *dmi_match; 797 798 cros_ec_lpc_acpi_device_found = !!cros_ec_lpc_get_device(ACPI_DRV_NAME); 799 800 dmi_match = dmi_first_match(cros_ec_lpc_dmi_table); 801 802 if (!cros_ec_lpc_acpi_device_found && !dmi_match) { 803 pr_err(DRV_NAME ": unsupported system.\n"); 804 return -ENODEV; 805 } 806 807 /* Register the driver */ 808 ret = platform_driver_register(&cros_ec_lpc_driver); 809 if (ret) { 810 pr_err(DRV_NAME ": can't register driver: %d\n", ret); 811 return ret; 812 } 813 814 if (!cros_ec_lpc_acpi_device_found) { 815 /* Pass the DMI match's driver data down to the platform device */ 816 platform_set_drvdata(&cros_ec_lpc_device, dmi_match->driver_data); 817 818 /* Register the device, and it'll get hooked up automatically */ 819 ret = platform_device_register(&cros_ec_lpc_device); 820 if (ret) { 821 pr_err(DRV_NAME ": can't register device: %d\n", ret); 822 platform_driver_unregister(&cros_ec_lpc_driver); 823 } 824 } 825 826 return ret; 827 } 828 829 static void __exit cros_ec_lpc_exit(void) 830 { 831 if (!cros_ec_lpc_acpi_device_found) 832 platform_device_unregister(&cros_ec_lpc_device); 833 platform_driver_unregister(&cros_ec_lpc_driver); 834 } 835 836 module_init(cros_ec_lpc_init); 837 module_exit(cros_ec_lpc_exit); 838 839 MODULE_LICENSE("GPL"); 840 MODULE_DESCRIPTION("ChromeOS EC LPC driver"); 841