1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Pinctrl data for the NVIDIA Tegra234 pinmux 4 * 5 * Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/property.h> 11 12 #include <linux/pinctrl/pinctrl.h> 13 #include <linux/pinctrl/pinmux.h> 14 15 #include "pinctrl-tegra.h" 16 17 /* Define unique ID for each pins */ 18 enum { 19 TEGRA_PIN_DAP6_SCLK_PA0, 20 TEGRA_PIN_DAP6_DOUT_PA1, 21 TEGRA_PIN_DAP6_DIN_PA2, 22 TEGRA_PIN_DAP6_FS_PA3, 23 TEGRA_PIN_DAP4_SCLK_PA4, 24 TEGRA_PIN_DAP4_DOUT_PA5, 25 TEGRA_PIN_DAP4_DIN_PA6, 26 TEGRA_PIN_DAP4_FS_PA7, 27 TEGRA_PIN_SOC_GPIO08_PB0, 28 TEGRA_PIN_QSPI0_SCK_PC0, 29 TEGRA_PIN_QSPI0_CS_N_PC1, 30 TEGRA_PIN_QSPI0_IO0_PC2, 31 TEGRA_PIN_QSPI0_IO1_PC3, 32 TEGRA_PIN_QSPI0_IO2_PC4, 33 TEGRA_PIN_QSPI0_IO3_PC5, 34 TEGRA_PIN_QSPI1_SCK_PC6, 35 TEGRA_PIN_QSPI1_CS_N_PC7, 36 TEGRA_PIN_QSPI1_IO0_PD0, 37 TEGRA_PIN_QSPI1_IO1_PD1, 38 TEGRA_PIN_QSPI1_IO2_PD2, 39 TEGRA_PIN_QSPI1_IO3_PD3, 40 TEGRA_PIN_EQOS_TXC_PE0, 41 TEGRA_PIN_EQOS_TD0_PE1, 42 TEGRA_PIN_EQOS_TD1_PE2, 43 TEGRA_PIN_EQOS_TD2_PE3, 44 TEGRA_PIN_EQOS_TD3_PE4, 45 TEGRA_PIN_EQOS_TX_CTL_PE5, 46 TEGRA_PIN_EQOS_RD0_PE6, 47 TEGRA_PIN_EQOS_RD1_PE7, 48 TEGRA_PIN_EQOS_RD2_PF0, 49 TEGRA_PIN_EQOS_RD3_PF1, 50 TEGRA_PIN_EQOS_RX_CTL_PF2, 51 TEGRA_PIN_EQOS_RXC_PF3, 52 TEGRA_PIN_EQOS_SMA_MDIO_PF4, 53 TEGRA_PIN_EQOS_SMA_MDC_PF5, 54 TEGRA_PIN_SOC_GPIO13_PG0, 55 TEGRA_PIN_SOC_GPIO14_PG1, 56 TEGRA_PIN_SOC_GPIO15_PG2, 57 TEGRA_PIN_SOC_GPIO16_PG3, 58 TEGRA_PIN_SOC_GPIO17_PG4, 59 TEGRA_PIN_SOC_GPIO18_PG5, 60 TEGRA_PIN_SOC_GPIO19_PG6, 61 TEGRA_PIN_SOC_GPIO20_PG7, 62 TEGRA_PIN_SOC_GPIO21_PH0, 63 TEGRA_PIN_SOC_GPIO22_PH1, 64 TEGRA_PIN_SOC_GPIO06_PH2, 65 TEGRA_PIN_UART4_TX_PH3, 66 TEGRA_PIN_UART4_RX_PH4, 67 TEGRA_PIN_UART4_RTS_PH5, 68 TEGRA_PIN_UART4_CTS_PH6, 69 TEGRA_PIN_SOC_GPIO41_PH7, 70 TEGRA_PIN_SOC_GPIO42_PI0, 71 TEGRA_PIN_SOC_GPIO43_PI1, 72 TEGRA_PIN_SOC_GPIO44_PI2, 73 TEGRA_PIN_GEN1_I2C_SCL_PI3, 74 TEGRA_PIN_GEN1_I2C_SDA_PI4, 75 TEGRA_PIN_CPU_PWR_REQ_PI5, 76 TEGRA_PIN_SOC_GPIO07_PI6, 77 TEGRA_PIN_SDMMC1_CLK_PJ0, 78 TEGRA_PIN_SDMMC1_CMD_PJ1, 79 TEGRA_PIN_SDMMC1_DAT0_PJ2, 80 TEGRA_PIN_SDMMC1_DAT1_PJ3, 81 TEGRA_PIN_SDMMC1_DAT2_PJ4, 82 TEGRA_PIN_SDMMC1_DAT3_PJ5, 83 TEGRA_PIN_PEX_L0_CLKREQ_N_PK0, 84 TEGRA_PIN_PEX_L0_RST_N_PK1, 85 TEGRA_PIN_PEX_L1_CLKREQ_N_PK2, 86 TEGRA_PIN_PEX_L1_RST_N_PK3, 87 TEGRA_PIN_PEX_L2_CLKREQ_N_PK4, 88 TEGRA_PIN_PEX_L2_RST_N_PK5, 89 TEGRA_PIN_PEX_L3_CLKREQ_N_PK6, 90 TEGRA_PIN_PEX_L3_RST_N_PK7, 91 TEGRA_PIN_PEX_L4_CLKREQ_N_PL0, 92 TEGRA_PIN_PEX_L4_RST_N_PL1, 93 TEGRA_PIN_PEX_WAKE_N_PL2, 94 TEGRA_PIN_SOC_GPIO34_PL3, 95 TEGRA_PIN_DP_AUX_CH0_HPD_PM0, 96 TEGRA_PIN_DP_AUX_CH1_HPD_PM1, 97 TEGRA_PIN_DP_AUX_CH2_HPD_PM2, 98 TEGRA_PIN_DP_AUX_CH3_HPD_PM3, 99 TEGRA_PIN_SOC_GPIO55_PM4, 100 TEGRA_PIN_SOC_GPIO36_PM5, 101 TEGRA_PIN_SOC_GPIO53_PM6, 102 TEGRA_PIN_SOC_GPIO38_PM7, 103 TEGRA_PIN_DP_AUX_CH3_N_PN0, 104 TEGRA_PIN_SOC_GPIO39_PN1, 105 TEGRA_PIN_SOC_GPIO40_PN2, 106 TEGRA_PIN_DP_AUX_CH1_P_PN3, 107 TEGRA_PIN_DP_AUX_CH1_N_PN4, 108 TEGRA_PIN_DP_AUX_CH2_P_PN5, 109 TEGRA_PIN_DP_AUX_CH2_N_PN6, 110 TEGRA_PIN_DP_AUX_CH3_P_PN7, 111 TEGRA_PIN_EXTPERIPH1_CLK_PP0, 112 TEGRA_PIN_EXTPERIPH2_CLK_PP1, 113 TEGRA_PIN_CAM_I2C_SCL_PP2, 114 TEGRA_PIN_CAM_I2C_SDA_PP3, 115 TEGRA_PIN_SOC_GPIO23_PP4, 116 TEGRA_PIN_SOC_GPIO24_PP5, 117 TEGRA_PIN_SOC_GPIO25_PP6, 118 TEGRA_PIN_PWR_I2C_SCL_PP7, 119 TEGRA_PIN_PWR_I2C_SDA_PQ0, 120 TEGRA_PIN_SOC_GPIO28_PQ1, 121 TEGRA_PIN_SOC_GPIO29_PQ2, 122 TEGRA_PIN_SOC_GPIO30_PQ3, 123 TEGRA_PIN_SOC_GPIO31_PQ4, 124 TEGRA_PIN_SOC_GPIO32_PQ5, 125 TEGRA_PIN_SOC_GPIO33_PQ6, 126 TEGRA_PIN_SOC_GPIO35_PQ7, 127 TEGRA_PIN_SOC_GPIO37_PR0, 128 TEGRA_PIN_SOC_GPIO56_PR1, 129 TEGRA_PIN_UART1_TX_PR2, 130 TEGRA_PIN_UART1_RX_PR3, 131 TEGRA_PIN_UART1_RTS_PR4, 132 TEGRA_PIN_UART1_CTS_PR5, 133 TEGRA_PIN_GPU_PWR_REQ_PX0, 134 TEGRA_PIN_CV_PWR_REQ_PX1, 135 TEGRA_PIN_GP_PWM2_PX2, 136 TEGRA_PIN_GP_PWM3_PX3, 137 TEGRA_PIN_UART2_TX_PX4, 138 TEGRA_PIN_UART2_RX_PX5, 139 TEGRA_PIN_UART2_RTS_PX6, 140 TEGRA_PIN_UART2_CTS_PX7, 141 TEGRA_PIN_SPI3_SCK_PY0, 142 TEGRA_PIN_SPI3_MISO_PY1, 143 TEGRA_PIN_SPI3_MOSI_PY2, 144 TEGRA_PIN_SPI3_CS0_PY3, 145 TEGRA_PIN_SPI3_CS1_PY4, 146 TEGRA_PIN_UART5_TX_PY5, 147 TEGRA_PIN_UART5_RX_PY6, 148 TEGRA_PIN_UART5_RTS_PY7, 149 TEGRA_PIN_UART5_CTS_PZ0, 150 TEGRA_PIN_USB_VBUS_EN0_PZ1, 151 TEGRA_PIN_USB_VBUS_EN1_PZ2, 152 TEGRA_PIN_SPI1_SCK_PZ3, 153 TEGRA_PIN_SPI1_MISO_PZ4, 154 TEGRA_PIN_SPI1_MOSI_PZ5, 155 TEGRA_PIN_SPI1_CS0_PZ6, 156 TEGRA_PIN_SPI1_CS1_PZ7, 157 TEGRA_PIN_SPI5_SCK_PAC0, 158 TEGRA_PIN_SPI5_MISO_PAC1, 159 TEGRA_PIN_SPI5_MOSI_PAC2, 160 TEGRA_PIN_SPI5_CS0_PAC3, 161 TEGRA_PIN_SOC_GPIO57_PAC4, 162 TEGRA_PIN_SOC_GPIO58_PAC5, 163 TEGRA_PIN_SOC_GPIO59_PAC6, 164 TEGRA_PIN_SOC_GPIO60_PAC7, 165 TEGRA_PIN_SOC_GPIO45_PAD0, 166 TEGRA_PIN_SOC_GPIO46_PAD1, 167 TEGRA_PIN_SOC_GPIO47_PAD2, 168 TEGRA_PIN_SOC_GPIO48_PAD3, 169 TEGRA_PIN_UFS0_REF_CLK_PAE0, 170 TEGRA_PIN_UFS0_RST_N_PAE1, 171 TEGRA_PIN_PEX_L5_CLKREQ_N_PAF0, 172 TEGRA_PIN_PEX_L5_RST_N_PAF1, 173 TEGRA_PIN_PEX_L6_CLKREQ_N_PAF2, 174 TEGRA_PIN_PEX_L6_RST_N_PAF3, 175 TEGRA_PIN_PEX_L7_CLKREQ_N_PAG0, 176 TEGRA_PIN_PEX_L7_RST_N_PAG1, 177 TEGRA_PIN_PEX_L8_CLKREQ_N_PAG2, 178 TEGRA_PIN_PEX_L8_RST_N_PAG3, 179 TEGRA_PIN_PEX_L9_CLKREQ_N_PAG4, 180 TEGRA_PIN_PEX_L9_RST_N_PAG5, 181 TEGRA_PIN_PEX_L10_CLKREQ_N_PAG6, 182 TEGRA_PIN_PEX_L10_RST_N_PAG7, 183 TEGRA_PIN_EQOS_COMP, 184 TEGRA_PIN_QSPI_COMP, 185 TEGRA_PIN_SDMMC1_COMP, 186 }; 187 188 enum { 189 TEGRA_PIN_CAN0_DOUT_PAA0, 190 TEGRA_PIN_CAN0_DIN_PAA1, 191 TEGRA_PIN_CAN1_DOUT_PAA2, 192 TEGRA_PIN_CAN1_DIN_PAA3, 193 TEGRA_PIN_CAN0_STB_PAA4, 194 TEGRA_PIN_CAN0_EN_PAA5, 195 TEGRA_PIN_SOC_GPIO49_PAA6, 196 TEGRA_PIN_CAN0_ERR_PAA7, 197 TEGRA_PIN_CAN1_STB_PBB0, 198 TEGRA_PIN_CAN1_EN_PBB1, 199 TEGRA_PIN_SOC_GPIO50_PBB2, 200 TEGRA_PIN_CAN1_ERR_PBB3, 201 TEGRA_PIN_SPI2_SCK_PCC0, 202 TEGRA_PIN_SPI2_MISO_PCC1, 203 TEGRA_PIN_SPI2_MOSI_PCC2, 204 TEGRA_PIN_SPI2_CS0_PCC3, 205 TEGRA_PIN_TOUCH_CLK_PCC4, 206 TEGRA_PIN_UART3_TX_PCC5, 207 TEGRA_PIN_UART3_RX_PCC6, 208 TEGRA_PIN_GEN2_I2C_SCL_PCC7, 209 TEGRA_PIN_GEN2_I2C_SDA_PDD0, 210 TEGRA_PIN_GEN8_I2C_SCL_PDD1, 211 TEGRA_PIN_GEN8_I2C_SDA_PDD2, 212 TEGRA_PIN_SCE_ERROR_PEE0, 213 TEGRA_PIN_VCOMP_ALERT_PEE1, 214 TEGRA_PIN_AO_RETENTION_N_PEE2, 215 TEGRA_PIN_BATT_OC_PEE3, 216 TEGRA_PIN_POWER_ON_PEE4, 217 TEGRA_PIN_SOC_GPIO26_PEE5, 218 TEGRA_PIN_SOC_GPIO27_PEE6, 219 TEGRA_PIN_BOOTV_CTL_N_PEE7, 220 TEGRA_PIN_HDMI_CEC_PGG0, 221 }; 222 223 /* Table for pin descriptor */ 224 static const struct pinctrl_pin_desc tegra234_pins[] = { 225 PINCTRL_PIN(TEGRA_PIN_DAP6_SCLK_PA0, "DAP6_SCLK_PA0"), 226 PINCTRL_PIN(TEGRA_PIN_DAP6_DOUT_PA1, "DAP6_DOUT_PA1"), 227 PINCTRL_PIN(TEGRA_PIN_DAP6_DIN_PA2, "DAP6_DIN_PA2"), 228 PINCTRL_PIN(TEGRA_PIN_DAP6_FS_PA3, "DAP6_FS_PA3"), 229 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PA4, "DAP4_SCLK_PA4"), 230 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PA5, "DAP4_DOUT_PA5"), 231 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PA6, "DAP4_DIN_PA6"), 232 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PA7, "DAP4_FS_PA7"), 233 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO08_PB0, "SOC_GPIO08_PB0"), 234 PINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PC0, "QSPI0_SCK_PC0"), 235 PINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PC1, "QSPI0_CS_N_PC1"), 236 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PC2, "QSPI0_IO0_PC2"), 237 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PC3, "QSPI0_IO1_PC3"), 238 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO2_PC4, "QSPI0_IO2_PC4"), 239 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO3_PC5, "QSPI0_IO3_PC5"), 240 PINCTRL_PIN(TEGRA_PIN_QSPI1_SCK_PC6, "QSPI1_SCK_PC6"), 241 PINCTRL_PIN(TEGRA_PIN_QSPI1_CS_N_PC7, "QSPI1_CS_N_PC7"), 242 PINCTRL_PIN(TEGRA_PIN_QSPI1_IO0_PD0, "QSPI1_IO0_PD0"), 243 PINCTRL_PIN(TEGRA_PIN_QSPI1_IO1_PD1, "QSPI1_IO1_PD1"), 244 PINCTRL_PIN(TEGRA_PIN_QSPI1_IO2_PD2, "QSPI1_IO2_PD2"), 245 PINCTRL_PIN(TEGRA_PIN_QSPI1_IO3_PD3, "QSPI1_IO3_PD3"), 246 PINCTRL_PIN(TEGRA_PIN_EQOS_TXC_PE0, "EQOS_TXC_PE0"), 247 PINCTRL_PIN(TEGRA_PIN_EQOS_TD0_PE1, "EQOS_TD0_PE1"), 248 PINCTRL_PIN(TEGRA_PIN_EQOS_TD1_PE2, "EQOS_TD1_PE2"), 249 PINCTRL_PIN(TEGRA_PIN_EQOS_TD2_PE3, "EQOS_TD2_PE3"), 250 PINCTRL_PIN(TEGRA_PIN_EQOS_TD3_PE4, "EQOS_TD3_PE4"), 251 PINCTRL_PIN(TEGRA_PIN_EQOS_TX_CTL_PE5, "EQOS_TX_CTL_PE5"), 252 PINCTRL_PIN(TEGRA_PIN_EQOS_RD0_PE6, "EQOS_RD0_PE6"), 253 PINCTRL_PIN(TEGRA_PIN_EQOS_RD1_PE7, "EQOS_RD1_PE7"), 254 PINCTRL_PIN(TEGRA_PIN_EQOS_RD2_PF0, "EQOS_RD2_PF0"), 255 PINCTRL_PIN(TEGRA_PIN_EQOS_RD3_PF1, "EQOS_RD3_PF1"), 256 PINCTRL_PIN(TEGRA_PIN_EQOS_RX_CTL_PF2, "EQOS_RX_CTL_PF2"), 257 PINCTRL_PIN(TEGRA_PIN_EQOS_RXC_PF3, "EQOS_RXC_PF3"), 258 PINCTRL_PIN(TEGRA_PIN_EQOS_SMA_MDIO_PF4, "EQOS_SMA_MDIO_PF4"), 259 PINCTRL_PIN(TEGRA_PIN_EQOS_SMA_MDC_PF5, "EQOS_SMA_MDC_PF5"), 260 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO13_PG0, "SOC_GPIO13_PG0"), 261 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO14_PG1, "SOC_GPIO14_PG1"), 262 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO15_PG2, "SOC_GPIO15_PG2"), 263 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO16_PG3, "SOC_GPIO16_PG3"), 264 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO17_PG4, "SOC_GPIO17_PG4"), 265 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO18_PG5, "SOC_GPIO18_PG5"), 266 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO19_PG6, "SOC_GPIO19_PG6"), 267 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO20_PG7, "SOC_GPIO20_PG7"), 268 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PH0, "SOC_GPIO21_PH0"), 269 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PH1, "SOC_GPIO22_PH1"), 270 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO06_PH2, "SOC_GPIO06_PH2"), 271 PINCTRL_PIN(TEGRA_PIN_UART4_TX_PH3, "UART4_TX_PH3"), 272 PINCTRL_PIN(TEGRA_PIN_UART4_RX_PH4, "UART4_RX_PH4"), 273 PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PH5, "UART4_RTS_PH5"), 274 PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PH6, "UART4_CTS_PH6"), 275 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO41_PH7, "SOC_GPIO41_PH7"), 276 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO42_PI0, "SOC_GPIO42_PI0"), 277 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO43_PI1, "SOC_GPIO43_PI1"), 278 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO44_PI2, "SOC_GPIO44_PI2"), 279 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PI3, "GEN1_I2C_SCL_PI3"), 280 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PI4, "GEN1_I2C_SDA_PI4"), 281 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_PI5, "CPU_PWR_REQ_PI5"), 282 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PI6, "SOC_GPIO07_PI6"), 283 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PJ0, "SDMMC1_CLK_PJ0"), 284 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PJ1, "SDMMC1_CMD_PJ1"), 285 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PJ2, "SDMMC1_DAT0_PJ2"), 286 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PJ3, "SDMMC1_DAT1_PJ3"), 287 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PJ4, "SDMMC1_DAT2_PJ4"), 288 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PJ5, "SDMMC1_DAT3_PJ5"), 289 PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PK0, "PEX_L0_CLKREQ_N_PK0"), 290 PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PK1, "PEX_L0_RST_N_PK1"), 291 PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PK2, "PEX_L1_CLKREQ_N_PK2"), 292 PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PK3, "PEX_L1_RST_N_PK3"), 293 PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PK4, "PEX_L2_CLKREQ_N_PK4"), 294 PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PK5, "PEX_L2_RST_N_PK5"), 295 PINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PK6, "PEX_L3_CLKREQ_N_PK6"), 296 PINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PK7, "PEX_L3_RST_N_PK7"), 297 PINCTRL_PIN(TEGRA_PIN_PEX_L4_CLKREQ_N_PL0, "PEX_L4_CLKREQ_N_PL0"), 298 PINCTRL_PIN(TEGRA_PIN_PEX_L4_RST_N_PL1, "PEX_L4_RST_N_PL1"), 299 PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PL2, "PEX_WAKE_N_PL2"), 300 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO34_PL3, "SOC_GPIO34_PL3"), 301 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PM0, "DP_AUX_CH0_HPD_PM0"), 302 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PM1, "DP_AUX_CH1_HPD_PM1"), 303 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_HPD_PM2, "DP_AUX_CH2_HPD_PM2"), 304 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_HPD_PM3, "DP_AUX_CH3_HPD_PM3"), 305 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO55_PM4, "SOC_GPIO55_PM4"), 306 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO36_PM5, "SOC_GPIO36_PM5"), 307 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO53_PM6, "SOC_GPIO53_PM6"), 308 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO38_PM7, "SOC_GPIO38_PM7"), 309 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_N_PN0, "DP_AUX_CH3_N_PN0"), 310 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO39_PN1, "SOC_GPIO39_PN1"), 311 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO40_PN2, "SOC_GPIO40_PN2"), 312 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_P_PN3, "DP_AUX_CH1_P_PN3"), 313 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_N_PN4, "DP_AUX_CH1_N_PN4"), 314 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_P_PN5, "DP_AUX_CH2_P_PN5"), 315 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_N_PN6, "DP_AUX_CH2_N_PN6"), 316 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_P_PN7, "DP_AUX_CH3_P_PN7"), 317 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PP0, "EXTPERIPH1_CLK_PP0"), 318 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PP1, "EXTPERIPH2_CLK_PP1"), 319 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PP2, "CAM_I2C_SCL_PP2"), 320 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PP3, "CAM_I2C_SDA_PP3"), 321 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PP4, "SOC_GPIO23_PP4"), 322 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO24_PP5, "SOC_GPIO24_PP5"), 323 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO25_PP6, "SOC_GPIO25_PP6"), 324 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PP7, "PWR_I2C_SCL_PP7"), 325 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PQ0, "PWR_I2C_SDA_PQ0"), 326 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO28_PQ1, "SOC_GPIO28_PQ1"), 327 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO29_PQ2, "SOC_GPIO29_PQ2"), 328 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO30_PQ3, "SOC_GPIO30_PQ3"), 329 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO31_PQ4, "SOC_GPIO31_PQ4"), 330 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO32_PQ5, "SOC_GPIO32_PQ5"), 331 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO33_PQ6, "SOC_GPIO33_PQ6"), 332 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO35_PQ7, "SOC_GPIO35_PQ7"), 333 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO37_PR0, "SOC_GPIO37_PR0"), 334 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO56_PR1, "SOC_GPIO56_PR1"), 335 PINCTRL_PIN(TEGRA_PIN_UART1_TX_PR2, "UART1_TX_PR2"), 336 PINCTRL_PIN(TEGRA_PIN_UART1_RX_PR3, "UART1_RX_PR3"), 337 PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PR4, "UART1_RTS_PR4"), 338 PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PR5, "UART1_CTS_PR5"), 339 PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PX0, "GPU_PWR_REQ_PX0"), 340 PINCTRL_PIN(TEGRA_PIN_CV_PWR_REQ_PX1, "CV_PWR_REQ_PX1"), 341 PINCTRL_PIN(TEGRA_PIN_GP_PWM2_PX2, "GP_PWM2_PX2"), 342 PINCTRL_PIN(TEGRA_PIN_GP_PWM3_PX3, "GP_PWM3_PX3"), 343 PINCTRL_PIN(TEGRA_PIN_UART2_TX_PX4, "UART2_TX_PX4"), 344 PINCTRL_PIN(TEGRA_PIN_UART2_RX_PX5, "UART2_RX_PX5"), 345 PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PX6, "UART2_RTS_PX6"), 346 PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PX7, "UART2_CTS_PX7"), 347 PINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PY0, "SPI3_SCK_PY0"), 348 PINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PY1, "SPI3_MISO_PY1"), 349 PINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PY2, "SPI3_MOSI_PY2"), 350 PINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PY3, "SPI3_CS0_PY3"), 351 PINCTRL_PIN(TEGRA_PIN_SPI3_CS1_PY4, "SPI3_CS1_PY4"), 352 PINCTRL_PIN(TEGRA_PIN_UART5_TX_PY5, "UART5_TX_PY5"), 353 PINCTRL_PIN(TEGRA_PIN_UART5_RX_PY6, "UART5_RX_PY6"), 354 PINCTRL_PIN(TEGRA_PIN_UART5_RTS_PY7, "UART5_RTS_PY7"), 355 PINCTRL_PIN(TEGRA_PIN_UART5_CTS_PZ0, "UART5_CTS_PZ0"), 356 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PZ1, "USB_VBUS_EN0_PZ1"), 357 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PZ2, "USB_VBUS_EN1_PZ2"), 358 PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PZ3, "SPI1_SCK_PZ3"), 359 PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PZ4, "SPI1_MISO_PZ4"), 360 PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PZ5, "SPI1_MOSI_PZ5"), 361 PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PZ6, "SPI1_CS0_PZ6"), 362 PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PZ7, "SPI1_CS1_PZ7"), 363 PINCTRL_PIN(TEGRA_PIN_SPI5_SCK_PAC0, "SPI5_SCK_PAC0"), 364 PINCTRL_PIN(TEGRA_PIN_SPI5_MISO_PAC1, "SPI5_MISO_PAC1"), 365 PINCTRL_PIN(TEGRA_PIN_SPI5_MOSI_PAC2, "SPI5_MOSI_PAC2"), 366 PINCTRL_PIN(TEGRA_PIN_SPI5_CS0_PAC3, "SPI5_CS0_PAC3"), 367 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO57_PAC4, "SOC_GPIO57_PAC4"), 368 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO58_PAC5, "SOC_GPIO58_PAC5"), 369 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO59_PAC6, "SOC_GPIO59_PAC6"), 370 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO60_PAC7, "SOC_GPIO60_PAC7"), 371 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO45_PAD0, "SOC_GPIO45_PAD0"), 372 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO46_PAD1, "SOC_GPIO46_PAD1"), 373 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO47_PAD2, "SOC_GPIO47_PAD2"), 374 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO48_PAD3, "SOC_GPIO48_PAD3"), 375 PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PAE0, "UFS0_REF_CLK_PAE0"), 376 PINCTRL_PIN(TEGRA_PIN_UFS0_RST_N_PAE1, "UFS0_RST_N_PAE1"), 377 PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PAF0, "PEX_L5_CLKREQ_N_PAF0"), 378 PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PAF1, "PEX_L5_RST_N_PAF1"), 379 PINCTRL_PIN(TEGRA_PIN_PEX_L6_CLKREQ_N_PAF2, "PEX_L6_CLKREQ_N_PAF2"), 380 PINCTRL_PIN(TEGRA_PIN_PEX_L6_RST_N_PAF3, "PEX_L6_RST_N_PAF3"), 381 PINCTRL_PIN(TEGRA_PIN_PEX_L7_CLKREQ_N_PAG0, "PEX_L7_CLKREQ_N_PAG0"), 382 PINCTRL_PIN(TEGRA_PIN_PEX_L7_RST_N_PAG1, "PEX_L7_RST_N_PAG1"), 383 PINCTRL_PIN(TEGRA_PIN_PEX_L8_CLKREQ_N_PAG2, "PEX_L8_CLKREQ_N_PAG2"), 384 PINCTRL_PIN(TEGRA_PIN_PEX_L8_RST_N_PAG3, "PEX_L8_RST_N_PAG3"), 385 PINCTRL_PIN(TEGRA_PIN_PEX_L9_CLKREQ_N_PAG4, "PEX_L9_CLKREQ_N_PAG4"), 386 PINCTRL_PIN(TEGRA_PIN_PEX_L9_RST_N_PAG5, "PEX_L9_RST_N_PAG5"), 387 PINCTRL_PIN(TEGRA_PIN_PEX_L10_CLKREQ_N_PAG6, "PEX_L10_CLKREQ_N_PAG6"), 388 PINCTRL_PIN(TEGRA_PIN_PEX_L10_RST_N_PAG7, "PEX_L10_RST_N_PAG7"), 389 PINCTRL_PIN(TEGRA_PIN_EQOS_COMP, "EQOS_COMP"), 390 PINCTRL_PIN(TEGRA_PIN_QSPI_COMP, "QSPI_COMP"), 391 PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"), 392 }; 393 394 static const unsigned int dap6_sclk_pa0_pins[] = { 395 TEGRA_PIN_DAP6_SCLK_PA0, 396 }; 397 398 static const unsigned int dap6_dout_pa1_pins[] = { 399 TEGRA_PIN_DAP6_DOUT_PA1, 400 }; 401 402 static const unsigned int dap6_din_pa2_pins[] = { 403 TEGRA_PIN_DAP6_DIN_PA2, 404 }; 405 406 static const unsigned int dap6_fs_pa3_pins[] = { 407 TEGRA_PIN_DAP6_FS_PA3, 408 }; 409 410 static const unsigned int dap4_sclk_pa4_pins[] = { 411 TEGRA_PIN_DAP4_SCLK_PA4, 412 }; 413 414 static const unsigned int dap4_dout_pa5_pins[] = { 415 TEGRA_PIN_DAP4_DOUT_PA5, 416 }; 417 418 static const unsigned int dap4_din_pa6_pins[] = { 419 TEGRA_PIN_DAP4_DIN_PA6, 420 }; 421 422 static const unsigned int dap4_fs_pa7_pins[] = { 423 TEGRA_PIN_DAP4_FS_PA7, 424 }; 425 426 static const unsigned int soc_gpio08_pb0_pins[] = { 427 TEGRA_PIN_SOC_GPIO08_PB0, 428 }; 429 430 static const unsigned int qspi0_sck_pc0_pins[] = { 431 TEGRA_PIN_QSPI0_SCK_PC0, 432 }; 433 434 static const unsigned int qspi0_cs_n_pc1_pins[] = { 435 TEGRA_PIN_QSPI0_CS_N_PC1, 436 }; 437 438 static const unsigned int qspi0_io0_pc2_pins[] = { 439 TEGRA_PIN_QSPI0_IO0_PC2, 440 }; 441 442 static const unsigned int qspi0_io1_pc3_pins[] = { 443 TEGRA_PIN_QSPI0_IO1_PC3, 444 }; 445 446 static const unsigned int qspi0_io2_pc4_pins[] = { 447 TEGRA_PIN_QSPI0_IO2_PC4, 448 }; 449 450 static const unsigned int qspi0_io3_pc5_pins[] = { 451 TEGRA_PIN_QSPI0_IO3_PC5, 452 }; 453 454 static const unsigned int qspi1_sck_pc6_pins[] = { 455 TEGRA_PIN_QSPI1_SCK_PC6, 456 }; 457 458 static const unsigned int qspi1_cs_n_pc7_pins[] = { 459 TEGRA_PIN_QSPI1_CS_N_PC7, 460 }; 461 462 static const unsigned int qspi1_io0_pd0_pins[] = { 463 TEGRA_PIN_QSPI1_IO0_PD0, 464 }; 465 466 static const unsigned int qspi1_io1_pd1_pins[] = { 467 TEGRA_PIN_QSPI1_IO1_PD1, 468 }; 469 470 static const unsigned int qspi1_io2_pd2_pins[] = { 471 TEGRA_PIN_QSPI1_IO2_PD2, 472 }; 473 474 static const unsigned int qspi1_io3_pd3_pins[] = { 475 TEGRA_PIN_QSPI1_IO3_PD3, 476 }; 477 478 static const unsigned int eqos_txc_pe0_pins[] = { 479 TEGRA_PIN_EQOS_TXC_PE0, 480 }; 481 482 static const unsigned int eqos_td0_pe1_pins[] = { 483 TEGRA_PIN_EQOS_TD0_PE1, 484 }; 485 486 static const unsigned int eqos_td1_pe2_pins[] = { 487 TEGRA_PIN_EQOS_TD1_PE2, 488 }; 489 490 static const unsigned int eqos_td2_pe3_pins[] = { 491 TEGRA_PIN_EQOS_TD2_PE3, 492 }; 493 494 static const unsigned int eqos_td3_pe4_pins[] = { 495 TEGRA_PIN_EQOS_TD3_PE4, 496 }; 497 498 static const unsigned int eqos_tx_ctl_pe5_pins[] = { 499 TEGRA_PIN_EQOS_TX_CTL_PE5, 500 }; 501 502 static const unsigned int eqos_rd0_pe6_pins[] = { 503 TEGRA_PIN_EQOS_RD0_PE6, 504 }; 505 506 static const unsigned int eqos_rd1_pe7_pins[] = { 507 TEGRA_PIN_EQOS_RD1_PE7, 508 }; 509 510 static const unsigned int eqos_rd2_pf0_pins[] = { 511 TEGRA_PIN_EQOS_RD2_PF0, 512 }; 513 514 static const unsigned int eqos_rd3_pf1_pins[] = { 515 TEGRA_PIN_EQOS_RD3_PF1, 516 }; 517 518 static const unsigned int eqos_rx_ctl_pf2_pins[] = { 519 TEGRA_PIN_EQOS_RX_CTL_PF2, 520 }; 521 522 static const unsigned int eqos_rxc_pf3_pins[] = { 523 TEGRA_PIN_EQOS_RXC_PF3, 524 }; 525 526 static const unsigned int eqos_sma_mdio_pf4_pins[] = { 527 TEGRA_PIN_EQOS_SMA_MDIO_PF4, 528 }; 529 530 static const unsigned int eqos_sma_mdc_pf5_pins[] = { 531 TEGRA_PIN_EQOS_SMA_MDC_PF5, 532 }; 533 534 static const unsigned int soc_gpio13_pg0_pins[] = { 535 TEGRA_PIN_SOC_GPIO13_PG0, 536 }; 537 538 static const unsigned int soc_gpio14_pg1_pins[] = { 539 TEGRA_PIN_SOC_GPIO14_PG1, 540 }; 541 542 static const unsigned int soc_gpio15_pg2_pins[] = { 543 TEGRA_PIN_SOC_GPIO15_PG2, 544 }; 545 546 static const unsigned int soc_gpio16_pg3_pins[] = { 547 TEGRA_PIN_SOC_GPIO16_PG3, 548 }; 549 550 static const unsigned int soc_gpio17_pg4_pins[] = { 551 TEGRA_PIN_SOC_GPIO17_PG4, 552 }; 553 554 static const unsigned int soc_gpio18_pg5_pins[] = { 555 TEGRA_PIN_SOC_GPIO18_PG5, 556 }; 557 558 static const unsigned int soc_gpio19_pg6_pins[] = { 559 TEGRA_PIN_SOC_GPIO19_PG6, 560 }; 561 562 static const unsigned int soc_gpio20_pg7_pins[] = { 563 TEGRA_PIN_SOC_GPIO20_PG7, 564 }; 565 566 static const unsigned int soc_gpio21_ph0_pins[] = { 567 TEGRA_PIN_SOC_GPIO21_PH0, 568 }; 569 570 static const unsigned int soc_gpio22_ph1_pins[] = { 571 TEGRA_PIN_SOC_GPIO22_PH1, 572 }; 573 574 static const unsigned int soc_gpio06_ph2_pins[] = { 575 TEGRA_PIN_SOC_GPIO06_PH2, 576 }; 577 578 static const unsigned int uart4_tx_ph3_pins[] = { 579 TEGRA_PIN_UART4_TX_PH3, 580 }; 581 582 static const unsigned int uart4_rx_ph4_pins[] = { 583 TEGRA_PIN_UART4_RX_PH4, 584 }; 585 586 static const unsigned int uart4_rts_ph5_pins[] = { 587 TEGRA_PIN_UART4_RTS_PH5, 588 }; 589 590 static const unsigned int uart4_cts_ph6_pins[] = { 591 TEGRA_PIN_UART4_CTS_PH6, 592 }; 593 594 static const unsigned int soc_gpio41_ph7_pins[] = { 595 TEGRA_PIN_SOC_GPIO41_PH7, 596 }; 597 598 static const unsigned int soc_gpio42_pi0_pins[] = { 599 TEGRA_PIN_SOC_GPIO42_PI0, 600 }; 601 602 static const unsigned int soc_gpio43_pi1_pins[] = { 603 TEGRA_PIN_SOC_GPIO43_PI1, 604 }; 605 606 static const unsigned int soc_gpio44_pi2_pins[] = { 607 TEGRA_PIN_SOC_GPIO44_PI2, 608 }; 609 610 static const unsigned int gen1_i2c_scl_pi3_pins[] = { 611 TEGRA_PIN_GEN1_I2C_SCL_PI3, 612 }; 613 614 static const unsigned int gen1_i2c_sda_pi4_pins[] = { 615 TEGRA_PIN_GEN1_I2C_SDA_PI4, 616 }; 617 618 static const unsigned int cpu_pwr_req_pi5_pins[] = { 619 TEGRA_PIN_CPU_PWR_REQ_PI5, 620 }; 621 622 static const unsigned int soc_gpio07_pi6_pins[] = { 623 TEGRA_PIN_SOC_GPIO07_PI6, 624 }; 625 626 static const unsigned int sdmmc1_clk_pj0_pins[] = { 627 TEGRA_PIN_SDMMC1_CLK_PJ0, 628 }; 629 630 static const unsigned int sdmmc1_cmd_pj1_pins[] = { 631 TEGRA_PIN_SDMMC1_CMD_PJ1, 632 }; 633 634 static const unsigned int sdmmc1_dat0_pj2_pins[] = { 635 TEGRA_PIN_SDMMC1_DAT0_PJ2, 636 }; 637 638 static const unsigned int sdmmc1_dat1_pj3_pins[] = { 639 TEGRA_PIN_SDMMC1_DAT1_PJ3, 640 }; 641 642 static const unsigned int sdmmc1_dat2_pj4_pins[] = { 643 TEGRA_PIN_SDMMC1_DAT2_PJ4, 644 }; 645 646 static const unsigned int sdmmc1_dat3_pj5_pins[] = { 647 TEGRA_PIN_SDMMC1_DAT3_PJ5, 648 }; 649 650 static const unsigned int pex_l0_clkreq_n_pk0_pins[] = { 651 TEGRA_PIN_PEX_L0_CLKREQ_N_PK0, 652 }; 653 654 static const unsigned int pex_l0_rst_n_pk1_pins[] = { 655 TEGRA_PIN_PEX_L0_RST_N_PK1, 656 }; 657 658 static const unsigned int pex_l1_clkreq_n_pk2_pins[] = { 659 TEGRA_PIN_PEX_L1_CLKREQ_N_PK2, 660 }; 661 662 static const unsigned int pex_l1_rst_n_pk3_pins[] = { 663 TEGRA_PIN_PEX_L1_RST_N_PK3, 664 }; 665 666 static const unsigned int pex_l2_clkreq_n_pk4_pins[] = { 667 TEGRA_PIN_PEX_L2_CLKREQ_N_PK4, 668 }; 669 670 static const unsigned int pex_l2_rst_n_pk5_pins[] = { 671 TEGRA_PIN_PEX_L2_RST_N_PK5, 672 }; 673 674 static const unsigned int pex_l3_clkreq_n_pk6_pins[] = { 675 TEGRA_PIN_PEX_L3_CLKREQ_N_PK6, 676 }; 677 678 static const unsigned int pex_l3_rst_n_pk7_pins[] = { 679 TEGRA_PIN_PEX_L3_RST_N_PK7, 680 }; 681 682 static const unsigned int pex_l4_clkreq_n_pl0_pins[] = { 683 TEGRA_PIN_PEX_L4_CLKREQ_N_PL0, 684 }; 685 686 static const unsigned int pex_l4_rst_n_pl1_pins[] = { 687 TEGRA_PIN_PEX_L4_RST_N_PL1, 688 }; 689 690 static const unsigned int pex_wake_n_pl2_pins[] = { 691 TEGRA_PIN_PEX_WAKE_N_PL2, 692 }; 693 694 static const unsigned int soc_gpio34_pl3_pins[] = { 695 TEGRA_PIN_SOC_GPIO34_PL3, 696 }; 697 698 static const unsigned int dp_aux_ch0_hpd_pm0_pins[] = { 699 TEGRA_PIN_DP_AUX_CH0_HPD_PM0, 700 }; 701 702 static const unsigned int dp_aux_ch1_hpd_pm1_pins[] = { 703 TEGRA_PIN_DP_AUX_CH1_HPD_PM1, 704 }; 705 706 static const unsigned int dp_aux_ch2_hpd_pm2_pins[] = { 707 TEGRA_PIN_DP_AUX_CH2_HPD_PM2, 708 }; 709 710 static const unsigned int dp_aux_ch3_hpd_pm3_pins[] = { 711 TEGRA_PIN_DP_AUX_CH3_HPD_PM3, 712 }; 713 714 static const unsigned int soc_gpio55_pm4_pins[] = { 715 TEGRA_PIN_SOC_GPIO55_PM4, 716 }; 717 718 static const unsigned int soc_gpio36_pm5_pins[] = { 719 TEGRA_PIN_SOC_GPIO36_PM5, 720 }; 721 722 static const unsigned int soc_gpio53_pm6_pins[] = { 723 TEGRA_PIN_SOC_GPIO53_PM6, 724 }; 725 726 static const unsigned int soc_gpio38_pm7_pins[] = { 727 TEGRA_PIN_SOC_GPIO38_PM7, 728 }; 729 730 static const unsigned int dp_aux_ch3_n_pn0_pins[] = { 731 TEGRA_PIN_DP_AUX_CH3_N_PN0, 732 }; 733 734 static const unsigned int soc_gpio39_pn1_pins[] = { 735 TEGRA_PIN_SOC_GPIO39_PN1, 736 }; 737 738 static const unsigned int soc_gpio40_pn2_pins[] = { 739 TEGRA_PIN_SOC_GPIO40_PN2, 740 }; 741 742 static const unsigned int dp_aux_ch1_p_pn3_pins[] = { 743 TEGRA_PIN_DP_AUX_CH1_P_PN3, 744 }; 745 746 static const unsigned int dp_aux_ch1_n_pn4_pins[] = { 747 TEGRA_PIN_DP_AUX_CH1_N_PN4, 748 }; 749 750 static const unsigned int dp_aux_ch2_p_pn5_pins[] = { 751 TEGRA_PIN_DP_AUX_CH2_P_PN5, 752 }; 753 754 static const unsigned int dp_aux_ch2_n_pn6_pins[] = { 755 TEGRA_PIN_DP_AUX_CH2_N_PN6, 756 }; 757 758 static const unsigned int dp_aux_ch3_p_pn7_pins[] = { 759 TEGRA_PIN_DP_AUX_CH3_P_PN7, 760 }; 761 762 static const unsigned int extperiph1_clk_pp0_pins[] = { 763 TEGRA_PIN_EXTPERIPH1_CLK_PP0, 764 }; 765 766 static const unsigned int extperiph2_clk_pp1_pins[] = { 767 TEGRA_PIN_EXTPERIPH2_CLK_PP1, 768 }; 769 770 static const unsigned int cam_i2c_scl_pp2_pins[] = { 771 TEGRA_PIN_CAM_I2C_SCL_PP2, 772 }; 773 774 static const unsigned int cam_i2c_sda_pp3_pins[] = { 775 TEGRA_PIN_CAM_I2C_SDA_PP3, 776 }; 777 778 static const unsigned int soc_gpio23_pp4_pins[] = { 779 TEGRA_PIN_SOC_GPIO23_PP4, 780 }; 781 782 static const unsigned int soc_gpio24_pp5_pins[] = { 783 TEGRA_PIN_SOC_GPIO24_PP5, 784 }; 785 786 static const unsigned int soc_gpio25_pp6_pins[] = { 787 TEGRA_PIN_SOC_GPIO25_PP6, 788 }; 789 790 static const unsigned int pwr_i2c_scl_pp7_pins[] = { 791 TEGRA_PIN_PWR_I2C_SCL_PP7, 792 }; 793 794 static const unsigned int pwr_i2c_sda_pq0_pins[] = { 795 TEGRA_PIN_PWR_I2C_SDA_PQ0, 796 }; 797 798 static const unsigned int soc_gpio28_pq1_pins[] = { 799 TEGRA_PIN_SOC_GPIO28_PQ1, 800 }; 801 802 static const unsigned int soc_gpio29_pq2_pins[] = { 803 TEGRA_PIN_SOC_GPIO29_PQ2, 804 }; 805 806 static const unsigned int soc_gpio30_pq3_pins[] = { 807 TEGRA_PIN_SOC_GPIO30_PQ3, 808 }; 809 810 static const unsigned int soc_gpio31_pq4_pins[] = { 811 TEGRA_PIN_SOC_GPIO31_PQ4, 812 }; 813 814 static const unsigned int soc_gpio32_pq5_pins[] = { 815 TEGRA_PIN_SOC_GPIO32_PQ5, 816 }; 817 818 static const unsigned int soc_gpio33_pq6_pins[] = { 819 TEGRA_PIN_SOC_GPIO33_PQ6, 820 }; 821 822 static const unsigned int soc_gpio35_pq7_pins[] = { 823 TEGRA_PIN_SOC_GPIO35_PQ7, 824 }; 825 826 static const unsigned int soc_gpio37_pr0_pins[] = { 827 TEGRA_PIN_SOC_GPIO37_PR0, 828 }; 829 830 static const unsigned int soc_gpio56_pr1_pins[] = { 831 TEGRA_PIN_SOC_GPIO56_PR1, 832 }; 833 834 static const unsigned int uart1_tx_pr2_pins[] = { 835 TEGRA_PIN_UART1_TX_PR2, 836 }; 837 838 static const unsigned int uart1_rx_pr3_pins[] = { 839 TEGRA_PIN_UART1_RX_PR3, 840 }; 841 842 static const unsigned int uart1_rts_pr4_pins[] = { 843 TEGRA_PIN_UART1_RTS_PR4, 844 }; 845 846 static const unsigned int uart1_cts_pr5_pins[] = { 847 TEGRA_PIN_UART1_CTS_PR5, 848 }; 849 850 static const unsigned int gpu_pwr_req_px0_pins[] = { 851 TEGRA_PIN_GPU_PWR_REQ_PX0, 852 }; 853 854 static const unsigned int cv_pwr_req_px1_pins[] = { 855 TEGRA_PIN_CV_PWR_REQ_PX1, 856 }; 857 858 static const unsigned int gp_pwm2_px2_pins[] = { 859 TEGRA_PIN_GP_PWM2_PX2, 860 }; 861 862 static const unsigned int gp_pwm3_px3_pins[] = { 863 TEGRA_PIN_GP_PWM3_PX3, 864 }; 865 866 static const unsigned int uart2_tx_px4_pins[] = { 867 TEGRA_PIN_UART2_TX_PX4, 868 }; 869 870 static const unsigned int uart2_rx_px5_pins[] = { 871 TEGRA_PIN_UART2_RX_PX5, 872 }; 873 874 static const unsigned int uart2_rts_px6_pins[] = { 875 TEGRA_PIN_UART2_RTS_PX6, 876 }; 877 878 static const unsigned int uart2_cts_px7_pins[] = { 879 TEGRA_PIN_UART2_CTS_PX7, 880 }; 881 882 static const unsigned int spi3_sck_py0_pins[] = { 883 TEGRA_PIN_SPI3_SCK_PY0, 884 }; 885 886 static const unsigned int spi3_miso_py1_pins[] = { 887 TEGRA_PIN_SPI3_MISO_PY1, 888 }; 889 890 static const unsigned int spi3_mosi_py2_pins[] = { 891 TEGRA_PIN_SPI3_MOSI_PY2, 892 }; 893 894 static const unsigned int spi3_cs0_py3_pins[] = { 895 TEGRA_PIN_SPI3_CS0_PY3, 896 }; 897 898 static const unsigned int spi3_cs1_py4_pins[] = { 899 TEGRA_PIN_SPI3_CS1_PY4, 900 }; 901 902 static const unsigned int uart5_tx_py5_pins[] = { 903 TEGRA_PIN_UART5_TX_PY5, 904 }; 905 906 static const unsigned int uart5_rx_py6_pins[] = { 907 TEGRA_PIN_UART5_RX_PY6, 908 }; 909 910 static const unsigned int uart5_rts_py7_pins[] = { 911 TEGRA_PIN_UART5_RTS_PY7, 912 }; 913 914 static const unsigned int uart5_cts_pz0_pins[] = { 915 TEGRA_PIN_UART5_CTS_PZ0, 916 }; 917 918 static const unsigned int usb_vbus_en0_pz1_pins[] = { 919 TEGRA_PIN_USB_VBUS_EN0_PZ1, 920 }; 921 922 static const unsigned int usb_vbus_en1_pz2_pins[] = { 923 TEGRA_PIN_USB_VBUS_EN1_PZ2, 924 }; 925 926 static const unsigned int spi1_sck_pz3_pins[] = { 927 TEGRA_PIN_SPI1_SCK_PZ3, 928 }; 929 930 static const unsigned int spi1_miso_pz4_pins[] = { 931 TEGRA_PIN_SPI1_MISO_PZ4, 932 }; 933 934 static const unsigned int spi1_mosi_pz5_pins[] = { 935 TEGRA_PIN_SPI1_MOSI_PZ5, 936 }; 937 938 static const unsigned int spi1_cs0_pz6_pins[] = { 939 TEGRA_PIN_SPI1_CS0_PZ6, 940 }; 941 942 static const unsigned int spi1_cs1_pz7_pins[] = { 943 TEGRA_PIN_SPI1_CS1_PZ7, 944 }; 945 946 static const unsigned int can0_dout_paa0_pins[] = { 947 TEGRA_PIN_CAN0_DOUT_PAA0, 948 }; 949 950 static const unsigned int can0_din_paa1_pins[] = { 951 TEGRA_PIN_CAN0_DIN_PAA1, 952 }; 953 954 static const unsigned int can1_dout_paa2_pins[] = { 955 TEGRA_PIN_CAN1_DOUT_PAA2, 956 }; 957 958 static const unsigned int can1_din_paa3_pins[] = { 959 TEGRA_PIN_CAN1_DIN_PAA3, 960 }; 961 962 static const unsigned int can0_stb_paa4_pins[] = { 963 TEGRA_PIN_CAN0_STB_PAA4, 964 }; 965 966 static const unsigned int can0_en_paa5_pins[] = { 967 TEGRA_PIN_CAN0_EN_PAA5, 968 }; 969 970 static const unsigned int soc_gpio49_paa6_pins[] = { 971 TEGRA_PIN_SOC_GPIO49_PAA6, 972 }; 973 974 static const unsigned int can0_err_paa7_pins[] = { 975 TEGRA_PIN_CAN0_ERR_PAA7, 976 }; 977 978 static const unsigned int spi5_sck_pac0_pins[] = { 979 TEGRA_PIN_SPI5_SCK_PAC0, 980 }; 981 982 static const unsigned int spi5_miso_pac1_pins[] = { 983 TEGRA_PIN_SPI5_MISO_PAC1, 984 }; 985 986 static const unsigned int spi5_mosi_pac2_pins[] = { 987 TEGRA_PIN_SPI5_MOSI_PAC2, 988 }; 989 990 static const unsigned int spi5_cs0_pac3_pins[] = { 991 TEGRA_PIN_SPI5_CS0_PAC3, 992 }; 993 994 static const unsigned int soc_gpio57_pac4_pins[] = { 995 TEGRA_PIN_SOC_GPIO57_PAC4, 996 }; 997 998 static const unsigned int soc_gpio58_pac5_pins[] = { 999 TEGRA_PIN_SOC_GPIO58_PAC5, 1000 }; 1001 1002 static const unsigned int soc_gpio59_pac6_pins[] = { 1003 TEGRA_PIN_SOC_GPIO59_PAC6, 1004 }; 1005 1006 static const unsigned int soc_gpio60_pac7_pins[] = { 1007 TEGRA_PIN_SOC_GPIO60_PAC7, 1008 }; 1009 1010 static const unsigned int soc_gpio45_pad0_pins[] = { 1011 TEGRA_PIN_SOC_GPIO45_PAD0, 1012 }; 1013 1014 static const unsigned int soc_gpio46_pad1_pins[] = { 1015 TEGRA_PIN_SOC_GPIO46_PAD1, 1016 }; 1017 1018 static const unsigned int soc_gpio47_pad2_pins[] = { 1019 TEGRA_PIN_SOC_GPIO47_PAD2, 1020 }; 1021 1022 static const unsigned int soc_gpio48_pad3_pins[] = { 1023 TEGRA_PIN_SOC_GPIO48_PAD3, 1024 }; 1025 1026 static const unsigned int ufs0_ref_clk_pae0_pins[] = { 1027 TEGRA_PIN_UFS0_REF_CLK_PAE0, 1028 }; 1029 1030 static const unsigned int ufs0_rst_n_pae1_pins[] = { 1031 TEGRA_PIN_UFS0_RST_N_PAE1, 1032 }; 1033 1034 static const unsigned int pex_l5_clkreq_n_paf0_pins[] = { 1035 TEGRA_PIN_PEX_L5_CLKREQ_N_PAF0, 1036 }; 1037 1038 static const unsigned int pex_l5_rst_n_paf1_pins[] = { 1039 TEGRA_PIN_PEX_L5_RST_N_PAF1, 1040 }; 1041 1042 static const unsigned int pex_l6_clkreq_n_paf2_pins[] = { 1043 TEGRA_PIN_PEX_L6_CLKREQ_N_PAF2, 1044 }; 1045 1046 static const unsigned int pex_l6_rst_n_paf3_pins[] = { 1047 TEGRA_PIN_PEX_L6_RST_N_PAF3, 1048 }; 1049 1050 static const unsigned int pex_l7_clkreq_n_pag0_pins[] = { 1051 TEGRA_PIN_PEX_L7_CLKREQ_N_PAG0, 1052 }; 1053 1054 static const unsigned int pex_l7_rst_n_pag1_pins[] = { 1055 TEGRA_PIN_PEX_L7_RST_N_PAG1, 1056 }; 1057 1058 static const unsigned int pex_l8_clkreq_n_pag2_pins[] = { 1059 TEGRA_PIN_PEX_L8_CLKREQ_N_PAG2, 1060 }; 1061 1062 static const unsigned int pex_l8_rst_n_pag3_pins[] = { 1063 TEGRA_PIN_PEX_L8_RST_N_PAG3, 1064 }; 1065 1066 static const unsigned int pex_l9_clkreq_n_pag4_pins[] = { 1067 TEGRA_PIN_PEX_L9_CLKREQ_N_PAG4, 1068 }; 1069 1070 static const unsigned int pex_l9_rst_n_pag5_pins[] = { 1071 TEGRA_PIN_PEX_L9_RST_N_PAG5, 1072 }; 1073 1074 static const unsigned int pex_l10_clkreq_n_pag6_pins[] = { 1075 TEGRA_PIN_PEX_L10_CLKREQ_N_PAG6, 1076 }; 1077 1078 static const unsigned int pex_l10_rst_n_pag7_pins[] = { 1079 TEGRA_PIN_PEX_L10_RST_N_PAG7, 1080 }; 1081 1082 static const unsigned int can1_stb_pbb0_pins[] = { 1083 TEGRA_PIN_CAN1_STB_PBB0, 1084 }; 1085 1086 static const unsigned int can1_en_pbb1_pins[] = { 1087 TEGRA_PIN_CAN1_EN_PBB1, 1088 }; 1089 1090 static const unsigned int soc_gpio50_pbb2_pins[] = { 1091 TEGRA_PIN_SOC_GPIO50_PBB2, 1092 }; 1093 1094 static const unsigned int can1_err_pbb3_pins[] = { 1095 TEGRA_PIN_CAN1_ERR_PBB3, 1096 }; 1097 1098 static const unsigned int spi2_sck_pcc0_pins[] = { 1099 TEGRA_PIN_SPI2_SCK_PCC0, 1100 }; 1101 1102 static const unsigned int spi2_miso_pcc1_pins[] = { 1103 TEGRA_PIN_SPI2_MISO_PCC1, 1104 }; 1105 1106 static const unsigned int spi2_mosi_pcc2_pins[] = { 1107 TEGRA_PIN_SPI2_MOSI_PCC2, 1108 }; 1109 1110 static const unsigned int spi2_cs0_pcc3_pins[] = { 1111 TEGRA_PIN_SPI2_CS0_PCC3, 1112 }; 1113 1114 static const unsigned int touch_clk_pcc4_pins[] = { 1115 TEGRA_PIN_TOUCH_CLK_PCC4, 1116 }; 1117 1118 static const unsigned int uart3_tx_pcc5_pins[] = { 1119 TEGRA_PIN_UART3_TX_PCC5, 1120 }; 1121 1122 static const unsigned int uart3_rx_pcc6_pins[] = { 1123 TEGRA_PIN_UART3_RX_PCC6, 1124 }; 1125 1126 static const unsigned int gen2_i2c_scl_pcc7_pins[] = { 1127 TEGRA_PIN_GEN2_I2C_SCL_PCC7, 1128 }; 1129 1130 static const unsigned int gen2_i2c_sda_pdd0_pins[] = { 1131 TEGRA_PIN_GEN2_I2C_SDA_PDD0, 1132 }; 1133 1134 static const unsigned int gen8_i2c_scl_pdd1_pins[] = { 1135 TEGRA_PIN_GEN8_I2C_SCL_PDD1, 1136 }; 1137 1138 static const unsigned int gen8_i2c_sda_pdd2_pins[] = { 1139 TEGRA_PIN_GEN8_I2C_SDA_PDD2, 1140 }; 1141 1142 static const unsigned int sce_error_pee0_pins[] = { 1143 TEGRA_PIN_SCE_ERROR_PEE0, 1144 }; 1145 1146 static const unsigned int vcomp_alert_pee1_pins[] = { 1147 TEGRA_PIN_VCOMP_ALERT_PEE1, 1148 }; 1149 1150 static const unsigned int ao_retention_n_pee2_pins[] = { 1151 TEGRA_PIN_AO_RETENTION_N_PEE2, 1152 }; 1153 1154 static const unsigned int batt_oc_pee3_pins[] = { 1155 TEGRA_PIN_BATT_OC_PEE3, 1156 }; 1157 1158 static const unsigned int power_on_pee4_pins[] = { 1159 TEGRA_PIN_POWER_ON_PEE4, 1160 }; 1161 1162 static const unsigned int soc_gpio26_pee5_pins[] = { 1163 TEGRA_PIN_SOC_GPIO26_PEE5, 1164 }; 1165 1166 static const unsigned int soc_gpio27_pee6_pins[] = { 1167 TEGRA_PIN_SOC_GPIO27_PEE6, 1168 }; 1169 1170 static const unsigned int bootv_ctl_n_pee7_pins[] = { 1171 TEGRA_PIN_BOOTV_CTL_N_PEE7, 1172 }; 1173 1174 static const unsigned int hdmi_cec_pgg0_pins[] = { 1175 TEGRA_PIN_HDMI_CEC_PGG0, 1176 }; 1177 1178 static const unsigned int eqos_comp_pins[] = { 1179 TEGRA_PIN_EQOS_COMP, 1180 }; 1181 1182 static const unsigned int qspi_comp_pins[] = { 1183 TEGRA_PIN_QSPI_COMP, 1184 }; 1185 1186 static const unsigned int sdmmc1_comp_pins[] = { 1187 TEGRA_PIN_SDMMC1_COMP, 1188 }; 1189 1190 /* Define unique ID for each function */ 1191 enum tegra_mux_dt { 1192 TEGRA_MUX_GP, 1193 TEGRA_MUX_UARTC, 1194 TEGRA_MUX_I2C8, 1195 TEGRA_MUX_SPI2, 1196 TEGRA_MUX_I2C2, 1197 TEGRA_MUX_CAN1, 1198 TEGRA_MUX_CAN0, 1199 TEGRA_MUX_RSVD0, 1200 TEGRA_MUX_ETH0, 1201 TEGRA_MUX_ETH2, 1202 TEGRA_MUX_ETH1, 1203 TEGRA_MUX_DP, 1204 TEGRA_MUX_ETH3, 1205 TEGRA_MUX_I2C4, 1206 TEGRA_MUX_I2C7, 1207 TEGRA_MUX_I2C9, 1208 TEGRA_MUX_EQOS, 1209 TEGRA_MUX_PE2, 1210 TEGRA_MUX_PE1, 1211 TEGRA_MUX_PE0, 1212 TEGRA_MUX_PE3, 1213 TEGRA_MUX_PE4, 1214 TEGRA_MUX_PE5, 1215 TEGRA_MUX_PE6, 1216 TEGRA_MUX_PE10, 1217 TEGRA_MUX_PE7, 1218 TEGRA_MUX_PE8, 1219 TEGRA_MUX_PE9, 1220 TEGRA_MUX_QSPI0, 1221 TEGRA_MUX_QSPI1, 1222 TEGRA_MUX_QSPI, 1223 TEGRA_MUX_SDMMC1, 1224 TEGRA_MUX_SCE, 1225 TEGRA_MUX_SOC, 1226 TEGRA_MUX_GPIO, 1227 TEGRA_MUX_HDMI, 1228 TEGRA_MUX_UFS0, 1229 TEGRA_MUX_SPI3, 1230 TEGRA_MUX_SPI1, 1231 TEGRA_MUX_UARTB, 1232 TEGRA_MUX_UARTE, 1233 TEGRA_MUX_USB, 1234 TEGRA_MUX_EXTPERIPH2, 1235 TEGRA_MUX_EXTPERIPH1, 1236 TEGRA_MUX_I2C3, 1237 TEGRA_MUX_VI0, 1238 TEGRA_MUX_I2C5, 1239 TEGRA_MUX_UARTA, 1240 TEGRA_MUX_UARTD, 1241 TEGRA_MUX_I2C1, 1242 TEGRA_MUX_I2S4, 1243 TEGRA_MUX_I2S6, 1244 TEGRA_MUX_AUD, 1245 TEGRA_MUX_SPI5, 1246 TEGRA_MUX_TOUCH, 1247 TEGRA_MUX_UARTJ, 1248 TEGRA_MUX_RSVD1, 1249 TEGRA_MUX_WDT, 1250 TEGRA_MUX_TSC, 1251 TEGRA_MUX_DMIC3, 1252 TEGRA_MUX_LED, 1253 TEGRA_MUX_VI0_ALT, 1254 TEGRA_MUX_I2S5, 1255 TEGRA_MUX_NV, 1256 TEGRA_MUX_EXTPERIPH3, 1257 TEGRA_MUX_EXTPERIPH4, 1258 TEGRA_MUX_SPI4, 1259 TEGRA_MUX_CCLA, 1260 TEGRA_MUX_I2S2, 1261 TEGRA_MUX_I2S1, 1262 TEGRA_MUX_I2S8, 1263 TEGRA_MUX_I2S3, 1264 TEGRA_MUX_RSVD2, 1265 TEGRA_MUX_DMIC5, 1266 TEGRA_MUX_DCA, 1267 TEGRA_MUX_DISPLAYB, 1268 TEGRA_MUX_DISPLAYA, 1269 TEGRA_MUX_VI1, 1270 TEGRA_MUX_DCB, 1271 TEGRA_MUX_DMIC1, 1272 TEGRA_MUX_DMIC4, 1273 TEGRA_MUX_I2S7, 1274 TEGRA_MUX_DMIC2, 1275 TEGRA_MUX_DSPK0, 1276 TEGRA_MUX_RSVD3, 1277 TEGRA_MUX_TSC_ALT, 1278 TEGRA_MUX_ISTCTRL, 1279 TEGRA_MUX_VI1_ALT, 1280 TEGRA_MUX_DSPK1, 1281 TEGRA_MUX_IGPU, 1282 }; 1283 1284 /* Make list of each function name */ 1285 #define TEGRA_PIN_FUNCTION(lid) #lid 1286 1287 static const char * const tegra234_functions[] = { 1288 TEGRA_PIN_FUNCTION(gp), 1289 TEGRA_PIN_FUNCTION(uartc), 1290 TEGRA_PIN_FUNCTION(i2c8), 1291 TEGRA_PIN_FUNCTION(spi2), 1292 TEGRA_PIN_FUNCTION(i2c2), 1293 TEGRA_PIN_FUNCTION(can1), 1294 TEGRA_PIN_FUNCTION(can0), 1295 TEGRA_PIN_FUNCTION(rsvd0), 1296 TEGRA_PIN_FUNCTION(eth0), 1297 TEGRA_PIN_FUNCTION(eth2), 1298 TEGRA_PIN_FUNCTION(eth1), 1299 TEGRA_PIN_FUNCTION(dp), 1300 TEGRA_PIN_FUNCTION(eth3), 1301 TEGRA_PIN_FUNCTION(i2c4), 1302 TEGRA_PIN_FUNCTION(i2c7), 1303 TEGRA_PIN_FUNCTION(i2c9), 1304 TEGRA_PIN_FUNCTION(eqos), 1305 TEGRA_PIN_FUNCTION(pe2), 1306 TEGRA_PIN_FUNCTION(pe1), 1307 TEGRA_PIN_FUNCTION(pe0), 1308 TEGRA_PIN_FUNCTION(pe3), 1309 TEGRA_PIN_FUNCTION(pe4), 1310 TEGRA_PIN_FUNCTION(pe5), 1311 TEGRA_PIN_FUNCTION(pe6), 1312 TEGRA_PIN_FUNCTION(pe10), 1313 TEGRA_PIN_FUNCTION(pe7), 1314 TEGRA_PIN_FUNCTION(pe8), 1315 TEGRA_PIN_FUNCTION(pe9), 1316 TEGRA_PIN_FUNCTION(qspi0), 1317 TEGRA_PIN_FUNCTION(qspi1), 1318 TEGRA_PIN_FUNCTION(qspi), 1319 TEGRA_PIN_FUNCTION(sdmmc1), 1320 TEGRA_PIN_FUNCTION(sce), 1321 TEGRA_PIN_FUNCTION(soc), 1322 TEGRA_PIN_FUNCTION(gpio), 1323 TEGRA_PIN_FUNCTION(hdmi), 1324 TEGRA_PIN_FUNCTION(ufs0), 1325 TEGRA_PIN_FUNCTION(spi3), 1326 TEGRA_PIN_FUNCTION(spi1), 1327 TEGRA_PIN_FUNCTION(uartb), 1328 TEGRA_PIN_FUNCTION(uarte), 1329 TEGRA_PIN_FUNCTION(usb), 1330 TEGRA_PIN_FUNCTION(extperiph2), 1331 TEGRA_PIN_FUNCTION(extperiph1), 1332 TEGRA_PIN_FUNCTION(i2c3), 1333 TEGRA_PIN_FUNCTION(vi0), 1334 TEGRA_PIN_FUNCTION(i2c5), 1335 TEGRA_PIN_FUNCTION(uarta), 1336 TEGRA_PIN_FUNCTION(uartd), 1337 TEGRA_PIN_FUNCTION(i2c1), 1338 TEGRA_PIN_FUNCTION(i2s4), 1339 TEGRA_PIN_FUNCTION(i2s6), 1340 TEGRA_PIN_FUNCTION(aud), 1341 TEGRA_PIN_FUNCTION(spi5), 1342 TEGRA_PIN_FUNCTION(touch), 1343 TEGRA_PIN_FUNCTION(uartj), 1344 TEGRA_PIN_FUNCTION(rsvd1), 1345 TEGRA_PIN_FUNCTION(wdt), 1346 TEGRA_PIN_FUNCTION(tsc), 1347 TEGRA_PIN_FUNCTION(dmic3), 1348 TEGRA_PIN_FUNCTION(led), 1349 TEGRA_PIN_FUNCTION(vi0_alt), 1350 TEGRA_PIN_FUNCTION(i2s5), 1351 TEGRA_PIN_FUNCTION(nv), 1352 TEGRA_PIN_FUNCTION(extperiph3), 1353 TEGRA_PIN_FUNCTION(extperiph4), 1354 TEGRA_PIN_FUNCTION(spi4), 1355 TEGRA_PIN_FUNCTION(ccla), 1356 TEGRA_PIN_FUNCTION(i2s2), 1357 TEGRA_PIN_FUNCTION(i2s1), 1358 TEGRA_PIN_FUNCTION(i2s8), 1359 TEGRA_PIN_FUNCTION(i2s3), 1360 TEGRA_PIN_FUNCTION(rsvd2), 1361 TEGRA_PIN_FUNCTION(dmic5), 1362 TEGRA_PIN_FUNCTION(dca), 1363 TEGRA_PIN_FUNCTION(displayb), 1364 TEGRA_PIN_FUNCTION(displaya), 1365 TEGRA_PIN_FUNCTION(vi1), 1366 TEGRA_PIN_FUNCTION(dcb), 1367 TEGRA_PIN_FUNCTION(dmic1), 1368 TEGRA_PIN_FUNCTION(dmic4), 1369 TEGRA_PIN_FUNCTION(i2s7), 1370 TEGRA_PIN_FUNCTION(dmic2), 1371 TEGRA_PIN_FUNCTION(dspk0), 1372 TEGRA_PIN_FUNCTION(rsvd3), 1373 TEGRA_PIN_FUNCTION(tsc_alt), 1374 TEGRA_PIN_FUNCTION(istctrl), 1375 TEGRA_PIN_FUNCTION(vi1_alt), 1376 TEGRA_PIN_FUNCTION(dspk1), 1377 TEGRA_PIN_FUNCTION(igpu), 1378 }; 1379 1380 #define PINGROUP_REG_Y(r) ((r)) 1381 #define PINGROUP_REG_N(r) -1 1382 1383 #define DRV_PINGROUP_Y(r) ((r)) 1384 #define DRV_PINGROUP_N(r) -1 1385 1386 #define DRV_PINGROUP_ENTRY_N(pg_name) \ 1387 .drv_reg = -1, \ 1388 .drv_bank = -1, \ 1389 .drvdn_bit = -1, \ 1390 .drvup_bit = -1, \ 1391 .slwr_bit = -1, \ 1392 .slwf_bit = -1 1393 1394 #define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \ 1395 drvup_w, slwr_b, slwr_w, slwf_b, \ 1396 slwf_w, bank) \ 1397 .drv_reg = DRV_PINGROUP_Y(r), \ 1398 .drv_bank = bank, \ 1399 .drvdn_bit = drvdn_b, \ 1400 .drvdn_width = drvdn_w, \ 1401 .drvup_bit = drvup_b, \ 1402 .drvup_width = drvup_w, \ 1403 .slwr_bit = slwr_b, \ 1404 .slwr_width = slwr_w, \ 1405 .slwf_bit = slwf_b, \ 1406 .slwf_width = slwf_w 1407 1408 #define PIN_PINGROUP_ENTRY_N(pg_name) \ 1409 .mux_reg = -1, \ 1410 .pupd_reg = -1, \ 1411 .tri_reg = -1, \ 1412 .einput_bit = -1, \ 1413 .e_io_hv_bit = -1, \ 1414 .odrain_bit = -1, \ 1415 .lock_bit = -1, \ 1416 .parked_bit = -1, \ 1417 .lpmd_bit = -1, \ 1418 .drvtype_bit = -1, \ 1419 .lpdr_bit = -1, \ 1420 .pbias_buf_bit = -1, \ 1421 .preemp_bit = -1, \ 1422 .rfu_in_bit = -1 1423 1424 #define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input, \ 1425 e_lpdr, e_pbias_buf, gpio_sfio_sel, \ 1426 schmitt_b) \ 1427 .mux_reg = PINGROUP_REG_Y(r), \ 1428 .lpmd_bit = -1, \ 1429 .lock_bit = -1, \ 1430 .hsm_bit = -1, \ 1431 .mux_bank = bank, \ 1432 .mux_bit = 0, \ 1433 .pupd_reg = PINGROUP_REG_##pupd(r), \ 1434 .pupd_bank = bank, \ 1435 .pupd_bit = 2, \ 1436 .tri_reg = PINGROUP_REG_Y(r), \ 1437 .tri_bank = bank, \ 1438 .tri_bit = 4, \ 1439 .einput_bit = e_input, \ 1440 .sfsel_bit = gpio_sfio_sel, \ 1441 .schmitt_bit = schmitt_b, \ 1442 .drvtype_bit = 13, \ 1443 .lpdr_bit = e_lpdr, \ 1444 1445 /* main drive pin groups */ 1446 #define drive_soc_gpio08_pb0 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1447 #define drive_soc_gpio36_pm5 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1448 #define drive_soc_gpio53_pm6 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1449 #define drive_soc_gpio55_pm4 DRV_PINGROUP_ENTRY_Y(0x10014, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1450 #define drive_soc_gpio38_pm7 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1451 #define drive_soc_gpio39_pn1 DRV_PINGROUP_ENTRY_Y(0x10024, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1452 #define drive_soc_gpio40_pn2 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1453 #define drive_dp_aux_ch0_hpd_pm0 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1454 #define drive_dp_aux_ch1_hpd_pm1 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1455 #define drive_dp_aux_ch2_hpd_pm2 DRV_PINGROUP_ENTRY_Y(0x10044, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1456 #define drive_dp_aux_ch3_hpd_pm3 DRV_PINGROUP_ENTRY_Y(0x1004c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1457 #define drive_dp_aux_ch1_p_pn3 DRV_PINGROUP_ENTRY_Y(0x10054, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1458 #define drive_dp_aux_ch1_n_pn4 DRV_PINGROUP_ENTRY_Y(0x1005c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1459 #define drive_dp_aux_ch2_p_pn5 DRV_PINGROUP_ENTRY_Y(0x10064, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1460 #define drive_dp_aux_ch2_n_pn6 DRV_PINGROUP_ENTRY_Y(0x1006c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1461 #define drive_dp_aux_ch3_p_pn7 DRV_PINGROUP_ENTRY_Y(0x10074, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1462 #define drive_dp_aux_ch3_n_pn0 DRV_PINGROUP_ENTRY_Y(0x1007c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1463 #define drive_pex_l2_clkreq_n_pk4 DRV_PINGROUP_ENTRY_Y(0x7004, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1464 #define drive_pex_wake_n_pl2 DRV_PINGROUP_ENTRY_Y(0x700c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1465 #define drive_pex_l1_clkreq_n_pk2 DRV_PINGROUP_ENTRY_Y(0x7014, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1466 #define drive_pex_l1_rst_n_pk3 DRV_PINGROUP_ENTRY_Y(0x701c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1467 #define drive_pex_l0_clkreq_n_pk0 DRV_PINGROUP_ENTRY_Y(0x7024, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1468 #define drive_pex_l0_rst_n_pk1 DRV_PINGROUP_ENTRY_Y(0x702c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1469 #define drive_pex_l2_rst_n_pk5 DRV_PINGROUP_ENTRY_Y(0x7034, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1470 #define drive_pex_l3_clkreq_n_pk6 DRV_PINGROUP_ENTRY_Y(0x703c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1471 #define drive_pex_l3_rst_n_pk7 DRV_PINGROUP_ENTRY_Y(0x7044, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1472 #define drive_pex_l4_clkreq_n_pl0 DRV_PINGROUP_ENTRY_Y(0x704c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1473 #define drive_pex_l4_rst_n_pl1 DRV_PINGROUP_ENTRY_Y(0x7054, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1474 #define drive_soc_gpio34_pl3 DRV_PINGROUP_ENTRY_Y(0x705c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1475 #define drive_pex_l5_clkreq_n_paf0 DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1476 #define drive_pex_l5_rst_n_paf1 DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1477 #define drive_pex_l6_clkreq_n_paf2 DRV_PINGROUP_ENTRY_Y(0x14014, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1478 #define drive_pex_l6_rst_n_paf3 DRV_PINGROUP_ENTRY_Y(0x1401c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1479 #define drive_pex_l10_clkreq_n_pag6 DRV_PINGROUP_ENTRY_Y(0x19004, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1480 #define drive_pex_l10_rst_n_pag7 DRV_PINGROUP_ENTRY_Y(0x1900c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1481 #define drive_pex_l7_clkreq_n_pag0 DRV_PINGROUP_ENTRY_Y(0x19014, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1482 #define drive_pex_l7_rst_n_pag1 DRV_PINGROUP_ENTRY_Y(0x1901c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1483 #define drive_pex_l8_clkreq_n_pag2 DRV_PINGROUP_ENTRY_Y(0x19024, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1484 #define drive_pex_l8_rst_n_pag3 DRV_PINGROUP_ENTRY_Y(0x1902c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1485 #define drive_pex_l9_clkreq_n_pag4 DRV_PINGROUP_ENTRY_Y(0x19034, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1486 #define drive_pex_l9_rst_n_pag5 DRV_PINGROUP_ENTRY_Y(0x1903c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1487 #define drive_sdmmc1_clk_pj0 DRV_PINGROUP_ENTRY_Y(0x8004, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1488 #define drive_sdmmc1_cmd_pj1 DRV_PINGROUP_ENTRY_Y(0x800c, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1489 #define drive_sdmmc1_dat3_pj5 DRV_PINGROUP_ENTRY_Y(0x801c, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1490 #define drive_sdmmc1_dat2_pj4 DRV_PINGROUP_ENTRY_Y(0x8024, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1491 #define drive_sdmmc1_dat1_pj3 DRV_PINGROUP_ENTRY_Y(0x802c, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1492 #define drive_sdmmc1_dat0_pj2 DRV_PINGROUP_ENTRY_Y(0x8034, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1493 #define drive_ufs0_rst_n_pae1 DRV_PINGROUP_ENTRY_Y(0x11004, 12, 5, 24, 5, -1, -1, -1, -1, 0) 1494 #define drive_ufs0_ref_clk_pae0 DRV_PINGROUP_ENTRY_Y(0x1100c, 12, 5, 24, 5, -1, -1, -1, -1, 0) 1495 #define drive_spi3_miso_py1 DRV_PINGROUP_ENTRY_Y(0xd004, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1496 #define drive_spi1_cs0_pz6 DRV_PINGROUP_ENTRY_Y(0xd00c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1497 #define drive_spi3_cs0_py3 DRV_PINGROUP_ENTRY_Y(0xd014, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1498 #define drive_spi1_miso_pz4 DRV_PINGROUP_ENTRY_Y(0xd01c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1499 #define drive_spi3_cs1_py4 DRV_PINGROUP_ENTRY_Y(0xd024, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1500 #define drive_spi1_sck_pz3 DRV_PINGROUP_ENTRY_Y(0xd02c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1501 #define drive_spi3_sck_py0 DRV_PINGROUP_ENTRY_Y(0xd034, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1502 #define drive_spi1_cs1_pz7 DRV_PINGROUP_ENTRY_Y(0xd03c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1503 #define drive_spi1_mosi_pz5 DRV_PINGROUP_ENTRY_Y(0xd044, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1504 #define drive_spi3_mosi_py2 DRV_PINGROUP_ENTRY_Y(0xd04c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1505 #define drive_uart2_tx_px4 DRV_PINGROUP_ENTRY_Y(0xd054, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1506 #define drive_uart2_rx_px5 DRV_PINGROUP_ENTRY_Y(0xd05c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1507 #define drive_uart2_rts_px6 DRV_PINGROUP_ENTRY_Y(0xd064, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1508 #define drive_uart2_cts_px7 DRV_PINGROUP_ENTRY_Y(0xd06c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1509 #define drive_uart5_tx_py5 DRV_PINGROUP_ENTRY_Y(0xd074, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1510 #define drive_uart5_rx_py6 DRV_PINGROUP_ENTRY_Y(0xd07c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1511 #define drive_uart5_rts_py7 DRV_PINGROUP_ENTRY_Y(0xd084, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1512 #define drive_uart5_cts_pz0 DRV_PINGROUP_ENTRY_Y(0xd08c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1513 #define drive_gpu_pwr_req_px0 DRV_PINGROUP_ENTRY_Y(0xd094, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1514 #define drive_gp_pwm3_px3 DRV_PINGROUP_ENTRY_Y(0xd09c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1515 #define drive_gp_pwm2_px2 DRV_PINGROUP_ENTRY_Y(0xd0a4, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1516 #define drive_cv_pwr_req_px1 DRV_PINGROUP_ENTRY_Y(0xd0ac, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1517 #define drive_usb_vbus_en0_pz1 DRV_PINGROUP_ENTRY_Y(0xd0b4, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1518 #define drive_usb_vbus_en1_pz2 DRV_PINGROUP_ENTRY_Y(0xd0bc, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1519 #define drive_extperiph2_clk_pp1 DRV_PINGROUP_ENTRY_Y(0x0004, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1520 #define drive_extperiph1_clk_pp0 DRV_PINGROUP_ENTRY_Y(0x000c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1521 #define drive_cam_i2c_sda_pp3 DRV_PINGROUP_ENTRY_Y(0x0014, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1522 #define drive_cam_i2c_scl_pp2 DRV_PINGROUP_ENTRY_Y(0x001c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1523 #define drive_soc_gpio23_pp4 DRV_PINGROUP_ENTRY_Y(0x0024, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1524 #define drive_soc_gpio24_pp5 DRV_PINGROUP_ENTRY_Y(0x002c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1525 #define drive_soc_gpio25_pp6 DRV_PINGROUP_ENTRY_Y(0x0034, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1526 #define drive_pwr_i2c_scl_pp7 DRV_PINGROUP_ENTRY_Y(0x003c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1527 #define drive_pwr_i2c_sda_pq0 DRV_PINGROUP_ENTRY_Y(0x0044, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1528 #define drive_soc_gpio28_pq1 DRV_PINGROUP_ENTRY_Y(0x004c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1529 #define drive_soc_gpio29_pq2 DRV_PINGROUP_ENTRY_Y(0x0054, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1530 #define drive_soc_gpio30_pq3 DRV_PINGROUP_ENTRY_Y(0x005c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1531 #define drive_soc_gpio31_pq4 DRV_PINGROUP_ENTRY_Y(0x0064, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1532 #define drive_soc_gpio32_pq5 DRV_PINGROUP_ENTRY_Y(0x006c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1533 #define drive_soc_gpio33_pq6 DRV_PINGROUP_ENTRY_Y(0x0074, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1534 #define drive_soc_gpio35_pq7 DRV_PINGROUP_ENTRY_Y(0x007c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1535 #define drive_soc_gpio37_pr0 DRV_PINGROUP_ENTRY_Y(0x0084, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1536 #define drive_soc_gpio56_pr1 DRV_PINGROUP_ENTRY_Y(0x008c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1537 #define drive_uart1_cts_pr5 DRV_PINGROUP_ENTRY_Y(0x0094, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1538 #define drive_uart1_rts_pr4 DRV_PINGROUP_ENTRY_Y(0x009c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1539 #define drive_uart1_rx_pr3 DRV_PINGROUP_ENTRY_Y(0x00a4, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1540 #define drive_uart1_tx_pr2 DRV_PINGROUP_ENTRY_Y(0x00ac, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1541 #define drive_cpu_pwr_req_pi5 DRV_PINGROUP_ENTRY_Y(0x4004, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1542 #define drive_uart4_cts_ph6 DRV_PINGROUP_ENTRY_Y(0x400c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1543 #define drive_uart4_rts_ph5 DRV_PINGROUP_ENTRY_Y(0x4014, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1544 #define drive_uart4_rx_ph4 DRV_PINGROUP_ENTRY_Y(0x401c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1545 #define drive_uart4_tx_ph3 DRV_PINGROUP_ENTRY_Y(0x4024, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1546 #define drive_gen1_i2c_scl_pi3 DRV_PINGROUP_ENTRY_Y(0x402c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1547 #define drive_gen1_i2c_sda_pi4 DRV_PINGROUP_ENTRY_Y(0x4034, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1548 #define drive_soc_gpio20_pg7 DRV_PINGROUP_ENTRY_Y(0x403c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1549 #define drive_soc_gpio21_ph0 DRV_PINGROUP_ENTRY_Y(0x4044, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1550 #define drive_soc_gpio22_ph1 DRV_PINGROUP_ENTRY_Y(0x404c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1551 #define drive_soc_gpio13_pg0 DRV_PINGROUP_ENTRY_Y(0x4054, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1552 #define drive_soc_gpio14_pg1 DRV_PINGROUP_ENTRY_Y(0x405c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1553 #define drive_soc_gpio15_pg2 DRV_PINGROUP_ENTRY_Y(0x4064, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1554 #define drive_soc_gpio16_pg3 DRV_PINGROUP_ENTRY_Y(0x406c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1555 #define drive_soc_gpio17_pg4 DRV_PINGROUP_ENTRY_Y(0x4074, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1556 #define drive_soc_gpio18_pg5 DRV_PINGROUP_ENTRY_Y(0x407c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1557 #define drive_soc_gpio19_pg6 DRV_PINGROUP_ENTRY_Y(0x4084, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1558 #define drive_soc_gpio41_ph7 DRV_PINGROUP_ENTRY_Y(0x408c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1559 #define drive_soc_gpio42_pi0 DRV_PINGROUP_ENTRY_Y(0x4094, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1560 #define drive_soc_gpio43_pi1 DRV_PINGROUP_ENTRY_Y(0x409c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1561 #define drive_soc_gpio44_pi2 DRV_PINGROUP_ENTRY_Y(0x40a4, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1562 #define drive_soc_gpio06_ph2 DRV_PINGROUP_ENTRY_Y(0x40ac, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1563 #define drive_soc_gpio07_pi6 DRV_PINGROUP_ENTRY_Y(0x40b4, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1564 #define drive_dap4_sclk_pa4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1565 #define drive_dap4_dout_pa5 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1566 #define drive_dap4_din_pa6 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1567 #define drive_dap4_fs_pa7 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1568 #define drive_dap6_sclk_pa0 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1569 #define drive_dap6_dout_pa1 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1570 #define drive_dap6_din_pa2 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1571 #define drive_dap6_fs_pa3 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1572 #define drive_soc_gpio45_pad0 DRV_PINGROUP_ENTRY_Y(0x18004, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1573 #define drive_soc_gpio46_pad1 DRV_PINGROUP_ENTRY_Y(0x1800c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1574 #define drive_soc_gpio47_pad2 DRV_PINGROUP_ENTRY_Y(0x18014, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1575 #define drive_soc_gpio48_pad3 DRV_PINGROUP_ENTRY_Y(0x1801c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1576 #define drive_soc_gpio57_pac4 DRV_PINGROUP_ENTRY_Y(0x18024, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1577 #define drive_soc_gpio58_pac5 DRV_PINGROUP_ENTRY_Y(0x1802c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1578 #define drive_soc_gpio59_pac6 DRV_PINGROUP_ENTRY_Y(0x18034, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1579 #define drive_soc_gpio60_pac7 DRV_PINGROUP_ENTRY_Y(0x1803c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1580 #define drive_spi5_cs0_pac3 DRV_PINGROUP_ENTRY_Y(0x18044, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1581 #define drive_spi5_miso_pac1 DRV_PINGROUP_ENTRY_Y(0x1804c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1582 #define drive_spi5_mosi_pac2 DRV_PINGROUP_ENTRY_Y(0x18054, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1583 #define drive_spi5_sck_pac0 DRV_PINGROUP_ENTRY_Y(0x1805c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1584 #define drive_eqos_td3_pe4 DRV_PINGROUP_ENTRY_N(no_entry) 1585 #define drive_eqos_td2_pe3 DRV_PINGROUP_ENTRY_N(no_entry) 1586 #define drive_eqos_td1_pe2 DRV_PINGROUP_ENTRY_N(no_entry) 1587 #define drive_eqos_td0_pe1 DRV_PINGROUP_ENTRY_N(no_entry) 1588 #define drive_eqos_rd3_pf1 DRV_PINGROUP_ENTRY_N(no_entry) 1589 #define drive_eqos_rd2_pf0 DRV_PINGROUP_ENTRY_N(no_entry) 1590 #define drive_eqos_rd1_pe7 DRV_PINGROUP_ENTRY_N(no_entry) 1591 #define drive_eqos_sma_mdio_pf4 DRV_PINGROUP_ENTRY_N(no_entry) 1592 #define drive_eqos_rd0_pe6 DRV_PINGROUP_ENTRY_N(no_entry) 1593 #define drive_eqos_sma_mdc_pf5 DRV_PINGROUP_ENTRY_N(no_entry) 1594 #define drive_eqos_comp DRV_PINGROUP_ENTRY_N(no_entry) 1595 #define drive_eqos_txc_pe0 DRV_PINGROUP_ENTRY_N(no_entry) 1596 #define drive_eqos_rxc_pf3 DRV_PINGROUP_ENTRY_N(no_entry) 1597 #define drive_eqos_tx_ctl_pe5 DRV_PINGROUP_ENTRY_N(no_entry) 1598 #define drive_eqos_rx_ctl_pf2 DRV_PINGROUP_ENTRY_N(no_entry) 1599 #define drive_qspi0_io3_pc5 DRV_PINGROUP_ENTRY_N(no_entry) 1600 #define drive_qspi0_io2_pc4 DRV_PINGROUP_ENTRY_N(no_entry) 1601 #define drive_qspi0_io1_pc3 DRV_PINGROUP_ENTRY_N(no_entry) 1602 #define drive_qspi0_io0_pc2 DRV_PINGROUP_ENTRY_N(no_entry) 1603 #define drive_qspi0_sck_pc0 DRV_PINGROUP_ENTRY_N(no_entry) 1604 #define drive_qspi0_cs_n_pc1 DRV_PINGROUP_ENTRY_N(no_entry) 1605 #define drive_qspi1_io3_pd3 DRV_PINGROUP_ENTRY_N(no_entry) 1606 #define drive_qspi1_io2_pd2 DRV_PINGROUP_ENTRY_N(no_entry) 1607 #define drive_qspi1_io1_pd1 DRV_PINGROUP_ENTRY_N(no_entry) 1608 #define drive_qspi1_io0_pd0 DRV_PINGROUP_ENTRY_N(no_entry) 1609 #define drive_qspi1_sck_pc6 DRV_PINGROUP_ENTRY_N(no_entry) 1610 #define drive_qspi1_cs_n_pc7 DRV_PINGROUP_ENTRY_N(no_entry) 1611 #define drive_qspi_comp DRV_PINGROUP_ENTRY_N(no_entry) 1612 #define drive_sdmmc1_comp DRV_PINGROUP_ENTRY_N(no_entry) 1613 1614 #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \ 1615 gpio_sfio_sel, schmitt_b) \ 1616 { \ 1617 .name = #pg_name, \ 1618 .pins = pg_name##_pins, \ 1619 .npins = ARRAY_SIZE(pg_name##_pins), \ 1620 .funcs = { \ 1621 TEGRA_MUX_##f0, \ 1622 TEGRA_MUX_##f1, \ 1623 TEGRA_MUX_##f2, \ 1624 TEGRA_MUX_##f3, \ 1625 }, \ 1626 PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \ 1627 e_input, e_lpdr, e_pbias_buf, \ 1628 gpio_sfio_sel, schmitt_b) \ 1629 drive_##pg_name, \ 1630 } 1631 1632 static const struct tegra_pingroup tegra234_groups[] = { 1633 PINGROUP(soc_gpio08_pb0, RSVD0, RSVD1, RSVD2, RSVD3, 0x5008, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1634 PINGROUP(soc_gpio36_pm5, ETH0, RSVD1, DCA, RSVD3, 0x10000, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1635 PINGROUP(soc_gpio53_pm6, ETH0, RSVD1, DCA, RSVD3, 0x10008, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1636 PINGROUP(soc_gpio55_pm4, ETH2, RSVD1, RSVD2, RSVD3, 0x10010, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1637 PINGROUP(soc_gpio38_pm7, ETH1, RSVD1, RSVD2, RSVD3, 0x10018, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1638 PINGROUP(soc_gpio39_pn1, GP, RSVD1, RSVD2, RSVD3, 0x10020, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1639 PINGROUP(soc_gpio40_pn2, ETH1, RSVD1, RSVD2, RSVD3, 0x10028, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1640 PINGROUP(dp_aux_ch0_hpd_pm0, DP, RSVD1, RSVD2, RSVD3, 0x10030, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1641 PINGROUP(dp_aux_ch1_hpd_pm1, ETH3, RSVD1, RSVD2, RSVD3, 0x10038, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1642 PINGROUP(dp_aux_ch2_hpd_pm2, ETH3, RSVD1, DISPLAYB, RSVD3, 0x10040, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1643 PINGROUP(dp_aux_ch3_hpd_pm3, ETH2, RSVD1, DISPLAYA, RSVD3, 0x10048, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1644 PINGROUP(dp_aux_ch1_p_pn3, I2C4, RSVD1, RSVD2, RSVD3, 0x10050, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1645 PINGROUP(dp_aux_ch1_n_pn4, I2C4, RSVD1, RSVD2, RSVD3, 0x10058, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1646 PINGROUP(dp_aux_ch2_p_pn5, I2C7, RSVD1, RSVD2, RSVD3, 0x10060, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1647 PINGROUP(dp_aux_ch2_n_pn6, I2C7, RSVD1, RSVD2, RSVD3, 0x10068, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1648 PINGROUP(dp_aux_ch3_p_pn7, I2C9, RSVD1, RSVD2, RSVD3, 0x10070, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1649 PINGROUP(dp_aux_ch3_n_pn0, I2C9, RSVD1, RSVD2, RSVD3, 0x10078, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1650 PINGROUP(eqos_td3_pe4, EQOS, RSVD1, RSVD2, RSVD3, 0x15000, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1651 PINGROUP(eqos_td2_pe3, EQOS, RSVD1, RSVD2, RSVD3, 0x15008, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1652 PINGROUP(eqos_td1_pe2, EQOS, RSVD1, RSVD2, RSVD3, 0x15010, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1653 PINGROUP(eqos_td0_pe1, EQOS, RSVD1, RSVD2, RSVD3, 0x15018, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1654 PINGROUP(eqos_rd3_pf1, EQOS, RSVD1, RSVD2, RSVD3, 0x15020, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1655 PINGROUP(eqos_rd2_pf0, EQOS, RSVD1, RSVD2, RSVD3, 0x15028, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1656 PINGROUP(eqos_rd1_pe7, EQOS, RSVD1, RSVD2, RSVD3, 0x15030, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1657 PINGROUP(eqos_sma_mdio_pf4, EQOS, RSVD1, RSVD2, RSVD3, 0x15038, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1658 PINGROUP(eqos_rd0_pe6, EQOS, RSVD1, RSVD2, RSVD3, 0x15040, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1659 PINGROUP(eqos_sma_mdc_pf5, EQOS, RSVD1, RSVD2, RSVD3, 0x15048, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1660 PINGROUP(eqos_comp, EQOS, RSVD1, RSVD2, RSVD3, 0x15050, 0, N, -1, -1, -1, -1, -1, -1, -1), 1661 PINGROUP(eqos_txc_pe0, EQOS, RSVD1, RSVD2, RSVD3, 0x15058, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1662 PINGROUP(eqos_rxc_pf3, EQOS, RSVD1, RSVD2, RSVD3, 0x15060, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1663 PINGROUP(eqos_tx_ctl_pe5, EQOS, RSVD1, RSVD2, RSVD3, 0x15068, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1664 PINGROUP(eqos_rx_ctl_pf2, EQOS, RSVD1, RSVD2, RSVD3, 0x15070, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1665 PINGROUP(pex_l2_clkreq_n_pk4, PE2, RSVD1, RSVD2, RSVD3, 0x7000, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1666 PINGROUP(pex_wake_n_pl2, RSVD0, RSVD1, RSVD2, RSVD3, 0x7008, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1667 PINGROUP(pex_l1_clkreq_n_pk2, PE1, RSVD1, RSVD2, RSVD3, 0x7010, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1668 PINGROUP(pex_l1_rst_n_pk3, PE1, RSVD1, RSVD2, RSVD3, 0x7018, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1669 PINGROUP(pex_l0_clkreq_n_pk0, PE0, RSVD1, RSVD2, RSVD3, 0x7020, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1670 PINGROUP(pex_l0_rst_n_pk1, PE0, RSVD1, RSVD2, RSVD3, 0x7028, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1671 PINGROUP(pex_l2_rst_n_pk5, PE2, RSVD1, RSVD2, RSVD3, 0x7030, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1672 PINGROUP(pex_l3_clkreq_n_pk6, PE3, RSVD1, RSVD2, RSVD3, 0x7038, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1673 PINGROUP(pex_l3_rst_n_pk7, PE3, RSVD1, RSVD2, RSVD3, 0x7040, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1674 PINGROUP(pex_l4_clkreq_n_pl0, PE4, RSVD1, RSVD2, RSVD3, 0x7048, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1675 PINGROUP(pex_l4_rst_n_pl1, PE4, RSVD1, RSVD2, RSVD3, 0x7050, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1676 PINGROUP(soc_gpio34_pl3, RSVD0, RSVD1, RSVD2, RSVD3, 0x7058, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1677 PINGROUP(pex_l5_clkreq_n_paf0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1678 PINGROUP(pex_l5_rst_n_paf1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1679 PINGROUP(pex_l6_clkreq_n_paf2, PE6, RSVD1, RSVD2, RSVD3, 0x14010, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1680 PINGROUP(pex_l6_rst_n_paf3, PE6, RSVD1, RSVD2, RSVD3, 0x14018, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1681 PINGROUP(pex_l10_clkreq_n_pag6, PE10, RSVD1, RSVD2, RSVD3, 0x19000, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1682 PINGROUP(pex_l10_rst_n_pag7, PE10, RSVD1, RSVD2, RSVD3, 0x19008, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1683 PINGROUP(pex_l7_clkreq_n_pag0, PE7, RSVD1, RSVD2, RSVD3, 0x19010, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1684 PINGROUP(pex_l7_rst_n_pag1, PE7, RSVD1, RSVD2, RSVD3, 0x19018, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1685 PINGROUP(pex_l8_clkreq_n_pag2, PE8, RSVD1, RSVD2, RSVD3, 0x19020, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1686 PINGROUP(pex_l8_rst_n_pag3, PE8, RSVD1, RSVD2, RSVD3, 0x19028, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1687 PINGROUP(pex_l9_clkreq_n_pag4, PE9, RSVD1, RSVD2, RSVD3, 0x19030, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1688 PINGROUP(pex_l9_rst_n_pag5, PE9, RSVD1, RSVD2, RSVD3, 0x19038, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1689 PINGROUP(qspi0_io3_pc5, QSPI0, RSVD1, RSVD2, RSVD3, 0xB000, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1690 PINGROUP(qspi0_io2_pc4, QSPI0, RSVD1, RSVD2, RSVD3, 0xB008, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1691 PINGROUP(qspi0_io1_pc3, QSPI0, RSVD1, RSVD2, RSVD3, 0xB010, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1692 PINGROUP(qspi0_io0_pc2, QSPI0, RSVD1, RSVD2, RSVD3, 0xB018, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1693 PINGROUP(qspi0_sck_pc0, QSPI0, RSVD1, RSVD2, RSVD3, 0xB020, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1694 PINGROUP(qspi0_cs_n_pc1, QSPI0, RSVD1, RSVD2, RSVD3, 0xB028, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1695 PINGROUP(qspi1_io3_pd3, QSPI1, RSVD1, RSVD2, RSVD3, 0xB030, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1696 PINGROUP(qspi1_io2_pd2, QSPI1, RSVD1, RSVD2, RSVD3, 0xB038, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1697 PINGROUP(qspi1_io1_pd1, QSPI1, RSVD1, RSVD2, RSVD3, 0xB040, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1698 PINGROUP(qspi1_io0_pd0, QSPI1, RSVD1, RSVD2, RSVD3, 0xB048, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1699 PINGROUP(qspi1_sck_pc6, QSPI1, RSVD1, RSVD2, RSVD3, 0xB050, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1700 PINGROUP(qspi1_cs_n_pc7, QSPI1, RSVD1, RSVD2, RSVD3, 0xB058, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1701 PINGROUP(qspi_comp, QSPI, RSVD1, RSVD2, RSVD3, 0xB060, 0, N, -1, -1, -1, -1, -1, -1, -1), 1702 PINGROUP(sdmmc1_clk_pj0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8000, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1703 PINGROUP(sdmmc1_cmd_pj1, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8008, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1704 PINGROUP(sdmmc1_comp, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8010, 0, N, -1, -1, -1, -1, -1, -1, -1), 1705 PINGROUP(sdmmc1_dat3_pj5, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8018, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1706 PINGROUP(sdmmc1_dat2_pj4, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8020, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1707 PINGROUP(sdmmc1_dat1_pj3, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8028, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1708 PINGROUP(sdmmc1_dat0_pj2, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8030, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1709 PINGROUP(ufs0_rst_n_pae1, UFS0, RSVD1, RSVD2, RSVD3, 0x11000, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1710 PINGROUP(ufs0_ref_clk_pae0, UFS0, RSVD1, RSVD2, RSVD3, 0x11008, 0, Y, -1, 5, 6, -1, -1, 10, 12), 1711 PINGROUP(spi3_miso_py1, SPI3, RSVD1, RSVD2, RSVD3, 0xD000, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1712 PINGROUP(spi1_cs0_pz6, SPI1, RSVD1, RSVD2, RSVD3, 0xD008, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1713 PINGROUP(spi3_cs0_py3, SPI3, RSVD1, RSVD2, RSVD3, 0xD010, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1714 PINGROUP(spi1_miso_pz4, SPI1, RSVD1, RSVD2, RSVD3, 0xD018, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1715 PINGROUP(spi3_cs1_py4, SPI3, RSVD1, RSVD2, RSVD3, 0xD020, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1716 PINGROUP(spi1_sck_pz3, SPI1, RSVD1, RSVD2, RSVD3, 0xD028, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1717 PINGROUP(spi3_sck_py0, SPI3, RSVD1, RSVD2, RSVD3, 0xD030, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1718 PINGROUP(spi1_cs1_pz7, SPI1, RSVD1, RSVD2, RSVD3, 0xD038, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1719 PINGROUP(spi1_mosi_pz5, SPI1, RSVD1, RSVD2, RSVD3, 0xD040, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1720 PINGROUP(spi3_mosi_py2, SPI3, RSVD1, RSVD2, RSVD3, 0xD048, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1721 PINGROUP(uart2_tx_px4, UARTB, RSVD1, RSVD2, RSVD3, 0xD050, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1722 PINGROUP(uart2_rx_px5, UARTB, RSVD1, RSVD2, RSVD3, 0xD058, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1723 PINGROUP(uart2_rts_px6, UARTB, RSVD1, RSVD2, RSVD3, 0xD060, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1724 PINGROUP(uart2_cts_px7, UARTB, RSVD1, RSVD2, RSVD3, 0xD068, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1725 PINGROUP(uart5_tx_py5, UARTE, RSVD1, RSVD2, RSVD3, 0xD070, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1726 PINGROUP(uart5_rx_py6, UARTE, RSVD1, RSVD2, RSVD3, 0xD078, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1727 PINGROUP(uart5_rts_py7, UARTE, RSVD1, RSVD2, RSVD3, 0xD080, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1728 PINGROUP(uart5_cts_pz0, UARTE, RSVD1, RSVD2, RSVD3, 0xD088, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1729 PINGROUP(gpu_pwr_req_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0xD090, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1730 PINGROUP(gp_pwm3_px3, GP, RSVD1, RSVD2, RSVD3, 0xD098, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1731 PINGROUP(gp_pwm2_px2, GP, RSVD1, RSVD2, RSVD3, 0xD0A0, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1732 PINGROUP(cv_pwr_req_px1, RSVD0, RSVD1, RSVD2, RSVD3, 0xD0A8, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1733 PINGROUP(usb_vbus_en0_pz1, USB, RSVD1, RSVD2, RSVD3, 0xD0B0, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1734 PINGROUP(usb_vbus_en1_pz2, USB, RSVD1, RSVD2, RSVD3, 0xD0B8, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1735 PINGROUP(extperiph2_clk_pp1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, 0x0000, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1736 PINGROUP(extperiph1_clk_pp0, EXTPERIPH1, RSVD1, RSVD2, RSVD3, 0x0008, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1737 PINGROUP(cam_i2c_sda_pp3, I2C3, VI0, RSVD2, VI1, 0x0010, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1738 PINGROUP(cam_i2c_scl_pp2, I2C3, VI0, VI0_ALT, VI1, 0x0018, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1739 PINGROUP(soc_gpio23_pp4, VI0, VI0_ALT, VI1, VI1_ALT, 0x0020, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1740 PINGROUP(soc_gpio24_pp5, VI0, SOC, VI1, VI1_ALT, 0x0028, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1741 PINGROUP(soc_gpio25_pp6, VI0, I2S5, VI1, DMIC1, 0x0030, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1742 PINGROUP(pwr_i2c_scl_pp7, I2C5, RSVD1, RSVD2, RSVD3, 0x0038, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1743 PINGROUP(pwr_i2c_sda_pq0, I2C5, RSVD1, RSVD2, RSVD3, 0x0040, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1744 PINGROUP(soc_gpio28_pq1, VI0, RSVD1, VI1, RSVD3, 0x0048, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1745 PINGROUP(soc_gpio29_pq2, RSVD0, NV, RSVD2, RSVD3, 0x0050, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1746 PINGROUP(soc_gpio30_pq3, RSVD0, WDT, RSVD2, RSVD3, 0x0058, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1747 PINGROUP(soc_gpio31_pq4, RSVD0, RSVD1, RSVD2, RSVD3, 0x0060, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1748 PINGROUP(soc_gpio32_pq5, RSVD0, EXTPERIPH3, DCB, RSVD3, 0x0068, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1749 PINGROUP(soc_gpio33_pq6, RSVD0, EXTPERIPH4, DCB, RSVD3, 0x0070, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1750 PINGROUP(soc_gpio35_pq7, RSVD0, I2S5, DMIC1, RSVD3, 0x0078, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1751 PINGROUP(soc_gpio37_pr0, GP, I2S5, DMIC4, DSPK1, 0x0080, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1752 PINGROUP(soc_gpio56_pr1, RSVD0, I2S5, DMIC4, DSPK1, 0x0088, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1753 PINGROUP(uart1_cts_pr5, UARTA, RSVD1, RSVD2, RSVD3, 0x0090, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1754 PINGROUP(uart1_rts_pr4, UARTA, RSVD1, RSVD2, RSVD3, 0x0098, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1755 PINGROUP(uart1_rx_pr3, UARTA, RSVD1, RSVD2, RSVD3, 0x00A0, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1756 PINGROUP(uart1_tx_pr2, UARTA, RSVD1, RSVD2, RSVD3, 0x00A8, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1757 PINGROUP(cpu_pwr_req_pi5, RSVD0, RSVD1, RSVD2, RSVD3, 0x4000, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1758 PINGROUP(uart4_cts_ph6, UARTD, RSVD1, I2S7, RSVD3, 0x4008, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1759 PINGROUP(uart4_rts_ph5, UARTD, SPI4, RSVD2, RSVD3, 0x4010, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1760 PINGROUP(uart4_rx_ph4, UARTD, RSVD1, I2S7, RSVD3, 0x4018, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1761 PINGROUP(uart4_tx_ph3, UARTD, SPI4, RSVD2, RSVD3, 0x4020, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1762 PINGROUP(gen1_i2c_scl_pi3, I2C1, RSVD1, RSVD2, RSVD3, 0x4028, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1763 PINGROUP(gen1_i2c_sda_pi4, I2C1, RSVD1, RSVD2, RSVD3, 0x4030, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1764 PINGROUP(soc_gpio20_pg7, RSVD0, SDMMC1, RSVD2, RSVD3, 0x4038, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1765 PINGROUP(soc_gpio21_ph0, RSVD0, GP, I2S7, RSVD3, 0x4040, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1766 PINGROUP(soc_gpio22_ph1, RSVD0, RSVD1, I2S7, RSVD3, 0x4048, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1767 PINGROUP(soc_gpio13_pg0, RSVD0, RSVD1, RSVD2, RSVD3, 0x4050, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1768 PINGROUP(soc_gpio14_pg1, RSVD0, SPI4, RSVD2, RSVD3, 0x4058, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1769 PINGROUP(soc_gpio15_pg2, RSVD0, SPI4, RSVD2, RSVD3, 0x4060, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1770 PINGROUP(soc_gpio16_pg3, RSVD0, SPI4, RSVD2, RSVD3, 0x4068, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1771 PINGROUP(soc_gpio17_pg4, RSVD0, CCLA, RSVD2, RSVD3, 0x4070, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1772 PINGROUP(soc_gpio18_pg5, RSVD0, RSVD1, RSVD2, RSVD3, 0x4078, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1773 PINGROUP(soc_gpio19_pg6, GP, RSVD1, RSVD2, RSVD3, 0x4080, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1774 PINGROUP(soc_gpio41_ph7, RSVD0, I2S2, RSVD2, RSVD3, 0x4088, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1775 PINGROUP(soc_gpio42_pi0, RSVD0, I2S2, RSVD2, RSVD3, 0x4090, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1776 PINGROUP(soc_gpio43_pi1, RSVD0, I2S2, RSVD2, RSVD3, 0x4098, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1777 PINGROUP(soc_gpio44_pi2, RSVD0, I2S2, RSVD2, RSVD3, 0x40A0, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1778 PINGROUP(soc_gpio06_ph2, RSVD0, RSVD1, RSVD2, RSVD3, 0x40A8, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1779 PINGROUP(soc_gpio07_pi6, GP, RSVD1, RSVD2, RSVD3, 0x40B0, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1780 PINGROUP(dap4_sclk_pa4, I2S4, RSVD1, RSVD2, RSVD3, 0x2000, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1781 PINGROUP(dap4_dout_pa5, I2S4, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1782 PINGROUP(dap4_din_pa6, I2S4, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1783 PINGROUP(dap4_fs_pa7, I2S4, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1784 PINGROUP(dap6_sclk_pa0, I2S6, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1785 PINGROUP(dap6_dout_pa1, I2S6, RSVD1, RSVD2, RSVD3, 0x2028, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1786 PINGROUP(dap6_din_pa2, I2S6, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1787 PINGROUP(dap6_fs_pa3, I2S6, RSVD1, RSVD2, RSVD3, 0x2038, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1788 PINGROUP(soc_gpio45_pad0, RSVD0, I2S1, RSVD2, RSVD3, 0x18000, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1789 PINGROUP(soc_gpio46_pad1, RSVD0, I2S1, RSVD2, RSVD3, 0x18008, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1790 PINGROUP(soc_gpio47_pad2, RSVD0, I2S1, RSVD2, RSVD3, 0x18010, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1791 PINGROUP(soc_gpio48_pad3, RSVD0, I2S1, RSVD2, RSVD3, 0x18018, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1792 PINGROUP(soc_gpio57_pac4, RSVD0, I2S8, RSVD2, SDMMC1, 0x18020, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1793 PINGROUP(soc_gpio58_pac5, RSVD0, I2S8, RSVD2, SDMMC1, 0x18028, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1794 PINGROUP(soc_gpio59_pac6, AUD, I2S8, RSVD2, RSVD3, 0x18030, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1795 PINGROUP(soc_gpio60_pac7, RSVD0, I2S8, NV, IGPU, 0x18038, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1796 PINGROUP(spi5_cs0_pac3, SPI5, I2S3, DMIC2, RSVD3, 0x18040, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1797 PINGROUP(spi5_miso_pac1, SPI5, I2S3, DSPK0, RSVD3, 0x18048, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1798 PINGROUP(spi5_mosi_pac2, SPI5, I2S3, DMIC2, RSVD3, 0x18050, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1799 PINGROUP(spi5_sck_pac0, SPI5, I2S3, DSPK0, RSVD3, 0x18058, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1800 1801 }; 1802 1803 static const struct tegra_pinctrl_soc_data tegra234_pinctrl = { 1804 .pins = tegra234_pins, 1805 .npins = ARRAY_SIZE(tegra234_pins), 1806 .functions = tegra234_functions, 1807 .nfunctions = ARRAY_SIZE(tegra234_functions), 1808 .groups = tegra234_groups, 1809 .ngroups = ARRAY_SIZE(tegra234_groups), 1810 .hsm_in_mux = false, 1811 .schmitt_in_mux = true, 1812 .drvtype_in_mux = true, 1813 .sfsel_in_mux = true, 1814 }; 1815 1816 static const struct pinctrl_pin_desc tegra234_aon_pins[] = { 1817 PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PAA0, "CAN0_DOUT_PAA0"), 1818 PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PAA1, "CAN0_DIN_PAA1"), 1819 PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PAA2, "CAN1_DOUT_PAA2"), 1820 PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PAA3, "CAN1_DIN_PAA3"), 1821 PINCTRL_PIN(TEGRA_PIN_CAN0_STB_PAA4, "CAN0_STB_PAA4"), 1822 PINCTRL_PIN(TEGRA_PIN_CAN0_EN_PAA5, "CAN0_EN_PAA5"), 1823 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO49_PAA6, "SOC_GPIO49_PAA6"), 1824 PINCTRL_PIN(TEGRA_PIN_CAN0_ERR_PAA7, "CAN0_ERR_PAA7"), 1825 PINCTRL_PIN(TEGRA_PIN_CAN1_STB_PBB0, "CAN1_STB_PBB0"), 1826 PINCTRL_PIN(TEGRA_PIN_CAN1_EN_PBB1, "CAN1_EN_PBB1"), 1827 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO50_PBB2, "SOC_GPIO50_PBB2"), 1828 PINCTRL_PIN(TEGRA_PIN_CAN1_ERR_PBB3, "CAN1_ERR_PBB3"), 1829 PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"), 1830 PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"), 1831 PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"), 1832 PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"), 1833 PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PCC4, "TOUCH_CLK_PCC4"), 1834 PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"), 1835 PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"), 1836 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"), 1837 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"), 1838 PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"), 1839 PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"), 1840 PINCTRL_PIN(TEGRA_PIN_SCE_ERROR_PEE0, "SCE_ERROR_PEE0"), 1841 PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PEE1, "VCOMP_ALERT_PEE1"), 1842 PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PEE2, "AO_RETENTION_N_PEE2"), 1843 PINCTRL_PIN(TEGRA_PIN_BATT_OC_PEE3, "BATT_OC_PEE3"), 1844 PINCTRL_PIN(TEGRA_PIN_POWER_ON_PEE4, "POWER_ON_PEE4"), 1845 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO26_PEE5, "SOC_GPIO26_PEE5"), 1846 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO27_PEE6, "SOC_GPIO27_PEE6"), 1847 PINCTRL_PIN(TEGRA_PIN_BOOTV_CTL_N_PEE7, "BOOTV_CTL_N_PEE7"), 1848 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PGG0, "HDMI_CEC_PGG0"), 1849 }; 1850 1851 /* AON drive pin groups */ 1852 #define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1853 #define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1854 #define drive_uart3_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1855 #define drive_gen8_i2c_sda_pdd2 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1856 #define drive_gen8_i2c_scl_pdd1 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1857 #define drive_spi2_mosi_pcc2 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1858 #define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1859 #define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1860 #define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1861 #define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1862 #define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1863 #define drive_can1_dout_paa2 DRV_PINGROUP_ENTRY_Y(0x3004, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1864 #define drive_can1_din_paa3 DRV_PINGROUP_ENTRY_Y(0x300c, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1865 #define drive_can0_dout_paa0 DRV_PINGROUP_ENTRY_Y(0x3014, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1866 #define drive_can0_din_paa1 DRV_PINGROUP_ENTRY_Y(0x301c, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1867 #define drive_can0_stb_paa4 DRV_PINGROUP_ENTRY_Y(0x3024, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1868 #define drive_can0_en_paa5 DRV_PINGROUP_ENTRY_Y(0x302c, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1869 #define drive_soc_gpio49_paa6 DRV_PINGROUP_ENTRY_Y(0x3034, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1870 #define drive_can0_err_paa7 DRV_PINGROUP_ENTRY_Y(0x303c, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1871 #define drive_can1_stb_pbb0 DRV_PINGROUP_ENTRY_Y(0x3044, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1872 #define drive_can1_en_pbb1 DRV_PINGROUP_ENTRY_Y(0x304c, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1873 #define drive_soc_gpio50_pbb2 DRV_PINGROUP_ENTRY_Y(0x3054, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1874 #define drive_can1_err_pbb3 DRV_PINGROUP_ENTRY_Y(0x305c, 28, 2, 30, 2, -1, -1, -1, -1, 0) 1875 #define drive_sce_error_pee0 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1876 #define drive_batt_oc_pee3 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1877 #define drive_bootv_ctl_n_pee7 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1878 #define drive_power_on_pee4 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1879 #define drive_soc_gpio26_pee5 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1880 #define drive_soc_gpio27_pee6 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1881 #define drive_ao_retention_n_pee2 DRV_PINGROUP_ENTRY_Y(0x1054, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1882 #define drive_vcomp_alert_pee1 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1883 #define drive_hdmi_cec_pgg0 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1884 1885 static const struct tegra_pingroup tegra234_aon_groups[] = { 1886 PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1887 PINGROUP(uart3_rx_pcc6, UARTC, UARTJ, RSVD2, RSVD3, 0x2008, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1888 PINGROUP(uart3_tx_pcc5, UARTC, UARTJ, RSVD2, RSVD3, 0x2010, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1889 PINGROUP(gen8_i2c_sda_pdd2, I2C8, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1890 PINGROUP(gen8_i2c_scl_pdd1, I2C8, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1891 PINGROUP(spi2_mosi_pcc2, SPI2, RSVD1, RSVD2, RSVD3, 0x2028, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1892 PINGROUP(gen2_i2c_scl_pcc7, I2C2, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1893 PINGROUP(spi2_cs0_pcc3, SPI2, RSVD1, RSVD2, RSVD3, 0x2038, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1894 PINGROUP(gen2_i2c_sda_pdd0, I2C2, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1895 PINGROUP(spi2_sck_pcc0, SPI2, RSVD1, RSVD2, RSVD3, 0x2048, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1896 PINGROUP(spi2_miso_pcc1, SPI2, RSVD1, RSVD2, RSVD3, 0x2050, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1897 PINGROUP(can1_dout_paa2, CAN1, RSVD1, RSVD2, RSVD3, 0x3000, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1898 PINGROUP(can1_din_paa3, CAN1, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1899 PINGROUP(can0_dout_paa0, CAN0, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1900 PINGROUP(can0_din_paa1, CAN0, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1901 PINGROUP(can0_stb_paa4, RSVD0, WDT, TSC, TSC_ALT, 0x3020, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1902 PINGROUP(can0_en_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3028, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1903 PINGROUP(soc_gpio49_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1904 PINGROUP(can0_err_paa7, RSVD0, TSC, RSVD2, TSC_ALT, 0x3038, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1905 PINGROUP(can1_stb_pbb0, RSVD0, DMIC3, DMIC5, RSVD3, 0x3040, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1906 PINGROUP(can1_en_pbb1, RSVD0, DMIC3, DMIC5, RSVD3, 0x3048, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1907 PINGROUP(soc_gpio50_pbb2, RSVD0, TSC, RSVD2, TSC_ALT, 0x3050, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1908 PINGROUP(can1_err_pbb3, RSVD0, TSC, RSVD2, TSC_ALT, 0x3058, 0, Y, -1, 5, 6, -1, 9, 10, 12), 1909 PINGROUP(sce_error_pee0, SCE, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1910 PINGROUP(batt_oc_pee3, SOC, RSVD1, RSVD2, RSVD3, 0x1020, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1911 PINGROUP(bootv_ctl_n_pee7, RSVD0, RSVD1, RSVD2, RSVD3, 0x1028, 0, Y, -1, 7, 6, 8, -1, 10, 12), 1912 PINGROUP(power_on_pee4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1038, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1913 PINGROUP(soc_gpio26_pee5, RSVD0, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1914 PINGROUP(soc_gpio27_pee6, RSVD0, RSVD1, RSVD2, RSVD3, 0x1048, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1915 PINGROUP(ao_retention_n_pee2, GPIO, LED, RSVD2, ISTCTRL, 0x1050, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1916 PINGROUP(vcomp_alert_pee1, SOC, RSVD1, RSVD2, RSVD3, 0x1058, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1917 PINGROUP(hdmi_cec_pgg0, HDMI, RSVD1, RSVD2, RSVD3, 0x1060, 0, Y, 5, 7, 6, 8, -1, 10, 12), 1918 }; 1919 1920 static const struct tegra_pinctrl_soc_data tegra234_pinctrl_aon = { 1921 .pins = tegra234_aon_pins, 1922 .npins = ARRAY_SIZE(tegra234_aon_pins), 1923 .functions = tegra234_functions, 1924 .nfunctions = ARRAY_SIZE(tegra234_functions), 1925 .groups = tegra234_aon_groups, 1926 .ngroups = ARRAY_SIZE(tegra234_aon_groups), 1927 .hsm_in_mux = false, 1928 .schmitt_in_mux = true, 1929 .drvtype_in_mux = true, 1930 .sfsel_in_mux = true, 1931 }; 1932 1933 static int tegra234_pinctrl_probe(struct platform_device *pdev) 1934 { 1935 const struct tegra_pinctrl_soc_data *soc = device_get_match_data(&pdev->dev); 1936 1937 return tegra_pinctrl_probe(pdev, soc); 1938 } 1939 1940 static const struct of_device_id tegra234_pinctrl_of_match[] = { 1941 { .compatible = "nvidia,tegra234-pinmux", .data = &tegra234_pinctrl}, 1942 { .compatible = "nvidia,tegra234-pinmux-aon", .data = &tegra234_pinctrl_aon }, 1943 { } 1944 }; 1945 MODULE_DEVICE_TABLE(of, tegra234_pinctrl_of_match); 1946 1947 static struct platform_driver tegra234_pinctrl_driver = { 1948 .driver = { 1949 .name = "tegra234-pinctrl", 1950 .of_match_table = tegra234_pinctrl_of_match, 1951 }, 1952 .probe = tegra234_pinctrl_probe, 1953 }; 1954 1955 static int __init tegra234_pinctrl_init(void) 1956 { 1957 return platform_driver_register(&tegra234_pinctrl_driver); 1958 } 1959 arch_initcall(tegra234_pinctrl_init); 1960