1 /* 2 * Driver for the NVIDIA Tegra pinmux 3 * 4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef __PINMUX_TEGRA_H__ 17 #define __PINMUX_TEGRA_H__ 18 19 enum tegra_pinconf_param { 20 /* argument: tegra_pinconf_pull */ 21 TEGRA_PINCONF_PARAM_PULL, 22 /* argument: tegra_pinconf_tristate */ 23 TEGRA_PINCONF_PARAM_TRISTATE, 24 /* argument: Boolean */ 25 TEGRA_PINCONF_PARAM_ENABLE_INPUT, 26 /* argument: Boolean */ 27 TEGRA_PINCONF_PARAM_OPEN_DRAIN, 28 /* argument: Boolean */ 29 TEGRA_PINCONF_PARAM_LOCK, 30 /* argument: Boolean */ 31 TEGRA_PINCONF_PARAM_IORESET, 32 /* argument: Boolean */ 33 TEGRA_PINCONF_PARAM_RCV_SEL, 34 /* argument: Boolean */ 35 TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 36 /* argument: Boolean */ 37 TEGRA_PINCONF_PARAM_SCHMITT, 38 /* argument: Boolean */ 39 TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 40 /* argument: Integer, range is HW-dependant */ 41 TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 42 /* argument: Integer, range is HW-dependant */ 43 TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 44 /* argument: Integer, range is HW-dependant */ 45 TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 46 /* argument: Integer, range is HW-dependant */ 47 TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 48 /* argument: Integer, range is HW-dependant */ 49 TEGRA_PINCONF_PARAM_DRIVE_TYPE, 50 }; 51 52 enum tegra_pinconf_pull { 53 TEGRA_PINCONFIG_PULL_NONE, 54 TEGRA_PINCONFIG_PULL_DOWN, 55 TEGRA_PINCONFIG_PULL_UP, 56 }; 57 58 enum tegra_pinconf_tristate { 59 TEGRA_PINCONFIG_DRIVEN, 60 TEGRA_PINCONFIG_TRISTATE, 61 }; 62 63 #define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_)) 64 #define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16) 65 #define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff) 66 67 /** 68 * struct tegra_function - Tegra pinctrl mux function 69 * @name: The name of the function, exported to pinctrl core. 70 * @groups: An array of pin groups that may select this function. 71 * @ngroups: The number of entries in @groups. 72 */ 73 struct tegra_function { 74 const char *name; 75 const char **groups; 76 unsigned ngroups; 77 }; 78 79 /** 80 * struct tegra_pingroup - Tegra pin group 81 * @name The name of the pin group. 82 * @pins An array of pin IDs included in this pin group. 83 * @npins The number of entries in @pins. 84 * @funcs The mux functions which can be muxed onto this group. 85 * @mux_reg: Mux register offset. 86 * This register contains the mux, einput, odrain, lock, 87 * ioreset, rcv_sel parameters. 88 * @mux_bank: Mux register bank. 89 * @mux_bit: Mux register bit. 90 * @pupd_reg: Pull-up/down register offset. 91 * @pupd_bank: Pull-up/down register bank. 92 * @pupd_bit: Pull-up/down register bit. 93 * @tri_reg: Tri-state register offset. 94 * @tri_bank: Tri-state register bank. 95 * @tri_bit: Tri-state register bit. 96 * @parked_bit: Parked register bit. -1 if unsupported. 97 * @einput_bit: Enable-input register bit. 98 * @odrain_bit: Open-drain register bit. 99 * @lock_bit: Lock register bit. 100 * @ioreset_bit: IO reset register bit. 101 * @rcv_sel_bit: Receiver select bit. 102 * @drv_reg: Drive fields register offset. 103 * This register contains hsm, schmitt, lpmd, drvdn, 104 * drvup, slwr, slwf, and drvtype parameters. 105 * @drv_bank: Drive fields register bank. 106 * @hsm_bit: High Speed Mode register bit. 107 * @schmitt_bit: Scmitt register bit. 108 * @lpmd_bit: Low Power Mode register bit. 109 * @drvdn_bit: Drive Down register bit. 110 * @drvdn_width: Drive Down field width. 111 * @drvup_bit: Drive Up register bit. 112 * @drvup_width: Drive Up field width. 113 * @slwr_bit: Slew Rising register bit. 114 * @slwr_width: Slew Rising field width. 115 * @slwf_bit: Slew Falling register bit. 116 * @slwf_width: Slew Falling field width. 117 * @drvtype_bit: Drive type register bit. 118 * 119 * -1 in a *_reg field means that feature is unsupported for this group. 120 * *_bank and *_reg values are irrelevant when *_reg is -1. 121 * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature. 122 * 123 * A representation of a group of pins (possibly just one pin) in the Tegra 124 * pin controller. Each group allows some parameter or parameters to be 125 * configured. The most common is mux function selection. Many others exist 126 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex; 127 * certain groups may only support configuring certain parameters, hence 128 * each parameter is optional. 129 */ 130 struct tegra_pingroup { 131 const char *name; 132 const unsigned *pins; 133 u8 npins; 134 u8 funcs[4]; 135 s16 mux_reg; 136 s16 pupd_reg; 137 s16 tri_reg; 138 s16 drv_reg; 139 u32 mux_bank:2; 140 u32 pupd_bank:2; 141 u32 tri_bank:2; 142 u32 drv_bank:2; 143 s32 mux_bit:6; 144 s32 pupd_bit:6; 145 s32 tri_bit:6; 146 s32 parked_bit:6; 147 s32 einput_bit:6; 148 s32 odrain_bit:6; 149 s32 lock_bit:6; 150 s32 ioreset_bit:6; 151 s32 rcv_sel_bit:6; 152 s32 hsm_bit:6; 153 s32 schmitt_bit:6; 154 s32 lpmd_bit:6; 155 s32 drvdn_bit:6; 156 s32 drvup_bit:6; 157 s32 slwr_bit:6; 158 s32 slwf_bit:6; 159 s32 drvtype_bit:6; 160 s32 drvdn_width:6; 161 s32 drvup_width:6; 162 s32 slwr_width:6; 163 s32 slwf_width:6; 164 }; 165 166 /** 167 * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration 168 * @ngpios: The number of GPIO pins the pin controller HW affects. 169 * @pins: An array describing all pins the pin controller affects. 170 * All pins which are also GPIOs must be listed first within the 171 * array, and be numbered identically to the GPIO controller's 172 * numbering. 173 * @npins: The numbmer of entries in @pins. 174 * @functions: An array describing all mux functions the SoC supports. 175 * @nfunctions: The numbmer of entries in @functions. 176 * @groups: An array describing all pin groups the pin SoC supports. 177 * @ngroups: The numbmer of entries in @groups. 178 */ 179 struct tegra_pinctrl_soc_data { 180 unsigned ngpios; 181 const struct pinctrl_pin_desc *pins; 182 unsigned npins; 183 struct tegra_function *functions; 184 unsigned nfunctions; 185 const struct tegra_pingroup *groups; 186 unsigned ngroups; 187 bool hsm_in_mux; 188 bool schmitt_in_mux; 189 bool drvtype_in_mux; 190 }; 191 192 int tegra_pinctrl_probe(struct platform_device *pdev, 193 const struct tegra_pinctrl_soc_data *soc_data); 194 #endif 195