1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the NVIDIA Tegra pinmux 4 * 5 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. 6 * 7 * Derived from code: 8 * Copyright (C) 2010 Google, Inc. 9 * Copyright (C) 2010 NVIDIA Corporation 10 * Copyright (C) 2009-2011 ST-Ericsson AB 11 */ 12 13 #include <linux/err.h> 14 #include <linux/init.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/seq_file.h> 20 #include <linux/slab.h> 21 22 #include <linux/pinctrl/machine.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 27 #include "../core.h" 28 #include "../pinctrl-utils.h" 29 #include "pinctrl-tegra.h" 30 31 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) 32 { 33 return readl(pmx->regs[bank] + reg); 34 } 35 36 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) 37 { 38 writel_relaxed(val, pmx->regs[bank] + reg); 39 /* make sure pinmux register write completed */ 40 pmx_readl(pmx, bank, reg); 41 } 42 43 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 44 { 45 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 46 47 return pmx->soc->ngroups; 48 } 49 50 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 51 unsigned group) 52 { 53 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 54 55 return pmx->soc->groups[group].name; 56 } 57 58 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 59 unsigned group, 60 const unsigned **pins, 61 unsigned *num_pins) 62 { 63 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 64 65 *pins = pmx->soc->groups[group].pins; 66 *num_pins = pmx->soc->groups[group].npins; 67 68 return 0; 69 } 70 71 #ifdef CONFIG_DEBUG_FS 72 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, 73 struct seq_file *s, 74 unsigned offset) 75 { 76 seq_printf(s, " %s", dev_name(pctldev->dev)); 77 } 78 #endif 79 80 static const struct cfg_param { 81 const char *property; 82 enum tegra_pinconf_param param; 83 } cfg_params[] = { 84 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL}, 85 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE}, 86 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT}, 87 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN}, 88 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK}, 89 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET}, 90 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL}, 91 {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL}, 92 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE}, 93 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT}, 94 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE}, 95 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH}, 96 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH}, 97 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, 98 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, 99 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE}, 100 {"nvidia,gpio-mode", TEGRA_PINCONF_PARAM_GPIO_MODE}, 101 }; 102 103 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 104 struct device_node *np, 105 struct pinctrl_map **map, 106 unsigned *reserved_maps, 107 unsigned *num_maps) 108 { 109 struct device *dev = pctldev->dev; 110 int ret, i; 111 const char *function; 112 u32 val; 113 unsigned long config; 114 unsigned long *configs = NULL; 115 unsigned num_configs = 0; 116 unsigned reserve; 117 struct property *prop; 118 const char *group; 119 120 ret = of_property_read_string(np, "nvidia,function", &function); 121 if (ret < 0) { 122 /* EINVAL=missing, which is fine since it's optional */ 123 if (ret != -EINVAL) 124 dev_err(dev, 125 "%pOF: could not parse property nvidia,function\n", np); 126 function = NULL; 127 } 128 129 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 130 ret = of_property_read_u32(np, cfg_params[i].property, &val); 131 if (!ret) { 132 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val); 133 ret = pinctrl_utils_add_config(pctldev, &configs, 134 &num_configs, config); 135 if (ret < 0) 136 goto exit; 137 /* EINVAL=missing, which is fine since it's optional */ 138 } else if (ret != -EINVAL) { 139 dev_err(dev, "%pOF: could not parse property %s\n", 140 np, cfg_params[i].property); 141 } 142 } 143 144 reserve = 0; 145 if (function != NULL) 146 reserve++; 147 if (num_configs) 148 reserve++; 149 ret = of_property_count_strings(np, "nvidia,pins"); 150 if (ret < 0) { 151 dev_err(dev, "%pOF: could not parse property nvidia,pins\n", np); 152 goto exit; 153 } 154 reserve *= ret; 155 156 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, 157 num_maps, reserve); 158 if (ret < 0) 159 goto exit; 160 161 of_property_for_each_string(np, "nvidia,pins", prop, group) { 162 if (function) { 163 ret = pinctrl_utils_add_map_mux(pctldev, map, 164 reserved_maps, num_maps, group, 165 function); 166 if (ret < 0) 167 goto exit; 168 } 169 170 if (num_configs) { 171 ret = pinctrl_utils_add_map_configs(pctldev, map, 172 reserved_maps, num_maps, group, 173 configs, num_configs, 174 PIN_MAP_TYPE_CONFIGS_GROUP); 175 if (ret < 0) 176 goto exit; 177 } 178 } 179 180 ret = 0; 181 182 exit: 183 kfree(configs); 184 return ret; 185 } 186 187 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 188 struct device_node *np_config, 189 struct pinctrl_map **map, 190 unsigned *num_maps) 191 { 192 unsigned reserved_maps; 193 int ret; 194 195 reserved_maps = 0; 196 *map = NULL; 197 *num_maps = 0; 198 199 for_each_child_of_node_scoped(np_config, np) { 200 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map, 201 &reserved_maps, num_maps); 202 if (ret < 0) { 203 pinctrl_utils_free_map(pctldev, *map, 204 *num_maps); 205 return ret; 206 } 207 } 208 209 return 0; 210 } 211 212 static const struct pinctrl_ops tegra_pinctrl_ops = { 213 .get_groups_count = tegra_pinctrl_get_groups_count, 214 .get_group_name = tegra_pinctrl_get_group_name, 215 .get_group_pins = tegra_pinctrl_get_group_pins, 216 #ifdef CONFIG_DEBUG_FS 217 .pin_dbg_show = tegra_pinctrl_pin_dbg_show, 218 #endif 219 .dt_node_to_map = tegra_pinctrl_dt_node_to_map, 220 .dt_free_map = pinctrl_utils_free_map, 221 }; 222 223 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) 224 { 225 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 226 227 return pmx->soc->nfunctions; 228 } 229 230 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev, 231 unsigned function) 232 { 233 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 234 235 return pmx->functions[function].name; 236 } 237 238 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, 239 unsigned function, 240 const char * const **groups, 241 unsigned * const num_groups) 242 { 243 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 244 245 *groups = pmx->functions[function].groups; 246 *num_groups = pmx->functions[function].ngroups; 247 248 return 0; 249 } 250 251 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev, 252 unsigned function, 253 unsigned group) 254 { 255 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 256 const struct tegra_pingroup *g; 257 int i; 258 u32 val; 259 260 g = &pmx->soc->groups[group]; 261 262 if (WARN_ON(g->mux_reg < 0)) 263 return -EINVAL; 264 265 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { 266 if (g->funcs[i] == function) 267 break; 268 } 269 if (WARN_ON(i == ARRAY_SIZE(g->funcs))) 270 return -EINVAL; 271 272 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); 273 val &= ~(0x3 << g->mux_bit); 274 val |= i << g->mux_bit; 275 /* Set the SFIO/GPIO selection to SFIO when under pinmux control*/ 276 if (pmx->soc->sfsel_in_mux) 277 val |= (1 << g->sfsel_bit); 278 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); 279 280 return 0; 281 } 282 283 static int tegra_pinctrl_get_group_index(struct pinctrl_dev *pctldev, 284 unsigned int offset) 285 { 286 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 287 unsigned int group, num_pins, j; 288 const unsigned int *pins; 289 int ret; 290 291 for (group = 0; group < pmx->soc->ngroups; ++group) { 292 ret = tegra_pinctrl_get_group_pins(pctldev, group, &pins, &num_pins); 293 if (ret < 0) 294 continue; 295 for (j = 0; j < num_pins; j++) { 296 if (offset == pins[j]) 297 return group; 298 } 299 } 300 301 return -EINVAL; 302 } 303 304 static const struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev *pctldev, 305 unsigned int offset, 306 int group_index) 307 { 308 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 309 310 if (group_index < 0 || group_index >= pmx->soc->ngroups) 311 return NULL; 312 313 return &pmx->soc->groups[group_index]; 314 } 315 316 static struct tegra_pingroup_config *tegra_pinctrl_get_group_config(struct pinctrl_dev *pctldev, 317 unsigned int offset, 318 int group_index) 319 { 320 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 321 322 if (group_index < 0) 323 return NULL; 324 325 return &pmx->pingroup_configs[group_index]; 326 } 327 328 static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, 329 struct pinctrl_gpio_range *range, 330 unsigned int offset) 331 { 332 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 333 const struct tegra_pingroup *group; 334 struct tegra_pingroup_config *config; 335 int group_index; 336 u32 value; 337 338 if (!pmx->soc->sfsel_in_mux) 339 return 0; 340 341 group_index = tegra_pinctrl_get_group_index(pctldev, offset); 342 group = tegra_pinctrl_get_group(pctldev, offset, group_index); 343 344 if (!group) 345 return -EINVAL; 346 347 if (group->mux_reg < 0 || group->sfsel_bit < 0) 348 return -EINVAL; 349 350 config = tegra_pinctrl_get_group_config(pctldev, offset, group_index); 351 if (!config) 352 return -EINVAL; 353 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); 354 config->is_sfsel = (value & BIT(group->sfsel_bit)) != 0; 355 value &= ~BIT(group->sfsel_bit); 356 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); 357 358 return 0; 359 } 360 361 static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev, 362 struct pinctrl_gpio_range *range, 363 unsigned int offset) 364 { 365 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 366 const struct tegra_pingroup *group; 367 struct tegra_pingroup_config *config; 368 int group_index; 369 u32 value; 370 371 if (!pmx->soc->sfsel_in_mux) 372 return; 373 374 group_index = tegra_pinctrl_get_group_index(pctldev, offset); 375 group = tegra_pinctrl_get_group(pctldev, offset, group_index); 376 377 if (!group) 378 return; 379 380 if (group->mux_reg < 0 || group->sfsel_bit < 0) 381 return; 382 383 config = tegra_pinctrl_get_group_config(pctldev, offset, group_index); 384 if (!config) 385 return; 386 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); 387 if (config->is_sfsel) 388 value |= BIT(group->sfsel_bit); 389 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); 390 } 391 392 static const struct pinmux_ops tegra_pinmux_ops = { 393 .get_functions_count = tegra_pinctrl_get_funcs_count, 394 .get_function_name = tegra_pinctrl_get_func_name, 395 .get_function_groups = tegra_pinctrl_get_func_groups, 396 .set_mux = tegra_pinctrl_set_mux, 397 .gpio_request_enable = tegra_pinctrl_gpio_request_enable, 398 .gpio_disable_free = tegra_pinctrl_gpio_disable_free, 399 }; 400 401 static int tegra_pinconf_reg(struct tegra_pmx *pmx, 402 const struct tegra_pingroup *g, 403 enum tegra_pinconf_param param, 404 bool report_err, 405 s8 *bank, s32 *reg, s8 *bit, s8 *width) 406 { 407 switch (param) { 408 case TEGRA_PINCONF_PARAM_PULL: 409 *bank = g->pupd_bank; 410 *reg = g->pupd_reg; 411 *bit = g->pupd_bit; 412 *width = 2; 413 break; 414 case TEGRA_PINCONF_PARAM_TRISTATE: 415 *bank = g->tri_bank; 416 *reg = g->tri_reg; 417 *bit = g->tri_bit; 418 *width = 1; 419 break; 420 case TEGRA_PINCONF_PARAM_ENABLE_INPUT: 421 *bank = g->mux_bank; 422 *reg = g->mux_reg; 423 *bit = g->einput_bit; 424 *width = 1; 425 break; 426 case TEGRA_PINCONF_PARAM_OPEN_DRAIN: 427 *bank = g->mux_bank; 428 *reg = g->mux_reg; 429 *bit = g->odrain_bit; 430 *width = 1; 431 break; 432 case TEGRA_PINCONF_PARAM_LOCK: 433 *bank = g->mux_bank; 434 *reg = g->mux_reg; 435 *bit = g->lock_bit; 436 *width = 1; 437 break; 438 case TEGRA_PINCONF_PARAM_IORESET: 439 *bank = g->mux_bank; 440 *reg = g->mux_reg; 441 *bit = g->ioreset_bit; 442 *width = 1; 443 break; 444 case TEGRA_PINCONF_PARAM_RCV_SEL: 445 *bank = g->mux_bank; 446 *reg = g->mux_reg; 447 *bit = g->rcv_sel_bit; 448 *width = 1; 449 break; 450 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE: 451 if (pmx->soc->hsm_in_mux) { 452 *bank = g->mux_bank; 453 *reg = g->mux_reg; 454 } else { 455 *bank = g->drv_bank; 456 *reg = g->drv_reg; 457 } 458 *bit = g->hsm_bit; 459 *width = 1; 460 break; 461 case TEGRA_PINCONF_PARAM_SCHMITT: 462 if (pmx->soc->schmitt_in_mux) { 463 *bank = g->mux_bank; 464 *reg = g->mux_reg; 465 } else { 466 *bank = g->drv_bank; 467 *reg = g->drv_reg; 468 } 469 *bit = g->schmitt_bit; 470 *width = 1; 471 break; 472 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE: 473 *bank = g->drv_bank; 474 *reg = g->drv_reg; 475 *bit = g->lpmd_bit; 476 *width = 2; 477 break; 478 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH: 479 *bank = g->drv_bank; 480 *reg = g->drv_reg; 481 *bit = g->drvdn_bit; 482 *width = g->drvdn_width; 483 break; 484 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH: 485 *bank = g->drv_bank; 486 *reg = g->drv_reg; 487 *bit = g->drvup_bit; 488 *width = g->drvup_width; 489 break; 490 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING: 491 *bank = g->drv_bank; 492 *reg = g->drv_reg; 493 *bit = g->slwf_bit; 494 *width = g->slwf_width; 495 break; 496 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING: 497 *bank = g->drv_bank; 498 *reg = g->drv_reg; 499 *bit = g->slwr_bit; 500 *width = g->slwr_width; 501 break; 502 case TEGRA_PINCONF_PARAM_DRIVE_TYPE: 503 if (pmx->soc->drvtype_in_mux) { 504 *bank = g->mux_bank; 505 *reg = g->mux_reg; 506 } else { 507 *bank = g->drv_bank; 508 *reg = g->drv_reg; 509 } 510 *bit = g->drvtype_bit; 511 *width = 2; 512 break; 513 case TEGRA_PINCONF_PARAM_GPIO_MODE: 514 if (pmx->soc->sfsel_in_mux) { 515 *bank = g->mux_bank; 516 *reg = g->mux_reg; 517 *bit = g->sfsel_bit; 518 *width = 1; 519 } else { 520 *reg = -EINVAL; 521 } 522 break; 523 default: 524 dev_err(pmx->dev, "Invalid config param %04x\n", param); 525 return -ENOTSUPP; 526 } 527 528 if (*reg < 0 || *bit < 0) { 529 if (report_err) { 530 const char *prop = "unknown"; 531 int i; 532 533 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 534 if (cfg_params[i].param == param) { 535 prop = cfg_params[i].property; 536 break; 537 } 538 } 539 540 dev_err(pmx->dev, 541 "Config param %04x (%s) not supported on group %s\n", 542 param, prop, g->name); 543 } 544 return -ENOTSUPP; 545 } 546 547 return 0; 548 } 549 550 static int tegra_pinconf_get(struct pinctrl_dev *pctldev, 551 unsigned pin, unsigned long *config) 552 { 553 dev_err(pctldev->dev, "pin_config_get op not supported\n"); 554 return -ENOTSUPP; 555 } 556 557 static int tegra_pinconf_set(struct pinctrl_dev *pctldev, 558 unsigned pin, unsigned long *configs, 559 unsigned num_configs) 560 { 561 dev_err(pctldev->dev, "pin_config_set op not supported\n"); 562 return -ENOTSUPP; 563 } 564 565 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, 566 unsigned group, unsigned long *config) 567 { 568 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 569 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config); 570 u16 arg; 571 const struct tegra_pingroup *g; 572 int ret; 573 s8 bank, bit, width; 574 s32 reg; 575 u32 val, mask; 576 577 g = &pmx->soc->groups[group]; 578 579 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, 580 &width); 581 if (ret < 0) 582 return ret; 583 584 val = pmx_readl(pmx, bank, reg); 585 mask = (1 << width) - 1; 586 arg = (val >> bit) & mask; 587 588 *config = TEGRA_PINCONF_PACK(param, arg); 589 590 return 0; 591 } 592 593 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, 594 unsigned group, unsigned long *configs, 595 unsigned num_configs) 596 { 597 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 598 enum tegra_pinconf_param param; 599 u16 arg; 600 const struct tegra_pingroup *g; 601 int ret, i; 602 s8 bank, bit, width; 603 s32 reg; 604 u32 val, mask; 605 606 g = &pmx->soc->groups[group]; 607 608 for (i = 0; i < num_configs; i++) { 609 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]); 610 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]); 611 612 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, 613 &width); 614 if (ret < 0) 615 return ret; 616 617 val = pmx_readl(pmx, bank, reg); 618 619 /* LOCK can't be cleared */ 620 if (param == TEGRA_PINCONF_PARAM_LOCK) { 621 if ((val & BIT(bit)) && !arg) { 622 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); 623 return -EINVAL; 624 } 625 } 626 627 /* Special-case Boolean values; allow any non-zero as true */ 628 if (width == 1) 629 arg = !!arg; 630 631 /* Range-check user-supplied value */ 632 mask = (1 << width) - 1; 633 if (arg & ~mask) { 634 dev_err(pctldev->dev, 635 "config %lx: %x too big for %d bit register\n", 636 configs[i], arg, width); 637 return -EINVAL; 638 } 639 640 /* Update register */ 641 val &= ~(mask << bit); 642 val |= arg << bit; 643 pmx_writel(pmx, val, bank, reg); 644 } /* for each config */ 645 646 return 0; 647 } 648 649 #ifdef CONFIG_DEBUG_FS 650 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev, 651 struct seq_file *s, unsigned offset) 652 { 653 } 654 655 static const char *strip_prefix(const char *s) 656 { 657 const char *comma = strchr(s, ','); 658 if (!comma) 659 return s; 660 661 return comma + 1; 662 } 663 664 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 665 struct seq_file *s, unsigned group) 666 { 667 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 668 const struct tegra_pingroup *g; 669 int i, ret; 670 s8 bank, bit, width; 671 s32 reg; 672 u32 val; 673 674 g = &pmx->soc->groups[group]; 675 676 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 677 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false, 678 &bank, ®, &bit, &width); 679 if (ret < 0) 680 continue; 681 682 val = pmx_readl(pmx, bank, reg); 683 val >>= bit; 684 val &= (1 << width) - 1; 685 686 seq_printf(s, "\n\t%s=%u", 687 strip_prefix(cfg_params[i].property), val); 688 } 689 690 if (g->mux_reg >= 0) { 691 /* read pinmux function and dump to seq_file */ 692 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); 693 val = g->funcs[(val >> g->mux_bit) & 0x3]; 694 695 seq_printf(s, "\n\tfunction=%s", pmx->functions[val].name); 696 } 697 } 698 699 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, 700 struct seq_file *s, 701 unsigned long config) 702 { 703 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config); 704 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config); 705 const char *pname = "unknown"; 706 int i; 707 708 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 709 if (cfg_params[i].param == param) { 710 pname = cfg_params[i].property; 711 break; 712 } 713 } 714 715 seq_printf(s, "%s=%d", strip_prefix(pname), arg); 716 } 717 #endif 718 719 static const struct pinconf_ops tegra_pinconf_ops = { 720 .pin_config_get = tegra_pinconf_get, 721 .pin_config_set = tegra_pinconf_set, 722 .pin_config_group_get = tegra_pinconf_group_get, 723 .pin_config_group_set = tegra_pinconf_group_set, 724 #ifdef CONFIG_DEBUG_FS 725 .pin_config_dbg_show = tegra_pinconf_dbg_show, 726 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show, 727 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show, 728 #endif 729 }; 730 731 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) 732 { 733 int i = 0; 734 const struct tegra_pingroup *g; 735 u32 val; 736 737 for (i = 0; i < pmx->soc->ngroups; ++i) { 738 g = &pmx->soc->groups[i]; 739 if (g->parked_bitmask > 0) { 740 unsigned int bank, reg; 741 742 if (g->mux_reg != -1) { 743 bank = g->mux_bank; 744 reg = g->mux_reg; 745 } else { 746 bank = g->drv_bank; 747 reg = g->drv_reg; 748 } 749 750 val = pmx_readl(pmx, bank, reg); 751 val &= ~g->parked_bitmask; 752 pmx_writel(pmx, val, bank, reg); 753 } 754 } 755 } 756 757 static size_t tegra_pinctrl_get_bank_size(struct device *dev, 758 unsigned int bank_id) 759 { 760 struct platform_device *pdev = to_platform_device(dev); 761 struct resource *res; 762 763 res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id); 764 765 return resource_size(res) / 4; 766 } 767 768 static int tegra_pinctrl_suspend(struct device *dev) 769 { 770 struct tegra_pmx *pmx = dev_get_drvdata(dev); 771 u32 *backup_regs = pmx->backup_regs; 772 u32 __iomem *regs; 773 size_t bank_size; 774 unsigned int i, k; 775 776 for (i = 0; i < pmx->nbanks; i++) { 777 bank_size = tegra_pinctrl_get_bank_size(dev, i); 778 regs = pmx->regs[i]; 779 for (k = 0; k < bank_size; k++) 780 *backup_regs++ = readl_relaxed(regs++); 781 } 782 783 return pinctrl_force_sleep(pmx->pctl); 784 } 785 786 static int tegra_pinctrl_resume(struct device *dev) 787 { 788 struct tegra_pmx *pmx = dev_get_drvdata(dev); 789 u32 *backup_regs = pmx->backup_regs; 790 u32 __iomem *regs; 791 size_t bank_size; 792 unsigned int i, k; 793 794 for (i = 0; i < pmx->nbanks; i++) { 795 bank_size = tegra_pinctrl_get_bank_size(dev, i); 796 regs = pmx->regs[i]; 797 for (k = 0; k < bank_size; k++) 798 writel_relaxed(*backup_regs++, regs++); 799 } 800 801 /* flush all the prior writes */ 802 readl_relaxed(pmx->regs[0]); 803 /* wait for pinctrl register read to complete */ 804 rmb(); 805 return 0; 806 } 807 808 DEFINE_NOIRQ_DEV_PM_OPS(tegra_pinctrl_pm, tegra_pinctrl_suspend, tegra_pinctrl_resume); 809 810 static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx) 811 { 812 struct device_node *np; 813 bool has_prop = false; 814 815 np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible); 816 if (!np) 817 return has_prop; 818 819 has_prop = of_find_property(np, "gpio-ranges", NULL); 820 821 of_node_put(np); 822 823 return has_prop; 824 } 825 826 int tegra_pinctrl_probe(struct platform_device *pdev, 827 const struct tegra_pinctrl_soc_data *soc_data) 828 { 829 struct tegra_pmx *pmx; 830 struct resource *res; 831 int i; 832 const char **group_pins; 833 int fn, gn, gfn; 834 unsigned long backup_regs_size = 0; 835 836 pmx = devm_kzalloc(&pdev->dev, 837 struct_size(pmx, pingroup_configs, soc_data->ngroups), GFP_KERNEL); 838 if (!pmx) 839 return -ENOMEM; 840 841 pmx->dev = &pdev->dev; 842 pmx->soc = soc_data; 843 pmx->num_pingroup_configs = soc_data->ngroups; 844 845 /* 846 * Each mux group will appear in 4 functions' list of groups. 847 * This over-allocates slightly, since not all groups are mux groups. 848 */ 849 pmx->group_pins = devm_kcalloc(&pdev->dev, pmx->soc->ngroups * 4, 850 sizeof(*pmx->group_pins), GFP_KERNEL); 851 if (!pmx->group_pins) 852 return -ENOMEM; 853 854 pmx->functions = devm_kcalloc(&pdev->dev, pmx->soc->nfunctions, 855 sizeof(*pmx->functions), GFP_KERNEL); 856 if (!pmx->functions) 857 return -ENOMEM; 858 859 group_pins = pmx->group_pins; 860 861 for (fn = 0; fn < pmx->soc->nfunctions; fn++) { 862 struct tegra_function *func = &pmx->functions[fn]; 863 864 func->name = pmx->soc->functions[fn]; 865 func->groups = group_pins; 866 867 for (gn = 0; gn < pmx->soc->ngroups; gn++) { 868 const struct tegra_pingroup *g = &pmx->soc->groups[gn]; 869 870 if (g->mux_reg == -1) 871 continue; 872 873 for (gfn = 0; gfn < 4; gfn++) 874 if (g->funcs[gfn] == fn) 875 break; 876 if (gfn == 4) 877 continue; 878 879 BUG_ON(group_pins - pmx->group_pins >= 880 pmx->soc->ngroups * 4); 881 *group_pins++ = g->name; 882 func->ngroups++; 883 } 884 } 885 886 pmx->gpio_range.name = "Tegra GPIOs"; 887 pmx->gpio_range.id = 0; 888 pmx->gpio_range.base = 0; 889 pmx->gpio_range.npins = pmx->soc->ngpios; 890 891 pmx->desc.pctlops = &tegra_pinctrl_ops; 892 pmx->desc.pmxops = &tegra_pinmux_ops; 893 pmx->desc.confops = &tegra_pinconf_ops; 894 pmx->desc.owner = THIS_MODULE; 895 pmx->desc.name = dev_name(&pdev->dev); 896 pmx->desc.pins = pmx->soc->pins; 897 pmx->desc.npins = pmx->soc->npins; 898 899 for (i = 0; ; i++) { 900 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 901 if (!res) 902 break; 903 backup_regs_size += resource_size(res); 904 } 905 pmx->nbanks = i; 906 907 pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs), 908 GFP_KERNEL); 909 if (!pmx->regs) 910 return -ENOMEM; 911 912 pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size, 913 GFP_KERNEL); 914 if (!pmx->backup_regs) 915 return -ENOMEM; 916 917 for (i = 0; i < pmx->nbanks; i++) { 918 pmx->regs[i] = devm_platform_ioremap_resource(pdev, i); 919 if (IS_ERR(pmx->regs[i])) 920 return PTR_ERR(pmx->regs[i]); 921 } 922 923 pmx->pctl = devm_pinctrl_register(&pdev->dev, &pmx->desc, pmx); 924 if (IS_ERR(pmx->pctl)) { 925 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 926 return PTR_ERR(pmx->pctl); 927 } 928 929 tegra_pinctrl_clear_parked_bits(pmx); 930 931 if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx)) 932 pinctrl_add_gpio_range(pmx->pctl, &pmx->gpio_range); 933 934 platform_set_drvdata(pdev, pmx); 935 936 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n"); 937 938 return 0; 939 } 940 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe); 941