1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/io.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/phy/phy.h> 11 #include <linux/platform_device.h> 12 #include <linux/reset.h> 13 #include <linux/seq_file.h> 14 #include <linux/slab.h> 15 16 #include <linux/pinctrl/pinconf.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinmux.h> 19 20 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 21 22 #include "../core.h" 23 #include "../pinctrl-utils.h" 24 25 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c 26 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26) 27 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25) 28 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24) 29 30 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040 31 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19) 32 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12) 33 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) 34 35 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044 36 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6) 37 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5) 38 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4) 39 40 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138 41 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27) 42 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24) 43 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3) 44 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1) 45 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0) 46 47 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148 48 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1) 49 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0) 50 51 struct tegra_xusb_padctl_function { 52 const char *name; 53 const char * const *groups; 54 unsigned int num_groups; 55 }; 56 57 struct tegra_xusb_padctl_soc { 58 const struct pinctrl_pin_desc *pins; 59 unsigned int num_pins; 60 61 const struct tegra_xusb_padctl_function *functions; 62 unsigned int num_functions; 63 64 const struct tegra_xusb_padctl_lane *lanes; 65 unsigned int num_lanes; 66 }; 67 68 struct tegra_xusb_padctl_lane { 69 const char *name; 70 71 unsigned int offset; 72 unsigned int shift; 73 unsigned int mask; 74 unsigned int iddq; 75 76 const unsigned int *funcs; 77 unsigned int num_funcs; 78 }; 79 80 struct tegra_xusb_padctl { 81 struct device *dev; 82 void __iomem *regs; 83 struct mutex lock; 84 struct reset_control *rst; 85 86 const struct tegra_xusb_padctl_soc *soc; 87 struct pinctrl_dev *pinctrl; 88 struct pinctrl_desc desc; 89 90 struct phy_provider *provider; 91 struct phy *phys[2]; 92 93 unsigned int enable; 94 }; 95 96 static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value, 97 unsigned long offset) 98 { 99 writel(value, padctl->regs + offset); 100 } 101 102 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, 103 unsigned long offset) 104 { 105 return readl(padctl->regs + offset); 106 } 107 108 static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl) 109 { 110 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); 111 112 return padctl->soc->num_pins; 113 } 114 115 static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl, 116 unsigned int group) 117 { 118 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); 119 120 return padctl->soc->pins[group].name; 121 } 122 123 static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl, 124 unsigned group, 125 const unsigned **pins, 126 unsigned *num_pins) 127 { 128 /* 129 * For the tegra-xusb pad controller groups are synonymous 130 * with lanes/pins and there is always one lane/pin per group. 131 */ 132 *pins = &pinctrl->desc->pins[group].number; 133 *num_pins = 1; 134 135 return 0; 136 } 137 138 enum tegra_xusb_padctl_param { 139 TEGRA_XUSB_PADCTL_IDDQ, 140 }; 141 142 static const struct tegra_xusb_padctl_property { 143 const char *name; 144 enum tegra_xusb_padctl_param param; 145 } properties[] = { 146 { "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ }, 147 }; 148 149 #define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value)) 150 #define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16) 151 #define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff) 152 153 static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl, 154 struct device_node *np, 155 struct pinctrl_map **maps, 156 unsigned int *reserved_maps, 157 unsigned int *num_maps) 158 { 159 unsigned int i, reserve = 0, num_configs = 0; 160 unsigned long config, *configs = NULL; 161 const char *function, *group; 162 struct property *prop; 163 int err = 0; 164 u32 value; 165 166 err = of_property_read_string(np, "nvidia,function", &function); 167 if (err < 0) { 168 if (err != -EINVAL) 169 return err; 170 171 function = NULL; 172 } 173 174 for (i = 0; i < ARRAY_SIZE(properties); i++) { 175 err = of_property_read_u32(np, properties[i].name, &value); 176 if (err < 0) { 177 if (err == -EINVAL) 178 continue; 179 180 goto out; 181 } 182 183 config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value); 184 185 err = pinctrl_utils_add_config(padctl->pinctrl, &configs, 186 &num_configs, config); 187 if (err < 0) 188 goto out; 189 } 190 191 if (function) 192 reserve++; 193 194 if (num_configs) 195 reserve++; 196 197 err = of_property_count_strings(np, "nvidia,lanes"); 198 if (err < 0) 199 goto out; 200 201 reserve *= err; 202 203 err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps, 204 num_maps, reserve); 205 if (err < 0) 206 goto out; 207 208 of_property_for_each_string(np, "nvidia,lanes", prop, group) { 209 if (function) { 210 err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps, 211 reserved_maps, num_maps, group, 212 function); 213 if (err < 0) 214 goto out; 215 } 216 217 if (num_configs) { 218 err = pinctrl_utils_add_map_configs(padctl->pinctrl, 219 maps, reserved_maps, num_maps, group, 220 configs, num_configs, 221 PIN_MAP_TYPE_CONFIGS_GROUP); 222 if (err < 0) 223 goto out; 224 } 225 } 226 227 err = 0; 228 229 out: 230 kfree(configs); 231 return err; 232 } 233 234 static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl, 235 struct device_node *parent, 236 struct pinctrl_map **maps, 237 unsigned int *num_maps) 238 { 239 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); 240 unsigned int reserved_maps = 0; 241 int err; 242 243 *num_maps = 0; 244 *maps = NULL; 245 246 for_each_child_of_node_scoped(parent, np) { 247 err = tegra_xusb_padctl_parse_subnode(padctl, np, maps, 248 &reserved_maps, 249 num_maps); 250 if (err < 0) 251 return err; 252 } 253 254 return 0; 255 } 256 257 static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = { 258 .get_groups_count = tegra_xusb_padctl_get_groups_count, 259 .get_group_name = tegra_xusb_padctl_get_group_name, 260 .get_group_pins = tegra_xusb_padctl_get_group_pins, 261 .dt_node_to_map = tegra_xusb_padctl_dt_node_to_map, 262 .dt_free_map = pinctrl_utils_free_map, 263 }; 264 265 static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl) 266 { 267 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); 268 269 return padctl->soc->num_functions; 270 } 271 272 static const char * 273 tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl, 274 unsigned int function) 275 { 276 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); 277 278 return padctl->soc->functions[function].name; 279 } 280 281 static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl, 282 unsigned int function, 283 const char * const **groups, 284 unsigned * const num_groups) 285 { 286 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); 287 288 *num_groups = padctl->soc->functions[function].num_groups; 289 *groups = padctl->soc->functions[function].groups; 290 291 return 0; 292 } 293 294 static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl, 295 unsigned int function, 296 unsigned int group) 297 { 298 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); 299 const struct tegra_xusb_padctl_lane *lane; 300 unsigned int i; 301 u32 value; 302 303 lane = &padctl->soc->lanes[group]; 304 305 for (i = 0; i < lane->num_funcs; i++) 306 if (lane->funcs[i] == function) 307 break; 308 309 if (i >= lane->num_funcs) 310 return -EINVAL; 311 312 value = padctl_readl(padctl, lane->offset); 313 value &= ~(lane->mask << lane->shift); 314 value |= i << lane->shift; 315 padctl_writel(padctl, value, lane->offset); 316 317 return 0; 318 } 319 320 static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = { 321 .get_functions_count = tegra_xusb_padctl_get_functions_count, 322 .get_function_name = tegra_xusb_padctl_get_function_name, 323 .get_function_groups = tegra_xusb_padctl_get_function_groups, 324 .set_mux = tegra_xusb_padctl_pinmux_set, 325 }; 326 327 static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl, 328 unsigned int group, 329 unsigned long *config) 330 { 331 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); 332 const struct tegra_xusb_padctl_lane *lane; 333 enum tegra_xusb_padctl_param param; 334 u32 value; 335 336 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config); 337 lane = &padctl->soc->lanes[group]; 338 339 switch (param) { 340 case TEGRA_XUSB_PADCTL_IDDQ: 341 /* lanes with iddq == 0 don't support this parameter */ 342 if (lane->iddq == 0) 343 return -EINVAL; 344 345 value = padctl_readl(padctl, lane->offset); 346 347 if (value & BIT(lane->iddq)) 348 value = 0; 349 else 350 value = 1; 351 352 *config = TEGRA_XUSB_PADCTL_PACK(param, value); 353 break; 354 355 default: 356 dev_err(padctl->dev, "invalid configuration parameter: %04x\n", 357 param); 358 return -ENOTSUPP; 359 } 360 361 return 0; 362 } 363 364 static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl, 365 unsigned int group, 366 unsigned long *configs, 367 unsigned int num_configs) 368 { 369 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); 370 const struct tegra_xusb_padctl_lane *lane; 371 enum tegra_xusb_padctl_param param; 372 unsigned long value; 373 unsigned int i; 374 u32 regval; 375 376 lane = &padctl->soc->lanes[group]; 377 378 for (i = 0; i < num_configs; i++) { 379 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]); 380 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]); 381 382 switch (param) { 383 case TEGRA_XUSB_PADCTL_IDDQ: 384 /* lanes with iddq == 0 don't support this parameter */ 385 if (lane->iddq == 0) 386 return -EINVAL; 387 388 regval = padctl_readl(padctl, lane->offset); 389 390 if (value) 391 regval &= ~BIT(lane->iddq); 392 else 393 regval |= BIT(lane->iddq); 394 395 padctl_writel(padctl, regval, lane->offset); 396 break; 397 398 default: 399 dev_err(padctl->dev, 400 "invalid configuration parameter: %04x\n", 401 param); 402 return -ENOTSUPP; 403 } 404 } 405 406 return 0; 407 } 408 409 #ifdef CONFIG_DEBUG_FS 410 static const char *strip_prefix(const char *s) 411 { 412 const char *comma = strchr(s, ','); 413 if (!comma) 414 return s; 415 416 return comma + 1; 417 } 418 419 static void 420 tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl, 421 struct seq_file *s, 422 unsigned int group) 423 { 424 unsigned int i; 425 426 for (i = 0; i < ARRAY_SIZE(properties); i++) { 427 unsigned long config, value; 428 int err; 429 430 config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0); 431 432 err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group, 433 &config); 434 if (err < 0) 435 continue; 436 437 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config); 438 439 seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name), 440 value); 441 } 442 } 443 444 static void 445 tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl, 446 struct seq_file *s, 447 unsigned long config) 448 { 449 enum tegra_xusb_padctl_param param; 450 const char *name = "unknown"; 451 unsigned long value; 452 unsigned int i; 453 454 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config); 455 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config); 456 457 for (i = 0; i < ARRAY_SIZE(properties); i++) { 458 if (properties[i].param == param) { 459 name = properties[i].name; 460 break; 461 } 462 } 463 464 seq_printf(s, "%s=%lu", strip_prefix(name), value); 465 } 466 #endif 467 468 static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = { 469 .pin_config_group_get = tegra_xusb_padctl_pinconf_group_get, 470 .pin_config_group_set = tegra_xusb_padctl_pinconf_group_set, 471 #ifdef CONFIG_DEBUG_FS 472 .pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show, 473 .pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show, 474 #endif 475 }; 476 477 static void tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) 478 { 479 u32 value; 480 481 guard(mutex)(&padctl->lock); 482 483 if (padctl->enable++ > 0) 484 return; 485 486 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 487 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 488 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 489 490 usleep_range(100, 200); 491 492 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 493 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 494 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 495 496 usleep_range(100, 200); 497 498 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 499 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 500 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 501 } 502 503 static void tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) 504 { 505 u32 value; 506 507 guard(mutex)(&padctl->lock); 508 509 if (WARN_ON(padctl->enable == 0)) 510 return; 511 512 if (--padctl->enable > 0) 513 return; 514 515 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 516 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 517 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 518 519 usleep_range(100, 200); 520 521 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 522 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 523 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 524 525 usleep_range(100, 200); 526 527 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 528 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 529 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 530 } 531 532 static int tegra_xusb_phy_init(struct phy *phy) 533 { 534 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); 535 536 tegra_xusb_padctl_enable(padctl); 537 538 return 0; 539 } 540 541 static int tegra_xusb_phy_exit(struct phy *phy) 542 { 543 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); 544 545 tegra_xusb_padctl_disable(padctl); 546 547 return 0; 548 } 549 550 static int pcie_phy_power_on(struct phy *phy) 551 { 552 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); 553 unsigned long timeout; 554 int err = -ETIMEDOUT; 555 u32 value; 556 557 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 558 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK; 559 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 560 561 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); 562 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN | 563 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN | 564 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL; 565 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); 566 567 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 568 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; 569 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 570 571 timeout = jiffies + msecs_to_jiffies(50); 572 573 while (time_before(jiffies, timeout)) { 574 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 575 if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) { 576 err = 0; 577 break; 578 } 579 580 usleep_range(100, 200); 581 } 582 583 return err; 584 } 585 586 static int pcie_phy_power_off(struct phy *phy) 587 { 588 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); 589 u32 value; 590 591 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 592 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; 593 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 594 595 return 0; 596 } 597 598 static const struct phy_ops pcie_phy_ops = { 599 .init = tegra_xusb_phy_init, 600 .exit = tegra_xusb_phy_exit, 601 .power_on = pcie_phy_power_on, 602 .power_off = pcie_phy_power_off, 603 .owner = THIS_MODULE, 604 }; 605 606 static int sata_phy_power_on(struct phy *phy) 607 { 608 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); 609 unsigned long timeout; 610 int err = -ETIMEDOUT; 611 u32 value; 612 613 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 614 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; 615 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ; 616 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 617 618 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 619 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; 620 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ; 621 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 622 623 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 624 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE; 625 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 626 627 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 628 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST; 629 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 630 631 timeout = jiffies + msecs_to_jiffies(50); 632 633 while (time_before(jiffies, timeout)) { 634 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 635 if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) { 636 err = 0; 637 break; 638 } 639 640 usleep_range(100, 200); 641 } 642 643 return err; 644 } 645 646 static int sata_phy_power_off(struct phy *phy) 647 { 648 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); 649 u32 value; 650 651 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 652 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST; 653 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 654 655 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 656 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE; 657 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 658 659 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 660 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; 661 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ; 662 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 663 664 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 665 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; 666 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ; 667 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 668 669 return 0; 670 } 671 672 static const struct phy_ops sata_phy_ops = { 673 .init = tegra_xusb_phy_init, 674 .exit = tegra_xusb_phy_exit, 675 .power_on = sata_phy_power_on, 676 .power_off = sata_phy_power_off, 677 .owner = THIS_MODULE, 678 }; 679 680 static struct phy *tegra_xusb_padctl_xlate(struct device *dev, 681 const struct of_phandle_args *args) 682 { 683 struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev); 684 unsigned int index = args->args[0]; 685 686 if (args->args_count <= 0) 687 return ERR_PTR(-EINVAL); 688 689 if (index >= ARRAY_SIZE(padctl->phys)) 690 return ERR_PTR(-EINVAL); 691 692 return padctl->phys[index]; 693 } 694 695 #define PIN_OTG_0 0 696 #define PIN_OTG_1 1 697 #define PIN_OTG_2 2 698 #define PIN_ULPI_0 3 699 #define PIN_HSIC_0 4 700 #define PIN_HSIC_1 5 701 #define PIN_PCIE_0 6 702 #define PIN_PCIE_1 7 703 #define PIN_PCIE_2 8 704 #define PIN_PCIE_3 9 705 #define PIN_PCIE_4 10 706 #define PIN_SATA_0 11 707 708 static const struct pinctrl_pin_desc tegra124_pins[] = { 709 PINCTRL_PIN(PIN_OTG_0, "otg-0"), 710 PINCTRL_PIN(PIN_OTG_1, "otg-1"), 711 PINCTRL_PIN(PIN_OTG_2, "otg-2"), 712 PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"), 713 PINCTRL_PIN(PIN_HSIC_0, "hsic-0"), 714 PINCTRL_PIN(PIN_HSIC_1, "hsic-1"), 715 PINCTRL_PIN(PIN_PCIE_0, "pcie-0"), 716 PINCTRL_PIN(PIN_PCIE_1, "pcie-1"), 717 PINCTRL_PIN(PIN_PCIE_2, "pcie-2"), 718 PINCTRL_PIN(PIN_PCIE_3, "pcie-3"), 719 PINCTRL_PIN(PIN_PCIE_4, "pcie-4"), 720 PINCTRL_PIN(PIN_SATA_0, "sata-0"), 721 }; 722 723 static const char * const tegra124_snps_groups[] = { 724 "otg-0", 725 "otg-1", 726 "otg-2", 727 "ulpi-0", 728 "hsic-0", 729 "hsic-1", 730 }; 731 732 static const char * const tegra124_xusb_groups[] = { 733 "otg-0", 734 "otg-1", 735 "otg-2", 736 "ulpi-0", 737 "hsic-0", 738 "hsic-1", 739 }; 740 741 static const char * const tegra124_uart_groups[] = { 742 "otg-0", 743 "otg-1", 744 "otg-2", 745 }; 746 747 static const char * const tegra124_pcie_groups[] = { 748 "pcie-0", 749 "pcie-1", 750 "pcie-2", 751 "pcie-3", 752 "pcie-4", 753 }; 754 755 static const char * const tegra124_usb3_groups[] = { 756 "pcie-0", 757 "pcie-1", 758 "sata-0", 759 }; 760 761 static const char * const tegra124_sata_groups[] = { 762 "sata-0", 763 }; 764 765 static const char * const tegra124_rsvd_groups[] = { 766 "otg-0", 767 "otg-1", 768 "otg-2", 769 "pcie-0", 770 "pcie-1", 771 "pcie-2", 772 "pcie-3", 773 "pcie-4", 774 "sata-0", 775 }; 776 777 #define TEGRA124_FUNCTION(_name) \ 778 { \ 779 .name = #_name, \ 780 .num_groups = ARRAY_SIZE(tegra124_##_name##_groups), \ 781 .groups = tegra124_##_name##_groups, \ 782 } 783 784 static struct tegra_xusb_padctl_function tegra124_functions[] = { 785 TEGRA124_FUNCTION(snps), 786 TEGRA124_FUNCTION(xusb), 787 TEGRA124_FUNCTION(uart), 788 TEGRA124_FUNCTION(pcie), 789 TEGRA124_FUNCTION(usb3), 790 TEGRA124_FUNCTION(sata), 791 TEGRA124_FUNCTION(rsvd), 792 }; 793 794 enum tegra124_function { 795 TEGRA124_FUNC_SNPS, 796 TEGRA124_FUNC_XUSB, 797 TEGRA124_FUNC_UART, 798 TEGRA124_FUNC_PCIE, 799 TEGRA124_FUNC_USB3, 800 TEGRA124_FUNC_SATA, 801 TEGRA124_FUNC_RSVD, 802 }; 803 804 static const unsigned int tegra124_otg_functions[] = { 805 TEGRA124_FUNC_SNPS, 806 TEGRA124_FUNC_XUSB, 807 TEGRA124_FUNC_UART, 808 TEGRA124_FUNC_RSVD, 809 }; 810 811 static const unsigned int tegra124_usb_functions[] = { 812 TEGRA124_FUNC_SNPS, 813 TEGRA124_FUNC_XUSB, 814 }; 815 816 static const unsigned int tegra124_pci_functions[] = { 817 TEGRA124_FUNC_PCIE, 818 TEGRA124_FUNC_USB3, 819 TEGRA124_FUNC_SATA, 820 TEGRA124_FUNC_RSVD, 821 }; 822 823 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ 824 { \ 825 .name = _name, \ 826 .offset = _offset, \ 827 .shift = _shift, \ 828 .mask = _mask, \ 829 .iddq = _iddq, \ 830 .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \ 831 .funcs = tegra124_##_funcs##_functions, \ 832 } 833 834 static const struct tegra_xusb_padctl_lane tegra124_lanes[] = { 835 TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg), 836 TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg), 837 TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg), 838 TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb), 839 TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb), 840 TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb), 841 TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci), 842 TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci), 843 TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci), 844 TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci), 845 TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci), 846 TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci), 847 }; 848 849 static const struct tegra_xusb_padctl_soc tegra124_soc = { 850 .num_pins = ARRAY_SIZE(tegra124_pins), 851 .pins = tegra124_pins, 852 .num_functions = ARRAY_SIZE(tegra124_functions), 853 .functions = tegra124_functions, 854 .num_lanes = ARRAY_SIZE(tegra124_lanes), 855 .lanes = tegra124_lanes, 856 }; 857 858 static const struct of_device_id tegra_xusb_padctl_of_match[] = { 859 { .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc }, 860 { } 861 }; 862 MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match); 863 864 /* predeclare these in order to silence sparse */ 865 int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev); 866 int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev); 867 868 int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev) 869 { 870 struct tegra_xusb_padctl *padctl; 871 const struct of_device_id *match; 872 struct phy *phy; 873 int err; 874 875 padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL); 876 if (!padctl) 877 return -ENOMEM; 878 879 platform_set_drvdata(pdev, padctl); 880 mutex_init(&padctl->lock); 881 padctl->dev = &pdev->dev; 882 883 /* 884 * Note that we can't replace this by of_device_get_match_data() 885 * because we need the separate matching table for this legacy code on 886 * Tegra124. of_device_get_match_data() would attempt to use the table 887 * from the updated driver and fail. 888 */ 889 match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node); 890 padctl->soc = match->data; 891 892 padctl->regs = devm_platform_ioremap_resource(pdev, 0); 893 if (IS_ERR(padctl->regs)) 894 return PTR_ERR(padctl->regs); 895 896 padctl->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 897 if (IS_ERR(padctl->rst)) 898 return PTR_ERR(padctl->rst); 899 900 err = reset_control_deassert(padctl->rst); 901 if (err < 0) 902 return err; 903 904 memset(&padctl->desc, 0, sizeof(padctl->desc)); 905 padctl->desc.name = dev_name(padctl->dev); 906 padctl->desc.pins = tegra124_pins; 907 padctl->desc.npins = ARRAY_SIZE(tegra124_pins); 908 padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops; 909 padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops; 910 padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops; 911 padctl->desc.owner = THIS_MODULE; 912 913 padctl->pinctrl = devm_pinctrl_register(&pdev->dev, &padctl->desc, 914 padctl); 915 if (IS_ERR(padctl->pinctrl)) { 916 dev_err(&pdev->dev, "failed to register pincontrol\n"); 917 err = PTR_ERR(padctl->pinctrl); 918 goto reset; 919 } 920 921 phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops); 922 if (IS_ERR(phy)) { 923 err = PTR_ERR(phy); 924 goto reset; 925 } 926 927 padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy; 928 phy_set_drvdata(phy, padctl); 929 930 phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops); 931 if (IS_ERR(phy)) { 932 err = PTR_ERR(phy); 933 goto reset; 934 } 935 936 padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy; 937 phy_set_drvdata(phy, padctl); 938 939 padctl->provider = devm_of_phy_provider_register(&pdev->dev, 940 tegra_xusb_padctl_xlate); 941 if (IS_ERR(padctl->provider)) { 942 err = PTR_ERR(padctl->provider); 943 dev_err(&pdev->dev, "failed to register PHYs: %d\n", err); 944 goto reset; 945 } 946 947 return 0; 948 949 reset: 950 reset_control_assert(padctl->rst); 951 return err; 952 } 953 EXPORT_SYMBOL_GPL(tegra_xusb_padctl_legacy_probe); 954 955 int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev) 956 { 957 struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev); 958 int err; 959 960 err = reset_control_assert(padctl->rst); 961 if (err < 0) 962 dev_err(&pdev->dev, "failed to assert reset: %d\n", err); 963 964 return err; 965 } 966 EXPORT_SYMBOL_GPL(tegra_xusb_padctl_legacy_remove); 967