1 /* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #ifndef __PINCTRL_SUNXI_H 14 #define __PINCTRL_SUNXI_H 15 16 #include <linux/kernel.h> 17 #include <linux/spinlock.h> 18 19 #define PA_BASE 0 20 #define PB_BASE 32 21 #define PC_BASE 64 22 #define PD_BASE 96 23 #define PE_BASE 128 24 #define PF_BASE 160 25 #define PG_BASE 192 26 #define PH_BASE 224 27 #define PI_BASE 256 28 #define PL_BASE 352 29 #define PM_BASE 384 30 #define PN_BASE 416 31 32 #define SUNXI_PINCTRL_PIN(bank, pin) \ 33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin) 34 35 #define SUNXI_PIN_NAME_MAX_LEN 5 36 37 #define BANK_MEM_SIZE 0x24 38 #define MUX_REGS_OFFSET 0x0 39 #define DATA_REGS_OFFSET 0x10 40 #define DLEVEL_REGS_OFFSET 0x14 41 #define PULL_REGS_OFFSET 0x1c 42 43 #define PINS_PER_BANK 32 44 #define MUX_PINS_PER_REG 8 45 #define MUX_PINS_BITS 4 46 #define MUX_PINS_MASK 0x0f 47 #define DATA_PINS_PER_REG 32 48 #define DATA_PINS_BITS 1 49 #define DATA_PINS_MASK 0x01 50 #define DLEVEL_PINS_PER_REG 16 51 #define DLEVEL_PINS_BITS 2 52 #define DLEVEL_PINS_MASK 0x03 53 #define PULL_PINS_PER_REG 16 54 #define PULL_PINS_BITS 2 55 #define PULL_PINS_MASK 0x03 56 57 #define IRQ_PER_BANK 32 58 59 #define IRQ_CFG_REG 0x200 60 #define IRQ_CFG_IRQ_PER_REG 8 61 #define IRQ_CFG_IRQ_BITS 4 62 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1) 63 #define IRQ_CTRL_REG 0x210 64 #define IRQ_CTRL_IRQ_PER_REG 32 65 #define IRQ_CTRL_IRQ_BITS 1 66 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1) 67 #define IRQ_STATUS_REG 0x214 68 #define IRQ_STATUS_IRQ_PER_REG 32 69 #define IRQ_STATUS_IRQ_BITS 1 70 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) 71 72 #define IRQ_DEBOUNCE_REG 0x218 73 74 #define IRQ_MEM_SIZE 0x20 75 76 #define IRQ_EDGE_RISING 0x00 77 #define IRQ_EDGE_FALLING 0x01 78 #define IRQ_LEVEL_HIGH 0x02 79 #define IRQ_LEVEL_LOW 0x03 80 #define IRQ_EDGE_BOTH 0x04 81 82 #define SUN4I_FUNC_INPUT 0 83 #define SUN4I_FUNC_IRQ 6 84 85 #define PINCTRL_SUN5I_A10S BIT(1) 86 #define PINCTRL_SUN5I_A13 BIT(2) 87 #define PINCTRL_SUN5I_GR8 BIT(3) 88 #define PINCTRL_SUN6I_A31 BIT(4) 89 #define PINCTRL_SUN6I_A31S BIT(5) 90 #define PINCTRL_SUN4I_A10 BIT(6) 91 #define PINCTRL_SUN7I_A20 BIT(7) 92 #define PINCTRL_SUN8I_R40 BIT(8) 93 94 struct sunxi_desc_function { 95 unsigned long variant; 96 const char *name; 97 u8 muxval; 98 u8 irqbank; 99 u8 irqnum; 100 }; 101 102 struct sunxi_desc_pin { 103 struct pinctrl_pin_desc pin; 104 unsigned long variant; 105 struct sunxi_desc_function *functions; 106 }; 107 108 struct sunxi_pinctrl_desc { 109 const struct sunxi_desc_pin *pins; 110 int npins; 111 unsigned pin_base; 112 unsigned irq_banks; 113 const unsigned int *irq_bank_map; 114 bool irq_read_needs_mux; 115 bool disable_strict_mode; 116 }; 117 118 struct sunxi_pinctrl_function { 119 const char *name; 120 const char **groups; 121 unsigned ngroups; 122 }; 123 124 struct sunxi_pinctrl_group { 125 const char *name; 126 unsigned pin; 127 }; 128 129 struct sunxi_pinctrl { 130 void __iomem *membase; 131 struct gpio_chip *chip; 132 const struct sunxi_pinctrl_desc *desc; 133 struct device *dev; 134 struct irq_domain *domain; 135 struct sunxi_pinctrl_function *functions; 136 unsigned nfunctions; 137 struct sunxi_pinctrl_group *groups; 138 unsigned ngroups; 139 int *irq; 140 unsigned *irq_array; 141 raw_spinlock_t lock; 142 struct pinctrl_dev *pctl_dev; 143 unsigned long variant; 144 }; 145 146 #define SUNXI_PIN(_pin, ...) \ 147 { \ 148 .pin = _pin, \ 149 .functions = (struct sunxi_desc_function[]){ \ 150 __VA_ARGS__, { } }, \ 151 } 152 153 #define SUNXI_PIN_VARIANT(_pin, _variant, ...) \ 154 { \ 155 .pin = _pin, \ 156 .variant = _variant, \ 157 .functions = (struct sunxi_desc_function[]){ \ 158 __VA_ARGS__, { } }, \ 159 } 160 161 #define SUNXI_FUNCTION(_val, _name) \ 162 { \ 163 .name = _name, \ 164 .muxval = _val, \ 165 } 166 167 #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \ 168 { \ 169 .name = _name, \ 170 .muxval = _val, \ 171 .variant = _variant, \ 172 } 173 174 #define SUNXI_FUNCTION_IRQ(_val, _irq) \ 175 { \ 176 .name = "irq", \ 177 .muxval = _val, \ 178 .irqnum = _irq, \ 179 } 180 181 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \ 182 { \ 183 .name = "irq", \ 184 .muxval = _val, \ 185 .irqbank = _bank, \ 186 .irqnum = _irq, \ 187 } 188 189 /* 190 * The sunXi PIO registers are organized as is: 191 * 0x00 - 0x0c Muxing values. 192 * 8 pins per register, each pin having a 4bits value 193 * 0x10 Pin values 194 * 32 bits per register, each pin corresponding to one bit 195 * 0x14 - 0x18 Drive level 196 * 16 pins per register, each pin having a 2bits value 197 * 0x1c - 0x20 Pull-Up values 198 * 16 pins per register, each pin having a 2bits value 199 * 200 * This is for the first bank. Each bank will have the same layout, 201 * with an offset being a multiple of 0x24. 202 * 203 * The following functions calculate from the pin number the register 204 * and the bit offset that we should access. 205 */ 206 static inline u32 sunxi_mux_reg(u16 pin) 207 { 208 u8 bank = pin / PINS_PER_BANK; 209 u32 offset = bank * BANK_MEM_SIZE; 210 offset += MUX_REGS_OFFSET; 211 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04; 212 return round_down(offset, 4); 213 } 214 215 static inline u32 sunxi_mux_offset(u16 pin) 216 { 217 u32 pin_num = pin % MUX_PINS_PER_REG; 218 return pin_num * MUX_PINS_BITS; 219 } 220 221 static inline u32 sunxi_data_reg(u16 pin) 222 { 223 u8 bank = pin / PINS_PER_BANK; 224 u32 offset = bank * BANK_MEM_SIZE; 225 offset += DATA_REGS_OFFSET; 226 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04; 227 return round_down(offset, 4); 228 } 229 230 static inline u32 sunxi_data_offset(u16 pin) 231 { 232 u32 pin_num = pin % DATA_PINS_PER_REG; 233 return pin_num * DATA_PINS_BITS; 234 } 235 236 static inline u32 sunxi_dlevel_reg(u16 pin) 237 { 238 u8 bank = pin / PINS_PER_BANK; 239 u32 offset = bank * BANK_MEM_SIZE; 240 offset += DLEVEL_REGS_OFFSET; 241 offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04; 242 return round_down(offset, 4); 243 } 244 245 static inline u32 sunxi_dlevel_offset(u16 pin) 246 { 247 u32 pin_num = pin % DLEVEL_PINS_PER_REG; 248 return pin_num * DLEVEL_PINS_BITS; 249 } 250 251 static inline u32 sunxi_pull_reg(u16 pin) 252 { 253 u8 bank = pin / PINS_PER_BANK; 254 u32 offset = bank * BANK_MEM_SIZE; 255 offset += PULL_REGS_OFFSET; 256 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04; 257 return round_down(offset, 4); 258 } 259 260 static inline u32 sunxi_pull_offset(u16 pin) 261 { 262 u32 pin_num = pin % PULL_PINS_PER_REG; 263 return pin_num * PULL_PINS_BITS; 264 } 265 266 static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank) 267 { 268 if (!desc->irq_bank_map) 269 return bank; 270 else 271 return desc->irq_bank_map[bank]; 272 } 273 274 static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc, 275 u16 irq) 276 { 277 u8 bank = irq / IRQ_PER_BANK; 278 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04; 279 280 return IRQ_CFG_REG + 281 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg; 282 } 283 284 static inline u32 sunxi_irq_cfg_offset(u16 irq) 285 { 286 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG; 287 return irq_num * IRQ_CFG_IRQ_BITS; 288 } 289 290 static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) 291 { 292 return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; 293 } 294 295 static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc, 296 u16 irq) 297 { 298 u8 bank = irq / IRQ_PER_BANK; 299 300 return sunxi_irq_ctrl_reg_from_bank(desc, bank); 301 } 302 303 static inline u32 sunxi_irq_ctrl_offset(u16 irq) 304 { 305 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG; 306 return irq_num * IRQ_CTRL_IRQ_BITS; 307 } 308 309 static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) 310 { 311 return IRQ_DEBOUNCE_REG + 312 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; 313 } 314 315 static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) 316 { 317 return IRQ_STATUS_REG + 318 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; 319 } 320 321 static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc, 322 u16 irq) 323 { 324 u8 bank = irq / IRQ_PER_BANK; 325 326 return sunxi_irq_status_reg_from_bank(desc, bank); 327 } 328 329 static inline u32 sunxi_irq_status_offset(u16 irq) 330 { 331 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG; 332 return irq_num * IRQ_STATUS_IRQ_BITS; 333 } 334 335 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, 336 const struct sunxi_pinctrl_desc *desc, 337 unsigned long variant); 338 339 #define sunxi_pinctrl_init(_dev, _desc) \ 340 sunxi_pinctrl_init_with_variant(_dev, _desc, 0) 341 342 #endif /* __PINCTRL_SUNXI_H */ 343