1 /* 2 * Allwinner H3 SoCs pinctrl driver. 3 * 4 * Copyright (C) 2016 Krzysztof Adamski <k@japko.eu> 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/of.h> 14 #include <linux/pinctrl/pinctrl.h> 15 16 #include "pinctrl-sunxi.h" 17 18 static const struct sunxi_desc_pin sun8i_h3_r_pins[] = { 19 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), 20 SUNXI_FUNCTION(0x0, "gpio_in"), 21 SUNXI_FUNCTION(0x1, "gpio_out"), 22 SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */ 23 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */ 24 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), 25 SUNXI_FUNCTION(0x0, "gpio_in"), 26 SUNXI_FUNCTION(0x1, "gpio_out"), 27 SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */ 28 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */ 29 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), 30 SUNXI_FUNCTION(0x0, "gpio_in"), 31 SUNXI_FUNCTION(0x1, "gpio_out"), 32 SUNXI_FUNCTION(0x2, "s_uart"), /* TX */ 33 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */ 34 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3), 35 SUNXI_FUNCTION(0x0, "gpio_in"), 36 SUNXI_FUNCTION(0x1, "gpio_out"), 37 SUNXI_FUNCTION(0x2, "s_uart"), /* RX */ 38 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */ 39 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4), 40 SUNXI_FUNCTION(0x0, "gpio_in"), 41 SUNXI_FUNCTION(0x1, "gpio_out"), 42 SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */ 43 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */ 44 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), 45 SUNXI_FUNCTION(0x0, "gpio_in"), 46 SUNXI_FUNCTION(0x1, "gpio_out"), 47 SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */ 48 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */ 49 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), 50 SUNXI_FUNCTION(0x0, "gpio_in"), 51 SUNXI_FUNCTION(0x1, "gpio_out"), 52 SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */ 53 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */ 54 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), 55 SUNXI_FUNCTION(0x0, "gpio_in"), 56 SUNXI_FUNCTION(0x1, "gpio_out"), 57 SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */ 58 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */ 59 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), 60 SUNXI_FUNCTION(0x0, "gpio_in"), 61 SUNXI_FUNCTION(0x1, "gpio_out"), 62 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */ 63 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9), 64 SUNXI_FUNCTION(0x0, "gpio_in"), 65 SUNXI_FUNCTION(0x1, "gpio_out"), 66 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */ 67 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10), 68 SUNXI_FUNCTION(0x0, "gpio_in"), 69 SUNXI_FUNCTION(0x1, "gpio_out"), 70 SUNXI_FUNCTION(0x2, "s_pwm"), 71 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */ 72 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11), 73 SUNXI_FUNCTION(0x0, "gpio_in"), 74 SUNXI_FUNCTION(0x1, "gpio_out"), 75 SUNXI_FUNCTION(0x2, "s_cir_rx"), 76 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */ 77 }; 78 79 static const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_data = { 80 .pins = sun8i_h3_r_pins, 81 .npins = ARRAY_SIZE(sun8i_h3_r_pins), 82 .irq_banks = 1, 83 .pin_base = PL_BASE, 84 .irq_read_needs_mux = true, 85 .disable_strict_mode = true, 86 }; 87 88 static int sun8i_h3_r_pinctrl_probe(struct platform_device *pdev) 89 { 90 return sunxi_pinctrl_init(pdev, 91 &sun8i_h3_r_pinctrl_data); 92 } 93 94 static const struct of_device_id sun8i_h3_r_pinctrl_match[] = { 95 { .compatible = "allwinner,sun8i-h3-r-pinctrl", }, 96 {} 97 }; 98 99 static struct platform_driver sun8i_h3_r_pinctrl_driver = { 100 .probe = sun8i_h3_r_pinctrl_probe, 101 .driver = { 102 .name = "sun8i-h3-r-pinctrl", 103 .of_match_table = sun8i_h3_r_pinctrl_match, 104 }, 105 }; 106 builtin_platform_driver(sun8i_h3_r_pinctrl_driver); 107