1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SP7021 Pin Controller Driver. 4 * Copyright (C) Sunplus Tech / Tibbo Tech. 5 */ 6 7 #include <linux/cleanup.h> 8 #include <linux/bitfield.h> 9 #include <linux/device.h> 10 #include <linux/err.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/init.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/overflow.h> 16 #include <linux/platform_device.h> 17 #include <linux/seq_file.h> 18 #include <linux/slab.h> 19 20 #include <linux/pinctrl/pinconf.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 #include <linux/pinctrl/pinmux.h> 23 24 #include <dt-bindings/pinctrl/sppctl-sp7021.h> 25 26 #include "../core.h" 27 #include "../pinctrl-utils.h" 28 29 #include "sppctl.h" 30 31 struct sppctl_gpio_chip { 32 void __iomem *gpioxt_base; /* MASTER, OE, OUT, IN, I_INV, O_INV, OD */ 33 void __iomem *first_base; /* GPIO_FIRST */ 34 35 struct gpio_chip chip; 36 spinlock_t lock; /* lock for accessing OE register */ 37 }; 38 39 static inline u32 sppctl_first_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) 40 { 41 return readl(spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); 42 } 43 44 static inline void sppctl_first_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) 45 { 46 writel(val, spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); 47 } 48 49 static inline u32 sppctl_gpio_master_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) 50 { 51 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); 52 } 53 54 static inline void sppctl_gpio_master_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, 55 u32 off) 56 { 57 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); 58 } 59 60 static inline u32 sppctl_gpio_oe_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) 61 { 62 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off); 63 } 64 65 static inline void sppctl_gpio_oe_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) 66 { 67 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off); 68 } 69 70 static inline void sppctl_gpio_out_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) 71 { 72 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OUT + off); 73 } 74 75 static inline u32 sppctl_gpio_in_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) 76 { 77 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IN + off); 78 } 79 80 static inline u32 sppctl_gpio_iinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) 81 { 82 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off); 83 } 84 85 static inline void sppctl_gpio_iinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, 86 u32 off) 87 { 88 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off); 89 } 90 91 static inline u32 sppctl_gpio_oinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) 92 { 93 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off); 94 } 95 96 static inline void sppctl_gpio_oinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, 97 u32 off) 98 { 99 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off); 100 } 101 102 static inline u32 sppctl_gpio_od_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) 103 { 104 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off); 105 } 106 107 static inline void sppctl_gpio_od_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) 108 { 109 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off); 110 } 111 112 static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off) 113 { 114 u32 bit_off; 115 116 /* Each register has 32 bits. */ 117 *reg_off = (offset / 32) * 4; 118 bit_off = offset % 32; 119 120 return bit_off; 121 } 122 123 static inline u32 sppctl_get_moon_reg_and_bit_offset(unsigned int offset, u32 *reg_off) 124 { 125 u32 bit_off; 126 127 /* 128 * Each MOON register has 32 bits. Upper 16-bit word are mask-fields. 129 * The lower 16-bit word are the control-fields. The corresponding 130 * bits in mask-field should be set then you can write something to 131 * control-field. 132 */ 133 *reg_off = (offset / 16) * 4; 134 bit_off = offset % 16; 135 136 return bit_off; 137 } 138 139 static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_off, int val) 140 { 141 u32 bit_off; 142 143 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off); 144 if (val) 145 return SPPCTL_SET_MOON_REG_BIT(bit_off); 146 else 147 return SPPCTL_CLR_MOON_REG_BIT(bit_off); 148 } 149 150 /** 151 * sppctl_func_set() - Set pin of fully-pinmux function. 152 * @pctl: SP7021 pinctrl driver data 153 * @func: function number of the pinmux pin 154 * @val: value to write to the control-field 155 * 156 * Mask-fields and control-fields of the fully-pinmux function of 157 * SP7021 are arranged like this: 158 * 159 * func# | register | mask-field | control-field 160 * -------+----------+--------------+--------------- 161 * 0 | base[0] | (22 : 16) | ( 6 : 0) 162 * 1 | base[0] | (30 : 24) | (14 : 8) 163 * 2 | base[1] | (22 : 16) | ( 6 : 0) 164 * 3 | base[1] | (30 : 24) | (14 : 8) 165 * : | : | : | : 166 * 167 * where each mask-field protects its control-field from accidental 168 * writes. Set the corresponding bits in the mask-field when writing a 169 * value into a control-field. 170 * 171 * Control-fields are used to set where the function pin is going to 172 * be routed to. 173 * 174 * Note that mask-fields and control-fields of even number 'func's 175 * are located at bits (22:16) and (6:0), while odd number 'func's 176 * are located at bits (30:24) and (14:8). 177 */ 178 static void sppctl_func_set(struct sppctl_pdata *pctl, u8 func, u8 val) 179 { 180 u32 reg, offset; 181 182 /* 183 * Note that upper 16-bit word are mask-fields and lower 16-bit 184 * word are the control-fields. Set corresponding bits in mask- 185 * field before write to a control-field. 186 */ 187 reg = SPPCTL_FULLY_PINMUX_MASK_MASK | val; 188 189 /* 190 * MUXF_L2SW_CLK_OUT is the first fully-pinmux pin 191 * and its register offset is 0. 192 */ 193 func -= MUXF_L2SW_CLK_OUT; 194 195 /* 196 * Check if 'func' is an odd number or not. Mask and control- 197 * fields of odd number 'func' is located at upper portion of 198 * a register. Extra shift is needed. 199 */ 200 if (func & BIT(0)) 201 reg <<= SPPCTL_FULLY_PINMUX_UPPER_SHIFT; 202 203 /* Convert func# to register offset w.r.t. base register. */ 204 offset = func * 2; 205 offset &= GENMASK(31, 2); 206 207 writel(reg, pctl->moon2_base + offset); 208 } 209 210 /** 211 * sppctl_gmx_set() - Set pin of group-pinmux. 212 * @pctl: SP7021 pinctrl driver data 213 * @reg_off: register offset from the base register 214 * @bit_off: bit offset within the register 215 * @bit_sz: size of the control-field in bits 216 * @val: value to write to the control-field 217 * 218 * Mask-fields and control-fields of the group-pinmux function of 219 * SP7021 are arranged like this: 220 * 221 * register | mask-fields | control-fields 222 * ----------+--------------+---------------- 223 * base[0] | (31 : 16) | (15 : 0) 224 * base[1] | (31 : 24) | (15 : 0) 225 * base[2] | (31 : 24) | (15 : 0) 226 * : | : | : 227 * 228 * where each mask-field protects its control-field from accidental 229 * writes. Set the corresponding bits in the mask-field when writing a 230 * value into a control-field. 231 * 232 * Control-fields are used to set where the function pin is going to 233 * be routed to. A control-field consists of one or more bits. 234 */ 235 static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 bit_sz, 236 u8 val) 237 { 238 u32 mask, reg; 239 240 /* 241 * Note that upper 16-bit word are mask-fields and lower 16-bit 242 * word are the control-fields. Set corresponding bits in mask- 243 * field before write to a control-field. 244 */ 245 mask = GENMASK(bit_sz - 1, 0) << SPPCTL_MOON_REG_MASK_SHIFT; 246 reg = (mask | val) << bit_off; 247 248 writel(reg, pctl->moon1_base + reg_off * 4); 249 } 250 251 /** 252 * sppctl_first_get() - get bit of FIRST register. 253 * @chip: GPIO chip data 254 * @offset: pin offset within the GPIO chip 255 * 256 * There are 4 FIRST registers. Each has 32 control-bits. 257 * Totally, there are 4 * 32 = 128 control-bits. 258 * Control-bits are arranged as shown below: 259 * 260 * registers | control-bits 261 * -----------+-------------- 262 * first[0] | (31 : 0) 263 * first[1] | (63 : 32) 264 * first[2] | (95 : 64) 265 * first[3] | (127 : 96) 266 * 267 * Each control-bit sets type of a GPIO pin. 268 * 0: a fully-pinmux pin 269 * 1: a GPIO or IOP pin 270 */ 271 static int sppctl_first_get(struct gpio_chip *chip, unsigned int offset) 272 { 273 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 274 u32 reg_off, bit_off, reg; 275 276 bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); 277 reg = sppctl_first_readl(spp_gchip, reg_off); 278 279 return (reg & BIT(bit_off)) ? 1 : 0; 280 } 281 282 /** 283 * sppctl_master_get() - get bit of MASTER register. 284 * @chip: GPIO chip data 285 * @offset: pin offset within the GPIO chip 286 * 287 * There are 8 MASTER registers. Each has 16 mask-bits and 16 control-bits. 288 * Upper 16-bit of MASTER registers are mask-bits while lower 16-bit are 289 * control-bits. Totally, there are 128 mask-bits and 128 control-bits. 290 * They are arranged as shown below: 291 * 292 * register | mask-bits | control-bits 293 * -----------+-------------+-------------- 294 * master[0] | (15 : 0) | (15 : 0) 295 * master[1] | (31 : 16) | (31 : 16) 296 * master[2] | (47 : 32) | (47 : 32) 297 * : | : | : 298 * master[7] | (127 : 112) | (127 : 112) 299 * 300 * where each mask-field protects its control-field from accidental 301 * writes. Set the corresponding bits in the mask-field when writing a 302 * value into a control-field. 303 * 304 * Each control-bit sets type of a GPIO pin when FIRST bit is 1. 305 * 0: a IOP pin 306 * 1: a GPIO pin 307 */ 308 static int sppctl_master_get(struct gpio_chip *chip, unsigned int offset) 309 { 310 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 311 u32 reg_off, bit_off, reg; 312 313 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); 314 reg = sppctl_gpio_master_readl(spp_gchip, reg_off); 315 return (reg & BIT(bit_off)) ? 1 : 0; 316 } 317 318 static void sppctl_first_master_set(struct gpio_chip *chip, unsigned int offset, 319 enum mux_first_reg first, enum mux_master_reg master) 320 { 321 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 322 u32 reg_off, bit_off, reg; 323 enum mux_first_reg val; 324 325 /* FIRST register */ 326 if (first != mux_f_keep) { 327 bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); 328 reg = sppctl_first_readl(spp_gchip, reg_off); 329 val = (reg & BIT(bit_off)) ? mux_f_gpio : mux_f_mux; 330 331 if (first != val) 332 switch (first) { 333 case mux_f_gpio: 334 reg |= BIT(bit_off); 335 sppctl_first_writel(spp_gchip, reg, reg_off); 336 break; 337 338 case mux_f_mux: 339 reg &= ~BIT(bit_off); 340 sppctl_first_writel(spp_gchip, reg, reg_off); 341 break; 342 343 case mux_f_keep: 344 break; 345 } 346 } 347 348 /* MASTER register */ 349 if (master != mux_m_keep) { 350 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, (master == mux_m_gpio)); 351 sppctl_gpio_master_writel(spp_gchip, reg, reg_off); 352 } 353 } 354 355 static void sppctl_gpio_input_inv_set(struct gpio_chip *chip, unsigned int offset) 356 { 357 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 358 u32 reg_off, reg; 359 360 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); 361 sppctl_gpio_iinv_writel(spp_gchip, reg, reg_off); 362 } 363 364 static void sppctl_gpio_output_inv_set(struct gpio_chip *chip, unsigned int offset) 365 { 366 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 367 u32 reg_off, reg; 368 369 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); 370 sppctl_gpio_oinv_writel(spp_gchip, reg, reg_off); 371 } 372 373 static int sppctl_gpio_output_od_get(struct gpio_chip *chip, unsigned int offset) 374 { 375 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 376 u32 reg_off, bit_off, reg; 377 378 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); 379 reg = sppctl_gpio_od_readl(spp_gchip, reg_off); 380 381 return (reg & BIT(bit_off)) ? 1 : 0; 382 } 383 384 static void sppctl_gpio_output_od_set(struct gpio_chip *chip, unsigned int offset, 385 unsigned int val) 386 { 387 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 388 u32 reg_off, reg; 389 390 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val); 391 sppctl_gpio_od_writel(spp_gchip, reg, reg_off); 392 } 393 394 static int sppctl_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 395 { 396 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 397 u32 reg_off, bit_off, reg; 398 399 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); 400 reg = sppctl_gpio_oe_readl(spp_gchip, reg_off); 401 402 return (reg & BIT(bit_off)) ? 0 : 1; 403 } 404 405 static int sppctl_gpio_inv_get(struct gpio_chip *chip, unsigned int offset) 406 { 407 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 408 u32 reg_off, bit_off, reg; 409 unsigned long flags; 410 411 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); 412 413 spin_lock_irqsave(&spp_gchip->lock, flags); 414 415 if (sppctl_gpio_get_direction(chip, offset)) 416 reg = sppctl_gpio_iinv_readl(spp_gchip, reg_off); 417 else 418 reg = sppctl_gpio_oinv_readl(spp_gchip, reg_off); 419 420 spin_unlock_irqrestore(&spp_gchip->lock, flags); 421 422 return (reg & BIT(bit_off)) ? 1 : 0; 423 } 424 425 static int sppctl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 426 { 427 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 428 unsigned long flags; 429 u32 reg_off, reg; 430 431 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 0); 432 433 spin_lock_irqsave(&spp_gchip->lock, flags); 434 435 sppctl_gpio_oe_writel(spp_gchip, reg, reg_off); 436 437 spin_unlock_irqrestore(&spp_gchip->lock, flags); 438 return 0; 439 } 440 441 static int sppctl_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int val) 442 { 443 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 444 unsigned long flags; 445 u32 reg_off, reg; 446 447 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); 448 449 spin_lock_irqsave(&spp_gchip->lock, flags); 450 451 sppctl_gpio_oe_writel(spp_gchip, reg, reg_off); 452 453 if (val < 0) { 454 spin_unlock_irqrestore(&spp_gchip->lock, flags); 455 return 0; 456 } 457 458 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val); 459 sppctl_gpio_out_writel(spp_gchip, reg, reg_off); 460 461 spin_unlock_irqrestore(&spp_gchip->lock, flags); 462 return 0; 463 } 464 465 static int sppctl_gpio_get(struct gpio_chip *chip, unsigned int offset) 466 { 467 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 468 u32 reg_off, bit_off, reg; 469 470 bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); 471 reg = sppctl_gpio_in_readl(spp_gchip, reg_off); 472 473 return (reg & BIT(bit_off)) ? 1 : 0; 474 } 475 476 static int sppctl_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) 477 { 478 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 479 u32 reg_off, reg; 480 481 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val); 482 sppctl_gpio_out_writel(spp_gchip, reg, reg_off); 483 484 return 0; 485 } 486 487 static int sppctl_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 488 unsigned long config) 489 { 490 enum pin_config_param param = pinconf_to_config_param(config); 491 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 492 u32 reg_off, reg; 493 494 switch (param) { 495 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 496 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); 497 sppctl_gpio_od_writel(spp_gchip, reg, reg_off); 498 break; 499 500 case PIN_CONFIG_INPUT_ENABLE: 501 break; 502 503 case PIN_CONFIG_LEVEL: 504 return sppctl_gpio_direction_output(chip, offset, 0); 505 506 case PIN_CONFIG_PERSIST_STATE: 507 return -ENOTSUPP; 508 509 default: 510 return -EINVAL; 511 } 512 513 return 0; 514 } 515 516 static void sppctl_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 517 { 518 int i; 519 520 for (i = 0; i < chip->ngpio; i++) { 521 char *label __free(kfree) = gpiochip_dup_line_label(chip, i); 522 if (IS_ERR(label)) 523 continue; 524 525 seq_printf(s, " gpio-%03d (%-16.16s | %-16.16s)", i + chip->base, 526 chip->names[i], label ?: ""); 527 seq_printf(s, " %c", sppctl_gpio_get_direction(chip, i) ? 'I' : 'O'); 528 seq_printf(s, ":%d", sppctl_gpio_get(chip, i)); 529 seq_printf(s, " %s", sppctl_first_get(chip, i) ? "gpi" : "mux"); 530 seq_printf(s, " %s", sppctl_master_get(chip, i) ? "gpi" : "iop"); 531 seq_printf(s, " %s", sppctl_gpio_inv_get(chip, i) ? "inv" : " "); 532 seq_printf(s, " %s", sppctl_gpio_output_od_get(chip, i) ? "oDr" : ""); 533 seq_puts(s, "\n"); 534 } 535 } 536 537 static int sppctl_gpio_new(struct platform_device *pdev, struct sppctl_pdata *pctl) 538 { 539 struct sppctl_gpio_chip *spp_gchip; 540 struct gpio_chip *gchip; 541 int err; 542 543 spp_gchip = devm_kzalloc(&pdev->dev, sizeof(*spp_gchip), GFP_KERNEL); 544 if (!spp_gchip) 545 return -ENOMEM; 546 pctl->spp_gchip = spp_gchip; 547 548 spp_gchip->gpioxt_base = pctl->gpioxt_base; 549 spp_gchip->first_base = pctl->first_base; 550 spin_lock_init(&spp_gchip->lock); 551 552 gchip = &spp_gchip->chip; 553 gchip->label = SPPCTL_MODULE_NAME; 554 gchip->parent = &pdev->dev; 555 gchip->owner = THIS_MODULE; 556 gchip->request = gpiochip_generic_request; 557 gchip->free = gpiochip_generic_free; 558 gchip->get_direction = sppctl_gpio_get_direction; 559 gchip->direction_input = sppctl_gpio_direction_input; 560 gchip->direction_output = sppctl_gpio_direction_output; 561 gchip->get = sppctl_gpio_get; 562 gchip->set = sppctl_gpio_set; 563 gchip->set_config = sppctl_gpio_set_config; 564 gchip->dbg_show = IS_ENABLED(CONFIG_DEBUG_FS) ? 565 sppctl_gpio_dbg_show : NULL; 566 gchip->base = -1; 567 gchip->ngpio = sppctl_gpio_list_sz; 568 gchip->names = sppctl_gpio_list_s; 569 570 pctl->pctl_grange.npins = gchip->ngpio; 571 pctl->pctl_grange.name = gchip->label; 572 pctl->pctl_grange.gc = gchip; 573 574 err = devm_gpiochip_add_data(&pdev->dev, gchip, spp_gchip); 575 if (err) 576 return dev_err_probe(&pdev->dev, err, "Failed to add gpiochip!\n"); 577 578 return 0; 579 } 580 581 static int sppctl_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 582 unsigned long *config) 583 { 584 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 585 unsigned int param = pinconf_to_config_param(*config); 586 unsigned int arg; 587 588 switch (param) { 589 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 590 if (!sppctl_gpio_output_od_get(&pctl->spp_gchip->chip, pin)) 591 return -EINVAL; 592 arg = 0; 593 break; 594 595 case PIN_CONFIG_LEVEL: 596 if (!sppctl_first_get(&pctl->spp_gchip->chip, pin)) 597 return -EINVAL; 598 if (!sppctl_master_get(&pctl->spp_gchip->chip, pin)) 599 return -EINVAL; 600 if (sppctl_gpio_get_direction(&pctl->spp_gchip->chip, pin)) 601 return -EINVAL; 602 arg = sppctl_gpio_get(&pctl->spp_gchip->chip, pin); 603 break; 604 605 default: 606 return -EOPNOTSUPP; 607 } 608 *config = pinconf_to_config_packed(param, arg); 609 610 return 0; 611 } 612 613 static int sppctl_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 614 unsigned long *configs, unsigned int num_configs) 615 { 616 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 617 int i; 618 619 /* Special handling for IOP pins */ 620 if (configs[0] == SPPCTL_IOP_CONFIGS) { 621 sppctl_first_master_set(&pctl->spp_gchip->chip, pin, mux_f_gpio, mux_m_iop); 622 return 0; 623 } 624 625 for (i = 0; i < num_configs; i++) { 626 if (configs[i] & SPPCTL_PCTL_L_OUT) 627 sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 0); 628 if (configs[i] & SPPCTL_PCTL_L_OU1) 629 sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 1); 630 if (configs[i] & SPPCTL_PCTL_L_INV) 631 sppctl_gpio_input_inv_set(&pctl->spp_gchip->chip, pin); 632 if (configs[i] & SPPCTL_PCTL_L_ONV) 633 sppctl_gpio_output_inv_set(&pctl->spp_gchip->chip, pin); 634 if (configs[i] & SPPCTL_PCTL_L_ODR) 635 sppctl_gpio_output_od_set(&pctl->spp_gchip->chip, pin, 1); 636 } 637 638 return 0; 639 } 640 641 static const struct pinconf_ops sppctl_pconf_ops = { 642 .is_generic = true, 643 .pin_config_get = sppctl_pin_config_get, 644 .pin_config_set = sppctl_pin_config_set, 645 }; 646 647 static int sppctl_get_functions_count(struct pinctrl_dev *pctldev) 648 { 649 return sppctl_list_funcs_sz; 650 } 651 652 static const char *sppctl_get_function_name(struct pinctrl_dev *pctldev, 653 unsigned int selector) 654 { 655 return sppctl_list_funcs[selector].name; 656 } 657 658 static int sppctl_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, 659 const char * const **groups, unsigned int *num_groups) 660 { 661 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 662 const struct sppctl_func *f = &sppctl_list_funcs[selector]; 663 int i; 664 665 *num_groups = 0; 666 switch (f->type) { 667 case pinmux_type_fpmx: 668 *num_groups = sppctl_pmux_list_sz; 669 *groups = sppctl_pmux_list_s; 670 break; 671 672 case pinmux_type_grp: 673 if (!f->grps) 674 break; 675 676 *num_groups = f->gnum; 677 for (i = 0; i < pctl->unq_grps_sz; i++) 678 if (pctl->g2fp_maps[i].f_idx == selector) 679 break; 680 *groups = &pctl->unq_grps[i]; 681 break; 682 683 default: 684 dev_err(pctldev->dev, "Unknown pinmux (selector: %d, type: %d)\n", 685 selector, f->type); 686 break; 687 } 688 689 return 0; 690 } 691 692 /** 693 * sppctl_fully_pinmux_conv - Convert GPIO# to fully-pinmux control-field setting 694 * @offset: GPIO pin number to convert 695 * 696 * Each fully-pinmux function can be mapped to any of GPIO 8 ~ 71 by 697 * settings its control-field. Refer to following table: 698 * 699 * control-field | GPIO 700 * --------------+-------- 701 * 0 | No map 702 * 1 | 8 703 * 2 | 9 704 * 3 | 10 705 * : | : 706 * 65 | 71 707 */ 708 static inline int sppctl_fully_pinmux_conv(unsigned int offset) 709 { 710 return (offset < 8) ? 0 : offset - 7; 711 } 712 713 static int sppctl_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, 714 unsigned int group_selector) 715 { 716 const struct sppctl_func *f = &sppctl_list_funcs[func_selector]; 717 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 718 struct grp2fp_map g2fpm = pctl->g2fp_maps[group_selector]; 719 int i; 720 721 switch (f->type) { 722 case pinmux_type_fpmx: 723 sppctl_first_master_set(&pctl->spp_gchip->chip, group_selector, 724 mux_f_mux, mux_m_keep); 725 sppctl_func_set(pctl, func_selector, sppctl_fully_pinmux_conv(group_selector)); 726 break; 727 728 case pinmux_type_grp: 729 for (i = 0; i < f->grps[g2fpm.g_idx].pnum; i++) 730 sppctl_first_master_set(&pctl->spp_gchip->chip, 731 f->grps[g2fpm.g_idx].pins[i], 732 mux_f_mux, mux_m_keep); 733 sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, f->grps[g2fpm.g_idx].gval); 734 break; 735 736 default: 737 dev_err(pctldev->dev, "Unknown pinmux type (func_selector: %d, type: %d)\n", 738 func_selector, f->type); 739 break; 740 } 741 742 return 0; 743 } 744 745 static int sppctl_gpio_request_enable(struct pinctrl_dev *pctldev, 746 struct pinctrl_gpio_range *range, unsigned int offset) 747 { 748 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 749 int g_f, g_m; 750 751 g_f = sppctl_first_get(&pctl->spp_gchip->chip, offset); 752 g_m = sppctl_master_get(&pctl->spp_gchip->chip, offset); 753 if (g_f == mux_f_gpio && g_m == mux_m_gpio) 754 return 0; 755 756 sppctl_first_master_set(&pctl->spp_gchip->chip, offset, mux_f_gpio, mux_m_gpio); 757 return 0; 758 } 759 760 static const struct pinmux_ops sppctl_pinmux_ops = { 761 .get_functions_count = sppctl_get_functions_count, 762 .get_function_name = sppctl_get_function_name, 763 .get_function_groups = sppctl_get_function_groups, 764 .set_mux = sppctl_set_mux, 765 .gpio_request_enable = sppctl_gpio_request_enable, 766 .strict = true, 767 }; 768 769 static int sppctl_get_groups_count(struct pinctrl_dev *pctldev) 770 { 771 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 772 773 return pctl->unq_grps_sz; 774 } 775 776 static const char *sppctl_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector) 777 { 778 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 779 780 return pctl->unq_grps[selector]; 781 } 782 783 static int sppctl_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, 784 const unsigned int **pins, unsigned int *num_pins) 785 { 786 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 787 struct grp2fp_map g2fpm = pctl->g2fp_maps[selector]; 788 const struct sppctl_func *f; 789 790 f = &sppctl_list_funcs[g2fpm.f_idx]; 791 *num_pins = 0; 792 793 /* Except group-pinmux, each group has 1 pin. */ 794 if (f->type != pinmux_type_grp) { 795 *num_pins = 1; 796 *pins = &sppctl_pins_gpio[selector]; 797 return 0; 798 } 799 800 /* Group-pinmux may have more than one pin. */ 801 if (!f->grps) 802 return 0; 803 804 if (f->gnum < 1) 805 return 0; 806 807 *num_pins = f->grps[g2fpm.g_idx].pnum; 808 *pins = f->grps[g2fpm.g_idx].pins; 809 810 return 0; 811 } 812 813 #ifdef CONFIG_DEBUG_FS 814 static void sppctl_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 815 unsigned int offset) 816 { 817 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 818 const char *pin_type; 819 u8 first, master; 820 821 first = sppctl_first_get(&pctl->spp_gchip->chip, offset); 822 master = sppctl_master_get(&pctl->spp_gchip->chip, offset); 823 if (first) 824 if (master) 825 pin_type = "GPIO"; 826 else 827 pin_type = " IOP"; 828 else 829 pin_type = " MUX"; 830 seq_printf(s, " %s", pin_type); 831 } 832 #endif 833 834 static int sppctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config, 835 struct pinctrl_map **map, unsigned int *num_maps) 836 { 837 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 838 int nmG = of_property_count_strings(np_config, "groups"); 839 const struct sppctl_func *f = NULL; 840 u8 pin_num, pin_type, pin_func; 841 struct device_node *parent; 842 unsigned long *configs; 843 struct property *prop; 844 const char *s_f, *s_g; 845 846 const __be32 *list; 847 u32 dt_pin, dt_fun; 848 int i, size = 0; 849 850 list = of_get_property(np_config, "sunplus,pins", &size); 851 *num_maps = size / sizeof(*list); 852 853 /* 854 * Process property: 855 * sunplus,pins = < u32 u32 u32 ... >; 856 * 857 * Each 32-bit integer defines a individual pin in which: 858 * 859 * Bit 32~24: defines GPIO pin number. Its range is 0 ~ 98. 860 * Bit 23~16: defines types: (1) fully-pinmux pins 861 * (2) IO processor pins 862 * (3) digital GPIO pins 863 * Bit 15~8: defines pins of peripherals (which are defined in 864 * 'include/dt-binging/pinctrl/sppctl.h'). 865 * Bit 7~0: defines types or initial-state of digital GPIO pins. 866 */ 867 for (i = 0; i < (*num_maps); i++) { 868 dt_pin = be32_to_cpu(list[i]); 869 pin_num = FIELD_GET(GENMASK(31, 24), dt_pin); 870 871 if (pin_num >= sppctl_pins_all_sz) { 872 dev_err(pctldev->dev, "Invalid pin property at index %d (0x%08x)\n", 873 i, dt_pin); 874 return -EINVAL; 875 } 876 } 877 878 if (nmG <= 0) 879 nmG = 0; 880 881 *map = kzalloc_objs(**map, *num_maps + nmG); 882 if (!(*map)) 883 return -ENOMEM; 884 885 parent = of_get_parent(np_config); 886 for (i = 0; i < (*num_maps); i++) { 887 dt_pin = be32_to_cpu(list[i]); 888 pin_num = FIELD_GET(GENMASK(31, 24), dt_pin); 889 pin_type = FIELD_GET(GENMASK(23, 16), dt_pin); 890 pin_func = FIELD_GET(GENMASK(15, 8), dt_pin); 891 (*map)[i].name = parent->name; 892 893 if (pin_type == SPPCTL_PCTL_G_GPIO) { 894 /* A digital GPIO pin */ 895 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 896 (*map)[i].data.configs.num_configs = 1; 897 (*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num); 898 configs = kmalloc_obj(*configs); 899 if (!configs) 900 goto sppctl_map_err; 901 *configs = FIELD_GET(GENMASK(7, 0), dt_pin); 902 (*map)[i].data.configs.configs = configs; 903 904 dev_dbg(pctldev->dev, "%s: GPIO (%s)\n", 905 (*map)[i].data.configs.group_or_pin, 906 (*configs & (SPPCTL_PCTL_L_OUT | SPPCTL_PCTL_L_OU1)) ? 907 "OUT" : "IN"); 908 } else if (pin_type == SPPCTL_PCTL_G_IOPP) { 909 /* A IO Processor (IOP) pin */ 910 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 911 (*map)[i].data.configs.num_configs = 1; 912 (*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num); 913 configs = kmalloc_obj(*configs); 914 if (!configs) 915 goto sppctl_map_err; 916 *configs = SPPCTL_IOP_CONFIGS; 917 (*map)[i].data.configs.configs = configs; 918 919 dev_dbg(pctldev->dev, "%s: IOP\n", 920 (*map)[i].data.configs.group_or_pin); 921 } else { 922 /* A fully-pinmux pin */ 923 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 924 (*map)[i].data.mux.function = sppctl_list_funcs[pin_func].name; 925 (*map)[i].data.mux.group = pin_get_name(pctldev, pin_num); 926 927 dev_dbg(pctldev->dev, "%s: %s\n", (*map)[i].data.mux.group, 928 (*map)[i].data.mux.function); 929 } 930 } 931 932 /* 933 * Process properties: 934 * function = "xxx"; 935 * groups = "yyy"; 936 */ 937 if (nmG > 0 && of_property_read_string(np_config, "function", &s_f) == 0) { 938 of_property_for_each_string(np_config, "groups", prop, s_g) { 939 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 940 (*map)[*num_maps].data.mux.function = s_f; 941 (*map)[*num_maps].data.mux.group = s_g; 942 (*num_maps)++; 943 944 dev_dbg(pctldev->dev, "%s: %s\n", s_f, s_g); 945 } 946 } 947 948 /* 949 * Process property: 950 * sunplus,zerofunc = < u32 u32 u32 ...> 951 */ 952 list = of_get_property(np_config, "sunplus,zerofunc", &size); 953 if (list) { 954 for (i = 0; i < (size / sizeof(*list)); i++) { 955 dt_fun = be32_to_cpu(list[i]); 956 if (dt_fun >= sppctl_list_funcs_sz) { 957 dev_err(pctldev->dev, "Zero-func %d out of range!\n", 958 dt_fun); 959 continue; 960 } 961 962 f = &sppctl_list_funcs[dt_fun]; 963 switch (f->type) { 964 case pinmux_type_fpmx: 965 sppctl_func_set(pctl, dt_fun, 0); 966 dev_dbg(pctldev->dev, "%s: No map\n", f->name); 967 break; 968 969 case pinmux_type_grp: 970 sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, 0); 971 dev_dbg(pctldev->dev, "%s: No map\n", f->name); 972 break; 973 974 default: 975 dev_err(pctldev->dev, "Wrong zero-group: %d (%s)\n", 976 dt_fun, f->name); 977 break; 978 } 979 } 980 } 981 982 of_node_put(parent); 983 dev_dbg(pctldev->dev, "%d pins mapped\n", *num_maps); 984 return 0; 985 986 sppctl_map_err: 987 for (i = 0; i < (*num_maps); i++) 988 if ((*map)[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 989 kfree((*map)[i].data.configs.configs); 990 kfree(*map); 991 of_node_put(parent); 992 return -ENOMEM; 993 } 994 995 static const struct pinctrl_ops sppctl_pctl_ops = { 996 .get_groups_count = sppctl_get_groups_count, 997 .get_group_name = sppctl_get_group_name, 998 .get_group_pins = sppctl_get_group_pins, 999 #ifdef CONFIG_DEBUG_FS 1000 .pin_dbg_show = sppctl_pin_dbg_show, 1001 #endif 1002 .dt_node_to_map = sppctl_dt_node_to_map, 1003 .dt_free_map = pinctrl_utils_free_map, 1004 }; 1005 1006 static int sppctl_group_groups(struct platform_device *pdev) 1007 { 1008 struct sppctl_pdata *sppctl = platform_get_drvdata(pdev); 1009 int i, k, j; 1010 1011 /* Calculate number of total group (GPIO + group-pinmux group). */ 1012 sppctl->unq_grps_sz = sppctl_gpio_list_sz; 1013 for (i = 0; i < sppctl_list_funcs_sz; i++) 1014 if (sppctl_list_funcs[i].type == pinmux_type_grp) 1015 sppctl->unq_grps_sz += sppctl_list_funcs[i].gnum; 1016 1017 sppctl->unq_grps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1, 1018 sizeof(*sppctl->unq_grps), GFP_KERNEL); 1019 if (!sppctl->unq_grps) 1020 return -ENOMEM; 1021 1022 sppctl->g2fp_maps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1, 1023 sizeof(*sppctl->g2fp_maps), GFP_KERNEL); 1024 if (!sppctl->g2fp_maps) 1025 return -ENOMEM; 1026 1027 /* Add GPIO pins. */ 1028 for (i = 0; i < sppctl_gpio_list_sz; i++) { 1029 sppctl->unq_grps[i] = sppctl_gpio_list_s[i]; 1030 sppctl->g2fp_maps[i].f_idx = 0; 1031 sppctl->g2fp_maps[i].g_idx = i; 1032 } 1033 1034 /* Add group-pinmux to end of GPIO pins. */ 1035 j = sppctl_gpio_list_sz; 1036 for (i = 0; i < sppctl_list_funcs_sz; i++) { 1037 if (sppctl_list_funcs[i].type != pinmux_type_grp) 1038 continue; 1039 1040 for (k = 0; k < sppctl_list_funcs[i].gnum; k++) { 1041 sppctl->unq_grps[j] = sppctl_list_funcs[i].grps[k].name; 1042 sppctl->g2fp_maps[j].f_idx = i; 1043 sppctl->g2fp_maps[j].g_idx = k; 1044 j++; 1045 } 1046 } 1047 1048 return 0; 1049 } 1050 1051 static int sppctl_pinctrl_init(struct platform_device *pdev) 1052 { 1053 struct sppctl_pdata *sppctl = platform_get_drvdata(pdev); 1054 int err; 1055 1056 sppctl->pctl_desc.owner = THIS_MODULE; 1057 sppctl->pctl_desc.name = dev_name(&pdev->dev); 1058 sppctl->pctl_desc.pins = sppctl_pins_all; 1059 sppctl->pctl_desc.npins = sppctl_pins_all_sz; 1060 sppctl->pctl_desc.pctlops = &sppctl_pctl_ops; 1061 sppctl->pctl_desc.confops = &sppctl_pconf_ops; 1062 sppctl->pctl_desc.pmxops = &sppctl_pinmux_ops; 1063 1064 err = sppctl_group_groups(pdev); 1065 if (err) 1066 return err; 1067 1068 err = devm_pinctrl_register_and_init(&pdev->dev, &sppctl->pctl_desc, 1069 sppctl, &sppctl->pctl_dev); 1070 if (err) 1071 return dev_err_probe(&pdev->dev, err, "Failed to register pinctrl!\n"); 1072 1073 pinctrl_enable(sppctl->pctl_dev); 1074 return 0; 1075 } 1076 1077 static int sppctl_resource_map(struct platform_device *pdev, struct sppctl_pdata *sppctl) 1078 { 1079 sppctl->moon2_base = devm_platform_ioremap_resource_byname(pdev, "moon2"); 1080 if (IS_ERR(sppctl->moon2_base)) 1081 return PTR_ERR(sppctl->moon2_base); 1082 1083 sppctl->gpioxt_base = devm_platform_ioremap_resource_byname(pdev, "gpioxt"); 1084 if (IS_ERR(sppctl->gpioxt_base)) 1085 return PTR_ERR(sppctl->gpioxt_base); 1086 1087 sppctl->first_base = devm_platform_ioremap_resource_byname(pdev, "first"); 1088 if (IS_ERR(sppctl->first_base)) 1089 return PTR_ERR(sppctl->first_base); 1090 1091 sppctl->moon1_base = devm_platform_ioremap_resource_byname(pdev, "moon1"); 1092 if (IS_ERR(sppctl->moon1_base)) 1093 return PTR_ERR(sppctl->moon1_base); 1094 1095 return 0; 1096 } 1097 1098 static int sppctl_probe(struct platform_device *pdev) 1099 { 1100 struct sppctl_pdata *sppctl; 1101 int ret; 1102 1103 sppctl = devm_kzalloc(&pdev->dev, sizeof(*sppctl), GFP_KERNEL); 1104 if (!sppctl) 1105 return -ENOMEM; 1106 platform_set_drvdata(pdev, sppctl); 1107 1108 ret = sppctl_resource_map(pdev, sppctl); 1109 if (ret) 1110 return ret; 1111 1112 ret = sppctl_gpio_new(pdev, sppctl); 1113 if (ret) 1114 return ret; 1115 1116 ret = sppctl_pinctrl_init(pdev); 1117 if (ret) 1118 return ret; 1119 1120 pinctrl_add_gpio_range(sppctl->pctl_dev, &sppctl->pctl_grange); 1121 1122 return 0; 1123 } 1124 1125 static const struct of_device_id sppctl_match_table[] = { 1126 { .compatible = "sunplus,sp7021-pctl" }, 1127 { /* sentinel */ } 1128 }; 1129 1130 static struct platform_driver sppctl_pinctrl_driver = { 1131 .driver = { 1132 .name = SPPCTL_MODULE_NAME, 1133 .of_match_table = sppctl_match_table, 1134 }, 1135 .probe = sppctl_probe, 1136 }; 1137 builtin_platform_driver(sppctl_pinctrl_driver) 1138 1139 MODULE_AUTHOR("Dvorkin Dmitry <dvorkin@tibbo.com>"); 1140 MODULE_AUTHOR("Wells Lu <wellslutw@gmail.com>"); 1141 MODULE_DESCRIPTION("Sunplus SP7021 Pin Control and GPIO driver"); 1142 MODULE_LICENSE("GPL v2"); 1143