1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SP7021 Pin Controller Driver. 4 * Copyright (C) Sunplus Tech / Tibbo Tech. 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/device.h> 9 #include <linux/err.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/init.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/overflow.h> 16 #include <linux/platform_device.h> 17 #include <linux/seq_file.h> 18 #include <linux/slab.h> 19 20 #include <linux/pinctrl/pinconf.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 #include <linux/pinctrl/pinmux.h> 23 24 #include <dt-bindings/pinctrl/sppctl-sp7021.h> 25 26 #include "../core.h" 27 #include "../pinctrl-utils.h" 28 29 #include "sppctl.h" 30 31 struct sppctl_gpio_chip { 32 void __iomem *gpioxt_base; /* MASTER, OE, OUT, IN, I_INV, O_INV, OD */ 33 void __iomem *first_base; /* GPIO_FIRST */ 34 35 struct gpio_chip chip; 36 spinlock_t lock; /* lock for accessing OE register */ 37 }; 38 39 static inline u32 sppctl_first_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) 40 { 41 return readl(spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); 42 } 43 44 static inline void sppctl_first_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) 45 { 46 writel(val, spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); 47 } 48 49 static inline u32 sppctl_gpio_master_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) 50 { 51 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); 52 } 53 54 static inline void sppctl_gpio_master_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, 55 u32 off) 56 { 57 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); 58 } 59 60 static inline u32 sppctl_gpio_oe_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) 61 { 62 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off); 63 } 64 65 static inline void sppctl_gpio_oe_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) 66 { 67 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off); 68 } 69 70 static inline void sppctl_gpio_out_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) 71 { 72 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OUT + off); 73 } 74 75 static inline u32 sppctl_gpio_in_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) 76 { 77 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IN + off); 78 } 79 80 static inline u32 sppctl_gpio_iinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) 81 { 82 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off); 83 } 84 85 static inline void sppctl_gpio_iinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, 86 u32 off) 87 { 88 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off); 89 } 90 91 static inline u32 sppctl_gpio_oinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) 92 { 93 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off); 94 } 95 96 static inline void sppctl_gpio_oinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, 97 u32 off) 98 { 99 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off); 100 } 101 102 static inline u32 sppctl_gpio_od_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) 103 { 104 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off); 105 } 106 107 static inline void sppctl_gpio_od_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) 108 { 109 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off); 110 } 111 112 static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off) 113 { 114 u32 bit_off; 115 116 /* Each register has 32 bits. */ 117 *reg_off = (offset / 32) * 4; 118 bit_off = offset % 32; 119 120 return bit_off; 121 } 122 123 static inline u32 sppctl_get_moon_reg_and_bit_offset(unsigned int offset, u32 *reg_off) 124 { 125 u32 bit_off; 126 127 /* 128 * Each MOON register has 32 bits. Upper 16-bit word are mask-fields. 129 * The lower 16-bit word are the control-fields. The corresponding 130 * bits in mask-field should be set then you can write something to 131 * control-field. 132 */ 133 *reg_off = (offset / 16) * 4; 134 bit_off = offset % 16; 135 136 return bit_off; 137 } 138 139 static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_off, int val) 140 { 141 u32 bit_off; 142 143 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off); 144 if (val) 145 return SPPCTL_SET_MOON_REG_BIT(bit_off); 146 else 147 return SPPCTL_CLR_MOON_REG_BIT(bit_off); 148 } 149 150 /** 151 * sppctl_func_set() - Set pin of fully-pinmux function. 152 * 153 * Mask-fields and control-fields of fully-pinmux function of SP7021 are 154 * arranged as shown below: 155 * 156 * func# | register | mask-field | control-field 157 * -------+----------+--------------+--------------- 158 * 0 | base[0] | (22 : 16) | ( 6 : 0) 159 * 1 | base[0] | (30 : 24) | (14 : 8) 160 * 2 | base[1] | (22 : 16) | ( 6 : 0) 161 * 3 | baeg[1] | (30 : 24) | (14 : 8) 162 * : | : | : | : 163 * 164 * where mask-fields are used to protect control-fields from write-in 165 * accidentally. Set the corresponding bits in the mask-field before 166 * you write a value into a control-field. 167 * 168 * Control-fields are used to set where the function pin is going to 169 * be routed to. 170 * 171 * Note that mask-fields and control-fields of even number of 'func' 172 * are located at bits (22:16) and (6:0), while odd number of 'func's 173 * are located at bits (30:24) and (14:8). 174 */ 175 static void sppctl_func_set(struct sppctl_pdata *pctl, u8 func, u8 val) 176 { 177 u32 reg, offset; 178 179 /* 180 * Note that upper 16-bit word are mask-fields and lower 16-bit 181 * word are the control-fields. Set corresponding bits in mask- 182 * field before write to a control-field. 183 */ 184 reg = SPPCTL_FULLY_PINMUX_MASK_MASK | val; 185 186 /* 187 * MUXF_L2SW_CLK_OUT is the first fully-pinmux pin 188 * and its register offset is 0. 189 */ 190 func -= MUXF_L2SW_CLK_OUT; 191 192 /* 193 * Check if 'func' is an odd number or not. Mask and control- 194 * fields of odd number 'func' is located at upper portion of 195 * a register. Extra shift is needed. 196 */ 197 if (func & BIT(0)) 198 reg <<= SPPCTL_FULLY_PINMUX_UPPER_SHIFT; 199 200 /* Convert func# to register offset w.r.t. base register. */ 201 offset = func * 2; 202 offset &= GENMASK(31, 2); 203 204 writel(reg, pctl->moon2_base + offset); 205 } 206 207 /** 208 * sppctl_gmx_set() - Set pin of group-pinmux. 209 * 210 * Mask-fields and control-fields of group-pinmux function of SP7021 are 211 * arranged as shown below: 212 * 213 * register | mask-fields | control-fields 214 * ----------+--------------+---------------- 215 * base[0] | (31 : 16) | (15 : 0) 216 * base[1] | (31 : 24) | (15 : 0) 217 * base[2] | (31 : 24) | (15 : 0) 218 * : | : | : 219 * 220 * where mask-fields are used to protect control-fields from write-in 221 * accidentally. Set the corresponding bits in the mask-field before 222 * you write a value into a control-field. 223 * 224 * Control-fields are used to set where the function pin is going to 225 * be routed to. A control-field consists of one or more bits. 226 */ 227 static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 bit_sz, 228 u8 val) 229 { 230 u32 mask, reg; 231 232 /* 233 * Note that upper 16-bit word are mask-fields and lower 16-bit 234 * word are the control-fields. Set corresponding bits in mask- 235 * field before write to a control-field. 236 */ 237 mask = GENMASK(bit_sz - 1, 0) << SPPCTL_MOON_REG_MASK_SHIFT; 238 reg = (mask | val) << bit_off; 239 240 writel(reg, pctl->moon1_base + reg_off * 4); 241 } 242 243 /** 244 * sppctl_first_get() - get bit of FIRST register. 245 * 246 * There are 4 FIRST registers. Each has 32 control-bits. 247 * Totally, there are 4 * 32 = 128 control-bits. 248 * Control-bits are arranged as shown below: 249 * 250 * registers | control-bits 251 * -----------+-------------- 252 * first[0] | (31 : 0) 253 * first[1] | (63 : 32) 254 * first[2] | (95 : 64) 255 * first[3] | (127 : 96) 256 * 257 * Each control-bit sets type of a GPIO pin. 258 * 0: a fully-pinmux pin 259 * 1: a GPIO or IOP pin 260 */ 261 static int sppctl_first_get(struct gpio_chip *chip, unsigned int offset) 262 { 263 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 264 u32 reg_off, bit_off, reg; 265 266 bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); 267 reg = sppctl_first_readl(spp_gchip, reg_off); 268 269 return (reg & BIT(bit_off)) ? 1 : 0; 270 } 271 272 /** 273 * sppctl_master_get() - get bit of MASTER register. 274 * 275 * There are 8 MASTER registers. Each has 16 mask-bits and 16 control-bits. 276 * Upper 16-bit of MASTER registers are mask-bits while lower 16-bit are 277 * control-bits. Totally, there are 128 mask-bits and 128 control-bits. 278 * They are arranged as shown below: 279 * 280 * register | mask-bits | control-bits 281 * -----------+-------------+-------------- 282 * master[0] | (15 : 0) | (15 : 0) 283 * master[1] | (31 : 16) | (31 : 16) 284 * master[2] | (47 : 32) | (47 : 32) 285 * : | : | : 286 * master[7] | (127 : 112) | (127 : 112) 287 * 288 * where mask-bits are used to protect control-bits from write-in 289 * accidentally. Set the corresponding mask-bit before you write 290 * a value into a control-bit. 291 * 292 * Each control-bit sets type of a GPIO pin when FIRST bit is 1. 293 * 0: a IOP pin 294 * 1: a GPIO pin 295 */ 296 static int sppctl_master_get(struct gpio_chip *chip, unsigned int offset) 297 { 298 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 299 u32 reg_off, bit_off, reg; 300 301 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); 302 reg = sppctl_gpio_master_readl(spp_gchip, reg_off); 303 return (reg & BIT(bit_off)) ? 1 : 0; 304 } 305 306 static void sppctl_first_master_set(struct gpio_chip *chip, unsigned int offset, 307 enum mux_first_reg first, enum mux_master_reg master) 308 { 309 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 310 u32 reg_off, bit_off, reg; 311 enum mux_first_reg val; 312 313 /* FIRST register */ 314 if (first != mux_f_keep) { 315 bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); 316 reg = sppctl_first_readl(spp_gchip, reg_off); 317 val = (reg & BIT(bit_off)) ? mux_f_gpio : mux_f_mux; 318 319 if (first != val) 320 switch (first) { 321 case mux_f_gpio: 322 reg |= BIT(bit_off); 323 sppctl_first_writel(spp_gchip, reg, reg_off); 324 break; 325 326 case mux_f_mux: 327 reg &= ~BIT(bit_off); 328 sppctl_first_writel(spp_gchip, reg, reg_off); 329 break; 330 331 case mux_f_keep: 332 break; 333 } 334 } 335 336 /* MASTER register */ 337 if (master != mux_m_keep) { 338 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, (master == mux_m_gpio)); 339 sppctl_gpio_master_writel(spp_gchip, reg, reg_off); 340 } 341 } 342 343 static void sppctl_gpio_input_inv_set(struct gpio_chip *chip, unsigned int offset) 344 { 345 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 346 u32 reg_off, reg; 347 348 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); 349 sppctl_gpio_iinv_writel(spp_gchip, reg, reg_off); 350 } 351 352 static void sppctl_gpio_output_inv_set(struct gpio_chip *chip, unsigned int offset) 353 { 354 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 355 u32 reg_off, reg; 356 357 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); 358 sppctl_gpio_oinv_writel(spp_gchip, reg, reg_off); 359 } 360 361 static int sppctl_gpio_output_od_get(struct gpio_chip *chip, unsigned int offset) 362 { 363 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 364 u32 reg_off, bit_off, reg; 365 366 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); 367 reg = sppctl_gpio_od_readl(spp_gchip, reg_off); 368 369 return (reg & BIT(bit_off)) ? 1 : 0; 370 } 371 372 static void sppctl_gpio_output_od_set(struct gpio_chip *chip, unsigned int offset, 373 unsigned int val) 374 { 375 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 376 u32 reg_off, reg; 377 378 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val); 379 sppctl_gpio_od_writel(spp_gchip, reg, reg_off); 380 } 381 382 static int sppctl_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 383 { 384 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 385 u32 reg_off, bit_off, reg; 386 387 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); 388 reg = sppctl_gpio_oe_readl(spp_gchip, reg_off); 389 390 return (reg & BIT(bit_off)) ? 0 : 1; 391 } 392 393 static int sppctl_gpio_inv_get(struct gpio_chip *chip, unsigned int offset) 394 { 395 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 396 u32 reg_off, bit_off, reg; 397 unsigned long flags; 398 399 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); 400 401 spin_lock_irqsave(&spp_gchip->lock, flags); 402 403 if (sppctl_gpio_get_direction(chip, offset)) 404 reg = sppctl_gpio_iinv_readl(spp_gchip, reg_off); 405 else 406 reg = sppctl_gpio_oinv_readl(spp_gchip, reg_off); 407 408 spin_unlock_irqrestore(&spp_gchip->lock, flags); 409 410 return (reg & BIT(bit_off)) ? 1 : 0; 411 } 412 413 static int sppctl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 414 { 415 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 416 unsigned long flags; 417 u32 reg_off, reg; 418 419 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 0); 420 421 spin_lock_irqsave(&spp_gchip->lock, flags); 422 423 sppctl_gpio_oe_writel(spp_gchip, reg, reg_off); 424 425 spin_unlock_irqrestore(&spp_gchip->lock, flags); 426 return 0; 427 } 428 429 static int sppctl_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int val) 430 { 431 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 432 unsigned long flags; 433 u32 reg_off, reg; 434 435 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); 436 437 spin_lock_irqsave(&spp_gchip->lock, flags); 438 439 sppctl_gpio_oe_writel(spp_gchip, reg, reg_off); 440 441 if (val < 0) { 442 spin_unlock_irqrestore(&spp_gchip->lock, flags); 443 return 0; 444 } 445 446 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val); 447 sppctl_gpio_out_writel(spp_gchip, reg, reg_off); 448 449 spin_unlock_irqrestore(&spp_gchip->lock, flags); 450 return 0; 451 } 452 453 static int sppctl_gpio_get(struct gpio_chip *chip, unsigned int offset) 454 { 455 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 456 u32 reg_off, bit_off, reg; 457 458 bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); 459 reg = sppctl_gpio_in_readl(spp_gchip, reg_off); 460 461 return (reg & BIT(bit_off)) ? 1 : 0; 462 } 463 464 static void sppctl_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) 465 { 466 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 467 u32 reg_off, reg; 468 469 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val); 470 sppctl_gpio_out_writel(spp_gchip, reg, reg_off); 471 } 472 473 static int sppctl_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 474 unsigned long config) 475 { 476 enum pin_config_param param = pinconf_to_config_param(config); 477 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); 478 u32 reg_off, reg; 479 480 switch (param) { 481 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 482 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); 483 sppctl_gpio_od_writel(spp_gchip, reg, reg_off); 484 break; 485 486 case PIN_CONFIG_INPUT_ENABLE: 487 break; 488 489 case PIN_CONFIG_OUTPUT: 490 return sppctl_gpio_direction_output(chip, offset, 0); 491 492 case PIN_CONFIG_PERSIST_STATE: 493 return -ENOTSUPP; 494 495 default: 496 return -EINVAL; 497 } 498 499 return 0; 500 } 501 502 static void sppctl_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 503 { 504 const char *label; 505 int i; 506 507 for (i = 0; i < chip->ngpio; i++) { 508 label = gpiochip_is_requested(chip, i); 509 if (!label) 510 label = ""; 511 512 seq_printf(s, " gpio-%03d (%-16.16s | %-16.16s)", i + chip->base, 513 chip->names[i], label); 514 seq_printf(s, " %c", sppctl_gpio_get_direction(chip, i) ? 'I' : 'O'); 515 seq_printf(s, ":%d", sppctl_gpio_get(chip, i)); 516 seq_printf(s, " %s", sppctl_first_get(chip, i) ? "gpi" : "mux"); 517 seq_printf(s, " %s", sppctl_master_get(chip, i) ? "gpi" : "iop"); 518 seq_printf(s, " %s", sppctl_gpio_inv_get(chip, i) ? "inv" : " "); 519 seq_printf(s, " %s", sppctl_gpio_output_od_get(chip, i) ? "oDr" : ""); 520 seq_puts(s, "\n"); 521 } 522 } 523 524 static int sppctl_gpio_new(struct platform_device *pdev, struct sppctl_pdata *pctl) 525 { 526 struct sppctl_gpio_chip *spp_gchip; 527 struct gpio_chip *gchip; 528 int err; 529 530 spp_gchip = devm_kzalloc(&pdev->dev, sizeof(*spp_gchip), GFP_KERNEL); 531 if (!spp_gchip) 532 return -ENOMEM; 533 pctl->spp_gchip = spp_gchip; 534 535 spp_gchip->gpioxt_base = pctl->gpioxt_base; 536 spp_gchip->first_base = pctl->first_base; 537 spin_lock_init(&spp_gchip->lock); 538 539 gchip = &spp_gchip->chip; 540 gchip->label = SPPCTL_MODULE_NAME; 541 gchip->parent = &pdev->dev; 542 gchip->owner = THIS_MODULE; 543 gchip->request = gpiochip_generic_request; 544 gchip->free = gpiochip_generic_free; 545 gchip->get_direction = sppctl_gpio_get_direction; 546 gchip->direction_input = sppctl_gpio_direction_input; 547 gchip->direction_output = sppctl_gpio_direction_output; 548 gchip->get = sppctl_gpio_get; 549 gchip->set = sppctl_gpio_set; 550 gchip->set_config = sppctl_gpio_set_config; 551 gchip->dbg_show = IS_ENABLED(CONFIG_DEBUG_FS) ? 552 sppctl_gpio_dbg_show : NULL; 553 gchip->base = -1; 554 gchip->ngpio = sppctl_gpio_list_sz; 555 gchip->names = sppctl_gpio_list_s; 556 557 pctl->pctl_grange.npins = gchip->ngpio; 558 pctl->pctl_grange.name = gchip->label; 559 pctl->pctl_grange.gc = gchip; 560 561 err = devm_gpiochip_add_data(&pdev->dev, gchip, spp_gchip); 562 if (err) 563 return dev_err_probe(&pdev->dev, err, "Failed to add gpiochip!\n"); 564 565 return 0; 566 } 567 568 static int sppctl_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 569 unsigned long *config) 570 { 571 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 572 unsigned int param = pinconf_to_config_param(*config); 573 unsigned int arg; 574 575 switch (param) { 576 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 577 if (!sppctl_gpio_output_od_get(&pctl->spp_gchip->chip, pin)) 578 return -EINVAL; 579 arg = 0; 580 break; 581 582 case PIN_CONFIG_OUTPUT: 583 if (!sppctl_first_get(&pctl->spp_gchip->chip, pin)) 584 return -EINVAL; 585 if (!sppctl_master_get(&pctl->spp_gchip->chip, pin)) 586 return -EINVAL; 587 if (sppctl_gpio_get_direction(&pctl->spp_gchip->chip, pin)) 588 return -EINVAL; 589 arg = sppctl_gpio_get(&pctl->spp_gchip->chip, pin); 590 break; 591 592 default: 593 return -EOPNOTSUPP; 594 } 595 *config = pinconf_to_config_packed(param, arg); 596 597 return 0; 598 } 599 600 static int sppctl_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 601 unsigned long *configs, unsigned int num_configs) 602 { 603 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 604 int i; 605 606 /* Special handling for IOP pins */ 607 if (configs[0] == SPPCTL_IOP_CONFIGS) { 608 sppctl_first_master_set(&pctl->spp_gchip->chip, pin, mux_f_gpio, mux_m_iop); 609 return 0; 610 } 611 612 for (i = 0; i < num_configs; i++) { 613 if (configs[i] & SPPCTL_PCTL_L_OUT) 614 sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 0); 615 if (configs[i] & SPPCTL_PCTL_L_OU1) 616 sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 1); 617 if (configs[i] & SPPCTL_PCTL_L_INV) 618 sppctl_gpio_input_inv_set(&pctl->spp_gchip->chip, pin); 619 if (configs[i] & SPPCTL_PCTL_L_ONV) 620 sppctl_gpio_output_inv_set(&pctl->spp_gchip->chip, pin); 621 if (configs[i] & SPPCTL_PCTL_L_ODR) 622 sppctl_gpio_output_od_set(&pctl->spp_gchip->chip, pin, 1); 623 } 624 625 return 0; 626 } 627 628 static const struct pinconf_ops sppctl_pconf_ops = { 629 .is_generic = true, 630 .pin_config_get = sppctl_pin_config_get, 631 .pin_config_set = sppctl_pin_config_set, 632 }; 633 634 static int sppctl_get_functions_count(struct pinctrl_dev *pctldev) 635 { 636 return sppctl_list_funcs_sz; 637 } 638 639 static const char *sppctl_get_function_name(struct pinctrl_dev *pctldev, 640 unsigned int selector) 641 { 642 return sppctl_list_funcs[selector].name; 643 } 644 645 static int sppctl_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, 646 const char * const **groups, unsigned int *num_groups) 647 { 648 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 649 const struct sppctl_func *f = &sppctl_list_funcs[selector]; 650 int i; 651 652 *num_groups = 0; 653 switch (f->type) { 654 case pinmux_type_fpmx: 655 *num_groups = sppctl_pmux_list_sz; 656 *groups = sppctl_pmux_list_s; 657 break; 658 659 case pinmux_type_grp: 660 if (!f->grps) 661 break; 662 663 *num_groups = f->gnum; 664 for (i = 0; i < pctl->unq_grps_sz; i++) 665 if (pctl->g2fp_maps[i].f_idx == selector) 666 break; 667 *groups = &pctl->unq_grps[i]; 668 break; 669 670 default: 671 dev_err(pctldev->dev, "Unknown pinmux (selector: %d, type: %d)\n", 672 selector, f->type); 673 break; 674 } 675 676 return 0; 677 } 678 679 /** 680 * sppctl_fully_pinmux_conv - Convert GPIO# to fully-pinmux control-field setting 681 * 682 * Each fully-pinmux function can be mapped to any of GPIO 8 ~ 71 by 683 * settings its control-field. Refer to following table: 684 * 685 * control-field | GPIO 686 * --------------+-------- 687 * 0 | No map 688 * 1 | 8 689 * 2 | 9 690 * 3 | 10 691 * : | : 692 * 65 | 71 693 */ 694 static inline int sppctl_fully_pinmux_conv(unsigned int offset) 695 { 696 return (offset < 8) ? 0 : offset - 7; 697 } 698 699 static int sppctl_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, 700 unsigned int group_selector) 701 { 702 const struct sppctl_func *f = &sppctl_list_funcs[func_selector]; 703 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 704 struct grp2fp_map g2fpm = pctl->g2fp_maps[group_selector]; 705 int i; 706 707 switch (f->type) { 708 case pinmux_type_fpmx: 709 sppctl_first_master_set(&pctl->spp_gchip->chip, group_selector, 710 mux_f_mux, mux_m_keep); 711 sppctl_func_set(pctl, func_selector, sppctl_fully_pinmux_conv(group_selector)); 712 break; 713 714 case pinmux_type_grp: 715 for (i = 0; i < f->grps[g2fpm.g_idx].pnum; i++) 716 sppctl_first_master_set(&pctl->spp_gchip->chip, 717 f->grps[g2fpm.g_idx].pins[i], 718 mux_f_mux, mux_m_keep); 719 sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, f->grps[g2fpm.g_idx].gval); 720 break; 721 722 default: 723 dev_err(pctldev->dev, "Unknown pinmux type (func_selector: %d, type: %d)\n", 724 func_selector, f->type); 725 break; 726 } 727 728 return 0; 729 } 730 731 static int sppctl_gpio_request_enable(struct pinctrl_dev *pctldev, 732 struct pinctrl_gpio_range *range, unsigned int offset) 733 { 734 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 735 int g_f, g_m; 736 737 g_f = sppctl_first_get(&pctl->spp_gchip->chip, offset); 738 g_m = sppctl_master_get(&pctl->spp_gchip->chip, offset); 739 if (g_f == mux_f_gpio && g_m == mux_m_gpio) 740 return 0; 741 742 sppctl_first_master_set(&pctl->spp_gchip->chip, offset, mux_f_gpio, mux_m_gpio); 743 return 0; 744 } 745 746 static const struct pinmux_ops sppctl_pinmux_ops = { 747 .get_functions_count = sppctl_get_functions_count, 748 .get_function_name = sppctl_get_function_name, 749 .get_function_groups = sppctl_get_function_groups, 750 .set_mux = sppctl_set_mux, 751 .gpio_request_enable = sppctl_gpio_request_enable, 752 .strict = true, 753 }; 754 755 static int sppctl_get_groups_count(struct pinctrl_dev *pctldev) 756 { 757 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 758 759 return pctl->unq_grps_sz; 760 } 761 762 static const char *sppctl_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector) 763 { 764 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 765 766 return pctl->unq_grps[selector]; 767 } 768 769 static int sppctl_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, 770 const unsigned int **pins, unsigned int *num_pins) 771 { 772 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 773 struct grp2fp_map g2fpm = pctl->g2fp_maps[selector]; 774 const struct sppctl_func *f; 775 776 f = &sppctl_list_funcs[g2fpm.f_idx]; 777 *num_pins = 0; 778 779 /* Except group-pinmux, each group has 1 pin. */ 780 if (f->type != pinmux_type_grp) { 781 *num_pins = 1; 782 *pins = &sppctl_pins_gpio[selector]; 783 return 0; 784 } 785 786 /* Group-pinmux may have more than one pin. */ 787 if (!f->grps) 788 return 0; 789 790 if (f->gnum < 1) 791 return 0; 792 793 *num_pins = f->grps[g2fpm.g_idx].pnum; 794 *pins = f->grps[g2fpm.g_idx].pins; 795 796 return 0; 797 } 798 799 #ifdef CONFIG_DEBUG_FS 800 static void sppctl_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 801 unsigned int offset) 802 { 803 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 804 const char *pin_type; 805 u8 first, master; 806 807 first = sppctl_first_get(&pctl->spp_gchip->chip, offset); 808 master = sppctl_master_get(&pctl->spp_gchip->chip, offset); 809 if (first) 810 if (master) 811 pin_type = "GPIO"; 812 else 813 pin_type = " IOP"; 814 else 815 pin_type = " MUX"; 816 seq_printf(s, " %s", pin_type); 817 } 818 #endif 819 820 static int sppctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config, 821 struct pinctrl_map **map, unsigned int *num_maps) 822 { 823 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); 824 int nmG = of_property_count_strings(np_config, "groups"); 825 const struct sppctl_func *f = NULL; 826 u8 pin_num, pin_type, pin_func; 827 struct device_node *parent; 828 unsigned long *configs; 829 struct property *prop; 830 const char *s_f, *s_g; 831 832 const __be32 *list; 833 u32 dt_pin, dt_fun; 834 int i, size = 0; 835 836 list = of_get_property(np_config, "sunplus,pins", &size); 837 838 if (nmG <= 0) 839 nmG = 0; 840 841 parent = of_get_parent(np_config); 842 *num_maps = size / sizeof(*list); 843 844 /* 845 * Process property: 846 * sunplus,pins = < u32 u32 u32 ... >; 847 * 848 * Each 32-bit integer defines a individual pin in which: 849 * 850 * Bit 32~24: defines GPIO pin number. Its range is 0 ~ 98. 851 * Bit 23~16: defines types: (1) fully-pinmux pins 852 * (2) IO processor pins 853 * (3) digital GPIO pins 854 * Bit 15~8: defines pins of peripherals (which are defined in 855 * 'include/dt-binging/pinctrl/sppctl.h'). 856 * Bit 7~0: defines types or initial-state of digital GPIO pins. 857 */ 858 for (i = 0; i < (*num_maps); i++) { 859 dt_pin = be32_to_cpu(list[i]); 860 pin_num = FIELD_GET(GENMASK(31, 24), dt_pin); 861 862 if (pin_num >= sppctl_pins_all_sz) { 863 dev_err(pctldev->dev, "Invalid pin property at index %d (0x%08x)\n", 864 i, dt_pin); 865 return -EINVAL; 866 } 867 } 868 869 *map = kcalloc(*num_maps + nmG, sizeof(**map), GFP_KERNEL); 870 if (*map == NULL) 871 return -ENOMEM; 872 873 for (i = 0; i < (*num_maps); i++) { 874 dt_pin = be32_to_cpu(list[i]); 875 pin_num = FIELD_GET(GENMASK(31, 24), dt_pin); 876 pin_type = FIELD_GET(GENMASK(23, 16), dt_pin); 877 pin_func = FIELD_GET(GENMASK(15, 8), dt_pin); 878 (*map)[i].name = parent->name; 879 880 if (pin_type == SPPCTL_PCTL_G_GPIO) { 881 /* A digital GPIO pin */ 882 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 883 (*map)[i].data.configs.num_configs = 1; 884 (*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num); 885 configs = kmalloc(sizeof(*configs), GFP_KERNEL); 886 *configs = FIELD_GET(GENMASK(7, 0), dt_pin); 887 (*map)[i].data.configs.configs = configs; 888 889 dev_dbg(pctldev->dev, "%s: GPIO (%s)\n", 890 (*map)[i].data.configs.group_or_pin, 891 (*configs & (SPPCTL_PCTL_L_OUT | SPPCTL_PCTL_L_OU1)) ? 892 "OUT" : "IN"); 893 } else if (pin_type == SPPCTL_PCTL_G_IOPP) { 894 /* A IO Processor (IOP) pin */ 895 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 896 (*map)[i].data.configs.num_configs = 1; 897 (*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num); 898 configs = kmalloc(sizeof(*configs), GFP_KERNEL); 899 *configs = SPPCTL_IOP_CONFIGS; 900 (*map)[i].data.configs.configs = configs; 901 902 dev_dbg(pctldev->dev, "%s: IOP\n", 903 (*map)[i].data.configs.group_or_pin); 904 } else { 905 /* A fully-pinmux pin */ 906 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 907 (*map)[i].data.mux.function = sppctl_list_funcs[pin_func].name; 908 (*map)[i].data.mux.group = pin_get_name(pctldev, pin_num); 909 910 dev_dbg(pctldev->dev, "%s: %s\n", (*map)[i].data.mux.group, 911 (*map)[i].data.mux.function); 912 } 913 } 914 915 /* 916 * Process properties: 917 * function = "xxx"; 918 * groups = "yyy"; 919 */ 920 if (nmG > 0 && of_property_read_string(np_config, "function", &s_f) == 0) { 921 of_property_for_each_string(np_config, "groups", prop, s_g) { 922 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 923 (*map)[*num_maps].data.mux.function = s_f; 924 (*map)[*num_maps].data.mux.group = s_g; 925 (*num_maps)++; 926 927 dev_dbg(pctldev->dev, "%s: %s\n", s_f, s_g); 928 } 929 } 930 931 /* 932 * Process property: 933 * sunplus,zerofunc = < u32 u32 u32 ...> 934 */ 935 list = of_get_property(np_config, "sunplus,zerofunc", &size); 936 if (list) { 937 for (i = 0; i < (size / sizeof(*list)); i++) { 938 dt_fun = be32_to_cpu(list[i]); 939 if (dt_fun >= sppctl_list_funcs_sz) { 940 dev_err(pctldev->dev, "Zero-func %d out of range!\n", 941 dt_fun); 942 continue; 943 } 944 945 f = &sppctl_list_funcs[dt_fun]; 946 switch (f->type) { 947 case pinmux_type_fpmx: 948 sppctl_func_set(pctl, dt_fun, 0); 949 dev_dbg(pctldev->dev, "%s: No map\n", f->name); 950 break; 951 952 case pinmux_type_grp: 953 sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, 0); 954 dev_dbg(pctldev->dev, "%s: No map\n", f->name); 955 break; 956 957 default: 958 dev_err(pctldev->dev, "Wrong zero-group: %d (%s)\n", 959 dt_fun, f->name); 960 break; 961 } 962 } 963 } 964 965 of_node_put(parent); 966 dev_dbg(pctldev->dev, "%d pins mapped\n", *num_maps); 967 return 0; 968 } 969 970 static const struct pinctrl_ops sppctl_pctl_ops = { 971 .get_groups_count = sppctl_get_groups_count, 972 .get_group_name = sppctl_get_group_name, 973 .get_group_pins = sppctl_get_group_pins, 974 #ifdef CONFIG_DEBUG_FS 975 .pin_dbg_show = sppctl_pin_dbg_show, 976 #endif 977 .dt_node_to_map = sppctl_dt_node_to_map, 978 .dt_free_map = pinctrl_utils_free_map, 979 }; 980 981 static int sppctl_group_groups(struct platform_device *pdev) 982 { 983 struct sppctl_pdata *sppctl = platform_get_drvdata(pdev); 984 int i, k, j; 985 986 /* Calculate number of total group (GPIO + group-pinmux group). */ 987 sppctl->unq_grps_sz = sppctl_gpio_list_sz; 988 for (i = 0; i < sppctl_list_funcs_sz; i++) 989 if (sppctl_list_funcs[i].type == pinmux_type_grp) 990 sppctl->unq_grps_sz += sppctl_list_funcs[i].gnum; 991 992 sppctl->unq_grps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1, 993 sizeof(*sppctl->unq_grps), GFP_KERNEL); 994 if (!sppctl->unq_grps) 995 return -ENOMEM; 996 997 sppctl->g2fp_maps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1, 998 sizeof(*sppctl->g2fp_maps), GFP_KERNEL); 999 if (!sppctl->g2fp_maps) 1000 return -ENOMEM; 1001 1002 /* Add GPIO pins. */ 1003 for (i = 0; i < sppctl_gpio_list_sz; i++) { 1004 sppctl->unq_grps[i] = sppctl_gpio_list_s[i]; 1005 sppctl->g2fp_maps[i].f_idx = 0; 1006 sppctl->g2fp_maps[i].g_idx = i; 1007 } 1008 1009 /* Add group-pinmux to end of GPIO pins. */ 1010 j = sppctl_gpio_list_sz; 1011 for (i = 0; i < sppctl_list_funcs_sz; i++) { 1012 if (sppctl_list_funcs[i].type != pinmux_type_grp) 1013 continue; 1014 1015 for (k = 0; k < sppctl_list_funcs[i].gnum; k++) { 1016 sppctl->unq_grps[j] = sppctl_list_funcs[i].grps[k].name; 1017 sppctl->g2fp_maps[j].f_idx = i; 1018 sppctl->g2fp_maps[j].g_idx = k; 1019 j++; 1020 } 1021 } 1022 1023 return 0; 1024 } 1025 1026 static int sppctl_pinctrl_init(struct platform_device *pdev) 1027 { 1028 struct sppctl_pdata *sppctl = platform_get_drvdata(pdev); 1029 int err; 1030 1031 sppctl->pctl_desc.owner = THIS_MODULE; 1032 sppctl->pctl_desc.name = dev_name(&pdev->dev); 1033 sppctl->pctl_desc.pins = sppctl_pins_all; 1034 sppctl->pctl_desc.npins = sppctl_pins_all_sz; 1035 sppctl->pctl_desc.pctlops = &sppctl_pctl_ops; 1036 sppctl->pctl_desc.confops = &sppctl_pconf_ops; 1037 sppctl->pctl_desc.pmxops = &sppctl_pinmux_ops; 1038 1039 err = sppctl_group_groups(pdev); 1040 if (err) 1041 return err; 1042 1043 err = devm_pinctrl_register_and_init(&pdev->dev, &sppctl->pctl_desc, 1044 sppctl, &sppctl->pctl_dev); 1045 if (err) 1046 return dev_err_probe(&pdev->dev, err, "Failed to register pinctrl!\n"); 1047 1048 pinctrl_enable(sppctl->pctl_dev); 1049 return 0; 1050 } 1051 1052 static int sppctl_resource_map(struct platform_device *pdev, struct sppctl_pdata *sppctl) 1053 { 1054 sppctl->moon2_base = devm_platform_ioremap_resource_byname(pdev, "moon2"); 1055 if (IS_ERR(sppctl->moon2_base)) 1056 return PTR_ERR(sppctl->moon2_base); 1057 1058 sppctl->gpioxt_base = devm_platform_ioremap_resource_byname(pdev, "gpioxt"); 1059 if (IS_ERR(sppctl->gpioxt_base)) 1060 return PTR_ERR(sppctl->gpioxt_base); 1061 1062 sppctl->first_base = devm_platform_ioremap_resource_byname(pdev, "first"); 1063 if (IS_ERR(sppctl->first_base)) 1064 return PTR_ERR(sppctl->first_base); 1065 1066 sppctl->moon1_base = devm_platform_ioremap_resource_byname(pdev, "moon1"); 1067 if (IS_ERR(sppctl->moon1_base)) 1068 return PTR_ERR(sppctl->moon1_base); 1069 1070 return 0; 1071 } 1072 1073 static int sppctl_probe(struct platform_device *pdev) 1074 { 1075 struct sppctl_pdata *sppctl; 1076 int ret; 1077 1078 sppctl = devm_kzalloc(&pdev->dev, sizeof(*sppctl), GFP_KERNEL); 1079 if (!sppctl) 1080 return -ENOMEM; 1081 platform_set_drvdata(pdev, sppctl); 1082 1083 ret = sppctl_resource_map(pdev, sppctl); 1084 if (ret) 1085 return ret; 1086 1087 ret = sppctl_gpio_new(pdev, sppctl); 1088 if (ret) 1089 return ret; 1090 1091 ret = sppctl_pinctrl_init(pdev); 1092 if (ret) 1093 return ret; 1094 1095 pinctrl_add_gpio_range(sppctl->pctl_dev, &sppctl->pctl_grange); 1096 1097 return 0; 1098 } 1099 1100 static const struct of_device_id sppctl_match_table[] = { 1101 { .compatible = "sunplus,sp7021-pctl" }, 1102 { /* sentinel */ } 1103 }; 1104 1105 static struct platform_driver sppctl_pinctrl_driver = { 1106 .driver = { 1107 .name = SPPCTL_MODULE_NAME, 1108 .of_match_table = sppctl_match_table, 1109 }, 1110 .probe = sppctl_probe, 1111 }; 1112 builtin_platform_driver(sppctl_pinctrl_driver) 1113 1114 MODULE_AUTHOR("Dvorkin Dmitry <dvorkin@tibbo.com>"); 1115 MODULE_AUTHOR("Wells Lu <wellslutw@gmail.com>"); 1116 MODULE_DESCRIPTION("Sunplus SP7021 Pin Control and GPIO driver"); 1117 MODULE_LICENSE("GPL v2"); 1118