xref: /linux/drivers/pinctrl/stm32/pinctrl-stm32.c (revision c79c3c34f75d72a066e292b10aa50fc758c97c89)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) Maxime Coquelin 2015
4  * Copyright (C) STMicroelectronics 2017
5  * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
6  *
7  * Heavily based on Mediatek's pinctrl driver
8  */
9 #include <linux/clk.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/hwspinlock.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/of_irq.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/platform_device.h>
27 #include <linux/regmap.h>
28 #include <linux/reset.h>
29 #include <linux/slab.h>
30 
31 #include "../core.h"
32 #include "../pinconf.h"
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-stm32.h"
35 
36 #define STM32_GPIO_MODER	0x00
37 #define STM32_GPIO_TYPER	0x04
38 #define STM32_GPIO_SPEEDR	0x08
39 #define STM32_GPIO_PUPDR	0x0c
40 #define STM32_GPIO_IDR		0x10
41 #define STM32_GPIO_ODR		0x14
42 #define STM32_GPIO_BSRR		0x18
43 #define STM32_GPIO_LCKR		0x1c
44 #define STM32_GPIO_AFRL		0x20
45 #define STM32_GPIO_AFRH		0x24
46 
47 /* custom bitfield to backup pin status */
48 #define STM32_GPIO_BKP_MODE_SHIFT	0
49 #define STM32_GPIO_BKP_MODE_MASK	GENMASK(1, 0)
50 #define STM32_GPIO_BKP_ALT_SHIFT	2
51 #define STM32_GPIO_BKP_ALT_MASK		GENMASK(5, 2)
52 #define STM32_GPIO_BKP_SPEED_SHIFT	6
53 #define STM32_GPIO_BKP_SPEED_MASK	GENMASK(7, 6)
54 #define STM32_GPIO_BKP_PUPD_SHIFT	8
55 #define STM32_GPIO_BKP_PUPD_MASK	GENMASK(9, 8)
56 #define STM32_GPIO_BKP_TYPE		10
57 #define STM32_GPIO_BKP_VAL		11
58 
59 #define STM32_GPIO_PINS_PER_BANK 16
60 #define STM32_GPIO_IRQ_LINE	 16
61 
62 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
63 
64 #define gpio_range_to_bank(chip) \
65 		container_of(chip, struct stm32_gpio_bank, range)
66 
67 #define HWSPNLCK_TIMEOUT	1000 /* usec */
68 
69 static const char * const stm32_gpio_functions[] = {
70 	"gpio", "af0", "af1",
71 	"af2", "af3", "af4",
72 	"af5", "af6", "af7",
73 	"af8", "af9", "af10",
74 	"af11", "af12", "af13",
75 	"af14", "af15", "analog",
76 };
77 
78 struct stm32_pinctrl_group {
79 	const char *name;
80 	unsigned long config;
81 	unsigned pin;
82 };
83 
84 struct stm32_gpio_bank {
85 	void __iomem *base;
86 	struct clk *clk;
87 	struct reset_control *rstc;
88 	spinlock_t lock;
89 	struct gpio_chip gpio_chip;
90 	struct pinctrl_gpio_range range;
91 	struct fwnode_handle *fwnode;
92 	struct irq_domain *domain;
93 	u32 bank_nr;
94 	u32 bank_ioport_nr;
95 	u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
96 	u8 irq_type[STM32_GPIO_PINS_PER_BANK];
97 };
98 
99 struct stm32_pinctrl {
100 	struct device *dev;
101 	struct pinctrl_dev *pctl_dev;
102 	struct pinctrl_desc pctl_desc;
103 	struct stm32_pinctrl_group *groups;
104 	unsigned ngroups;
105 	const char **grp_names;
106 	struct stm32_gpio_bank *banks;
107 	unsigned nbanks;
108 	const struct stm32_pinctrl_match_data *match_data;
109 	struct irq_domain	*domain;
110 	struct regmap		*regmap;
111 	struct regmap_field	*irqmux[STM32_GPIO_PINS_PER_BANK];
112 	struct hwspinlock *hwlock;
113 	struct stm32_desc_pin *pins;
114 	u32 npins;
115 	u32 pkg;
116 	u16 irqmux_map;
117 	spinlock_t irqmux_lock;
118 };
119 
120 static inline int stm32_gpio_pin(int gpio)
121 {
122 	return gpio % STM32_GPIO_PINS_PER_BANK;
123 }
124 
125 static inline u32 stm32_gpio_get_mode(u32 function)
126 {
127 	switch (function) {
128 	case STM32_PIN_GPIO:
129 		return 0;
130 	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
131 		return 2;
132 	case STM32_PIN_ANALOG:
133 		return 3;
134 	}
135 
136 	return 0;
137 }
138 
139 static inline u32 stm32_gpio_get_alt(u32 function)
140 {
141 	switch (function) {
142 	case STM32_PIN_GPIO:
143 		return 0;
144 	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
145 		return function - 1;
146 	case STM32_PIN_ANALOG:
147 		return 0;
148 	}
149 
150 	return 0;
151 }
152 
153 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
154 				    u32 offset, u32 value)
155 {
156 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
157 	bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
158 }
159 
160 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
161 				   u32 mode, u32 alt)
162 {
163 	bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
164 				      STM32_GPIO_BKP_ALT_MASK);
165 	bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
166 	bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
167 }
168 
169 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
170 				      u32 drive)
171 {
172 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
173 	bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
174 }
175 
176 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
177 				    u32 speed)
178 {
179 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
180 	bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
181 }
182 
183 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
184 				   u32 bias)
185 {
186 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
187 	bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
188 }
189 
190 /* GPIO functions */
191 
192 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
193 	unsigned offset, int value)
194 {
195 	stm32_gpio_backup_value(bank, offset, value);
196 
197 	if (!value)
198 		offset += STM32_GPIO_PINS_PER_BANK;
199 
200 	clk_enable(bank->clk);
201 
202 	writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
203 
204 	clk_disable(bank->clk);
205 }
206 
207 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
208 {
209 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
210 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
211 	struct pinctrl_gpio_range *range;
212 	int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
213 
214 	range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
215 	if (!range) {
216 		dev_err(pctl->dev, "pin %d not in range.\n", pin);
217 		return -EINVAL;
218 	}
219 
220 	return pinctrl_gpio_request(chip->base + offset);
221 }
222 
223 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
224 {
225 	pinctrl_gpio_free(chip->base + offset);
226 }
227 
228 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
229 {
230 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
231 	int ret;
232 
233 	clk_enable(bank->clk);
234 
235 	ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
236 
237 	clk_disable(bank->clk);
238 
239 	return ret;
240 }
241 
242 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
243 {
244 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
245 
246 	__stm32_gpio_set(bank, offset, value);
247 }
248 
249 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
250 {
251 	return pinctrl_gpio_direction_input(chip->base + offset);
252 }
253 
254 static int stm32_gpio_direction_output(struct gpio_chip *chip,
255 	unsigned offset, int value)
256 {
257 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
258 
259 	__stm32_gpio_set(bank, offset, value);
260 	pinctrl_gpio_direction_output(chip->base + offset);
261 
262 	return 0;
263 }
264 
265 
266 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
267 {
268 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
269 	struct irq_fwspec fwspec;
270 
271 	fwspec.fwnode = bank->fwnode;
272 	fwspec.param_count = 2;
273 	fwspec.param[0] = offset;
274 	fwspec.param[1] = IRQ_TYPE_NONE;
275 
276 	return irq_create_fwspec_mapping(&fwspec);
277 }
278 
279 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
280 {
281 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
282 	int pin = stm32_gpio_pin(offset);
283 	int ret;
284 	u32 mode, alt;
285 
286 	stm32_pmx_get_mode(bank, pin, &mode, &alt);
287 	if ((alt == 0) && (mode == 0))
288 		ret = GPIO_LINE_DIRECTION_IN;
289 	else if ((alt == 0) && (mode == 1))
290 		ret = GPIO_LINE_DIRECTION_OUT;
291 	else
292 		ret = -EINVAL;
293 
294 	return ret;
295 }
296 
297 static const struct gpio_chip stm32_gpio_template = {
298 	.request		= stm32_gpio_request,
299 	.free			= stm32_gpio_free,
300 	.get			= stm32_gpio_get,
301 	.set			= stm32_gpio_set,
302 	.direction_input	= stm32_gpio_direction_input,
303 	.direction_output	= stm32_gpio_direction_output,
304 	.to_irq			= stm32_gpio_to_irq,
305 	.get_direction		= stm32_gpio_get_direction,
306 	.set_config		= gpiochip_generic_config,
307 };
308 
309 static void stm32_gpio_irq_trigger(struct irq_data *d)
310 {
311 	struct stm32_gpio_bank *bank = d->domain->host_data;
312 	int level;
313 
314 	/* If level interrupt type then retrig */
315 	level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
316 	if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
317 	    (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
318 		irq_chip_retrigger_hierarchy(d);
319 }
320 
321 static void stm32_gpio_irq_eoi(struct irq_data *d)
322 {
323 	irq_chip_eoi_parent(d);
324 	stm32_gpio_irq_trigger(d);
325 };
326 
327 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
328 {
329 	struct stm32_gpio_bank *bank = d->domain->host_data;
330 	u32 parent_type;
331 
332 	switch (type) {
333 	case IRQ_TYPE_EDGE_RISING:
334 	case IRQ_TYPE_EDGE_FALLING:
335 	case IRQ_TYPE_EDGE_BOTH:
336 		parent_type = type;
337 		break;
338 	case IRQ_TYPE_LEVEL_HIGH:
339 		parent_type = IRQ_TYPE_EDGE_RISING;
340 		break;
341 	case IRQ_TYPE_LEVEL_LOW:
342 		parent_type = IRQ_TYPE_EDGE_FALLING;
343 		break;
344 	default:
345 		return -EINVAL;
346 	}
347 
348 	bank->irq_type[d->hwirq] = type;
349 
350 	return irq_chip_set_type_parent(d, parent_type);
351 };
352 
353 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
354 {
355 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
356 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
357 	int ret;
358 
359 	ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
360 	if (ret)
361 		return ret;
362 
363 	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
364 	if (ret) {
365 		dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
366 			irq_data->hwirq);
367 		return ret;
368 	}
369 
370 	return 0;
371 }
372 
373 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
374 {
375 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
376 
377 	gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
378 }
379 
380 static void stm32_gpio_irq_unmask(struct irq_data *d)
381 {
382 	irq_chip_unmask_parent(d);
383 	stm32_gpio_irq_trigger(d);
384 }
385 
386 static struct irq_chip stm32_gpio_irq_chip = {
387 	.name		= "stm32gpio",
388 	.irq_eoi	= stm32_gpio_irq_eoi,
389 	.irq_ack	= irq_chip_ack_parent,
390 	.irq_mask	= irq_chip_mask_parent,
391 	.irq_unmask	= stm32_gpio_irq_unmask,
392 	.irq_set_type	= stm32_gpio_set_type,
393 	.irq_set_wake	= irq_chip_set_wake_parent,
394 	.irq_request_resources = stm32_gpio_irq_request_resources,
395 	.irq_release_resources = stm32_gpio_irq_release_resources,
396 };
397 
398 static int stm32_gpio_domain_translate(struct irq_domain *d,
399 				       struct irq_fwspec *fwspec,
400 				       unsigned long *hwirq,
401 				       unsigned int *type)
402 {
403 	if ((fwspec->param_count != 2) ||
404 	    (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
405 		return -EINVAL;
406 
407 	*hwirq = fwspec->param[0];
408 	*type = fwspec->param[1];
409 	return 0;
410 }
411 
412 static int stm32_gpio_domain_activate(struct irq_domain *d,
413 				      struct irq_data *irq_data, bool reserve)
414 {
415 	struct stm32_gpio_bank *bank = d->host_data;
416 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
417 	unsigned long flags;
418 	int ret = 0;
419 
420 	/*
421 	 * gpio irq mux is shared between several banks, a lock has to be done
422 	 * to avoid overriding.
423 	 */
424 	spin_lock_irqsave(&pctl->irqmux_lock, flags);
425 
426 	if (pctl->hwlock) {
427 		ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
428 						    HWSPNLCK_TIMEOUT);
429 		if (ret) {
430 			dev_err(pctl->dev, "Can't get hwspinlock\n");
431 			goto unlock;
432 		}
433 	}
434 
435 	if (pctl->irqmux_map & BIT(irq_data->hwirq)) {
436 		dev_err(pctl->dev, "irq line %ld already requested.\n",
437 			irq_data->hwirq);
438 		ret = -EBUSY;
439 		if (pctl->hwlock)
440 			hwspin_unlock_in_atomic(pctl->hwlock);
441 		goto unlock;
442 	} else {
443 		pctl->irqmux_map |= BIT(irq_data->hwirq);
444 	}
445 
446 	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
447 
448 	if (pctl->hwlock)
449 		hwspin_unlock_in_atomic(pctl->hwlock);
450 
451 unlock:
452 	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
453 	return ret;
454 }
455 
456 static void stm32_gpio_domain_deactivate(struct irq_domain *d,
457 					 struct irq_data *irq_data)
458 {
459 	struct stm32_gpio_bank *bank = d->host_data;
460 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
461 	unsigned long flags;
462 
463 	spin_lock_irqsave(&pctl->irqmux_lock, flags);
464 	pctl->irqmux_map &= ~BIT(irq_data->hwirq);
465 	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
466 }
467 
468 static int stm32_gpio_domain_alloc(struct irq_domain *d,
469 				   unsigned int virq,
470 				   unsigned int nr_irqs, void *data)
471 {
472 	struct stm32_gpio_bank *bank = d->host_data;
473 	struct irq_fwspec *fwspec = data;
474 	struct irq_fwspec parent_fwspec;
475 	irq_hw_number_t hwirq;
476 
477 	hwirq = fwspec->param[0];
478 	parent_fwspec.fwnode = d->parent->fwnode;
479 	parent_fwspec.param_count = 2;
480 	parent_fwspec.param[0] = fwspec->param[0];
481 	parent_fwspec.param[1] = fwspec->param[1];
482 
483 	irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
484 				      bank);
485 
486 	return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
487 }
488 
489 static const struct irq_domain_ops stm32_gpio_domain_ops = {
490 	.translate      = stm32_gpio_domain_translate,
491 	.alloc          = stm32_gpio_domain_alloc,
492 	.free           = irq_domain_free_irqs_common,
493 	.activate	= stm32_gpio_domain_activate,
494 	.deactivate	= stm32_gpio_domain_deactivate,
495 };
496 
497 /* Pinctrl functions */
498 static struct stm32_pinctrl_group *
499 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
500 {
501 	int i;
502 
503 	for (i = 0; i < pctl->ngroups; i++) {
504 		struct stm32_pinctrl_group *grp = pctl->groups + i;
505 
506 		if (grp->pin == pin)
507 			return grp;
508 	}
509 
510 	return NULL;
511 }
512 
513 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
514 		u32 pin_num, u32 fnum)
515 {
516 	int i;
517 
518 	for (i = 0; i < pctl->npins; i++) {
519 		const struct stm32_desc_pin *pin = pctl->pins + i;
520 		const struct stm32_desc_function *func = pin->functions;
521 
522 		if (pin->pin.number != pin_num)
523 			continue;
524 
525 		while (func && func->name) {
526 			if (func->num == fnum)
527 				return true;
528 			func++;
529 		}
530 
531 		break;
532 	}
533 
534 	return false;
535 }
536 
537 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
538 		u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
539 		struct pinctrl_map **map, unsigned *reserved_maps,
540 		unsigned *num_maps)
541 {
542 	if (*num_maps == *reserved_maps)
543 		return -ENOSPC;
544 
545 	(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
546 	(*map)[*num_maps].data.mux.group = grp->name;
547 
548 	if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
549 		dev_err(pctl->dev, "invalid function %d on pin %d .\n",
550 				fnum, pin);
551 		return -EINVAL;
552 	}
553 
554 	(*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
555 	(*num_maps)++;
556 
557 	return 0;
558 }
559 
560 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
561 				      struct device_node *node,
562 				      struct pinctrl_map **map,
563 				      unsigned *reserved_maps,
564 				      unsigned *num_maps)
565 {
566 	struct stm32_pinctrl *pctl;
567 	struct stm32_pinctrl_group *grp;
568 	struct property *pins;
569 	u32 pinfunc, pin, func;
570 	unsigned long *configs;
571 	unsigned int num_configs;
572 	bool has_config = 0;
573 	unsigned reserve = 0;
574 	int num_pins, num_funcs, maps_per_pin, i, err = 0;
575 
576 	pctl = pinctrl_dev_get_drvdata(pctldev);
577 
578 	pins = of_find_property(node, "pinmux", NULL);
579 	if (!pins) {
580 		dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
581 				node);
582 		return -EINVAL;
583 	}
584 
585 	err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
586 		&num_configs);
587 	if (err)
588 		return err;
589 
590 	if (num_configs)
591 		has_config = 1;
592 
593 	num_pins = pins->length / sizeof(u32);
594 	num_funcs = num_pins;
595 	maps_per_pin = 0;
596 	if (num_funcs)
597 		maps_per_pin++;
598 	if (has_config && num_pins >= 1)
599 		maps_per_pin++;
600 
601 	if (!num_pins || !maps_per_pin) {
602 		err = -EINVAL;
603 		goto exit;
604 	}
605 
606 	reserve = num_pins * maps_per_pin;
607 
608 	err = pinctrl_utils_reserve_map(pctldev, map,
609 			reserved_maps, num_maps, reserve);
610 	if (err)
611 		goto exit;
612 
613 	for (i = 0; i < num_pins; i++) {
614 		err = of_property_read_u32_index(node, "pinmux",
615 				i, &pinfunc);
616 		if (err)
617 			goto exit;
618 
619 		pin = STM32_GET_PIN_NO(pinfunc);
620 		func = STM32_GET_PIN_FUNC(pinfunc);
621 
622 		if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
623 			dev_err(pctl->dev, "invalid function.\n");
624 			err = -EINVAL;
625 			goto exit;
626 		}
627 
628 		grp = stm32_pctrl_find_group_by_pin(pctl, pin);
629 		if (!grp) {
630 			dev_err(pctl->dev, "unable to match pin %d to group\n",
631 					pin);
632 			err = -EINVAL;
633 			goto exit;
634 		}
635 
636 		err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
637 				reserved_maps, num_maps);
638 		if (err)
639 			goto exit;
640 
641 		if (has_config) {
642 			err = pinctrl_utils_add_map_configs(pctldev, map,
643 					reserved_maps, num_maps, grp->name,
644 					configs, num_configs,
645 					PIN_MAP_TYPE_CONFIGS_GROUP);
646 			if (err)
647 				goto exit;
648 		}
649 	}
650 
651 exit:
652 	kfree(configs);
653 	return err;
654 }
655 
656 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
657 				 struct device_node *np_config,
658 				 struct pinctrl_map **map, unsigned *num_maps)
659 {
660 	struct device_node *np;
661 	unsigned reserved_maps;
662 	int ret;
663 
664 	*map = NULL;
665 	*num_maps = 0;
666 	reserved_maps = 0;
667 
668 	for_each_child_of_node(np_config, np) {
669 		ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
670 				&reserved_maps, num_maps);
671 		if (ret < 0) {
672 			pinctrl_utils_free_map(pctldev, *map, *num_maps);
673 			of_node_put(np);
674 			return ret;
675 		}
676 	}
677 
678 	return 0;
679 }
680 
681 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
682 {
683 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
684 
685 	return pctl->ngroups;
686 }
687 
688 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
689 					      unsigned group)
690 {
691 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
692 
693 	return pctl->groups[group].name;
694 }
695 
696 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
697 				      unsigned group,
698 				      const unsigned **pins,
699 				      unsigned *num_pins)
700 {
701 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
702 
703 	*pins = (unsigned *)&pctl->groups[group].pin;
704 	*num_pins = 1;
705 
706 	return 0;
707 }
708 
709 static const struct pinctrl_ops stm32_pctrl_ops = {
710 	.dt_node_to_map		= stm32_pctrl_dt_node_to_map,
711 	.dt_free_map		= pinctrl_utils_free_map,
712 	.get_groups_count	= stm32_pctrl_get_groups_count,
713 	.get_group_name		= stm32_pctrl_get_group_name,
714 	.get_group_pins		= stm32_pctrl_get_group_pins,
715 };
716 
717 
718 /* Pinmux functions */
719 
720 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
721 {
722 	return ARRAY_SIZE(stm32_gpio_functions);
723 }
724 
725 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
726 					   unsigned selector)
727 {
728 	return stm32_gpio_functions[selector];
729 }
730 
731 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
732 				     unsigned function,
733 				     const char * const **groups,
734 				     unsigned * const num_groups)
735 {
736 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
737 
738 	*groups = pctl->grp_names;
739 	*num_groups = pctl->ngroups;
740 
741 	return 0;
742 }
743 
744 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
745 			      int pin, u32 mode, u32 alt)
746 {
747 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
748 	u32 val;
749 	int alt_shift = (pin % 8) * 4;
750 	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
751 	unsigned long flags;
752 	int err = 0;
753 
754 	clk_enable(bank->clk);
755 	spin_lock_irqsave(&bank->lock, flags);
756 
757 	if (pctl->hwlock) {
758 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
759 						    HWSPNLCK_TIMEOUT);
760 		if (err) {
761 			dev_err(pctl->dev, "Can't get hwspinlock\n");
762 			goto unlock;
763 		}
764 	}
765 
766 	val = readl_relaxed(bank->base + alt_offset);
767 	val &= ~GENMASK(alt_shift + 3, alt_shift);
768 	val |= (alt << alt_shift);
769 	writel_relaxed(val, bank->base + alt_offset);
770 
771 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
772 	val &= ~GENMASK(pin * 2 + 1, pin * 2);
773 	val |= mode << (pin * 2);
774 	writel_relaxed(val, bank->base + STM32_GPIO_MODER);
775 
776 	if (pctl->hwlock)
777 		hwspin_unlock_in_atomic(pctl->hwlock);
778 
779 	stm32_gpio_backup_mode(bank, pin, mode, alt);
780 
781 unlock:
782 	spin_unlock_irqrestore(&bank->lock, flags);
783 	clk_disable(bank->clk);
784 
785 	return err;
786 }
787 
788 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
789 			u32 *alt)
790 {
791 	u32 val;
792 	int alt_shift = (pin % 8) * 4;
793 	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
794 	unsigned long flags;
795 
796 	clk_enable(bank->clk);
797 	spin_lock_irqsave(&bank->lock, flags);
798 
799 	val = readl_relaxed(bank->base + alt_offset);
800 	val &= GENMASK(alt_shift + 3, alt_shift);
801 	*alt = val >> alt_shift;
802 
803 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
804 	val &= GENMASK(pin * 2 + 1, pin * 2);
805 	*mode = val >> (pin * 2);
806 
807 	spin_unlock_irqrestore(&bank->lock, flags);
808 	clk_disable(bank->clk);
809 }
810 
811 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
812 			    unsigned function,
813 			    unsigned group)
814 {
815 	bool ret;
816 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
817 	struct stm32_pinctrl_group *g = pctl->groups + group;
818 	struct pinctrl_gpio_range *range;
819 	struct stm32_gpio_bank *bank;
820 	u32 mode, alt;
821 	int pin;
822 
823 	ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
824 	if (!ret) {
825 		dev_err(pctl->dev, "invalid function %d on group %d .\n",
826 				function, group);
827 		return -EINVAL;
828 	}
829 
830 	range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
831 	if (!range) {
832 		dev_err(pctl->dev, "No gpio range defined.\n");
833 		return -EINVAL;
834 	}
835 
836 	bank = gpiochip_get_data(range->gc);
837 	pin = stm32_gpio_pin(g->pin);
838 
839 	mode = stm32_gpio_get_mode(function);
840 	alt = stm32_gpio_get_alt(function);
841 
842 	return stm32_pmx_set_mode(bank, pin, mode, alt);
843 }
844 
845 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
846 			struct pinctrl_gpio_range *range, unsigned gpio,
847 			bool input)
848 {
849 	struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
850 	int pin = stm32_gpio_pin(gpio);
851 
852 	return stm32_pmx_set_mode(bank, pin, !input, 0);
853 }
854 
855 static const struct pinmux_ops stm32_pmx_ops = {
856 	.get_functions_count	= stm32_pmx_get_funcs_cnt,
857 	.get_function_name	= stm32_pmx_get_func_name,
858 	.get_function_groups	= stm32_pmx_get_func_groups,
859 	.set_mux		= stm32_pmx_set_mux,
860 	.gpio_set_direction	= stm32_pmx_gpio_set_direction,
861 	.strict			= true,
862 };
863 
864 /* Pinconf functions */
865 
866 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
867 				   unsigned offset, u32 drive)
868 {
869 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
870 	unsigned long flags;
871 	u32 val;
872 	int err = 0;
873 
874 	clk_enable(bank->clk);
875 	spin_lock_irqsave(&bank->lock, flags);
876 
877 	if (pctl->hwlock) {
878 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
879 						    HWSPNLCK_TIMEOUT);
880 		if (err) {
881 			dev_err(pctl->dev, "Can't get hwspinlock\n");
882 			goto unlock;
883 		}
884 	}
885 
886 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
887 	val &= ~BIT(offset);
888 	val |= drive << offset;
889 	writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
890 
891 	if (pctl->hwlock)
892 		hwspin_unlock_in_atomic(pctl->hwlock);
893 
894 	stm32_gpio_backup_driving(bank, offset, drive);
895 
896 unlock:
897 	spin_unlock_irqrestore(&bank->lock, flags);
898 	clk_disable(bank->clk);
899 
900 	return err;
901 }
902 
903 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
904 	unsigned int offset)
905 {
906 	unsigned long flags;
907 	u32 val;
908 
909 	clk_enable(bank->clk);
910 	spin_lock_irqsave(&bank->lock, flags);
911 
912 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
913 	val &= BIT(offset);
914 
915 	spin_unlock_irqrestore(&bank->lock, flags);
916 	clk_disable(bank->clk);
917 
918 	return (val >> offset);
919 }
920 
921 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
922 				 unsigned offset, u32 speed)
923 {
924 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
925 	unsigned long flags;
926 	u32 val;
927 	int err = 0;
928 
929 	clk_enable(bank->clk);
930 	spin_lock_irqsave(&bank->lock, flags);
931 
932 	if (pctl->hwlock) {
933 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
934 						    HWSPNLCK_TIMEOUT);
935 		if (err) {
936 			dev_err(pctl->dev, "Can't get hwspinlock\n");
937 			goto unlock;
938 		}
939 	}
940 
941 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
942 	val &= ~GENMASK(offset * 2 + 1, offset * 2);
943 	val |= speed << (offset * 2);
944 	writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
945 
946 	if (pctl->hwlock)
947 		hwspin_unlock_in_atomic(pctl->hwlock);
948 
949 	stm32_gpio_backup_speed(bank, offset, speed);
950 
951 unlock:
952 	spin_unlock_irqrestore(&bank->lock, flags);
953 	clk_disable(bank->clk);
954 
955 	return err;
956 }
957 
958 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
959 	unsigned int offset)
960 {
961 	unsigned long flags;
962 	u32 val;
963 
964 	clk_enable(bank->clk);
965 	spin_lock_irqsave(&bank->lock, flags);
966 
967 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
968 	val &= GENMASK(offset * 2 + 1, offset * 2);
969 
970 	spin_unlock_irqrestore(&bank->lock, flags);
971 	clk_disable(bank->clk);
972 
973 	return (val >> (offset * 2));
974 }
975 
976 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
977 				unsigned offset, u32 bias)
978 {
979 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
980 	unsigned long flags;
981 	u32 val;
982 	int err = 0;
983 
984 	clk_enable(bank->clk);
985 	spin_lock_irqsave(&bank->lock, flags);
986 
987 	if (pctl->hwlock) {
988 		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
989 						    HWSPNLCK_TIMEOUT);
990 		if (err) {
991 			dev_err(pctl->dev, "Can't get hwspinlock\n");
992 			goto unlock;
993 		}
994 	}
995 
996 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
997 	val &= ~GENMASK(offset * 2 + 1, offset * 2);
998 	val |= bias << (offset * 2);
999 	writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
1000 
1001 	if (pctl->hwlock)
1002 		hwspin_unlock_in_atomic(pctl->hwlock);
1003 
1004 	stm32_gpio_backup_bias(bank, offset, bias);
1005 
1006 unlock:
1007 	spin_unlock_irqrestore(&bank->lock, flags);
1008 	clk_disable(bank->clk);
1009 
1010 	return err;
1011 }
1012 
1013 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1014 	unsigned int offset)
1015 {
1016 	unsigned long flags;
1017 	u32 val;
1018 
1019 	clk_enable(bank->clk);
1020 	spin_lock_irqsave(&bank->lock, flags);
1021 
1022 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1023 	val &= GENMASK(offset * 2 + 1, offset * 2);
1024 
1025 	spin_unlock_irqrestore(&bank->lock, flags);
1026 	clk_disable(bank->clk);
1027 
1028 	return (val >> (offset * 2));
1029 }
1030 
1031 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1032 	unsigned int offset, bool dir)
1033 {
1034 	unsigned long flags;
1035 	u32 val;
1036 
1037 	clk_enable(bank->clk);
1038 	spin_lock_irqsave(&bank->lock, flags);
1039 
1040 	if (dir)
1041 		val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1042 			 BIT(offset));
1043 	else
1044 		val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1045 			 BIT(offset));
1046 
1047 	spin_unlock_irqrestore(&bank->lock, flags);
1048 	clk_disable(bank->clk);
1049 
1050 	return val;
1051 }
1052 
1053 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
1054 		unsigned int pin, enum pin_config_param param,
1055 		enum pin_config_param arg)
1056 {
1057 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1058 	struct pinctrl_gpio_range *range;
1059 	struct stm32_gpio_bank *bank;
1060 	int offset, ret = 0;
1061 
1062 	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1063 	if (!range) {
1064 		dev_err(pctl->dev, "No gpio range defined.\n");
1065 		return -EINVAL;
1066 	}
1067 
1068 	bank = gpiochip_get_data(range->gc);
1069 	offset = stm32_gpio_pin(pin);
1070 
1071 	switch (param) {
1072 	case PIN_CONFIG_DRIVE_PUSH_PULL:
1073 		ret = stm32_pconf_set_driving(bank, offset, 0);
1074 		break;
1075 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1076 		ret = stm32_pconf_set_driving(bank, offset, 1);
1077 		break;
1078 	case PIN_CONFIG_SLEW_RATE:
1079 		ret = stm32_pconf_set_speed(bank, offset, arg);
1080 		break;
1081 	case PIN_CONFIG_BIAS_DISABLE:
1082 		ret = stm32_pconf_set_bias(bank, offset, 0);
1083 		break;
1084 	case PIN_CONFIG_BIAS_PULL_UP:
1085 		ret = stm32_pconf_set_bias(bank, offset, 1);
1086 		break;
1087 	case PIN_CONFIG_BIAS_PULL_DOWN:
1088 		ret = stm32_pconf_set_bias(bank, offset, 2);
1089 		break;
1090 	case PIN_CONFIG_OUTPUT:
1091 		__stm32_gpio_set(bank, offset, arg);
1092 		ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1093 		break;
1094 	default:
1095 		ret = -ENOTSUPP;
1096 	}
1097 
1098 	return ret;
1099 }
1100 
1101 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
1102 				 unsigned group,
1103 				 unsigned long *config)
1104 {
1105 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1106 
1107 	*config = pctl->groups[group].config;
1108 
1109 	return 0;
1110 }
1111 
1112 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
1113 				 unsigned long *configs, unsigned num_configs)
1114 {
1115 	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1116 	struct stm32_pinctrl_group *g = &pctl->groups[group];
1117 	int i, ret;
1118 
1119 	for (i = 0; i < num_configs; i++) {
1120 		mutex_lock(&pctldev->mutex);
1121 		ret = stm32_pconf_parse_conf(pctldev, g->pin,
1122 			pinconf_to_config_param(configs[i]),
1123 			pinconf_to_config_argument(configs[i]));
1124 		mutex_unlock(&pctldev->mutex);
1125 		if (ret < 0)
1126 			return ret;
1127 
1128 		g->config = configs[i];
1129 	}
1130 
1131 	return 0;
1132 }
1133 
1134 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1135 			   unsigned long *configs, unsigned int num_configs)
1136 {
1137 	int i, ret;
1138 
1139 	for (i = 0; i < num_configs; i++) {
1140 		ret = stm32_pconf_parse_conf(pctldev, pin,
1141 				pinconf_to_config_param(configs[i]),
1142 				pinconf_to_config_argument(configs[i]));
1143 		if (ret < 0)
1144 			return ret;
1145 	}
1146 
1147 	return 0;
1148 }
1149 
1150 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
1151 				 struct seq_file *s,
1152 				 unsigned int pin)
1153 {
1154 	struct pinctrl_gpio_range *range;
1155 	struct stm32_gpio_bank *bank;
1156 	int offset;
1157 	u32 mode, alt, drive, speed, bias;
1158 	static const char * const modes[] = {
1159 			"input", "output", "alternate", "analog" };
1160 	static const char * const speeds[] = {
1161 			"low", "medium", "high", "very high" };
1162 	static const char * const biasing[] = {
1163 			"floating", "pull up", "pull down", "" };
1164 	bool val;
1165 
1166 	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1167 	if (!range)
1168 		return;
1169 
1170 	bank = gpiochip_get_data(range->gc);
1171 	offset = stm32_gpio_pin(pin);
1172 
1173 	stm32_pmx_get_mode(bank, offset, &mode, &alt);
1174 	bias = stm32_pconf_get_bias(bank, offset);
1175 
1176 	seq_printf(s, "%s ", modes[mode]);
1177 
1178 	switch (mode) {
1179 	/* input */
1180 	case 0:
1181 		val = stm32_pconf_get(bank, offset, true);
1182 		seq_printf(s, "- %s - %s",
1183 			   val ? "high" : "low",
1184 			   biasing[bias]);
1185 		break;
1186 
1187 	/* output */
1188 	case 1:
1189 		drive = stm32_pconf_get_driving(bank, offset);
1190 		speed = stm32_pconf_get_speed(bank, offset);
1191 		val = stm32_pconf_get(bank, offset, false);
1192 		seq_printf(s, "- %s - %s - %s - %s %s",
1193 			   val ? "high" : "low",
1194 			   drive ? "open drain" : "push pull",
1195 			   biasing[bias],
1196 			   speeds[speed], "speed");
1197 		break;
1198 
1199 	/* alternate */
1200 	case 2:
1201 		drive = stm32_pconf_get_driving(bank, offset);
1202 		speed = stm32_pconf_get_speed(bank, offset);
1203 		seq_printf(s, "%d - %s - %s - %s %s", alt,
1204 			   drive ? "open drain" : "push pull",
1205 			   biasing[bias],
1206 			   speeds[speed], "speed");
1207 		break;
1208 
1209 	/* analog */
1210 	case 3:
1211 		break;
1212 	}
1213 }
1214 
1215 static const struct pinconf_ops stm32_pconf_ops = {
1216 	.pin_config_group_get	= stm32_pconf_group_get,
1217 	.pin_config_group_set	= stm32_pconf_group_set,
1218 	.pin_config_set		= stm32_pconf_set,
1219 	.pin_config_dbg_show	= stm32_pconf_dbg_show,
1220 };
1221 
1222 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
1223 	struct device_node *np)
1224 {
1225 	struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1226 	int bank_ioport_nr;
1227 	struct pinctrl_gpio_range *range = &bank->range;
1228 	struct of_phandle_args args;
1229 	struct device *dev = pctl->dev;
1230 	struct resource res;
1231 	int npins = STM32_GPIO_PINS_PER_BANK;
1232 	int bank_nr, err;
1233 
1234 	if (!IS_ERR(bank->rstc))
1235 		reset_control_deassert(bank->rstc);
1236 
1237 	if (of_address_to_resource(np, 0, &res))
1238 		return -ENODEV;
1239 
1240 	bank->base = devm_ioremap_resource(dev, &res);
1241 	if (IS_ERR(bank->base))
1242 		return PTR_ERR(bank->base);
1243 
1244 	err = clk_prepare(bank->clk);
1245 	if (err) {
1246 		dev_err(dev, "failed to prepare clk (%d)\n", err);
1247 		return err;
1248 	}
1249 
1250 	bank->gpio_chip = stm32_gpio_template;
1251 
1252 	of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
1253 
1254 	if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) {
1255 		bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1256 		bank->gpio_chip.base = args.args[1];
1257 	} else {
1258 		bank_nr = pctl->nbanks;
1259 		bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1260 		range->name = bank->gpio_chip.label;
1261 		range->id = bank_nr;
1262 		range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1263 		range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1264 		range->npins = npins;
1265 		range->gc = &bank->gpio_chip;
1266 		pinctrl_add_gpio_range(pctl->pctl_dev,
1267 				       &pctl->banks[bank_nr].range);
1268 	}
1269 
1270 	if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))
1271 		bank_ioport_nr = bank_nr;
1272 
1273 	bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1274 
1275 	bank->gpio_chip.ngpio = npins;
1276 	bank->gpio_chip.of_node = np;
1277 	bank->gpio_chip.parent = dev;
1278 	bank->bank_nr = bank_nr;
1279 	bank->bank_ioport_nr = bank_ioport_nr;
1280 	spin_lock_init(&bank->lock);
1281 
1282 	/* create irq hierarchical domain */
1283 	bank->fwnode = of_node_to_fwnode(np);
1284 
1285 	bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
1286 					STM32_GPIO_IRQ_LINE, bank->fwnode,
1287 					&stm32_gpio_domain_ops, bank);
1288 
1289 	if (!bank->domain)
1290 		return -ENODEV;
1291 
1292 	err = gpiochip_add_data(&bank->gpio_chip, bank);
1293 	if (err) {
1294 		dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1295 		return err;
1296 	}
1297 
1298 	dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1299 	return 0;
1300 }
1301 
1302 static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np)
1303 {
1304 	struct device_node *parent;
1305 	struct irq_domain *domain;
1306 
1307 	if (!of_find_property(np, "interrupt-parent", NULL))
1308 		return NULL;
1309 
1310 	parent = of_irq_find_parent(np);
1311 	if (!parent)
1312 		return ERR_PTR(-ENXIO);
1313 
1314 	domain = irq_find_host(parent);
1315 	if (!domain)
1316 		/* domain not registered yet */
1317 		return ERR_PTR(-EPROBE_DEFER);
1318 
1319 	return domain;
1320 }
1321 
1322 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1323 			   struct stm32_pinctrl *pctl)
1324 {
1325 	struct device_node *np = pdev->dev.of_node;
1326 	struct device *dev = &pdev->dev;
1327 	struct regmap *rm;
1328 	int offset, ret, i;
1329 	int mask, mask_width;
1330 
1331 	pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1332 	if (IS_ERR(pctl->regmap))
1333 		return PTR_ERR(pctl->regmap);
1334 
1335 	rm = pctl->regmap;
1336 
1337 	ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1338 	if (ret)
1339 		return ret;
1340 
1341 	ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1342 	if (ret)
1343 		mask = SYSCFG_IRQMUX_MASK;
1344 
1345 	mask_width = fls(mask);
1346 
1347 	for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1348 		struct reg_field mux;
1349 
1350 		mux.reg = offset + (i / 4) * 4;
1351 		mux.lsb = (i % 4) * mask_width;
1352 		mux.msb = mux.lsb + mask_width - 1;
1353 
1354 		dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1355 			i, mux.reg, mux.lsb, mux.msb);
1356 
1357 		pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1358 		if (IS_ERR(pctl->irqmux[i]))
1359 			return PTR_ERR(pctl->irqmux[i]);
1360 	}
1361 
1362 	return 0;
1363 }
1364 
1365 static int stm32_pctrl_build_state(struct platform_device *pdev)
1366 {
1367 	struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1368 	int i;
1369 
1370 	pctl->ngroups = pctl->npins;
1371 
1372 	/* Allocate groups */
1373 	pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1374 				    sizeof(*pctl->groups), GFP_KERNEL);
1375 	if (!pctl->groups)
1376 		return -ENOMEM;
1377 
1378 	/* We assume that one pin is one group, use pin name as group name. */
1379 	pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1380 				       sizeof(*pctl->grp_names), GFP_KERNEL);
1381 	if (!pctl->grp_names)
1382 		return -ENOMEM;
1383 
1384 	for (i = 0; i < pctl->npins; i++) {
1385 		const struct stm32_desc_pin *pin = pctl->pins + i;
1386 		struct stm32_pinctrl_group *group = pctl->groups + i;
1387 
1388 		group->name = pin->pin.name;
1389 		group->pin = pin->pin.number;
1390 		pctl->grp_names[i] = pin->pin.name;
1391 	}
1392 
1393 	return 0;
1394 }
1395 
1396 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1397 				       struct stm32_desc_pin *pins)
1398 {
1399 	const struct stm32_desc_pin *p;
1400 	int i, nb_pins_available = 0;
1401 
1402 	for (i = 0; i < pctl->match_data->npins; i++) {
1403 		p = pctl->match_data->pins + i;
1404 		if (pctl->pkg && !(pctl->pkg & p->pkg))
1405 			continue;
1406 		pins->pin = p->pin;
1407 		pins->functions = p->functions;
1408 		pins++;
1409 		nb_pins_available++;
1410 	}
1411 
1412 	pctl->npins = nb_pins_available;
1413 
1414 	return 0;
1415 }
1416 
1417 static void stm32_pctl_get_package(struct device_node *np,
1418 				   struct stm32_pinctrl *pctl)
1419 {
1420 	if (of_property_read_u32(np, "st,package", &pctl->pkg)) {
1421 		pctl->pkg = 0;
1422 		dev_warn(pctl->dev, "No package detected, use default one\n");
1423 	} else {
1424 		dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1425 	}
1426 }
1427 
1428 int stm32_pctl_probe(struct platform_device *pdev)
1429 {
1430 	struct device_node *np = pdev->dev.of_node;
1431 	struct device_node *child;
1432 	const struct of_device_id *match;
1433 	struct device *dev = &pdev->dev;
1434 	struct stm32_pinctrl *pctl;
1435 	struct pinctrl_pin_desc *pins;
1436 	int i, ret, hwlock_id, banks = 0;
1437 
1438 	if (!np)
1439 		return -EINVAL;
1440 
1441 	match = of_match_device(dev->driver->of_match_table, dev);
1442 	if (!match || !match->data)
1443 		return -EINVAL;
1444 
1445 	if (!of_find_property(np, "pins-are-numbered", NULL)) {
1446 		dev_err(dev, "only support pins-are-numbered format\n");
1447 		return -EINVAL;
1448 	}
1449 
1450 	pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1451 	if (!pctl)
1452 		return -ENOMEM;
1453 
1454 	platform_set_drvdata(pdev, pctl);
1455 
1456 	/* check for IRQ controller (may require deferred probe) */
1457 	pctl->domain = stm32_pctrl_get_irq_domain(np);
1458 	if (IS_ERR(pctl->domain))
1459 		return PTR_ERR(pctl->domain);
1460 
1461 	/* hwspinlock is optional */
1462 	hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1463 	if (hwlock_id < 0) {
1464 		if (hwlock_id == -EPROBE_DEFER)
1465 			return hwlock_id;
1466 	} else {
1467 		pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1468 	}
1469 
1470 	spin_lock_init(&pctl->irqmux_lock);
1471 
1472 	pctl->dev = dev;
1473 	pctl->match_data = match->data;
1474 
1475 	/*  get package information */
1476 	stm32_pctl_get_package(np, pctl);
1477 
1478 	pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1479 				  sizeof(*pctl->pins), GFP_KERNEL);
1480 	if (!pctl->pins)
1481 		return -ENOMEM;
1482 
1483 	ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1484 	if (ret)
1485 		return ret;
1486 
1487 	ret = stm32_pctrl_build_state(pdev);
1488 	if (ret) {
1489 		dev_err(dev, "build state failed: %d\n", ret);
1490 		return -EINVAL;
1491 	}
1492 
1493 	if (pctl->domain) {
1494 		ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1495 		if (ret)
1496 			return ret;
1497 	}
1498 
1499 	pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1500 			    GFP_KERNEL);
1501 	if (!pins)
1502 		return -ENOMEM;
1503 
1504 	for (i = 0; i < pctl->npins; i++)
1505 		pins[i] = pctl->pins[i].pin;
1506 
1507 	pctl->pctl_desc.name = dev_name(&pdev->dev);
1508 	pctl->pctl_desc.owner = THIS_MODULE;
1509 	pctl->pctl_desc.pins = pins;
1510 	pctl->pctl_desc.npins = pctl->npins;
1511 	pctl->pctl_desc.link_consumers = true;
1512 	pctl->pctl_desc.confops = &stm32_pconf_ops;
1513 	pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1514 	pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1515 	pctl->dev = &pdev->dev;
1516 
1517 	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1518 					       pctl);
1519 
1520 	if (IS_ERR(pctl->pctl_dev)) {
1521 		dev_err(&pdev->dev, "Failed pinctrl registration\n");
1522 		return PTR_ERR(pctl->pctl_dev);
1523 	}
1524 
1525 	for_each_available_child_of_node(np, child)
1526 		if (of_property_read_bool(child, "gpio-controller"))
1527 			banks++;
1528 
1529 	if (!banks) {
1530 		dev_err(dev, "at least one GPIO bank is required\n");
1531 		return -EINVAL;
1532 	}
1533 	pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1534 			GFP_KERNEL);
1535 	if (!pctl->banks)
1536 		return -ENOMEM;
1537 
1538 	i = 0;
1539 	for_each_available_child_of_node(np, child) {
1540 		struct stm32_gpio_bank *bank = &pctl->banks[i];
1541 
1542 		if (of_property_read_bool(child, "gpio-controller")) {
1543 			bank->rstc = of_reset_control_get_exclusive(child,
1544 								    NULL);
1545 			if (PTR_ERR(bank->rstc) == -EPROBE_DEFER)
1546 				return -EPROBE_DEFER;
1547 
1548 			bank->clk = of_clk_get_by_name(child, NULL);
1549 			if (IS_ERR(bank->clk)) {
1550 				if (PTR_ERR(bank->clk) != -EPROBE_DEFER)
1551 					dev_err(dev,
1552 						"failed to get clk (%ld)\n",
1553 						PTR_ERR(bank->clk));
1554 				return PTR_ERR(bank->clk);
1555 			}
1556 			i++;
1557 		}
1558 	}
1559 
1560 	for_each_available_child_of_node(np, child) {
1561 		if (of_property_read_bool(child, "gpio-controller")) {
1562 			ret = stm32_gpiolib_register_bank(pctl, child);
1563 			if (ret) {
1564 				of_node_put(child);
1565 				return ret;
1566 			}
1567 
1568 			pctl->nbanks++;
1569 		}
1570 	}
1571 
1572 	dev_info(dev, "Pinctrl STM32 initialized\n");
1573 
1574 	return 0;
1575 }
1576 
1577 static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
1578 					struct stm32_pinctrl *pctl, u32 pin)
1579 {
1580 	const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1581 	u32 val, alt, mode, offset = stm32_gpio_pin(pin);
1582 	struct pinctrl_gpio_range *range;
1583 	struct stm32_gpio_bank *bank;
1584 	bool pin_is_irq;
1585 	int ret;
1586 
1587 	range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1588 	if (!range)
1589 		return 0;
1590 
1591 	pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
1592 
1593 	if (!desc || (!pin_is_irq && !desc->gpio_owner))
1594 		return 0;
1595 
1596 	bank = gpiochip_get_data(range->gc);
1597 
1598 	alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1599 	alt >>= STM32_GPIO_BKP_ALT_SHIFT;
1600 	mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1601 	mode >>= STM32_GPIO_BKP_MODE_SHIFT;
1602 
1603 	ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1604 	if (ret)
1605 		return ret;
1606 
1607 	if (mode == 1) {
1608 		val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1609 		val = val >> STM32_GPIO_BKP_VAL;
1610 		__stm32_gpio_set(bank, offset, val);
1611 	}
1612 
1613 	val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1614 	val >>= STM32_GPIO_BKP_TYPE;
1615 	ret = stm32_pconf_set_driving(bank, offset, val);
1616 	if (ret)
1617 		return ret;
1618 
1619 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1620 	val >>= STM32_GPIO_BKP_SPEED_SHIFT;
1621 	ret = stm32_pconf_set_speed(bank, offset, val);
1622 	if (ret)
1623 		return ret;
1624 
1625 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1626 	val >>= STM32_GPIO_BKP_PUPD_SHIFT;
1627 	ret = stm32_pconf_set_bias(bank, offset, val);
1628 	if (ret)
1629 		return ret;
1630 
1631 	if (pin_is_irq)
1632 		regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1633 
1634 	return 0;
1635 }
1636 
1637 int __maybe_unused stm32_pinctrl_resume(struct device *dev)
1638 {
1639 	struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1640 	struct stm32_pinctrl_group *g = pctl->groups;
1641 	int i;
1642 
1643 	for (i = g->pin; i < g->pin + pctl->ngroups; i++)
1644 		stm32_pinctrl_restore_gpio_regs(pctl, i);
1645 
1646 	return 0;
1647 }
1648