1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * 7 * Heavily based on Mediatek's pinctrl driver 8 */ 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/hwspinlock.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_irq.h> 19 #include <linux/platform_device.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/reset.h> 23 #include <linux/seq_file.h> 24 #include <linux/slab.h> 25 #include <linux/string_choices.h> 26 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/pinctrl/machine.h> 29 #include <linux/pinctrl/pinconf-generic.h> 30 #include <linux/pinctrl/pinconf.h> 31 #include <linux/pinctrl/pinctrl.h> 32 #include <linux/pinctrl/pinmux.h> 33 34 #include "../core.h" 35 #include "../pinconf.h" 36 #include "../pinctrl-utils.h" 37 #include "pinctrl-stm32.h" 38 39 #define STM32_GPIO_MODER 0x00 40 #define STM32_GPIO_TYPER 0x04 41 #define STM32_GPIO_SPEEDR 0x08 42 #define STM32_GPIO_PUPDR 0x0c 43 #define STM32_GPIO_IDR 0x10 44 #define STM32_GPIO_ODR 0x14 45 #define STM32_GPIO_BSRR 0x18 46 #define STM32_GPIO_LCKR 0x1c 47 #define STM32_GPIO_AFRL 0x20 48 #define STM32_GPIO_AFRH 0x24 49 #define STM32_GPIO_SECCFGR 0x30 50 51 /* custom bitfield to backup pin status */ 52 #define STM32_GPIO_BKP_MODE_SHIFT 0 53 #define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0) 54 #define STM32_GPIO_BKP_ALT_SHIFT 2 55 #define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2) 56 #define STM32_GPIO_BKP_SPEED_SHIFT 6 57 #define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6) 58 #define STM32_GPIO_BKP_PUPD_SHIFT 8 59 #define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8) 60 #define STM32_GPIO_BKP_TYPE 10 61 #define STM32_GPIO_BKP_VAL 11 62 63 #define STM32_GPIO_PINS_PER_BANK 16 64 #define STM32_GPIO_IRQ_LINE 16 65 66 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0) 67 68 #define gpio_range_to_bank(chip) \ 69 container_of(chip, struct stm32_gpio_bank, range) 70 71 #define HWSPNLCK_TIMEOUT 1000 /* usec */ 72 73 static const char * const stm32_gpio_functions[] = { 74 "gpio", "af0", "af1", 75 "af2", "af3", "af4", 76 "af5", "af6", "af7", 77 "af8", "af9", "af10", 78 "af11", "af12", "af13", 79 "af14", "af15", "analog", 80 }; 81 82 struct stm32_pinctrl_group { 83 const char *name; 84 unsigned long config; 85 unsigned pin; 86 }; 87 88 struct stm32_gpio_bank { 89 void __iomem *base; 90 struct reset_control *rstc; 91 spinlock_t lock; 92 struct gpio_chip gpio_chip; 93 struct pinctrl_gpio_range range; 94 struct fwnode_handle *fwnode; 95 struct irq_domain *domain; 96 u32 bank_nr; 97 u32 bank_ioport_nr; 98 u32 pin_backup[STM32_GPIO_PINS_PER_BANK]; 99 u8 irq_type[STM32_GPIO_PINS_PER_BANK]; 100 bool secure_control; 101 }; 102 103 struct stm32_pinctrl { 104 struct device *dev; 105 struct pinctrl_dev *pctl_dev; 106 struct pinctrl_desc pctl_desc; 107 struct stm32_pinctrl_group *groups; 108 unsigned ngroups; 109 const char **grp_names; 110 struct stm32_gpio_bank *banks; 111 struct clk_bulk_data *clks; 112 unsigned nbanks; 113 const struct stm32_pinctrl_match_data *match_data; 114 struct irq_domain *domain; 115 struct regmap *regmap; 116 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; 117 struct hwspinlock *hwlock; 118 struct stm32_desc_pin *pins; 119 u32 npins; 120 u32 pkg; 121 u16 irqmux_map; 122 spinlock_t irqmux_lock; 123 }; 124 125 static inline int stm32_gpio_pin(int gpio) 126 { 127 return gpio % STM32_GPIO_PINS_PER_BANK; 128 } 129 130 static inline u32 stm32_gpio_get_mode(u32 function) 131 { 132 switch (function) { 133 case STM32_PIN_GPIO: 134 return 0; 135 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 136 return 2; 137 case STM32_PIN_ANALOG: 138 return 3; 139 } 140 141 return 0; 142 } 143 144 static inline u32 stm32_gpio_get_alt(u32 function) 145 { 146 switch (function) { 147 case STM32_PIN_GPIO: 148 return 0; 149 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 150 return function - 1; 151 case STM32_PIN_ANALOG: 152 return 0; 153 } 154 155 return 0; 156 } 157 158 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, 159 u32 offset, u32 value) 160 { 161 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); 162 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; 163 } 164 165 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, 166 u32 mode, u32 alt) 167 { 168 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | 169 STM32_GPIO_BKP_ALT_MASK); 170 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; 171 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; 172 } 173 174 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, 175 u32 drive) 176 { 177 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); 178 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; 179 } 180 181 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, 182 u32 speed) 183 { 184 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; 185 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; 186 } 187 188 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, 189 u32 bias) 190 { 191 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; 192 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; 193 } 194 195 /* GPIO functions */ 196 197 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, 198 unsigned offset, int value) 199 { 200 stm32_gpio_backup_value(bank, offset, value); 201 202 if (!value) 203 offset += STM32_GPIO_PINS_PER_BANK; 204 205 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); 206 } 207 208 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) 209 { 210 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 211 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 212 struct pinctrl_gpio_range *range; 213 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); 214 215 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); 216 if (!range) { 217 dev_err(pctl->dev, "pin %d not in range.\n", pin); 218 return -EINVAL; 219 } 220 221 return pinctrl_gpio_request(chip, offset); 222 } 223 224 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) 225 { 226 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 227 228 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 229 } 230 231 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 232 { 233 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 234 235 __stm32_gpio_set(bank, offset, value); 236 } 237 238 static int stm32_gpio_direction_output(struct gpio_chip *chip, 239 unsigned offset, int value) 240 { 241 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 242 243 __stm32_gpio_set(bank, offset, value); 244 245 return pinctrl_gpio_direction_output(chip, offset); 246 } 247 248 249 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 250 { 251 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 252 struct irq_fwspec fwspec; 253 254 fwspec.fwnode = bank->fwnode; 255 fwspec.param_count = 2; 256 fwspec.param[0] = offset; 257 fwspec.param[1] = IRQ_TYPE_NONE; 258 259 return irq_create_fwspec_mapping(&fwspec); 260 } 261 262 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 263 { 264 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 265 int pin = stm32_gpio_pin(offset); 266 int ret; 267 u32 mode, alt; 268 269 stm32_pmx_get_mode(bank, pin, &mode, &alt); 270 if ((alt == 0) && (mode == 0)) 271 ret = GPIO_LINE_DIRECTION_IN; 272 else if ((alt == 0) && (mode == 1)) 273 ret = GPIO_LINE_DIRECTION_OUT; 274 else 275 ret = -EINVAL; 276 277 return ret; 278 } 279 280 static int stm32_gpio_init_valid_mask(struct gpio_chip *chip, 281 unsigned long *valid_mask, 282 unsigned int ngpios) 283 { 284 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 285 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 286 unsigned int i; 287 u32 sec; 288 289 /* All gpio are valid per default */ 290 bitmap_fill(valid_mask, ngpios); 291 292 if (bank->secure_control) { 293 /* Tag secured pins as invalid */ 294 sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR); 295 296 for (i = 0; i < ngpios; i++) { 297 if (sec & BIT(i)) { 298 clear_bit(i, valid_mask); 299 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i); 300 } 301 } 302 } 303 304 return 0; 305 } 306 307 static const struct gpio_chip stm32_gpio_template = { 308 .request = stm32_gpio_request, 309 .free = pinctrl_gpio_free, 310 .get = stm32_gpio_get, 311 .set = stm32_gpio_set, 312 .direction_input = pinctrl_gpio_direction_input, 313 .direction_output = stm32_gpio_direction_output, 314 .to_irq = stm32_gpio_to_irq, 315 .get_direction = stm32_gpio_get_direction, 316 .set_config = gpiochip_generic_config, 317 .init_valid_mask = stm32_gpio_init_valid_mask, 318 }; 319 320 static void stm32_gpio_irq_trigger(struct irq_data *d) 321 { 322 struct stm32_gpio_bank *bank = d->domain->host_data; 323 int level; 324 325 /* Do not access the GPIO if this is not LEVEL triggered IRQ. */ 326 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK)) 327 return; 328 329 /* If level interrupt type then retrig */ 330 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq); 331 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || 332 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) 333 irq_chip_retrigger_hierarchy(d); 334 } 335 336 static void stm32_gpio_irq_eoi(struct irq_data *d) 337 { 338 irq_chip_eoi_parent(d); 339 stm32_gpio_irq_trigger(d); 340 }; 341 342 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type) 343 { 344 struct stm32_gpio_bank *bank = d->domain->host_data; 345 u32 parent_type; 346 347 switch (type) { 348 case IRQ_TYPE_EDGE_RISING: 349 case IRQ_TYPE_EDGE_FALLING: 350 case IRQ_TYPE_EDGE_BOTH: 351 parent_type = type; 352 break; 353 case IRQ_TYPE_LEVEL_HIGH: 354 parent_type = IRQ_TYPE_EDGE_RISING; 355 break; 356 case IRQ_TYPE_LEVEL_LOW: 357 parent_type = IRQ_TYPE_EDGE_FALLING; 358 break; 359 default: 360 return -EINVAL; 361 } 362 363 bank->irq_type[d->hwirq] = type; 364 365 return irq_chip_set_type_parent(d, parent_type); 366 }; 367 368 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) 369 { 370 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 371 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 372 int ret; 373 374 ret = pinctrl_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); 375 if (ret) 376 return ret; 377 378 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); 379 if (ret) { 380 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 381 irq_data->hwirq); 382 return ret; 383 } 384 385 return 0; 386 } 387 388 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) 389 { 390 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 391 392 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); 393 } 394 395 static void stm32_gpio_irq_unmask(struct irq_data *d) 396 { 397 irq_chip_unmask_parent(d); 398 stm32_gpio_irq_trigger(d); 399 } 400 401 static struct irq_chip stm32_gpio_irq_chip = { 402 .name = "stm32gpio", 403 .irq_eoi = stm32_gpio_irq_eoi, 404 .irq_ack = irq_chip_ack_parent, 405 .irq_mask = irq_chip_mask_parent, 406 .irq_unmask = stm32_gpio_irq_unmask, 407 .irq_set_type = stm32_gpio_set_type, 408 .irq_set_wake = irq_chip_set_wake_parent, 409 .irq_request_resources = stm32_gpio_irq_request_resources, 410 .irq_release_resources = stm32_gpio_irq_release_resources, 411 }; 412 413 static int stm32_gpio_domain_translate(struct irq_domain *d, 414 struct irq_fwspec *fwspec, 415 unsigned long *hwirq, 416 unsigned int *type) 417 { 418 if ((fwspec->param_count != 2) || 419 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) 420 return -EINVAL; 421 422 *hwirq = fwspec->param[0]; 423 *type = fwspec->param[1]; 424 return 0; 425 } 426 427 static int stm32_gpio_domain_activate(struct irq_domain *d, 428 struct irq_data *irq_data, bool reserve) 429 { 430 struct stm32_gpio_bank *bank = d->host_data; 431 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 432 int ret = 0; 433 434 if (pctl->hwlock) { 435 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, 436 HWSPNLCK_TIMEOUT); 437 if (ret) { 438 dev_err(pctl->dev, "Can't get hwspinlock\n"); 439 return ret; 440 } 441 } 442 443 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); 444 445 if (pctl->hwlock) 446 hwspin_unlock_in_atomic(pctl->hwlock); 447 448 return ret; 449 } 450 451 static int stm32_gpio_domain_alloc(struct irq_domain *d, 452 unsigned int virq, 453 unsigned int nr_irqs, void *data) 454 { 455 struct stm32_gpio_bank *bank = d->host_data; 456 struct irq_fwspec *fwspec = data; 457 struct irq_fwspec parent_fwspec; 458 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 459 irq_hw_number_t hwirq = fwspec->param[0]; 460 unsigned long flags; 461 int ret = 0; 462 463 /* 464 * Check first that the IRQ MUX of that line is free. 465 * gpio irq mux is shared between several banks, protect with a lock 466 */ 467 spin_lock_irqsave(&pctl->irqmux_lock, flags); 468 469 if (pctl->irqmux_map & BIT(hwirq)) { 470 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq); 471 ret = -EBUSY; 472 } else { 473 pctl->irqmux_map |= BIT(hwirq); 474 } 475 476 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 477 if (ret) 478 return ret; 479 480 parent_fwspec.fwnode = d->parent->fwnode; 481 parent_fwspec.param_count = 2; 482 parent_fwspec.param[0] = fwspec->param[0]; 483 parent_fwspec.param[1] = fwspec->param[1]; 484 485 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, 486 bank); 487 488 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); 489 } 490 491 static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq, 492 unsigned int nr_irqs) 493 { 494 struct stm32_gpio_bank *bank = d->host_data; 495 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 496 struct irq_data *irq_data = irq_domain_get_irq_data(d, virq); 497 unsigned long flags, hwirq = irq_data->hwirq; 498 499 irq_domain_free_irqs_common(d, virq, nr_irqs); 500 501 spin_lock_irqsave(&pctl->irqmux_lock, flags); 502 pctl->irqmux_map &= ~BIT(hwirq); 503 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 504 } 505 506 static const struct irq_domain_ops stm32_gpio_domain_ops = { 507 .translate = stm32_gpio_domain_translate, 508 .alloc = stm32_gpio_domain_alloc, 509 .free = stm32_gpio_domain_free, 510 .activate = stm32_gpio_domain_activate, 511 }; 512 513 /* Pinctrl functions */ 514 static struct stm32_pinctrl_group * 515 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) 516 { 517 int i; 518 519 for (i = 0; i < pctl->ngroups; i++) { 520 struct stm32_pinctrl_group *grp = pctl->groups + i; 521 522 if (grp->pin == pin) 523 return grp; 524 } 525 526 return NULL; 527 } 528 529 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, 530 u32 pin_num, u32 fnum) 531 { 532 int i, k; 533 534 for (i = 0; i < pctl->npins; i++) { 535 const struct stm32_desc_pin *pin = pctl->pins + i; 536 const struct stm32_desc_function *func = pin->functions; 537 538 if (pin->pin.number != pin_num) 539 continue; 540 541 for (k = 0; k < STM32_CONFIG_NUM; k++) { 542 if (func->num == fnum) 543 return true; 544 func++; 545 } 546 547 break; 548 } 549 550 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num); 551 552 return false; 553 } 554 555 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, 556 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, 557 struct pinctrl_map **map, unsigned *reserved_maps, 558 unsigned *num_maps) 559 { 560 if (*num_maps == *reserved_maps) 561 return -ENOSPC; 562 563 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 564 (*map)[*num_maps].data.mux.group = grp->name; 565 566 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) 567 return -EINVAL; 568 569 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; 570 (*num_maps)++; 571 572 return 0; 573 } 574 575 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 576 struct device_node *node, 577 struct pinctrl_map **map, 578 unsigned *reserved_maps, 579 unsigned *num_maps) 580 { 581 struct stm32_pinctrl *pctl; 582 struct stm32_pinctrl_group *grp; 583 struct property *pins; 584 u32 pinfunc, pin, func; 585 unsigned long *configs; 586 unsigned int num_configs; 587 bool has_config = 0; 588 unsigned reserve = 0; 589 int num_pins, num_funcs, maps_per_pin, i, err = 0; 590 591 pctl = pinctrl_dev_get_drvdata(pctldev); 592 593 pins = of_find_property(node, "pinmux", NULL); 594 if (!pins) { 595 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", 596 node); 597 return -EINVAL; 598 } 599 600 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 601 &num_configs); 602 if (err) 603 return err; 604 605 if (num_configs) 606 has_config = 1; 607 608 num_pins = pins->length / sizeof(u32); 609 num_funcs = num_pins; 610 maps_per_pin = 0; 611 if (num_funcs) 612 maps_per_pin++; 613 if (has_config && num_pins >= 1) 614 maps_per_pin++; 615 616 if (!num_pins || !maps_per_pin) { 617 err = -EINVAL; 618 goto exit; 619 } 620 621 reserve = num_pins * maps_per_pin; 622 623 err = pinctrl_utils_reserve_map(pctldev, map, 624 reserved_maps, num_maps, reserve); 625 if (err) 626 goto exit; 627 628 for (i = 0; i < num_pins; i++) { 629 err = of_property_read_u32_index(node, "pinmux", 630 i, &pinfunc); 631 if (err) 632 goto exit; 633 634 pin = STM32_GET_PIN_NO(pinfunc); 635 func = STM32_GET_PIN_FUNC(pinfunc); 636 637 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { 638 err = -EINVAL; 639 goto exit; 640 } 641 642 grp = stm32_pctrl_find_group_by_pin(pctl, pin); 643 if (!grp) { 644 dev_err(pctl->dev, "unable to match pin %d to group\n", 645 pin); 646 err = -EINVAL; 647 goto exit; 648 } 649 650 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 651 reserved_maps, num_maps); 652 if (err) 653 goto exit; 654 655 if (has_config) { 656 err = pinctrl_utils_add_map_configs(pctldev, map, 657 reserved_maps, num_maps, grp->name, 658 configs, num_configs, 659 PIN_MAP_TYPE_CONFIGS_GROUP); 660 if (err) 661 goto exit; 662 } 663 } 664 665 exit: 666 kfree(configs); 667 return err; 668 } 669 670 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 671 struct device_node *np_config, 672 struct pinctrl_map **map, unsigned *num_maps) 673 { 674 unsigned reserved_maps; 675 int ret; 676 677 *map = NULL; 678 *num_maps = 0; 679 reserved_maps = 0; 680 681 for_each_child_of_node_scoped(np_config, np) { 682 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, 683 &reserved_maps, num_maps); 684 if (ret < 0) { 685 pinctrl_utils_free_map(pctldev, *map, *num_maps); 686 return ret; 687 } 688 } 689 690 return 0; 691 } 692 693 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 694 { 695 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 696 697 return pctl->ngroups; 698 } 699 700 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, 701 unsigned group) 702 { 703 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 704 705 return pctl->groups[group].name; 706 } 707 708 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 709 unsigned group, 710 const unsigned **pins, 711 unsigned *num_pins) 712 { 713 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 714 715 *pins = (unsigned *)&pctl->groups[group].pin; 716 *num_pins = 1; 717 718 return 0; 719 } 720 721 static const struct pinctrl_ops stm32_pctrl_ops = { 722 .dt_node_to_map = stm32_pctrl_dt_node_to_map, 723 .dt_free_map = pinctrl_utils_free_map, 724 .get_groups_count = stm32_pctrl_get_groups_count, 725 .get_group_name = stm32_pctrl_get_group_name, 726 .get_group_pins = stm32_pctrl_get_group_pins, 727 }; 728 729 730 /* Pinmux functions */ 731 732 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 733 { 734 return ARRAY_SIZE(stm32_gpio_functions); 735 } 736 737 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, 738 unsigned selector) 739 { 740 return stm32_gpio_functions[selector]; 741 } 742 743 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, 744 unsigned function, 745 const char * const **groups, 746 unsigned * const num_groups) 747 { 748 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 749 750 *groups = pctl->grp_names; 751 *num_groups = pctl->ngroups; 752 753 return 0; 754 } 755 756 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 757 int pin, u32 mode, u32 alt) 758 { 759 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 760 u32 val; 761 int alt_shift = (pin % 8) * 4; 762 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 763 unsigned long flags; 764 int err = 0; 765 766 spin_lock_irqsave(&bank->lock, flags); 767 768 if (pctl->hwlock) { 769 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 770 HWSPNLCK_TIMEOUT); 771 if (err) { 772 dev_err(pctl->dev, "Can't get hwspinlock\n"); 773 goto unlock; 774 } 775 } 776 777 val = readl_relaxed(bank->base + alt_offset); 778 val &= ~GENMASK(alt_shift + 3, alt_shift); 779 val |= (alt << alt_shift); 780 writel_relaxed(val, bank->base + alt_offset); 781 782 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 783 val &= ~GENMASK(pin * 2 + 1, pin * 2); 784 val |= mode << (pin * 2); 785 writel_relaxed(val, bank->base + STM32_GPIO_MODER); 786 787 if (pctl->hwlock) 788 hwspin_unlock_in_atomic(pctl->hwlock); 789 790 stm32_gpio_backup_mode(bank, pin, mode, alt); 791 792 unlock: 793 spin_unlock_irqrestore(&bank->lock, flags); 794 795 return err; 796 } 797 798 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, 799 u32 *alt) 800 { 801 u32 val; 802 int alt_shift = (pin % 8) * 4; 803 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 804 unsigned long flags; 805 806 spin_lock_irqsave(&bank->lock, flags); 807 808 val = readl_relaxed(bank->base + alt_offset); 809 val &= GENMASK(alt_shift + 3, alt_shift); 810 *alt = val >> alt_shift; 811 812 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 813 val &= GENMASK(pin * 2 + 1, pin * 2); 814 *mode = val >> (pin * 2); 815 816 spin_unlock_irqrestore(&bank->lock, flags); 817 } 818 819 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, 820 unsigned function, 821 unsigned group) 822 { 823 bool ret; 824 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 825 struct stm32_pinctrl_group *g = pctl->groups + group; 826 struct pinctrl_gpio_range *range; 827 struct stm32_gpio_bank *bank; 828 u32 mode, alt; 829 int pin; 830 831 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); 832 if (!ret) 833 return -EINVAL; 834 835 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); 836 if (!range) { 837 dev_err(pctl->dev, "No gpio range defined.\n"); 838 return -EINVAL; 839 } 840 841 bank = gpiochip_get_data(range->gc); 842 pin = stm32_gpio_pin(g->pin); 843 844 mode = stm32_gpio_get_mode(function); 845 alt = stm32_gpio_get_alt(function); 846 847 return stm32_pmx_set_mode(bank, pin, mode, alt); 848 } 849 850 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 851 struct pinctrl_gpio_range *range, unsigned gpio, 852 bool input) 853 { 854 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); 855 int pin = stm32_gpio_pin(gpio); 856 857 return stm32_pmx_set_mode(bank, pin, !input, 0); 858 } 859 860 static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio) 861 { 862 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 863 struct pinctrl_gpio_range *range; 864 865 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, gpio); 866 if (!range) { 867 dev_err(pctl->dev, "No gpio range defined.\n"); 868 return -EINVAL; 869 } 870 871 if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) { 872 dev_warn(pctl->dev, "Can't access gpio %d\n", gpio); 873 return -EACCES; 874 } 875 876 return 0; 877 } 878 879 static const struct pinmux_ops stm32_pmx_ops = { 880 .get_functions_count = stm32_pmx_get_funcs_cnt, 881 .get_function_name = stm32_pmx_get_func_name, 882 .get_function_groups = stm32_pmx_get_func_groups, 883 .set_mux = stm32_pmx_set_mux, 884 .gpio_set_direction = stm32_pmx_gpio_set_direction, 885 .request = stm32_pmx_request, 886 .strict = true, 887 }; 888 889 /* Pinconf functions */ 890 891 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 892 unsigned offset, u32 drive) 893 { 894 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 895 unsigned long flags; 896 u32 val; 897 int err = 0; 898 899 spin_lock_irqsave(&bank->lock, flags); 900 901 if (pctl->hwlock) { 902 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 903 HWSPNLCK_TIMEOUT); 904 if (err) { 905 dev_err(pctl->dev, "Can't get hwspinlock\n"); 906 goto unlock; 907 } 908 } 909 910 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 911 val &= ~BIT(offset); 912 val |= drive << offset; 913 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); 914 915 if (pctl->hwlock) 916 hwspin_unlock_in_atomic(pctl->hwlock); 917 918 stm32_gpio_backup_driving(bank, offset, drive); 919 920 unlock: 921 spin_unlock_irqrestore(&bank->lock, flags); 922 923 return err; 924 } 925 926 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, 927 unsigned int offset) 928 { 929 unsigned long flags; 930 u32 val; 931 932 spin_lock_irqsave(&bank->lock, flags); 933 934 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 935 val &= BIT(offset); 936 937 spin_unlock_irqrestore(&bank->lock, flags); 938 939 return (val >> offset); 940 } 941 942 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 943 unsigned offset, u32 speed) 944 { 945 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 946 unsigned long flags; 947 u32 val; 948 int err = 0; 949 950 spin_lock_irqsave(&bank->lock, flags); 951 952 if (pctl->hwlock) { 953 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 954 HWSPNLCK_TIMEOUT); 955 if (err) { 956 dev_err(pctl->dev, "Can't get hwspinlock\n"); 957 goto unlock; 958 } 959 } 960 961 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 962 val &= ~GENMASK(offset * 2 + 1, offset * 2); 963 val |= speed << (offset * 2); 964 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); 965 966 if (pctl->hwlock) 967 hwspin_unlock_in_atomic(pctl->hwlock); 968 969 stm32_gpio_backup_speed(bank, offset, speed); 970 971 unlock: 972 spin_unlock_irqrestore(&bank->lock, flags); 973 974 return err; 975 } 976 977 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, 978 unsigned int offset) 979 { 980 unsigned long flags; 981 u32 val; 982 983 spin_lock_irqsave(&bank->lock, flags); 984 985 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 986 val &= GENMASK(offset * 2 + 1, offset * 2); 987 988 spin_unlock_irqrestore(&bank->lock, flags); 989 990 return (val >> (offset * 2)); 991 } 992 993 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 994 unsigned offset, u32 bias) 995 { 996 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 997 unsigned long flags; 998 u32 val; 999 int err = 0; 1000 1001 spin_lock_irqsave(&bank->lock, flags); 1002 1003 if (pctl->hwlock) { 1004 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 1005 HWSPNLCK_TIMEOUT); 1006 if (err) { 1007 dev_err(pctl->dev, "Can't get hwspinlock\n"); 1008 goto unlock; 1009 } 1010 } 1011 1012 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 1013 val &= ~GENMASK(offset * 2 + 1, offset * 2); 1014 val |= bias << (offset * 2); 1015 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); 1016 1017 if (pctl->hwlock) 1018 hwspin_unlock_in_atomic(pctl->hwlock); 1019 1020 stm32_gpio_backup_bias(bank, offset, bias); 1021 1022 unlock: 1023 spin_unlock_irqrestore(&bank->lock, flags); 1024 1025 return err; 1026 } 1027 1028 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 1029 unsigned int offset) 1030 { 1031 unsigned long flags; 1032 u32 val; 1033 1034 spin_lock_irqsave(&bank->lock, flags); 1035 1036 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 1037 val &= GENMASK(offset * 2 + 1, offset * 2); 1038 1039 spin_unlock_irqrestore(&bank->lock, flags); 1040 1041 return (val >> (offset * 2)); 1042 } 1043 1044 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, 1045 unsigned int offset, bool dir) 1046 { 1047 unsigned long flags; 1048 u32 val; 1049 1050 spin_lock_irqsave(&bank->lock, flags); 1051 1052 if (dir) 1053 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & 1054 BIT(offset)); 1055 else 1056 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & 1057 BIT(offset)); 1058 1059 spin_unlock_irqrestore(&bank->lock, flags); 1060 1061 return val; 1062 } 1063 1064 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 1065 unsigned int pin, enum pin_config_param param, 1066 enum pin_config_param arg) 1067 { 1068 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1069 struct pinctrl_gpio_range *range; 1070 struct stm32_gpio_bank *bank; 1071 int offset, ret = 0; 1072 1073 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 1074 if (!range) { 1075 dev_err(pctl->dev, "No gpio range defined.\n"); 1076 return -EINVAL; 1077 } 1078 1079 bank = gpiochip_get_data(range->gc); 1080 offset = stm32_gpio_pin(pin); 1081 1082 if (!gpiochip_line_is_valid(range->gc, offset)) { 1083 dev_warn(pctl->dev, "Can't access gpio %d\n", pin); 1084 return -EACCES; 1085 } 1086 1087 switch (param) { 1088 case PIN_CONFIG_DRIVE_PUSH_PULL: 1089 ret = stm32_pconf_set_driving(bank, offset, 0); 1090 break; 1091 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1092 ret = stm32_pconf_set_driving(bank, offset, 1); 1093 break; 1094 case PIN_CONFIG_SLEW_RATE: 1095 ret = stm32_pconf_set_speed(bank, offset, arg); 1096 break; 1097 case PIN_CONFIG_BIAS_DISABLE: 1098 ret = stm32_pconf_set_bias(bank, offset, 0); 1099 break; 1100 case PIN_CONFIG_BIAS_PULL_UP: 1101 ret = stm32_pconf_set_bias(bank, offset, 1); 1102 break; 1103 case PIN_CONFIG_BIAS_PULL_DOWN: 1104 ret = stm32_pconf_set_bias(bank, offset, 2); 1105 break; 1106 case PIN_CONFIG_OUTPUT: 1107 __stm32_gpio_set(bank, offset, arg); 1108 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); 1109 break; 1110 default: 1111 ret = -ENOTSUPP; 1112 } 1113 1114 return ret; 1115 } 1116 1117 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, 1118 unsigned group, 1119 unsigned long *config) 1120 { 1121 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1122 1123 *config = pctl->groups[group].config; 1124 1125 return 0; 1126 } 1127 1128 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 1129 unsigned long *configs, unsigned num_configs) 1130 { 1131 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1132 struct stm32_pinctrl_group *g = &pctl->groups[group]; 1133 int i, ret; 1134 1135 for (i = 0; i < num_configs; i++) { 1136 mutex_lock(&pctldev->mutex); 1137 ret = stm32_pconf_parse_conf(pctldev, g->pin, 1138 pinconf_to_config_param(configs[i]), 1139 pinconf_to_config_argument(configs[i])); 1140 mutex_unlock(&pctldev->mutex); 1141 if (ret < 0) 1142 return ret; 1143 1144 g->config = configs[i]; 1145 } 1146 1147 return 0; 1148 } 1149 1150 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1151 unsigned long *configs, unsigned int num_configs) 1152 { 1153 int i, ret; 1154 1155 for (i = 0; i < num_configs; i++) { 1156 ret = stm32_pconf_parse_conf(pctldev, pin, 1157 pinconf_to_config_param(configs[i]), 1158 pinconf_to_config_argument(configs[i])); 1159 if (ret < 0) 1160 return ret; 1161 } 1162 1163 return 0; 1164 } 1165 1166 static struct stm32_desc_pin * 1167 stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl, 1168 unsigned int pin_number) 1169 { 1170 struct stm32_desc_pin *pins = pctl->pins; 1171 int i; 1172 1173 for (i = 0; i < pctl->npins; i++) { 1174 if (pins->pin.number == pin_number) 1175 return pins; 1176 pins++; 1177 } 1178 return NULL; 1179 } 1180 1181 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 1182 struct seq_file *s, 1183 unsigned int pin) 1184 { 1185 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1186 const struct stm32_desc_pin *pin_desc; 1187 struct pinctrl_gpio_range *range; 1188 struct stm32_gpio_bank *bank; 1189 int offset; 1190 u32 mode, alt, drive, speed, bias; 1191 static const char * const modes[] = { 1192 "input", "output", "alternate", "analog" }; 1193 static const char * const speeds[] = { 1194 "low", "medium", "high", "very high" }; 1195 static const char * const biasing[] = { 1196 "floating", "pull up", "pull down", "" }; 1197 bool val; 1198 1199 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 1200 if (!range) 1201 return; 1202 1203 bank = gpiochip_get_data(range->gc); 1204 offset = stm32_gpio_pin(pin); 1205 1206 if (!gpiochip_line_is_valid(range->gc, offset)) { 1207 seq_puts(s, "NO ACCESS"); 1208 return; 1209 } 1210 1211 stm32_pmx_get_mode(bank, offset, &mode, &alt); 1212 bias = stm32_pconf_get_bias(bank, offset); 1213 1214 seq_printf(s, "%s ", modes[mode]); 1215 1216 switch (mode) { 1217 /* input */ 1218 case 0: 1219 val = stm32_pconf_get(bank, offset, true); 1220 seq_printf(s, "- %s - %s", 1221 str_high_low(val), 1222 biasing[bias]); 1223 break; 1224 1225 /* output */ 1226 case 1: 1227 drive = stm32_pconf_get_driving(bank, offset); 1228 speed = stm32_pconf_get_speed(bank, offset); 1229 val = stm32_pconf_get(bank, offset, false); 1230 seq_printf(s, "- %s - %s - %s - %s %s", 1231 str_high_low(val), 1232 drive ? "open drain" : "push pull", 1233 biasing[bias], 1234 speeds[speed], "speed"); 1235 break; 1236 1237 /* alternate */ 1238 case 2: 1239 drive = stm32_pconf_get_driving(bank, offset); 1240 speed = stm32_pconf_get_speed(bank, offset); 1241 pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin); 1242 if (!pin_desc) 1243 return; 1244 1245 seq_printf(s, "%d (%s) - %s - %s - %s %s", alt, 1246 pin_desc->functions[alt + 1].name, 1247 drive ? "open drain" : "push pull", 1248 biasing[bias], 1249 speeds[speed], "speed"); 1250 break; 1251 1252 /* analog */ 1253 case 3: 1254 break; 1255 } 1256 } 1257 1258 static const struct pinconf_ops stm32_pconf_ops = { 1259 .pin_config_group_get = stm32_pconf_group_get, 1260 .pin_config_group_set = stm32_pconf_group_set, 1261 .pin_config_set = stm32_pconf_set, 1262 .pin_config_dbg_show = stm32_pconf_dbg_show, 1263 }; 1264 1265 static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl, 1266 struct stm32_gpio_bank *bank, 1267 unsigned int offset) 1268 { 1269 unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset; 1270 struct stm32_desc_pin *pin_desc; 1271 int i; 1272 1273 /* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */ 1274 if (stm32_pin_nb < pctl->npins) { 1275 pin_desc = pctl->pins + stm32_pin_nb; 1276 if (pin_desc->pin.number == stm32_pin_nb) 1277 return pin_desc; 1278 } 1279 1280 /* Otherwise, loop all array to find the pin with the right number */ 1281 for (i = 0; i < pctl->npins; i++) { 1282 pin_desc = pctl->pins + i; 1283 if (pin_desc->pin.number == stm32_pin_nb) 1284 return pin_desc; 1285 } 1286 return NULL; 1287 } 1288 1289 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode) 1290 { 1291 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; 1292 int bank_ioport_nr; 1293 struct pinctrl_gpio_range *range = &bank->range; 1294 struct fwnode_reference_args args; 1295 struct device *dev = pctl->dev; 1296 struct resource res; 1297 int npins = STM32_GPIO_PINS_PER_BANK; 1298 int bank_nr, err, i = 0; 1299 struct stm32_desc_pin *stm32_pin; 1300 char **names; 1301 1302 if (!IS_ERR(bank->rstc)) 1303 reset_control_deassert(bank->rstc); 1304 1305 if (of_address_to_resource(to_of_node(fwnode), 0, &res)) 1306 return -ENODEV; 1307 1308 bank->base = devm_ioremap_resource(dev, &res); 1309 if (IS_ERR(bank->base)) 1310 return PTR_ERR(bank->base); 1311 1312 bank->gpio_chip = stm32_gpio_template; 1313 1314 fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label); 1315 1316 if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) { 1317 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; 1318 bank->gpio_chip.base = args.args[1]; 1319 1320 /* get the last defined gpio line (offset + nb of pins) */ 1321 npins = args.args[0] + args.args[2]; 1322 while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args)) 1323 npins = max(npins, (int)(args.args[0] + args.args[2])); 1324 } else { 1325 bank_nr = pctl->nbanks; 1326 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1327 range->name = bank->gpio_chip.label; 1328 range->id = bank_nr; 1329 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; 1330 range->base = range->id * STM32_GPIO_PINS_PER_BANK; 1331 range->npins = npins; 1332 range->gc = &bank->gpio_chip; 1333 pinctrl_add_gpio_range(pctl->pctl_dev, 1334 &pctl->banks[bank_nr].range); 1335 } 1336 1337 if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr)) 1338 bank_ioport_nr = bank_nr; 1339 1340 bank->gpio_chip.base = -1; 1341 1342 bank->gpio_chip.ngpio = npins; 1343 bank->gpio_chip.fwnode = fwnode; 1344 bank->gpio_chip.parent = dev; 1345 bank->bank_nr = bank_nr; 1346 bank->bank_ioport_nr = bank_ioport_nr; 1347 bank->secure_control = pctl->match_data->secure_control; 1348 spin_lock_init(&bank->lock); 1349 1350 if (pctl->domain) { 1351 /* create irq hierarchical domain */ 1352 bank->fwnode = fwnode; 1353 1354 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE, 1355 bank->fwnode, &stm32_gpio_domain_ops, 1356 bank); 1357 1358 if (!bank->domain) 1359 return -ENODEV; 1360 } 1361 1362 names = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL); 1363 if (!names) 1364 return -ENOMEM; 1365 1366 for (i = 0; i < npins; i++) { 1367 stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i); 1368 if (stm32_pin && stm32_pin->pin.name) { 1369 names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name); 1370 if (!names[i]) 1371 return -ENOMEM; 1372 } else { 1373 names[i] = NULL; 1374 } 1375 } 1376 1377 bank->gpio_chip.names = (const char * const *)names; 1378 1379 err = gpiochip_add_data(&bank->gpio_chip, bank); 1380 if (err) { 1381 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); 1382 return err; 1383 } 1384 1385 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); 1386 return 0; 1387 } 1388 1389 static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev) 1390 { 1391 struct device_node *np = pdev->dev.of_node; 1392 struct device_node *parent; 1393 struct irq_domain *domain; 1394 1395 if (!of_property_present(np, "interrupt-parent")) 1396 return NULL; 1397 1398 parent = of_irq_find_parent(np); 1399 if (!parent) 1400 return ERR_PTR(-ENXIO); 1401 1402 domain = irq_find_host(parent); 1403 of_node_put(parent); 1404 if (!domain) 1405 /* domain not registered yet */ 1406 return ERR_PTR(-EPROBE_DEFER); 1407 1408 return domain; 1409 } 1410 1411 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 1412 struct stm32_pinctrl *pctl) 1413 { 1414 struct device_node *np = pdev->dev.of_node; 1415 struct device *dev = &pdev->dev; 1416 struct regmap *rm; 1417 int offset, ret, i; 1418 int mask, mask_width; 1419 1420 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1421 if (IS_ERR(pctl->regmap)) 1422 return PTR_ERR(pctl->regmap); 1423 1424 rm = pctl->regmap; 1425 1426 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); 1427 if (ret) 1428 return ret; 1429 1430 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask); 1431 if (ret) 1432 mask = SYSCFG_IRQMUX_MASK; 1433 1434 mask_width = fls(mask); 1435 1436 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { 1437 struct reg_field mux; 1438 1439 mux.reg = offset + (i / 4) * 4; 1440 mux.lsb = (i % 4) * mask_width; 1441 mux.msb = mux.lsb + mask_width - 1; 1442 1443 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n", 1444 i, mux.reg, mux.lsb, mux.msb); 1445 1446 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); 1447 if (IS_ERR(pctl->irqmux[i])) 1448 return PTR_ERR(pctl->irqmux[i]); 1449 } 1450 1451 return 0; 1452 } 1453 1454 static int stm32_pctrl_build_state(struct platform_device *pdev) 1455 { 1456 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); 1457 int i; 1458 1459 pctl->ngroups = pctl->npins; 1460 1461 /* Allocate groups */ 1462 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1463 sizeof(*pctl->groups), GFP_KERNEL); 1464 if (!pctl->groups) 1465 return -ENOMEM; 1466 1467 /* We assume that one pin is one group, use pin name as group name. */ 1468 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1469 sizeof(*pctl->grp_names), GFP_KERNEL); 1470 if (!pctl->grp_names) 1471 return -ENOMEM; 1472 1473 for (i = 0; i < pctl->npins; i++) { 1474 const struct stm32_desc_pin *pin = pctl->pins + i; 1475 struct stm32_pinctrl_group *group = pctl->groups + i; 1476 1477 group->name = pin->pin.name; 1478 group->pin = pin->pin.number; 1479 pctl->grp_names[i] = pin->pin.name; 1480 } 1481 1482 return 0; 1483 } 1484 1485 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl, 1486 struct stm32_desc_pin *pins) 1487 { 1488 const struct stm32_desc_pin *p; 1489 int i, nb_pins_available = 0; 1490 1491 for (i = 0; i < pctl->match_data->npins; i++) { 1492 p = pctl->match_data->pins + i; 1493 if (pctl->pkg && !(pctl->pkg & p->pkg)) 1494 continue; 1495 pins->pin = p->pin; 1496 memcpy((struct stm32_desc_pin *)pins->functions, p->functions, 1497 STM32_CONFIG_NUM * sizeof(struct stm32_desc_function)); 1498 pins++; 1499 nb_pins_available++; 1500 } 1501 1502 pctl->npins = nb_pins_available; 1503 1504 return 0; 1505 } 1506 1507 int stm32_pctl_probe(struct platform_device *pdev) 1508 { 1509 const struct stm32_pinctrl_match_data *match_data; 1510 struct fwnode_handle *child; 1511 struct device *dev = &pdev->dev; 1512 struct stm32_pinctrl *pctl; 1513 struct pinctrl_pin_desc *pins; 1514 int i, ret, hwlock_id; 1515 unsigned int banks; 1516 1517 match_data = device_get_match_data(dev); 1518 if (!match_data) 1519 return -EINVAL; 1520 1521 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1522 if (!pctl) 1523 return -ENOMEM; 1524 1525 platform_set_drvdata(pdev, pctl); 1526 1527 /* check for IRQ controller (may require deferred probe) */ 1528 pctl->domain = stm32_pctrl_get_irq_domain(pdev); 1529 if (IS_ERR(pctl->domain)) 1530 return PTR_ERR(pctl->domain); 1531 if (!pctl->domain) 1532 dev_warn(dev, "pinctrl without interrupt support\n"); 1533 1534 /* hwspinlock is optional */ 1535 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); 1536 if (hwlock_id < 0) { 1537 if (hwlock_id == -EPROBE_DEFER) 1538 return hwlock_id; 1539 } else { 1540 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); 1541 } 1542 1543 spin_lock_init(&pctl->irqmux_lock); 1544 1545 pctl->dev = dev; 1546 pctl->match_data = match_data; 1547 1548 /* get optional package information */ 1549 if (!device_property_read_u32(dev, "st,package", &pctl->pkg)) 1550 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg); 1551 1552 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins, 1553 sizeof(*pctl->pins), GFP_KERNEL); 1554 if (!pctl->pins) 1555 return -ENOMEM; 1556 1557 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins); 1558 if (ret) 1559 return ret; 1560 1561 ret = stm32_pctrl_build_state(pdev); 1562 if (ret) { 1563 dev_err(dev, "build state failed: %d\n", ret); 1564 return -EINVAL; 1565 } 1566 1567 if (pctl->domain) { 1568 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1569 if (ret) 1570 return ret; 1571 } 1572 1573 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins), 1574 GFP_KERNEL); 1575 if (!pins) 1576 return -ENOMEM; 1577 1578 for (i = 0; i < pctl->npins; i++) 1579 pins[i] = pctl->pins[i].pin; 1580 1581 pctl->pctl_desc.name = dev_name(&pdev->dev); 1582 pctl->pctl_desc.owner = THIS_MODULE; 1583 pctl->pctl_desc.pins = pins; 1584 pctl->pctl_desc.npins = pctl->npins; 1585 pctl->pctl_desc.link_consumers = true; 1586 pctl->pctl_desc.confops = &stm32_pconf_ops; 1587 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; 1588 pctl->pctl_desc.pmxops = &stm32_pmx_ops; 1589 pctl->dev = &pdev->dev; 1590 1591 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1592 pctl); 1593 1594 if (IS_ERR(pctl->pctl_dev)) { 1595 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1596 return PTR_ERR(pctl->pctl_dev); 1597 } 1598 1599 banks = gpiochip_node_count(dev); 1600 if (!banks) { 1601 dev_err(dev, "at least one GPIO bank is required\n"); 1602 return -EINVAL; 1603 } 1604 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), 1605 GFP_KERNEL); 1606 if (!pctl->banks) 1607 return -ENOMEM; 1608 1609 pctl->clks = devm_kcalloc(dev, banks, sizeof(*pctl->clks), 1610 GFP_KERNEL); 1611 if (!pctl->clks) 1612 return -ENOMEM; 1613 1614 i = 0; 1615 for_each_gpiochip_node(dev, child) { 1616 struct stm32_gpio_bank *bank = &pctl->banks[i]; 1617 struct device_node *np = to_of_node(child); 1618 1619 bank->rstc = of_reset_control_get_exclusive(np, NULL); 1620 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) { 1621 fwnode_handle_put(child); 1622 return -EPROBE_DEFER; 1623 } 1624 1625 pctl->clks[i].clk = of_clk_get_by_name(np, NULL); 1626 if (IS_ERR(pctl->clks[i].clk)) { 1627 fwnode_handle_put(child); 1628 return dev_err_probe(dev, PTR_ERR(pctl->clks[i].clk), 1629 "failed to get clk\n"); 1630 } 1631 pctl->clks[i].id = "pctl"; 1632 i++; 1633 } 1634 1635 ret = clk_bulk_prepare_enable(banks, pctl->clks); 1636 if (ret) { 1637 dev_err(dev, "failed to prepare_enable clk (%d)\n", ret); 1638 return ret; 1639 } 1640 1641 for_each_gpiochip_node(dev, child) { 1642 ret = stm32_gpiolib_register_bank(pctl, child); 1643 if (ret) { 1644 fwnode_handle_put(child); 1645 goto err_register; 1646 } 1647 1648 pctl->nbanks++; 1649 } 1650 1651 dev_info(dev, "Pinctrl STM32 initialized\n"); 1652 1653 return 0; 1654 err_register: 1655 for (i = 0; i < pctl->nbanks; i++) { 1656 struct stm32_gpio_bank *bank = &pctl->banks[i]; 1657 1658 gpiochip_remove(&bank->gpio_chip); 1659 } 1660 1661 clk_bulk_disable_unprepare(banks, pctl->clks); 1662 return ret; 1663 } 1664 1665 static int __maybe_unused stm32_pinctrl_restore_gpio_regs( 1666 struct stm32_pinctrl *pctl, u32 pin) 1667 { 1668 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); 1669 u32 val, alt, mode, offset = stm32_gpio_pin(pin); 1670 struct pinctrl_gpio_range *range; 1671 struct stm32_gpio_bank *bank; 1672 bool pin_is_irq; 1673 int ret; 1674 1675 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin); 1676 if (!range) 1677 return 0; 1678 1679 if (!gpiochip_line_is_valid(range->gc, offset)) 1680 return 0; 1681 1682 pin_is_irq = gpiochip_line_is_irq(range->gc, offset); 1683 1684 if (!desc || (!pin_is_irq && !desc->gpio_owner)) 1685 return 0; 1686 1687 bank = gpiochip_get_data(range->gc); 1688 1689 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; 1690 alt >>= STM32_GPIO_BKP_ALT_SHIFT; 1691 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; 1692 mode >>= STM32_GPIO_BKP_MODE_SHIFT; 1693 1694 ret = stm32_pmx_set_mode(bank, offset, mode, alt); 1695 if (ret) 1696 return ret; 1697 1698 if (mode == 1) { 1699 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); 1700 val = val >> STM32_GPIO_BKP_VAL; 1701 __stm32_gpio_set(bank, offset, val); 1702 } 1703 1704 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); 1705 val >>= STM32_GPIO_BKP_TYPE; 1706 ret = stm32_pconf_set_driving(bank, offset, val); 1707 if (ret) 1708 return ret; 1709 1710 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; 1711 val >>= STM32_GPIO_BKP_SPEED_SHIFT; 1712 ret = stm32_pconf_set_speed(bank, offset, val); 1713 if (ret) 1714 return ret; 1715 1716 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; 1717 val >>= STM32_GPIO_BKP_PUPD_SHIFT; 1718 ret = stm32_pconf_set_bias(bank, offset, val); 1719 if (ret) 1720 return ret; 1721 1722 if (pin_is_irq) 1723 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); 1724 1725 return 0; 1726 } 1727 1728 int __maybe_unused stm32_pinctrl_suspend(struct device *dev) 1729 { 1730 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); 1731 1732 clk_bulk_disable(pctl->nbanks, pctl->clks); 1733 1734 return 0; 1735 } 1736 1737 int __maybe_unused stm32_pinctrl_resume(struct device *dev) 1738 { 1739 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); 1740 struct stm32_pinctrl_group *g = pctl->groups; 1741 int i, ret; 1742 1743 ret = clk_bulk_enable(pctl->nbanks, pctl->clks); 1744 if (ret) 1745 return ret; 1746 1747 for (i = 0; i < pctl->ngroups; i++, g++) 1748 stm32_pinctrl_restore_gpio_regs(pctl, g->pin); 1749 1750 return 0; 1751 } 1752