1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * 7 * Heavily based on Mediatek's pinctrl driver 8 */ 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/hwspinlock.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_device.h> 19 #include <linux/of_irq.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/pinctrl/machine.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinconf-generic.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 #include <linux/platform_device.h> 27 #include <linux/regmap.h> 28 #include <linux/reset.h> 29 #include <linux/slab.h> 30 31 #include "../core.h" 32 #include "../pinconf.h" 33 #include "../pinctrl-utils.h" 34 #include "pinctrl-stm32.h" 35 36 #define STM32_GPIO_MODER 0x00 37 #define STM32_GPIO_TYPER 0x04 38 #define STM32_GPIO_SPEEDR 0x08 39 #define STM32_GPIO_PUPDR 0x0c 40 #define STM32_GPIO_IDR 0x10 41 #define STM32_GPIO_ODR 0x14 42 #define STM32_GPIO_BSRR 0x18 43 #define STM32_GPIO_LCKR 0x1c 44 #define STM32_GPIO_AFRL 0x20 45 #define STM32_GPIO_AFRH 0x24 46 47 /* custom bitfield to backup pin status */ 48 #define STM32_GPIO_BKP_MODE_SHIFT 0 49 #define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0) 50 #define STM32_GPIO_BKP_ALT_SHIFT 2 51 #define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2) 52 #define STM32_GPIO_BKP_SPEED_SHIFT 6 53 #define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6) 54 #define STM32_GPIO_BKP_PUPD_SHIFT 8 55 #define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8) 56 #define STM32_GPIO_BKP_TYPE 10 57 #define STM32_GPIO_BKP_VAL 11 58 59 #define STM32_GPIO_PINS_PER_BANK 16 60 #define STM32_GPIO_IRQ_LINE 16 61 62 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0) 63 64 #define gpio_range_to_bank(chip) \ 65 container_of(chip, struct stm32_gpio_bank, range) 66 67 #define HWSPINLOCK_TIMEOUT 5 /* msec */ 68 69 static const char * const stm32_gpio_functions[] = { 70 "gpio", "af0", "af1", 71 "af2", "af3", "af4", 72 "af5", "af6", "af7", 73 "af8", "af9", "af10", 74 "af11", "af12", "af13", 75 "af14", "af15", "analog", 76 }; 77 78 struct stm32_pinctrl_group { 79 const char *name; 80 unsigned long config; 81 unsigned pin; 82 }; 83 84 struct stm32_gpio_bank { 85 void __iomem *base; 86 struct clk *clk; 87 struct reset_control *rstc; 88 spinlock_t lock; 89 struct gpio_chip gpio_chip; 90 struct pinctrl_gpio_range range; 91 struct fwnode_handle *fwnode; 92 struct irq_domain *domain; 93 u32 bank_nr; 94 u32 bank_ioport_nr; 95 u32 pin_backup[STM32_GPIO_PINS_PER_BANK]; 96 u8 irq_type[STM32_GPIO_PINS_PER_BANK]; 97 }; 98 99 struct stm32_pinctrl { 100 struct device *dev; 101 struct pinctrl_dev *pctl_dev; 102 struct pinctrl_desc pctl_desc; 103 struct stm32_pinctrl_group *groups; 104 unsigned ngroups; 105 const char **grp_names; 106 struct stm32_gpio_bank *banks; 107 unsigned nbanks; 108 const struct stm32_pinctrl_match_data *match_data; 109 struct irq_domain *domain; 110 struct regmap *regmap; 111 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; 112 struct hwspinlock *hwlock; 113 struct stm32_desc_pin *pins; 114 u32 npins; 115 u32 pkg; 116 u16 irqmux_map; 117 spinlock_t irqmux_lock; 118 }; 119 120 static inline int stm32_gpio_pin(int gpio) 121 { 122 return gpio % STM32_GPIO_PINS_PER_BANK; 123 } 124 125 static inline u32 stm32_gpio_get_mode(u32 function) 126 { 127 switch (function) { 128 case STM32_PIN_GPIO: 129 return 0; 130 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 131 return 2; 132 case STM32_PIN_ANALOG: 133 return 3; 134 } 135 136 return 0; 137 } 138 139 static inline u32 stm32_gpio_get_alt(u32 function) 140 { 141 switch (function) { 142 case STM32_PIN_GPIO: 143 return 0; 144 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 145 return function - 1; 146 case STM32_PIN_ANALOG: 147 return 0; 148 } 149 150 return 0; 151 } 152 153 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, 154 u32 offset, u32 value) 155 { 156 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); 157 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; 158 } 159 160 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, 161 u32 mode, u32 alt) 162 { 163 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | 164 STM32_GPIO_BKP_ALT_MASK); 165 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; 166 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; 167 } 168 169 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, 170 u32 drive) 171 { 172 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); 173 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; 174 } 175 176 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, 177 u32 speed) 178 { 179 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; 180 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; 181 } 182 183 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, 184 u32 bias) 185 { 186 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; 187 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; 188 } 189 190 /* GPIO functions */ 191 192 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, 193 unsigned offset, int value) 194 { 195 stm32_gpio_backup_value(bank, offset, value); 196 197 if (!value) 198 offset += STM32_GPIO_PINS_PER_BANK; 199 200 clk_enable(bank->clk); 201 202 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); 203 204 clk_disable(bank->clk); 205 } 206 207 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) 208 { 209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 211 struct pinctrl_gpio_range *range; 212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); 213 214 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); 215 if (!range) { 216 dev_err(pctl->dev, "pin %d not in range.\n", pin); 217 return -EINVAL; 218 } 219 220 return pinctrl_gpio_request(chip->base + offset); 221 } 222 223 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) 224 { 225 pinctrl_gpio_free(chip->base + offset); 226 } 227 228 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) 229 { 230 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 231 int ret; 232 233 clk_enable(bank->clk); 234 235 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 236 237 clk_disable(bank->clk); 238 239 return ret; 240 } 241 242 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 243 { 244 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 245 246 __stm32_gpio_set(bank, offset, value); 247 } 248 249 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 250 { 251 return pinctrl_gpio_direction_input(chip->base + offset); 252 } 253 254 static int stm32_gpio_direction_output(struct gpio_chip *chip, 255 unsigned offset, int value) 256 { 257 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 258 259 __stm32_gpio_set(bank, offset, value); 260 pinctrl_gpio_direction_output(chip->base + offset); 261 262 return 0; 263 } 264 265 266 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 267 { 268 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 269 struct irq_fwspec fwspec; 270 271 fwspec.fwnode = bank->fwnode; 272 fwspec.param_count = 2; 273 fwspec.param[0] = offset; 274 fwspec.param[1] = IRQ_TYPE_NONE; 275 276 return irq_create_fwspec_mapping(&fwspec); 277 } 278 279 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 280 { 281 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 282 int pin = stm32_gpio_pin(offset); 283 int ret; 284 u32 mode, alt; 285 286 stm32_pmx_get_mode(bank, pin, &mode, &alt); 287 if ((alt == 0) && (mode == 0)) 288 ret = GPIO_LINE_DIRECTION_IN; 289 else if ((alt == 0) && (mode == 1)) 290 ret = GPIO_LINE_DIRECTION_OUT; 291 else 292 ret = -EINVAL; 293 294 return ret; 295 } 296 297 static const struct gpio_chip stm32_gpio_template = { 298 .request = stm32_gpio_request, 299 .free = stm32_gpio_free, 300 .get = stm32_gpio_get, 301 .set = stm32_gpio_set, 302 .direction_input = stm32_gpio_direction_input, 303 .direction_output = stm32_gpio_direction_output, 304 .to_irq = stm32_gpio_to_irq, 305 .get_direction = stm32_gpio_get_direction, 306 .set_config = gpiochip_generic_config, 307 }; 308 309 static void stm32_gpio_irq_trigger(struct irq_data *d) 310 { 311 struct stm32_gpio_bank *bank = d->domain->host_data; 312 int level; 313 314 /* If level interrupt type then retrig */ 315 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq); 316 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || 317 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) 318 irq_chip_retrigger_hierarchy(d); 319 } 320 321 static void stm32_gpio_irq_eoi(struct irq_data *d) 322 { 323 irq_chip_eoi_parent(d); 324 stm32_gpio_irq_trigger(d); 325 }; 326 327 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type) 328 { 329 struct stm32_gpio_bank *bank = d->domain->host_data; 330 u32 parent_type; 331 332 switch (type) { 333 case IRQ_TYPE_EDGE_RISING: 334 case IRQ_TYPE_EDGE_FALLING: 335 case IRQ_TYPE_EDGE_BOTH: 336 parent_type = type; 337 break; 338 case IRQ_TYPE_LEVEL_HIGH: 339 parent_type = IRQ_TYPE_EDGE_RISING; 340 break; 341 case IRQ_TYPE_LEVEL_LOW: 342 parent_type = IRQ_TYPE_EDGE_FALLING; 343 break; 344 default: 345 return -EINVAL; 346 } 347 348 bank->irq_type[d->hwirq] = type; 349 350 return irq_chip_set_type_parent(d, parent_type); 351 }; 352 353 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) 354 { 355 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 356 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 357 int ret; 358 359 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); 360 if (ret) 361 return ret; 362 363 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); 364 if (ret) { 365 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 366 irq_data->hwirq); 367 return ret; 368 } 369 370 return 0; 371 } 372 373 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) 374 { 375 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 376 377 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); 378 } 379 380 static void stm32_gpio_irq_unmask(struct irq_data *d) 381 { 382 irq_chip_unmask_parent(d); 383 stm32_gpio_irq_trigger(d); 384 } 385 386 static struct irq_chip stm32_gpio_irq_chip = { 387 .name = "stm32gpio", 388 .irq_eoi = stm32_gpio_irq_eoi, 389 .irq_ack = irq_chip_ack_parent, 390 .irq_mask = irq_chip_mask_parent, 391 .irq_unmask = stm32_gpio_irq_unmask, 392 .irq_set_type = stm32_gpio_set_type, 393 .irq_set_wake = irq_chip_set_wake_parent, 394 .irq_request_resources = stm32_gpio_irq_request_resources, 395 .irq_release_resources = stm32_gpio_irq_release_resources, 396 }; 397 398 static int stm32_gpio_domain_translate(struct irq_domain *d, 399 struct irq_fwspec *fwspec, 400 unsigned long *hwirq, 401 unsigned int *type) 402 { 403 if ((fwspec->param_count != 2) || 404 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) 405 return -EINVAL; 406 407 *hwirq = fwspec->param[0]; 408 *type = fwspec->param[1]; 409 return 0; 410 } 411 412 static int stm32_gpio_domain_activate(struct irq_domain *d, 413 struct irq_data *irq_data, bool reserve) 414 { 415 struct stm32_gpio_bank *bank = d->host_data; 416 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 417 unsigned long flags; 418 int ret = 0; 419 420 /* 421 * gpio irq mux is shared between several banks, a lock has to be done 422 * to avoid overriding. 423 */ 424 spin_lock_irqsave(&pctl->irqmux_lock, flags); 425 if (pctl->hwlock) 426 ret = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 427 428 if (ret) { 429 dev_err(pctl->dev, "Can't get hwspinlock\n"); 430 goto unlock; 431 } 432 433 if (pctl->irqmux_map & BIT(irq_data->hwirq)) { 434 dev_err(pctl->dev, "irq line %ld already requested.\n", 435 irq_data->hwirq); 436 ret = -EBUSY; 437 if (pctl->hwlock) 438 hwspin_unlock(pctl->hwlock); 439 goto unlock; 440 } else { 441 pctl->irqmux_map |= BIT(irq_data->hwirq); 442 } 443 444 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); 445 446 if (pctl->hwlock) 447 hwspin_unlock(pctl->hwlock); 448 449 unlock: 450 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 451 return ret; 452 } 453 454 static void stm32_gpio_domain_deactivate(struct irq_domain *d, 455 struct irq_data *irq_data) 456 { 457 struct stm32_gpio_bank *bank = d->host_data; 458 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 459 unsigned long flags; 460 461 spin_lock_irqsave(&pctl->irqmux_lock, flags); 462 pctl->irqmux_map &= ~BIT(irq_data->hwirq); 463 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 464 } 465 466 static int stm32_gpio_domain_alloc(struct irq_domain *d, 467 unsigned int virq, 468 unsigned int nr_irqs, void *data) 469 { 470 struct stm32_gpio_bank *bank = d->host_data; 471 struct irq_fwspec *fwspec = data; 472 struct irq_fwspec parent_fwspec; 473 irq_hw_number_t hwirq; 474 475 hwirq = fwspec->param[0]; 476 parent_fwspec.fwnode = d->parent->fwnode; 477 parent_fwspec.param_count = 2; 478 parent_fwspec.param[0] = fwspec->param[0]; 479 parent_fwspec.param[1] = fwspec->param[1]; 480 481 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, 482 bank); 483 484 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); 485 } 486 487 static const struct irq_domain_ops stm32_gpio_domain_ops = { 488 .translate = stm32_gpio_domain_translate, 489 .alloc = stm32_gpio_domain_alloc, 490 .free = irq_domain_free_irqs_common, 491 .activate = stm32_gpio_domain_activate, 492 .deactivate = stm32_gpio_domain_deactivate, 493 }; 494 495 /* Pinctrl functions */ 496 static struct stm32_pinctrl_group * 497 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) 498 { 499 int i; 500 501 for (i = 0; i < pctl->ngroups; i++) { 502 struct stm32_pinctrl_group *grp = pctl->groups + i; 503 504 if (grp->pin == pin) 505 return grp; 506 } 507 508 return NULL; 509 } 510 511 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, 512 u32 pin_num, u32 fnum) 513 { 514 int i; 515 516 for (i = 0; i < pctl->npins; i++) { 517 const struct stm32_desc_pin *pin = pctl->pins + i; 518 const struct stm32_desc_function *func = pin->functions; 519 520 if (pin->pin.number != pin_num) 521 continue; 522 523 while (func && func->name) { 524 if (func->num == fnum) 525 return true; 526 func++; 527 } 528 529 break; 530 } 531 532 return false; 533 } 534 535 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, 536 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, 537 struct pinctrl_map **map, unsigned *reserved_maps, 538 unsigned *num_maps) 539 { 540 if (*num_maps == *reserved_maps) 541 return -ENOSPC; 542 543 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 544 (*map)[*num_maps].data.mux.group = grp->name; 545 546 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { 547 dev_err(pctl->dev, "invalid function %d on pin %d .\n", 548 fnum, pin); 549 return -EINVAL; 550 } 551 552 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; 553 (*num_maps)++; 554 555 return 0; 556 } 557 558 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 559 struct device_node *node, 560 struct pinctrl_map **map, 561 unsigned *reserved_maps, 562 unsigned *num_maps) 563 { 564 struct stm32_pinctrl *pctl; 565 struct stm32_pinctrl_group *grp; 566 struct property *pins; 567 u32 pinfunc, pin, func; 568 unsigned long *configs; 569 unsigned int num_configs; 570 bool has_config = 0; 571 unsigned reserve = 0; 572 int num_pins, num_funcs, maps_per_pin, i, err = 0; 573 574 pctl = pinctrl_dev_get_drvdata(pctldev); 575 576 pins = of_find_property(node, "pinmux", NULL); 577 if (!pins) { 578 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", 579 node); 580 return -EINVAL; 581 } 582 583 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 584 &num_configs); 585 if (err) 586 return err; 587 588 if (num_configs) 589 has_config = 1; 590 591 num_pins = pins->length / sizeof(u32); 592 num_funcs = num_pins; 593 maps_per_pin = 0; 594 if (num_funcs) 595 maps_per_pin++; 596 if (has_config && num_pins >= 1) 597 maps_per_pin++; 598 599 if (!num_pins || !maps_per_pin) { 600 err = -EINVAL; 601 goto exit; 602 } 603 604 reserve = num_pins * maps_per_pin; 605 606 err = pinctrl_utils_reserve_map(pctldev, map, 607 reserved_maps, num_maps, reserve); 608 if (err) 609 goto exit; 610 611 for (i = 0; i < num_pins; i++) { 612 err = of_property_read_u32_index(node, "pinmux", 613 i, &pinfunc); 614 if (err) 615 goto exit; 616 617 pin = STM32_GET_PIN_NO(pinfunc); 618 func = STM32_GET_PIN_FUNC(pinfunc); 619 620 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { 621 dev_err(pctl->dev, "invalid function.\n"); 622 err = -EINVAL; 623 goto exit; 624 } 625 626 grp = stm32_pctrl_find_group_by_pin(pctl, pin); 627 if (!grp) { 628 dev_err(pctl->dev, "unable to match pin %d to group\n", 629 pin); 630 err = -EINVAL; 631 goto exit; 632 } 633 634 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 635 reserved_maps, num_maps); 636 if (err) 637 goto exit; 638 639 if (has_config) { 640 err = pinctrl_utils_add_map_configs(pctldev, map, 641 reserved_maps, num_maps, grp->name, 642 configs, num_configs, 643 PIN_MAP_TYPE_CONFIGS_GROUP); 644 if (err) 645 goto exit; 646 } 647 } 648 649 exit: 650 kfree(configs); 651 return err; 652 } 653 654 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 655 struct device_node *np_config, 656 struct pinctrl_map **map, unsigned *num_maps) 657 { 658 struct device_node *np; 659 unsigned reserved_maps; 660 int ret; 661 662 *map = NULL; 663 *num_maps = 0; 664 reserved_maps = 0; 665 666 for_each_child_of_node(np_config, np) { 667 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, 668 &reserved_maps, num_maps); 669 if (ret < 0) { 670 pinctrl_utils_free_map(pctldev, *map, *num_maps); 671 of_node_put(np); 672 return ret; 673 } 674 } 675 676 return 0; 677 } 678 679 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 680 { 681 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 682 683 return pctl->ngroups; 684 } 685 686 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, 687 unsigned group) 688 { 689 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 690 691 return pctl->groups[group].name; 692 } 693 694 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 695 unsigned group, 696 const unsigned **pins, 697 unsigned *num_pins) 698 { 699 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 700 701 *pins = (unsigned *)&pctl->groups[group].pin; 702 *num_pins = 1; 703 704 return 0; 705 } 706 707 static const struct pinctrl_ops stm32_pctrl_ops = { 708 .dt_node_to_map = stm32_pctrl_dt_node_to_map, 709 .dt_free_map = pinctrl_utils_free_map, 710 .get_groups_count = stm32_pctrl_get_groups_count, 711 .get_group_name = stm32_pctrl_get_group_name, 712 .get_group_pins = stm32_pctrl_get_group_pins, 713 }; 714 715 716 /* Pinmux functions */ 717 718 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 719 { 720 return ARRAY_SIZE(stm32_gpio_functions); 721 } 722 723 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, 724 unsigned selector) 725 { 726 return stm32_gpio_functions[selector]; 727 } 728 729 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, 730 unsigned function, 731 const char * const **groups, 732 unsigned * const num_groups) 733 { 734 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 735 736 *groups = pctl->grp_names; 737 *num_groups = pctl->ngroups; 738 739 return 0; 740 } 741 742 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 743 int pin, u32 mode, u32 alt) 744 { 745 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 746 u32 val; 747 int alt_shift = (pin % 8) * 4; 748 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 749 unsigned long flags; 750 int err = 0; 751 752 clk_enable(bank->clk); 753 spin_lock_irqsave(&bank->lock, flags); 754 755 if (pctl->hwlock) 756 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 757 758 if (err) { 759 dev_err(pctl->dev, "Can't get hwspinlock\n"); 760 goto unlock; 761 } 762 763 val = readl_relaxed(bank->base + alt_offset); 764 val &= ~GENMASK(alt_shift + 3, alt_shift); 765 val |= (alt << alt_shift); 766 writel_relaxed(val, bank->base + alt_offset); 767 768 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 769 val &= ~GENMASK(pin * 2 + 1, pin * 2); 770 val |= mode << (pin * 2); 771 writel_relaxed(val, bank->base + STM32_GPIO_MODER); 772 773 if (pctl->hwlock) 774 hwspin_unlock(pctl->hwlock); 775 776 stm32_gpio_backup_mode(bank, pin, mode, alt); 777 778 unlock: 779 spin_unlock_irqrestore(&bank->lock, flags); 780 clk_disable(bank->clk); 781 782 return err; 783 } 784 785 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, 786 u32 *alt) 787 { 788 u32 val; 789 int alt_shift = (pin % 8) * 4; 790 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 791 unsigned long flags; 792 793 clk_enable(bank->clk); 794 spin_lock_irqsave(&bank->lock, flags); 795 796 val = readl_relaxed(bank->base + alt_offset); 797 val &= GENMASK(alt_shift + 3, alt_shift); 798 *alt = val >> alt_shift; 799 800 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 801 val &= GENMASK(pin * 2 + 1, pin * 2); 802 *mode = val >> (pin * 2); 803 804 spin_unlock_irqrestore(&bank->lock, flags); 805 clk_disable(bank->clk); 806 } 807 808 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, 809 unsigned function, 810 unsigned group) 811 { 812 bool ret; 813 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 814 struct stm32_pinctrl_group *g = pctl->groups + group; 815 struct pinctrl_gpio_range *range; 816 struct stm32_gpio_bank *bank; 817 u32 mode, alt; 818 int pin; 819 820 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); 821 if (!ret) { 822 dev_err(pctl->dev, "invalid function %d on group %d .\n", 823 function, group); 824 return -EINVAL; 825 } 826 827 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); 828 if (!range) { 829 dev_err(pctl->dev, "No gpio range defined.\n"); 830 return -EINVAL; 831 } 832 833 bank = gpiochip_get_data(range->gc); 834 pin = stm32_gpio_pin(g->pin); 835 836 mode = stm32_gpio_get_mode(function); 837 alt = stm32_gpio_get_alt(function); 838 839 return stm32_pmx_set_mode(bank, pin, mode, alt); 840 } 841 842 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 843 struct pinctrl_gpio_range *range, unsigned gpio, 844 bool input) 845 { 846 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); 847 int pin = stm32_gpio_pin(gpio); 848 849 return stm32_pmx_set_mode(bank, pin, !input, 0); 850 } 851 852 static const struct pinmux_ops stm32_pmx_ops = { 853 .get_functions_count = stm32_pmx_get_funcs_cnt, 854 .get_function_name = stm32_pmx_get_func_name, 855 .get_function_groups = stm32_pmx_get_func_groups, 856 .set_mux = stm32_pmx_set_mux, 857 .gpio_set_direction = stm32_pmx_gpio_set_direction, 858 .strict = true, 859 }; 860 861 /* Pinconf functions */ 862 863 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 864 unsigned offset, u32 drive) 865 { 866 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 867 unsigned long flags; 868 u32 val; 869 int err = 0; 870 871 clk_enable(bank->clk); 872 spin_lock_irqsave(&bank->lock, flags); 873 874 if (pctl->hwlock) 875 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 876 877 if (err) { 878 dev_err(pctl->dev, "Can't get hwspinlock\n"); 879 goto unlock; 880 } 881 882 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 883 val &= ~BIT(offset); 884 val |= drive << offset; 885 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); 886 887 if (pctl->hwlock) 888 hwspin_unlock(pctl->hwlock); 889 890 stm32_gpio_backup_driving(bank, offset, drive); 891 892 unlock: 893 spin_unlock_irqrestore(&bank->lock, flags); 894 clk_disable(bank->clk); 895 896 return err; 897 } 898 899 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, 900 unsigned int offset) 901 { 902 unsigned long flags; 903 u32 val; 904 905 clk_enable(bank->clk); 906 spin_lock_irqsave(&bank->lock, flags); 907 908 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 909 val &= BIT(offset); 910 911 spin_unlock_irqrestore(&bank->lock, flags); 912 clk_disable(bank->clk); 913 914 return (val >> offset); 915 } 916 917 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 918 unsigned offset, u32 speed) 919 { 920 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 921 unsigned long flags; 922 u32 val; 923 int err = 0; 924 925 clk_enable(bank->clk); 926 spin_lock_irqsave(&bank->lock, flags); 927 928 if (pctl->hwlock) 929 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 930 931 if (err) { 932 dev_err(pctl->dev, "Can't get hwspinlock\n"); 933 goto unlock; 934 } 935 936 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 937 val &= ~GENMASK(offset * 2 + 1, offset * 2); 938 val |= speed << (offset * 2); 939 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); 940 941 if (pctl->hwlock) 942 hwspin_unlock(pctl->hwlock); 943 944 stm32_gpio_backup_speed(bank, offset, speed); 945 946 unlock: 947 spin_unlock_irqrestore(&bank->lock, flags); 948 clk_disable(bank->clk); 949 950 return err; 951 } 952 953 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, 954 unsigned int offset) 955 { 956 unsigned long flags; 957 u32 val; 958 959 clk_enable(bank->clk); 960 spin_lock_irqsave(&bank->lock, flags); 961 962 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 963 val &= GENMASK(offset * 2 + 1, offset * 2); 964 965 spin_unlock_irqrestore(&bank->lock, flags); 966 clk_disable(bank->clk); 967 968 return (val >> (offset * 2)); 969 } 970 971 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 972 unsigned offset, u32 bias) 973 { 974 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 975 unsigned long flags; 976 u32 val; 977 int err = 0; 978 979 clk_enable(bank->clk); 980 spin_lock_irqsave(&bank->lock, flags); 981 982 if (pctl->hwlock) 983 err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); 984 985 if (err) { 986 dev_err(pctl->dev, "Can't get hwspinlock\n"); 987 goto unlock; 988 } 989 990 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 991 val &= ~GENMASK(offset * 2 + 1, offset * 2); 992 val |= bias << (offset * 2); 993 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); 994 995 if (pctl->hwlock) 996 hwspin_unlock(pctl->hwlock); 997 998 stm32_gpio_backup_bias(bank, offset, bias); 999 1000 unlock: 1001 spin_unlock_irqrestore(&bank->lock, flags); 1002 clk_disable(bank->clk); 1003 1004 return err; 1005 } 1006 1007 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 1008 unsigned int offset) 1009 { 1010 unsigned long flags; 1011 u32 val; 1012 1013 clk_enable(bank->clk); 1014 spin_lock_irqsave(&bank->lock, flags); 1015 1016 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 1017 val &= GENMASK(offset * 2 + 1, offset * 2); 1018 1019 spin_unlock_irqrestore(&bank->lock, flags); 1020 clk_disable(bank->clk); 1021 1022 return (val >> (offset * 2)); 1023 } 1024 1025 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, 1026 unsigned int offset, bool dir) 1027 { 1028 unsigned long flags; 1029 u32 val; 1030 1031 clk_enable(bank->clk); 1032 spin_lock_irqsave(&bank->lock, flags); 1033 1034 if (dir) 1035 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & 1036 BIT(offset)); 1037 else 1038 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & 1039 BIT(offset)); 1040 1041 spin_unlock_irqrestore(&bank->lock, flags); 1042 clk_disable(bank->clk); 1043 1044 return val; 1045 } 1046 1047 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 1048 unsigned int pin, enum pin_config_param param, 1049 enum pin_config_param arg) 1050 { 1051 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1052 struct pinctrl_gpio_range *range; 1053 struct stm32_gpio_bank *bank; 1054 int offset, ret = 0; 1055 1056 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 1057 if (!range) { 1058 dev_err(pctl->dev, "No gpio range defined.\n"); 1059 return -EINVAL; 1060 } 1061 1062 bank = gpiochip_get_data(range->gc); 1063 offset = stm32_gpio_pin(pin); 1064 1065 switch (param) { 1066 case PIN_CONFIG_DRIVE_PUSH_PULL: 1067 ret = stm32_pconf_set_driving(bank, offset, 0); 1068 break; 1069 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1070 ret = stm32_pconf_set_driving(bank, offset, 1); 1071 break; 1072 case PIN_CONFIG_SLEW_RATE: 1073 ret = stm32_pconf_set_speed(bank, offset, arg); 1074 break; 1075 case PIN_CONFIG_BIAS_DISABLE: 1076 ret = stm32_pconf_set_bias(bank, offset, 0); 1077 break; 1078 case PIN_CONFIG_BIAS_PULL_UP: 1079 ret = stm32_pconf_set_bias(bank, offset, 1); 1080 break; 1081 case PIN_CONFIG_BIAS_PULL_DOWN: 1082 ret = stm32_pconf_set_bias(bank, offset, 2); 1083 break; 1084 case PIN_CONFIG_OUTPUT: 1085 __stm32_gpio_set(bank, offset, arg); 1086 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); 1087 break; 1088 default: 1089 ret = -ENOTSUPP; 1090 } 1091 1092 return ret; 1093 } 1094 1095 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, 1096 unsigned group, 1097 unsigned long *config) 1098 { 1099 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1100 1101 *config = pctl->groups[group].config; 1102 1103 return 0; 1104 } 1105 1106 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 1107 unsigned long *configs, unsigned num_configs) 1108 { 1109 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1110 struct stm32_pinctrl_group *g = &pctl->groups[group]; 1111 int i, ret; 1112 1113 for (i = 0; i < num_configs; i++) { 1114 mutex_lock(&pctldev->mutex); 1115 ret = stm32_pconf_parse_conf(pctldev, g->pin, 1116 pinconf_to_config_param(configs[i]), 1117 pinconf_to_config_argument(configs[i])); 1118 mutex_unlock(&pctldev->mutex); 1119 if (ret < 0) 1120 return ret; 1121 1122 g->config = configs[i]; 1123 } 1124 1125 return 0; 1126 } 1127 1128 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1129 unsigned long *configs, unsigned int num_configs) 1130 { 1131 int i, ret; 1132 1133 for (i = 0; i < num_configs; i++) { 1134 ret = stm32_pconf_parse_conf(pctldev, pin, 1135 pinconf_to_config_param(configs[i]), 1136 pinconf_to_config_argument(configs[i])); 1137 if (ret < 0) 1138 return ret; 1139 } 1140 1141 return 0; 1142 } 1143 1144 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 1145 struct seq_file *s, 1146 unsigned int pin) 1147 { 1148 struct pinctrl_gpio_range *range; 1149 struct stm32_gpio_bank *bank; 1150 int offset; 1151 u32 mode, alt, drive, speed, bias; 1152 static const char * const modes[] = { 1153 "input", "output", "alternate", "analog" }; 1154 static const char * const speeds[] = { 1155 "low", "medium", "high", "very high" }; 1156 static const char * const biasing[] = { 1157 "floating", "pull up", "pull down", "" }; 1158 bool val; 1159 1160 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 1161 if (!range) 1162 return; 1163 1164 bank = gpiochip_get_data(range->gc); 1165 offset = stm32_gpio_pin(pin); 1166 1167 stm32_pmx_get_mode(bank, offset, &mode, &alt); 1168 bias = stm32_pconf_get_bias(bank, offset); 1169 1170 seq_printf(s, "%s ", modes[mode]); 1171 1172 switch (mode) { 1173 /* input */ 1174 case 0: 1175 val = stm32_pconf_get(bank, offset, true); 1176 seq_printf(s, "- %s - %s", 1177 val ? "high" : "low", 1178 biasing[bias]); 1179 break; 1180 1181 /* output */ 1182 case 1: 1183 drive = stm32_pconf_get_driving(bank, offset); 1184 speed = stm32_pconf_get_speed(bank, offset); 1185 val = stm32_pconf_get(bank, offset, false); 1186 seq_printf(s, "- %s - %s - %s - %s %s", 1187 val ? "high" : "low", 1188 drive ? "open drain" : "push pull", 1189 biasing[bias], 1190 speeds[speed], "speed"); 1191 break; 1192 1193 /* alternate */ 1194 case 2: 1195 drive = stm32_pconf_get_driving(bank, offset); 1196 speed = stm32_pconf_get_speed(bank, offset); 1197 seq_printf(s, "%d - %s - %s - %s %s", alt, 1198 drive ? "open drain" : "push pull", 1199 biasing[bias], 1200 speeds[speed], "speed"); 1201 break; 1202 1203 /* analog */ 1204 case 3: 1205 break; 1206 } 1207 } 1208 1209 static const struct pinconf_ops stm32_pconf_ops = { 1210 .pin_config_group_get = stm32_pconf_group_get, 1211 .pin_config_group_set = stm32_pconf_group_set, 1212 .pin_config_set = stm32_pconf_set, 1213 .pin_config_dbg_show = stm32_pconf_dbg_show, 1214 }; 1215 1216 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, 1217 struct device_node *np) 1218 { 1219 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; 1220 int bank_ioport_nr; 1221 struct pinctrl_gpio_range *range = &bank->range; 1222 struct of_phandle_args args; 1223 struct device *dev = pctl->dev; 1224 struct resource res; 1225 int npins = STM32_GPIO_PINS_PER_BANK; 1226 int bank_nr, err; 1227 1228 if (!IS_ERR(bank->rstc)) 1229 reset_control_deassert(bank->rstc); 1230 1231 if (of_address_to_resource(np, 0, &res)) 1232 return -ENODEV; 1233 1234 bank->base = devm_ioremap_resource(dev, &res); 1235 if (IS_ERR(bank->base)) 1236 return PTR_ERR(bank->base); 1237 1238 err = clk_prepare(bank->clk); 1239 if (err) { 1240 dev_err(dev, "failed to prepare clk (%d)\n", err); 1241 return err; 1242 } 1243 1244 bank->gpio_chip = stm32_gpio_template; 1245 1246 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); 1247 1248 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) { 1249 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; 1250 bank->gpio_chip.base = args.args[1]; 1251 } else { 1252 bank_nr = pctl->nbanks; 1253 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1254 range->name = bank->gpio_chip.label; 1255 range->id = bank_nr; 1256 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; 1257 range->base = range->id * STM32_GPIO_PINS_PER_BANK; 1258 range->npins = npins; 1259 range->gc = &bank->gpio_chip; 1260 pinctrl_add_gpio_range(pctl->pctl_dev, 1261 &pctl->banks[bank_nr].range); 1262 } 1263 1264 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr)) 1265 bank_ioport_nr = bank_nr; 1266 1267 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1268 1269 bank->gpio_chip.ngpio = npins; 1270 bank->gpio_chip.of_node = np; 1271 bank->gpio_chip.parent = dev; 1272 bank->bank_nr = bank_nr; 1273 bank->bank_ioport_nr = bank_ioport_nr; 1274 spin_lock_init(&bank->lock); 1275 1276 /* create irq hierarchical domain */ 1277 bank->fwnode = of_node_to_fwnode(np); 1278 1279 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, 1280 STM32_GPIO_IRQ_LINE, bank->fwnode, 1281 &stm32_gpio_domain_ops, bank); 1282 1283 if (!bank->domain) 1284 return -ENODEV; 1285 1286 err = gpiochip_add_data(&bank->gpio_chip, bank); 1287 if (err) { 1288 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); 1289 return err; 1290 } 1291 1292 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); 1293 return 0; 1294 } 1295 1296 static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np) 1297 { 1298 struct device_node *parent; 1299 struct irq_domain *domain; 1300 1301 if (!of_find_property(np, "interrupt-parent", NULL)) 1302 return NULL; 1303 1304 parent = of_irq_find_parent(np); 1305 if (!parent) 1306 return ERR_PTR(-ENXIO); 1307 1308 domain = irq_find_host(parent); 1309 if (!domain) 1310 /* domain not registered yet */ 1311 return ERR_PTR(-EPROBE_DEFER); 1312 1313 return domain; 1314 } 1315 1316 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 1317 struct stm32_pinctrl *pctl) 1318 { 1319 struct device_node *np = pdev->dev.of_node; 1320 struct device *dev = &pdev->dev; 1321 struct regmap *rm; 1322 int offset, ret, i; 1323 int mask, mask_width; 1324 1325 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1326 if (IS_ERR(pctl->regmap)) 1327 return PTR_ERR(pctl->regmap); 1328 1329 rm = pctl->regmap; 1330 1331 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); 1332 if (ret) 1333 return ret; 1334 1335 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask); 1336 if (ret) 1337 mask = SYSCFG_IRQMUX_MASK; 1338 1339 mask_width = fls(mask); 1340 1341 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { 1342 struct reg_field mux; 1343 1344 mux.reg = offset + (i / 4) * 4; 1345 mux.lsb = (i % 4) * mask_width; 1346 mux.msb = mux.lsb + mask_width - 1; 1347 1348 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n", 1349 i, mux.reg, mux.lsb, mux.msb); 1350 1351 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); 1352 if (IS_ERR(pctl->irqmux[i])) 1353 return PTR_ERR(pctl->irqmux[i]); 1354 } 1355 1356 return 0; 1357 } 1358 1359 static int stm32_pctrl_build_state(struct platform_device *pdev) 1360 { 1361 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); 1362 int i; 1363 1364 pctl->ngroups = pctl->npins; 1365 1366 /* Allocate groups */ 1367 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1368 sizeof(*pctl->groups), GFP_KERNEL); 1369 if (!pctl->groups) 1370 return -ENOMEM; 1371 1372 /* We assume that one pin is one group, use pin name as group name. */ 1373 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1374 sizeof(*pctl->grp_names), GFP_KERNEL); 1375 if (!pctl->grp_names) 1376 return -ENOMEM; 1377 1378 for (i = 0; i < pctl->npins; i++) { 1379 const struct stm32_desc_pin *pin = pctl->pins + i; 1380 struct stm32_pinctrl_group *group = pctl->groups + i; 1381 1382 group->name = pin->pin.name; 1383 group->pin = pin->pin.number; 1384 pctl->grp_names[i] = pin->pin.name; 1385 } 1386 1387 return 0; 1388 } 1389 1390 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl, 1391 struct stm32_desc_pin *pins) 1392 { 1393 const struct stm32_desc_pin *p; 1394 int i, nb_pins_available = 0; 1395 1396 for (i = 0; i < pctl->match_data->npins; i++) { 1397 p = pctl->match_data->pins + i; 1398 if (pctl->pkg && !(pctl->pkg & p->pkg)) 1399 continue; 1400 pins->pin = p->pin; 1401 pins->functions = p->functions; 1402 pins++; 1403 nb_pins_available++; 1404 } 1405 1406 pctl->npins = nb_pins_available; 1407 1408 return 0; 1409 } 1410 1411 static void stm32_pctl_get_package(struct device_node *np, 1412 struct stm32_pinctrl *pctl) 1413 { 1414 if (of_property_read_u32(np, "st,package", &pctl->pkg)) { 1415 pctl->pkg = 0; 1416 dev_warn(pctl->dev, "No package detected, use default one\n"); 1417 } else { 1418 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg); 1419 } 1420 } 1421 1422 int stm32_pctl_probe(struct platform_device *pdev) 1423 { 1424 struct device_node *np = pdev->dev.of_node; 1425 struct device_node *child; 1426 const struct of_device_id *match; 1427 struct device *dev = &pdev->dev; 1428 struct stm32_pinctrl *pctl; 1429 struct pinctrl_pin_desc *pins; 1430 int i, ret, hwlock_id, banks = 0; 1431 1432 if (!np) 1433 return -EINVAL; 1434 1435 match = of_match_device(dev->driver->of_match_table, dev); 1436 if (!match || !match->data) 1437 return -EINVAL; 1438 1439 if (!of_find_property(np, "pins-are-numbered", NULL)) { 1440 dev_err(dev, "only support pins-are-numbered format\n"); 1441 return -EINVAL; 1442 } 1443 1444 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1445 if (!pctl) 1446 return -ENOMEM; 1447 1448 platform_set_drvdata(pdev, pctl); 1449 1450 /* check for IRQ controller (may require deferred probe) */ 1451 pctl->domain = stm32_pctrl_get_irq_domain(np); 1452 if (IS_ERR(pctl->domain)) 1453 return PTR_ERR(pctl->domain); 1454 1455 /* hwspinlock is optional */ 1456 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); 1457 if (hwlock_id < 0) { 1458 if (hwlock_id == -EPROBE_DEFER) 1459 return hwlock_id; 1460 } else { 1461 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); 1462 } 1463 1464 spin_lock_init(&pctl->irqmux_lock); 1465 1466 pctl->dev = dev; 1467 pctl->match_data = match->data; 1468 1469 /* get package information */ 1470 stm32_pctl_get_package(np, pctl); 1471 1472 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins, 1473 sizeof(*pctl->pins), GFP_KERNEL); 1474 if (!pctl->pins) 1475 return -ENOMEM; 1476 1477 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins); 1478 if (ret) 1479 return ret; 1480 1481 ret = stm32_pctrl_build_state(pdev); 1482 if (ret) { 1483 dev_err(dev, "build state failed: %d\n", ret); 1484 return -EINVAL; 1485 } 1486 1487 if (pctl->domain) { 1488 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1489 if (ret) 1490 return ret; 1491 } 1492 1493 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins), 1494 GFP_KERNEL); 1495 if (!pins) 1496 return -ENOMEM; 1497 1498 for (i = 0; i < pctl->npins; i++) 1499 pins[i] = pctl->pins[i].pin; 1500 1501 pctl->pctl_desc.name = dev_name(&pdev->dev); 1502 pctl->pctl_desc.owner = THIS_MODULE; 1503 pctl->pctl_desc.pins = pins; 1504 pctl->pctl_desc.npins = pctl->npins; 1505 pctl->pctl_desc.link_consumers = true; 1506 pctl->pctl_desc.confops = &stm32_pconf_ops; 1507 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; 1508 pctl->pctl_desc.pmxops = &stm32_pmx_ops; 1509 pctl->dev = &pdev->dev; 1510 1511 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1512 pctl); 1513 1514 if (IS_ERR(pctl->pctl_dev)) { 1515 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1516 return PTR_ERR(pctl->pctl_dev); 1517 } 1518 1519 for_each_available_child_of_node(np, child) 1520 if (of_property_read_bool(child, "gpio-controller")) 1521 banks++; 1522 1523 if (!banks) { 1524 dev_err(dev, "at least one GPIO bank is required\n"); 1525 return -EINVAL; 1526 } 1527 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), 1528 GFP_KERNEL); 1529 if (!pctl->banks) 1530 return -ENOMEM; 1531 1532 i = 0; 1533 for_each_available_child_of_node(np, child) { 1534 struct stm32_gpio_bank *bank = &pctl->banks[i]; 1535 1536 if (of_property_read_bool(child, "gpio-controller")) { 1537 bank->rstc = of_reset_control_get_exclusive(child, 1538 NULL); 1539 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) 1540 return -EPROBE_DEFER; 1541 1542 bank->clk = of_clk_get_by_name(child, NULL); 1543 if (IS_ERR(bank->clk)) { 1544 if (PTR_ERR(bank->clk) != -EPROBE_DEFER) 1545 dev_err(dev, 1546 "failed to get clk (%ld)\n", 1547 PTR_ERR(bank->clk)); 1548 return PTR_ERR(bank->clk); 1549 } 1550 i++; 1551 } 1552 } 1553 1554 for_each_available_child_of_node(np, child) { 1555 if (of_property_read_bool(child, "gpio-controller")) { 1556 ret = stm32_gpiolib_register_bank(pctl, child); 1557 if (ret) { 1558 of_node_put(child); 1559 return ret; 1560 } 1561 1562 pctl->nbanks++; 1563 } 1564 } 1565 1566 dev_info(dev, "Pinctrl STM32 initialized\n"); 1567 1568 return 0; 1569 } 1570 1571 static int __maybe_unused stm32_pinctrl_restore_gpio_regs( 1572 struct stm32_pinctrl *pctl, u32 pin) 1573 { 1574 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); 1575 u32 val, alt, mode, offset = stm32_gpio_pin(pin); 1576 struct pinctrl_gpio_range *range; 1577 struct stm32_gpio_bank *bank; 1578 bool pin_is_irq; 1579 int ret; 1580 1581 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin); 1582 if (!range) 1583 return 0; 1584 1585 pin_is_irq = gpiochip_line_is_irq(range->gc, offset); 1586 1587 if (!desc || (!pin_is_irq && !desc->gpio_owner)) 1588 return 0; 1589 1590 bank = gpiochip_get_data(range->gc); 1591 1592 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; 1593 alt >>= STM32_GPIO_BKP_ALT_SHIFT; 1594 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; 1595 mode >>= STM32_GPIO_BKP_MODE_SHIFT; 1596 1597 ret = stm32_pmx_set_mode(bank, offset, mode, alt); 1598 if (ret) 1599 return ret; 1600 1601 if (mode == 1) { 1602 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); 1603 val = val >> STM32_GPIO_BKP_VAL; 1604 __stm32_gpio_set(bank, offset, val); 1605 } 1606 1607 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); 1608 val >>= STM32_GPIO_BKP_TYPE; 1609 ret = stm32_pconf_set_driving(bank, offset, val); 1610 if (ret) 1611 return ret; 1612 1613 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; 1614 val >>= STM32_GPIO_BKP_SPEED_SHIFT; 1615 ret = stm32_pconf_set_speed(bank, offset, val); 1616 if (ret) 1617 return ret; 1618 1619 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; 1620 val >>= STM32_GPIO_BKP_PUPD_SHIFT; 1621 ret = stm32_pconf_set_bias(bank, offset, val); 1622 if (ret) 1623 return ret; 1624 1625 if (pin_is_irq) 1626 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); 1627 1628 return 0; 1629 } 1630 1631 int __maybe_unused stm32_pinctrl_resume(struct device *dev) 1632 { 1633 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); 1634 struct stm32_pinctrl_group *g = pctl->groups; 1635 int i; 1636 1637 for (i = g->pin; i < g->pin + pctl->ngroups; i++) 1638 stm32_pinctrl_restore_gpio_regs(pctl, i); 1639 1640 return 0; 1641 } 1642