1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * 7 * Heavily based on Mediatek's pinctrl driver 8 */ 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/hwspinlock.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_irq.h> 19 #include <linux/platform_device.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/reset.h> 23 #include <linux/seq_file.h> 24 #include <linux/slab.h> 25 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/pinctrl/machine.h> 28 #include <linux/pinctrl/pinconf-generic.h> 29 #include <linux/pinctrl/pinconf.h> 30 #include <linux/pinctrl/pinctrl.h> 31 #include <linux/pinctrl/pinmux.h> 32 33 #include "../core.h" 34 #include "../pinconf.h" 35 #include "../pinctrl-utils.h" 36 #include "pinctrl-stm32.h" 37 38 #define STM32_GPIO_MODER 0x00 39 #define STM32_GPIO_TYPER 0x04 40 #define STM32_GPIO_SPEEDR 0x08 41 #define STM32_GPIO_PUPDR 0x0c 42 #define STM32_GPIO_IDR 0x10 43 #define STM32_GPIO_ODR 0x14 44 #define STM32_GPIO_BSRR 0x18 45 #define STM32_GPIO_LCKR 0x1c 46 #define STM32_GPIO_AFRL 0x20 47 #define STM32_GPIO_AFRH 0x24 48 #define STM32_GPIO_SECCFGR 0x30 49 50 /* custom bitfield to backup pin status */ 51 #define STM32_GPIO_BKP_MODE_SHIFT 0 52 #define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0) 53 #define STM32_GPIO_BKP_ALT_SHIFT 2 54 #define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2) 55 #define STM32_GPIO_BKP_SPEED_SHIFT 6 56 #define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6) 57 #define STM32_GPIO_BKP_PUPD_SHIFT 8 58 #define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8) 59 #define STM32_GPIO_BKP_TYPE 10 60 #define STM32_GPIO_BKP_VAL 11 61 62 #define STM32_GPIO_PINS_PER_BANK 16 63 #define STM32_GPIO_IRQ_LINE 16 64 65 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0) 66 67 #define gpio_range_to_bank(chip) \ 68 container_of(chip, struct stm32_gpio_bank, range) 69 70 #define HWSPNLCK_TIMEOUT 1000 /* usec */ 71 72 static const char * const stm32_gpio_functions[] = { 73 "gpio", "af0", "af1", 74 "af2", "af3", "af4", 75 "af5", "af6", "af7", 76 "af8", "af9", "af10", 77 "af11", "af12", "af13", 78 "af14", "af15", "analog", 79 }; 80 81 struct stm32_pinctrl_group { 82 const char *name; 83 unsigned long config; 84 unsigned pin; 85 }; 86 87 struct stm32_gpio_bank { 88 void __iomem *base; 89 struct clk *clk; 90 struct reset_control *rstc; 91 spinlock_t lock; 92 struct gpio_chip gpio_chip; 93 struct pinctrl_gpio_range range; 94 struct fwnode_handle *fwnode; 95 struct irq_domain *domain; 96 u32 bank_nr; 97 u32 bank_ioport_nr; 98 u32 pin_backup[STM32_GPIO_PINS_PER_BANK]; 99 u8 irq_type[STM32_GPIO_PINS_PER_BANK]; 100 bool secure_control; 101 }; 102 103 struct stm32_pinctrl { 104 struct device *dev; 105 struct pinctrl_dev *pctl_dev; 106 struct pinctrl_desc pctl_desc; 107 struct stm32_pinctrl_group *groups; 108 unsigned ngroups; 109 const char **grp_names; 110 struct stm32_gpio_bank *banks; 111 unsigned nbanks; 112 const struct stm32_pinctrl_match_data *match_data; 113 struct irq_domain *domain; 114 struct regmap *regmap; 115 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; 116 struct hwspinlock *hwlock; 117 struct stm32_desc_pin *pins; 118 u32 npins; 119 u32 pkg; 120 u16 irqmux_map; 121 spinlock_t irqmux_lock; 122 }; 123 124 static inline int stm32_gpio_pin(int gpio) 125 { 126 return gpio % STM32_GPIO_PINS_PER_BANK; 127 } 128 129 static inline u32 stm32_gpio_get_mode(u32 function) 130 { 131 switch (function) { 132 case STM32_PIN_GPIO: 133 return 0; 134 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 135 return 2; 136 case STM32_PIN_ANALOG: 137 return 3; 138 } 139 140 return 0; 141 } 142 143 static inline u32 stm32_gpio_get_alt(u32 function) 144 { 145 switch (function) { 146 case STM32_PIN_GPIO: 147 return 0; 148 case STM32_PIN_AF(0) ... STM32_PIN_AF(15): 149 return function - 1; 150 case STM32_PIN_ANALOG: 151 return 0; 152 } 153 154 return 0; 155 } 156 157 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, 158 u32 offset, u32 value) 159 { 160 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); 161 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; 162 } 163 164 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, 165 u32 mode, u32 alt) 166 { 167 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | 168 STM32_GPIO_BKP_ALT_MASK); 169 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; 170 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; 171 } 172 173 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, 174 u32 drive) 175 { 176 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); 177 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; 178 } 179 180 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, 181 u32 speed) 182 { 183 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; 184 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; 185 } 186 187 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, 188 u32 bias) 189 { 190 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; 191 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; 192 } 193 194 /* GPIO functions */ 195 196 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, 197 unsigned offset, int value) 198 { 199 stm32_gpio_backup_value(bank, offset, value); 200 201 if (!value) 202 offset += STM32_GPIO_PINS_PER_BANK; 203 204 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); 205 } 206 207 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) 208 { 209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 211 struct pinctrl_gpio_range *range; 212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); 213 214 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); 215 if (!range) { 216 dev_err(pctl->dev, "pin %d not in range.\n", pin); 217 return -EINVAL; 218 } 219 220 return pinctrl_gpio_request(chip, offset); 221 } 222 223 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) 224 { 225 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 226 227 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); 228 } 229 230 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 231 { 232 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 233 234 __stm32_gpio_set(bank, offset, value); 235 } 236 237 static int stm32_gpio_direction_output(struct gpio_chip *chip, 238 unsigned offset, int value) 239 { 240 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 241 242 __stm32_gpio_set(bank, offset, value); 243 244 return pinctrl_gpio_direction_output(chip, offset); 245 } 246 247 248 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 249 { 250 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 251 struct irq_fwspec fwspec; 252 253 fwspec.fwnode = bank->fwnode; 254 fwspec.param_count = 2; 255 fwspec.param[0] = offset; 256 fwspec.param[1] = IRQ_TYPE_NONE; 257 258 return irq_create_fwspec_mapping(&fwspec); 259 } 260 261 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 262 { 263 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 264 int pin = stm32_gpio_pin(offset); 265 int ret; 266 u32 mode, alt; 267 268 stm32_pmx_get_mode(bank, pin, &mode, &alt); 269 if ((alt == 0) && (mode == 0)) 270 ret = GPIO_LINE_DIRECTION_IN; 271 else if ((alt == 0) && (mode == 1)) 272 ret = GPIO_LINE_DIRECTION_OUT; 273 else 274 ret = -EINVAL; 275 276 return ret; 277 } 278 279 static int stm32_gpio_init_valid_mask(struct gpio_chip *chip, 280 unsigned long *valid_mask, 281 unsigned int ngpios) 282 { 283 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); 284 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 285 unsigned int i; 286 u32 sec; 287 288 /* All gpio are valid per default */ 289 bitmap_fill(valid_mask, ngpios); 290 291 if (bank->secure_control) { 292 /* Tag secured pins as invalid */ 293 sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR); 294 295 for (i = 0; i < ngpios; i++) { 296 if (sec & BIT(i)) { 297 clear_bit(i, valid_mask); 298 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i); 299 } 300 } 301 } 302 303 return 0; 304 } 305 306 static const struct gpio_chip stm32_gpio_template = { 307 .request = stm32_gpio_request, 308 .free = pinctrl_gpio_free, 309 .get = stm32_gpio_get, 310 .set = stm32_gpio_set, 311 .direction_input = pinctrl_gpio_direction_input, 312 .direction_output = stm32_gpio_direction_output, 313 .to_irq = stm32_gpio_to_irq, 314 .get_direction = stm32_gpio_get_direction, 315 .set_config = gpiochip_generic_config, 316 .init_valid_mask = stm32_gpio_init_valid_mask, 317 }; 318 319 static void stm32_gpio_irq_trigger(struct irq_data *d) 320 { 321 struct stm32_gpio_bank *bank = d->domain->host_data; 322 int level; 323 324 /* Do not access the GPIO if this is not LEVEL triggered IRQ. */ 325 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK)) 326 return; 327 328 /* If level interrupt type then retrig */ 329 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq); 330 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || 331 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) 332 irq_chip_retrigger_hierarchy(d); 333 } 334 335 static void stm32_gpio_irq_eoi(struct irq_data *d) 336 { 337 irq_chip_eoi_parent(d); 338 stm32_gpio_irq_trigger(d); 339 }; 340 341 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type) 342 { 343 struct stm32_gpio_bank *bank = d->domain->host_data; 344 u32 parent_type; 345 346 switch (type) { 347 case IRQ_TYPE_EDGE_RISING: 348 case IRQ_TYPE_EDGE_FALLING: 349 case IRQ_TYPE_EDGE_BOTH: 350 parent_type = type; 351 break; 352 case IRQ_TYPE_LEVEL_HIGH: 353 parent_type = IRQ_TYPE_EDGE_RISING; 354 break; 355 case IRQ_TYPE_LEVEL_LOW: 356 parent_type = IRQ_TYPE_EDGE_FALLING; 357 break; 358 default: 359 return -EINVAL; 360 } 361 362 bank->irq_type[d->hwirq] = type; 363 364 return irq_chip_set_type_parent(d, parent_type); 365 }; 366 367 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) 368 { 369 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 370 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 371 int ret; 372 373 ret = pinctrl_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); 374 if (ret) 375 return ret; 376 377 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); 378 if (ret) { 379 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 380 irq_data->hwirq); 381 return ret; 382 } 383 384 return 0; 385 } 386 387 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) 388 { 389 struct stm32_gpio_bank *bank = irq_data->domain->host_data; 390 391 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); 392 } 393 394 static void stm32_gpio_irq_unmask(struct irq_data *d) 395 { 396 irq_chip_unmask_parent(d); 397 stm32_gpio_irq_trigger(d); 398 } 399 400 static struct irq_chip stm32_gpio_irq_chip = { 401 .name = "stm32gpio", 402 .irq_eoi = stm32_gpio_irq_eoi, 403 .irq_ack = irq_chip_ack_parent, 404 .irq_mask = irq_chip_mask_parent, 405 .irq_unmask = stm32_gpio_irq_unmask, 406 .irq_set_type = stm32_gpio_set_type, 407 .irq_set_wake = irq_chip_set_wake_parent, 408 .irq_request_resources = stm32_gpio_irq_request_resources, 409 .irq_release_resources = stm32_gpio_irq_release_resources, 410 }; 411 412 static int stm32_gpio_domain_translate(struct irq_domain *d, 413 struct irq_fwspec *fwspec, 414 unsigned long *hwirq, 415 unsigned int *type) 416 { 417 if ((fwspec->param_count != 2) || 418 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) 419 return -EINVAL; 420 421 *hwirq = fwspec->param[0]; 422 *type = fwspec->param[1]; 423 return 0; 424 } 425 426 static int stm32_gpio_domain_activate(struct irq_domain *d, 427 struct irq_data *irq_data, bool reserve) 428 { 429 struct stm32_gpio_bank *bank = d->host_data; 430 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 431 int ret = 0; 432 433 if (pctl->hwlock) { 434 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, 435 HWSPNLCK_TIMEOUT); 436 if (ret) { 437 dev_err(pctl->dev, "Can't get hwspinlock\n"); 438 return ret; 439 } 440 } 441 442 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); 443 444 if (pctl->hwlock) 445 hwspin_unlock_in_atomic(pctl->hwlock); 446 447 return ret; 448 } 449 450 static int stm32_gpio_domain_alloc(struct irq_domain *d, 451 unsigned int virq, 452 unsigned int nr_irqs, void *data) 453 { 454 struct stm32_gpio_bank *bank = d->host_data; 455 struct irq_fwspec *fwspec = data; 456 struct irq_fwspec parent_fwspec; 457 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 458 irq_hw_number_t hwirq = fwspec->param[0]; 459 unsigned long flags; 460 int ret = 0; 461 462 /* 463 * Check first that the IRQ MUX of that line is free. 464 * gpio irq mux is shared between several banks, protect with a lock 465 */ 466 spin_lock_irqsave(&pctl->irqmux_lock, flags); 467 468 if (pctl->irqmux_map & BIT(hwirq)) { 469 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq); 470 ret = -EBUSY; 471 } else { 472 pctl->irqmux_map |= BIT(hwirq); 473 } 474 475 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 476 if (ret) 477 return ret; 478 479 parent_fwspec.fwnode = d->parent->fwnode; 480 parent_fwspec.param_count = 2; 481 parent_fwspec.param[0] = fwspec->param[0]; 482 parent_fwspec.param[1] = fwspec->param[1]; 483 484 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, 485 bank); 486 487 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); 488 } 489 490 static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq, 491 unsigned int nr_irqs) 492 { 493 struct stm32_gpio_bank *bank = d->host_data; 494 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 495 struct irq_data *irq_data = irq_domain_get_irq_data(d, virq); 496 unsigned long flags, hwirq = irq_data->hwirq; 497 498 irq_domain_free_irqs_common(d, virq, nr_irqs); 499 500 spin_lock_irqsave(&pctl->irqmux_lock, flags); 501 pctl->irqmux_map &= ~BIT(hwirq); 502 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); 503 } 504 505 static const struct irq_domain_ops stm32_gpio_domain_ops = { 506 .translate = stm32_gpio_domain_translate, 507 .alloc = stm32_gpio_domain_alloc, 508 .free = stm32_gpio_domain_free, 509 .activate = stm32_gpio_domain_activate, 510 }; 511 512 /* Pinctrl functions */ 513 static struct stm32_pinctrl_group * 514 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) 515 { 516 int i; 517 518 for (i = 0; i < pctl->ngroups; i++) { 519 struct stm32_pinctrl_group *grp = pctl->groups + i; 520 521 if (grp->pin == pin) 522 return grp; 523 } 524 525 return NULL; 526 } 527 528 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, 529 u32 pin_num, u32 fnum) 530 { 531 int i, k; 532 533 for (i = 0; i < pctl->npins; i++) { 534 const struct stm32_desc_pin *pin = pctl->pins + i; 535 const struct stm32_desc_function *func = pin->functions; 536 537 if (pin->pin.number != pin_num) 538 continue; 539 540 for (k = 0; k < STM32_CONFIG_NUM; k++) { 541 if (func->num == fnum) 542 return true; 543 func++; 544 } 545 546 break; 547 } 548 549 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num); 550 551 return false; 552 } 553 554 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, 555 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, 556 struct pinctrl_map **map, unsigned *reserved_maps, 557 unsigned *num_maps) 558 { 559 if (*num_maps == *reserved_maps) 560 return -ENOSPC; 561 562 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 563 (*map)[*num_maps].data.mux.group = grp->name; 564 565 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) 566 return -EINVAL; 567 568 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; 569 (*num_maps)++; 570 571 return 0; 572 } 573 574 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 575 struct device_node *node, 576 struct pinctrl_map **map, 577 unsigned *reserved_maps, 578 unsigned *num_maps) 579 { 580 struct stm32_pinctrl *pctl; 581 struct stm32_pinctrl_group *grp; 582 struct property *pins; 583 u32 pinfunc, pin, func; 584 unsigned long *configs; 585 unsigned int num_configs; 586 bool has_config = 0; 587 unsigned reserve = 0; 588 int num_pins, num_funcs, maps_per_pin, i, err = 0; 589 590 pctl = pinctrl_dev_get_drvdata(pctldev); 591 592 pins = of_find_property(node, "pinmux", NULL); 593 if (!pins) { 594 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", 595 node); 596 return -EINVAL; 597 } 598 599 err = pinconf_generic_parse_dt_config(node, pctldev, &configs, 600 &num_configs); 601 if (err) 602 return err; 603 604 if (num_configs) 605 has_config = 1; 606 607 num_pins = pins->length / sizeof(u32); 608 num_funcs = num_pins; 609 maps_per_pin = 0; 610 if (num_funcs) 611 maps_per_pin++; 612 if (has_config && num_pins >= 1) 613 maps_per_pin++; 614 615 if (!num_pins || !maps_per_pin) { 616 err = -EINVAL; 617 goto exit; 618 } 619 620 reserve = num_pins * maps_per_pin; 621 622 err = pinctrl_utils_reserve_map(pctldev, map, 623 reserved_maps, num_maps, reserve); 624 if (err) 625 goto exit; 626 627 for (i = 0; i < num_pins; i++) { 628 err = of_property_read_u32_index(node, "pinmux", 629 i, &pinfunc); 630 if (err) 631 goto exit; 632 633 pin = STM32_GET_PIN_NO(pinfunc); 634 func = STM32_GET_PIN_FUNC(pinfunc); 635 636 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { 637 err = -EINVAL; 638 goto exit; 639 } 640 641 grp = stm32_pctrl_find_group_by_pin(pctl, pin); 642 if (!grp) { 643 dev_err(pctl->dev, "unable to match pin %d to group\n", 644 pin); 645 err = -EINVAL; 646 goto exit; 647 } 648 649 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, 650 reserved_maps, num_maps); 651 if (err) 652 goto exit; 653 654 if (has_config) { 655 err = pinctrl_utils_add_map_configs(pctldev, map, 656 reserved_maps, num_maps, grp->name, 657 configs, num_configs, 658 PIN_MAP_TYPE_CONFIGS_GROUP); 659 if (err) 660 goto exit; 661 } 662 } 663 664 exit: 665 kfree(configs); 666 return err; 667 } 668 669 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 670 struct device_node *np_config, 671 struct pinctrl_map **map, unsigned *num_maps) 672 { 673 unsigned reserved_maps; 674 int ret; 675 676 *map = NULL; 677 *num_maps = 0; 678 reserved_maps = 0; 679 680 for_each_child_of_node_scoped(np_config, np) { 681 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, 682 &reserved_maps, num_maps); 683 if (ret < 0) { 684 pinctrl_utils_free_map(pctldev, *map, *num_maps); 685 return ret; 686 } 687 } 688 689 return 0; 690 } 691 692 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 693 { 694 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 695 696 return pctl->ngroups; 697 } 698 699 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, 700 unsigned group) 701 { 702 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 703 704 return pctl->groups[group].name; 705 } 706 707 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 708 unsigned group, 709 const unsigned **pins, 710 unsigned *num_pins) 711 { 712 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 713 714 *pins = (unsigned *)&pctl->groups[group].pin; 715 *num_pins = 1; 716 717 return 0; 718 } 719 720 static const struct pinctrl_ops stm32_pctrl_ops = { 721 .dt_node_to_map = stm32_pctrl_dt_node_to_map, 722 .dt_free_map = pinctrl_utils_free_map, 723 .get_groups_count = stm32_pctrl_get_groups_count, 724 .get_group_name = stm32_pctrl_get_group_name, 725 .get_group_pins = stm32_pctrl_get_group_pins, 726 }; 727 728 729 /* Pinmux functions */ 730 731 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 732 { 733 return ARRAY_SIZE(stm32_gpio_functions); 734 } 735 736 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, 737 unsigned selector) 738 { 739 return stm32_gpio_functions[selector]; 740 } 741 742 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, 743 unsigned function, 744 const char * const **groups, 745 unsigned * const num_groups) 746 { 747 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 748 749 *groups = pctl->grp_names; 750 *num_groups = pctl->ngroups; 751 752 return 0; 753 } 754 755 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, 756 int pin, u32 mode, u32 alt) 757 { 758 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 759 u32 val; 760 int alt_shift = (pin % 8) * 4; 761 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 762 unsigned long flags; 763 int err = 0; 764 765 spin_lock_irqsave(&bank->lock, flags); 766 767 if (pctl->hwlock) { 768 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 769 HWSPNLCK_TIMEOUT); 770 if (err) { 771 dev_err(pctl->dev, "Can't get hwspinlock\n"); 772 goto unlock; 773 } 774 } 775 776 val = readl_relaxed(bank->base + alt_offset); 777 val &= ~GENMASK(alt_shift + 3, alt_shift); 778 val |= (alt << alt_shift); 779 writel_relaxed(val, bank->base + alt_offset); 780 781 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 782 val &= ~GENMASK(pin * 2 + 1, pin * 2); 783 val |= mode << (pin * 2); 784 writel_relaxed(val, bank->base + STM32_GPIO_MODER); 785 786 if (pctl->hwlock) 787 hwspin_unlock_in_atomic(pctl->hwlock); 788 789 stm32_gpio_backup_mode(bank, pin, mode, alt); 790 791 unlock: 792 spin_unlock_irqrestore(&bank->lock, flags); 793 794 return err; 795 } 796 797 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, 798 u32 *alt) 799 { 800 u32 val; 801 int alt_shift = (pin % 8) * 4; 802 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; 803 unsigned long flags; 804 805 spin_lock_irqsave(&bank->lock, flags); 806 807 val = readl_relaxed(bank->base + alt_offset); 808 val &= GENMASK(alt_shift + 3, alt_shift); 809 *alt = val >> alt_shift; 810 811 val = readl_relaxed(bank->base + STM32_GPIO_MODER); 812 val &= GENMASK(pin * 2 + 1, pin * 2); 813 *mode = val >> (pin * 2); 814 815 spin_unlock_irqrestore(&bank->lock, flags); 816 } 817 818 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, 819 unsigned function, 820 unsigned group) 821 { 822 bool ret; 823 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 824 struct stm32_pinctrl_group *g = pctl->groups + group; 825 struct pinctrl_gpio_range *range; 826 struct stm32_gpio_bank *bank; 827 u32 mode, alt; 828 int pin; 829 830 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); 831 if (!ret) 832 return -EINVAL; 833 834 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); 835 if (!range) { 836 dev_err(pctl->dev, "No gpio range defined.\n"); 837 return -EINVAL; 838 } 839 840 bank = gpiochip_get_data(range->gc); 841 pin = stm32_gpio_pin(g->pin); 842 843 mode = stm32_gpio_get_mode(function); 844 alt = stm32_gpio_get_alt(function); 845 846 return stm32_pmx_set_mode(bank, pin, mode, alt); 847 } 848 849 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 850 struct pinctrl_gpio_range *range, unsigned gpio, 851 bool input) 852 { 853 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); 854 int pin = stm32_gpio_pin(gpio); 855 856 return stm32_pmx_set_mode(bank, pin, !input, 0); 857 } 858 859 static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio) 860 { 861 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 862 struct pinctrl_gpio_range *range; 863 864 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, gpio); 865 if (!range) { 866 dev_err(pctl->dev, "No gpio range defined.\n"); 867 return -EINVAL; 868 } 869 870 if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) { 871 dev_warn(pctl->dev, "Can't access gpio %d\n", gpio); 872 return -EACCES; 873 } 874 875 return 0; 876 } 877 878 static const struct pinmux_ops stm32_pmx_ops = { 879 .get_functions_count = stm32_pmx_get_funcs_cnt, 880 .get_function_name = stm32_pmx_get_func_name, 881 .get_function_groups = stm32_pmx_get_func_groups, 882 .set_mux = stm32_pmx_set_mux, 883 .gpio_set_direction = stm32_pmx_gpio_set_direction, 884 .request = stm32_pmx_request, 885 .strict = true, 886 }; 887 888 /* Pinconf functions */ 889 890 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, 891 unsigned offset, u32 drive) 892 { 893 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 894 unsigned long flags; 895 u32 val; 896 int err = 0; 897 898 spin_lock_irqsave(&bank->lock, flags); 899 900 if (pctl->hwlock) { 901 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 902 HWSPNLCK_TIMEOUT); 903 if (err) { 904 dev_err(pctl->dev, "Can't get hwspinlock\n"); 905 goto unlock; 906 } 907 } 908 909 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 910 val &= ~BIT(offset); 911 val |= drive << offset; 912 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); 913 914 if (pctl->hwlock) 915 hwspin_unlock_in_atomic(pctl->hwlock); 916 917 stm32_gpio_backup_driving(bank, offset, drive); 918 919 unlock: 920 spin_unlock_irqrestore(&bank->lock, flags); 921 922 return err; 923 } 924 925 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, 926 unsigned int offset) 927 { 928 unsigned long flags; 929 u32 val; 930 931 spin_lock_irqsave(&bank->lock, flags); 932 933 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); 934 val &= BIT(offset); 935 936 spin_unlock_irqrestore(&bank->lock, flags); 937 938 return (val >> offset); 939 } 940 941 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, 942 unsigned offset, u32 speed) 943 { 944 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 945 unsigned long flags; 946 u32 val; 947 int err = 0; 948 949 spin_lock_irqsave(&bank->lock, flags); 950 951 if (pctl->hwlock) { 952 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 953 HWSPNLCK_TIMEOUT); 954 if (err) { 955 dev_err(pctl->dev, "Can't get hwspinlock\n"); 956 goto unlock; 957 } 958 } 959 960 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 961 val &= ~GENMASK(offset * 2 + 1, offset * 2); 962 val |= speed << (offset * 2); 963 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); 964 965 if (pctl->hwlock) 966 hwspin_unlock_in_atomic(pctl->hwlock); 967 968 stm32_gpio_backup_speed(bank, offset, speed); 969 970 unlock: 971 spin_unlock_irqrestore(&bank->lock, flags); 972 973 return err; 974 } 975 976 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, 977 unsigned int offset) 978 { 979 unsigned long flags; 980 u32 val; 981 982 spin_lock_irqsave(&bank->lock, flags); 983 984 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); 985 val &= GENMASK(offset * 2 + 1, offset * 2); 986 987 spin_unlock_irqrestore(&bank->lock, flags); 988 989 return (val >> (offset * 2)); 990 } 991 992 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, 993 unsigned offset, u32 bias) 994 { 995 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 996 unsigned long flags; 997 u32 val; 998 int err = 0; 999 1000 spin_lock_irqsave(&bank->lock, flags); 1001 1002 if (pctl->hwlock) { 1003 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, 1004 HWSPNLCK_TIMEOUT); 1005 if (err) { 1006 dev_err(pctl->dev, "Can't get hwspinlock\n"); 1007 goto unlock; 1008 } 1009 } 1010 1011 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 1012 val &= ~GENMASK(offset * 2 + 1, offset * 2); 1013 val |= bias << (offset * 2); 1014 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); 1015 1016 if (pctl->hwlock) 1017 hwspin_unlock_in_atomic(pctl->hwlock); 1018 1019 stm32_gpio_backup_bias(bank, offset, bias); 1020 1021 unlock: 1022 spin_unlock_irqrestore(&bank->lock, flags); 1023 1024 return err; 1025 } 1026 1027 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, 1028 unsigned int offset) 1029 { 1030 unsigned long flags; 1031 u32 val; 1032 1033 spin_lock_irqsave(&bank->lock, flags); 1034 1035 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); 1036 val &= GENMASK(offset * 2 + 1, offset * 2); 1037 1038 spin_unlock_irqrestore(&bank->lock, flags); 1039 1040 return (val >> (offset * 2)); 1041 } 1042 1043 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, 1044 unsigned int offset, bool dir) 1045 { 1046 unsigned long flags; 1047 u32 val; 1048 1049 spin_lock_irqsave(&bank->lock, flags); 1050 1051 if (dir) 1052 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & 1053 BIT(offset)); 1054 else 1055 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & 1056 BIT(offset)); 1057 1058 spin_unlock_irqrestore(&bank->lock, flags); 1059 1060 return val; 1061 } 1062 1063 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, 1064 unsigned int pin, enum pin_config_param param, 1065 enum pin_config_param arg) 1066 { 1067 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1068 struct pinctrl_gpio_range *range; 1069 struct stm32_gpio_bank *bank; 1070 int offset, ret = 0; 1071 1072 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 1073 if (!range) { 1074 dev_err(pctl->dev, "No gpio range defined.\n"); 1075 return -EINVAL; 1076 } 1077 1078 bank = gpiochip_get_data(range->gc); 1079 offset = stm32_gpio_pin(pin); 1080 1081 if (!gpiochip_line_is_valid(range->gc, offset)) { 1082 dev_warn(pctl->dev, "Can't access gpio %d\n", pin); 1083 return -EACCES; 1084 } 1085 1086 switch (param) { 1087 case PIN_CONFIG_DRIVE_PUSH_PULL: 1088 ret = stm32_pconf_set_driving(bank, offset, 0); 1089 break; 1090 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1091 ret = stm32_pconf_set_driving(bank, offset, 1); 1092 break; 1093 case PIN_CONFIG_SLEW_RATE: 1094 ret = stm32_pconf_set_speed(bank, offset, arg); 1095 break; 1096 case PIN_CONFIG_BIAS_DISABLE: 1097 ret = stm32_pconf_set_bias(bank, offset, 0); 1098 break; 1099 case PIN_CONFIG_BIAS_PULL_UP: 1100 ret = stm32_pconf_set_bias(bank, offset, 1); 1101 break; 1102 case PIN_CONFIG_BIAS_PULL_DOWN: 1103 ret = stm32_pconf_set_bias(bank, offset, 2); 1104 break; 1105 case PIN_CONFIG_OUTPUT: 1106 __stm32_gpio_set(bank, offset, arg); 1107 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); 1108 break; 1109 default: 1110 ret = -ENOTSUPP; 1111 } 1112 1113 return ret; 1114 } 1115 1116 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, 1117 unsigned group, 1118 unsigned long *config) 1119 { 1120 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1121 1122 *config = pctl->groups[group].config; 1123 1124 return 0; 1125 } 1126 1127 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 1128 unsigned long *configs, unsigned num_configs) 1129 { 1130 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1131 struct stm32_pinctrl_group *g = &pctl->groups[group]; 1132 int i, ret; 1133 1134 for (i = 0; i < num_configs; i++) { 1135 mutex_lock(&pctldev->mutex); 1136 ret = stm32_pconf_parse_conf(pctldev, g->pin, 1137 pinconf_to_config_param(configs[i]), 1138 pinconf_to_config_argument(configs[i])); 1139 mutex_unlock(&pctldev->mutex); 1140 if (ret < 0) 1141 return ret; 1142 1143 g->config = configs[i]; 1144 } 1145 1146 return 0; 1147 } 1148 1149 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1150 unsigned long *configs, unsigned int num_configs) 1151 { 1152 int i, ret; 1153 1154 for (i = 0; i < num_configs; i++) { 1155 ret = stm32_pconf_parse_conf(pctldev, pin, 1156 pinconf_to_config_param(configs[i]), 1157 pinconf_to_config_argument(configs[i])); 1158 if (ret < 0) 1159 return ret; 1160 } 1161 1162 return 0; 1163 } 1164 1165 static struct stm32_desc_pin * 1166 stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl, 1167 unsigned int pin_number) 1168 { 1169 struct stm32_desc_pin *pins = pctl->pins; 1170 int i; 1171 1172 for (i = 0; i < pctl->npins; i++) { 1173 if (pins->pin.number == pin_number) 1174 return pins; 1175 pins++; 1176 } 1177 return NULL; 1178 } 1179 1180 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, 1181 struct seq_file *s, 1182 unsigned int pin) 1183 { 1184 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 1185 const struct stm32_desc_pin *pin_desc; 1186 struct pinctrl_gpio_range *range; 1187 struct stm32_gpio_bank *bank; 1188 int offset; 1189 u32 mode, alt, drive, speed, bias; 1190 static const char * const modes[] = { 1191 "input", "output", "alternate", "analog" }; 1192 static const char * const speeds[] = { 1193 "low", "medium", "high", "very high" }; 1194 static const char * const biasing[] = { 1195 "floating", "pull up", "pull down", "" }; 1196 bool val; 1197 1198 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 1199 if (!range) 1200 return; 1201 1202 bank = gpiochip_get_data(range->gc); 1203 offset = stm32_gpio_pin(pin); 1204 1205 if (!gpiochip_line_is_valid(range->gc, offset)) { 1206 seq_puts(s, "NO ACCESS"); 1207 return; 1208 } 1209 1210 stm32_pmx_get_mode(bank, offset, &mode, &alt); 1211 bias = stm32_pconf_get_bias(bank, offset); 1212 1213 seq_printf(s, "%s ", modes[mode]); 1214 1215 switch (mode) { 1216 /* input */ 1217 case 0: 1218 val = stm32_pconf_get(bank, offset, true); 1219 seq_printf(s, "- %s - %s", 1220 val ? "high" : "low", 1221 biasing[bias]); 1222 break; 1223 1224 /* output */ 1225 case 1: 1226 drive = stm32_pconf_get_driving(bank, offset); 1227 speed = stm32_pconf_get_speed(bank, offset); 1228 val = stm32_pconf_get(bank, offset, false); 1229 seq_printf(s, "- %s - %s - %s - %s %s", 1230 val ? "high" : "low", 1231 drive ? "open drain" : "push pull", 1232 biasing[bias], 1233 speeds[speed], "speed"); 1234 break; 1235 1236 /* alternate */ 1237 case 2: 1238 drive = stm32_pconf_get_driving(bank, offset); 1239 speed = stm32_pconf_get_speed(bank, offset); 1240 pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin); 1241 if (!pin_desc) 1242 return; 1243 1244 seq_printf(s, "%d (%s) - %s - %s - %s %s", alt, 1245 pin_desc->functions[alt + 1].name, 1246 drive ? "open drain" : "push pull", 1247 biasing[bias], 1248 speeds[speed], "speed"); 1249 break; 1250 1251 /* analog */ 1252 case 3: 1253 break; 1254 } 1255 } 1256 1257 static const struct pinconf_ops stm32_pconf_ops = { 1258 .pin_config_group_get = stm32_pconf_group_get, 1259 .pin_config_group_set = stm32_pconf_group_set, 1260 .pin_config_set = stm32_pconf_set, 1261 .pin_config_dbg_show = stm32_pconf_dbg_show, 1262 }; 1263 1264 static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl, 1265 struct stm32_gpio_bank *bank, 1266 unsigned int offset) 1267 { 1268 unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset; 1269 struct stm32_desc_pin *pin_desc; 1270 int i; 1271 1272 /* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */ 1273 if (stm32_pin_nb < pctl->npins) { 1274 pin_desc = pctl->pins + stm32_pin_nb; 1275 if (pin_desc->pin.number == stm32_pin_nb) 1276 return pin_desc; 1277 } 1278 1279 /* Otherwise, loop all array to find the pin with the right number */ 1280 for (i = 0; i < pctl->npins; i++) { 1281 pin_desc = pctl->pins + i; 1282 if (pin_desc->pin.number == stm32_pin_nb) 1283 return pin_desc; 1284 } 1285 return NULL; 1286 } 1287 1288 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode) 1289 { 1290 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; 1291 int bank_ioport_nr; 1292 struct pinctrl_gpio_range *range = &bank->range; 1293 struct fwnode_reference_args args; 1294 struct device *dev = pctl->dev; 1295 struct resource res; 1296 int npins = STM32_GPIO_PINS_PER_BANK; 1297 int bank_nr, err, i = 0; 1298 struct stm32_desc_pin *stm32_pin; 1299 char **names; 1300 1301 if (!IS_ERR(bank->rstc)) 1302 reset_control_deassert(bank->rstc); 1303 1304 if (of_address_to_resource(to_of_node(fwnode), 0, &res)) 1305 return -ENODEV; 1306 1307 bank->base = devm_ioremap_resource(dev, &res); 1308 if (IS_ERR(bank->base)) 1309 return PTR_ERR(bank->base); 1310 1311 err = clk_prepare_enable(bank->clk); 1312 if (err) { 1313 dev_err(dev, "failed to prepare_enable clk (%d)\n", err); 1314 return err; 1315 } 1316 1317 bank->gpio_chip = stm32_gpio_template; 1318 1319 fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label); 1320 1321 if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) { 1322 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; 1323 bank->gpio_chip.base = args.args[1]; 1324 1325 /* get the last defined gpio line (offset + nb of pins) */ 1326 npins = args.args[0] + args.args[2]; 1327 while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args)) 1328 npins = max(npins, (int)(args.args[0] + args.args[2])); 1329 } else { 1330 bank_nr = pctl->nbanks; 1331 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1332 range->name = bank->gpio_chip.label; 1333 range->id = bank_nr; 1334 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; 1335 range->base = range->id * STM32_GPIO_PINS_PER_BANK; 1336 range->npins = npins; 1337 range->gc = &bank->gpio_chip; 1338 pinctrl_add_gpio_range(pctl->pctl_dev, 1339 &pctl->banks[bank_nr].range); 1340 } 1341 1342 if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr)) 1343 bank_ioport_nr = bank_nr; 1344 1345 bank->gpio_chip.base = -1; 1346 1347 bank->gpio_chip.ngpio = npins; 1348 bank->gpio_chip.fwnode = fwnode; 1349 bank->gpio_chip.parent = dev; 1350 bank->bank_nr = bank_nr; 1351 bank->bank_ioport_nr = bank_ioport_nr; 1352 bank->secure_control = pctl->match_data->secure_control; 1353 spin_lock_init(&bank->lock); 1354 1355 if (pctl->domain) { 1356 /* create irq hierarchical domain */ 1357 bank->fwnode = fwnode; 1358 1359 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE, 1360 bank->fwnode, &stm32_gpio_domain_ops, 1361 bank); 1362 1363 if (!bank->domain) { 1364 err = -ENODEV; 1365 goto err_clk; 1366 } 1367 } 1368 1369 names = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL); 1370 if (!names) { 1371 err = -ENOMEM; 1372 goto err_clk; 1373 } 1374 1375 for (i = 0; i < npins; i++) { 1376 stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i); 1377 if (stm32_pin && stm32_pin->pin.name) 1378 names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name); 1379 else 1380 names[i] = NULL; 1381 } 1382 1383 bank->gpio_chip.names = (const char * const *)names; 1384 1385 err = gpiochip_add_data(&bank->gpio_chip, bank); 1386 if (err) { 1387 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); 1388 goto err_clk; 1389 } 1390 1391 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); 1392 return 0; 1393 1394 err_clk: 1395 clk_disable_unprepare(bank->clk); 1396 return err; 1397 } 1398 1399 static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev) 1400 { 1401 struct device_node *np = pdev->dev.of_node; 1402 struct device_node *parent; 1403 struct irq_domain *domain; 1404 1405 if (!of_property_present(np, "interrupt-parent")) 1406 return NULL; 1407 1408 parent = of_irq_find_parent(np); 1409 if (!parent) 1410 return ERR_PTR(-ENXIO); 1411 1412 domain = irq_find_host(parent); 1413 of_node_put(parent); 1414 if (!domain) 1415 /* domain not registered yet */ 1416 return ERR_PTR(-EPROBE_DEFER); 1417 1418 return domain; 1419 } 1420 1421 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 1422 struct stm32_pinctrl *pctl) 1423 { 1424 struct device_node *np = pdev->dev.of_node; 1425 struct device *dev = &pdev->dev; 1426 struct regmap *rm; 1427 int offset, ret, i; 1428 int mask, mask_width; 1429 1430 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1431 if (IS_ERR(pctl->regmap)) 1432 return PTR_ERR(pctl->regmap); 1433 1434 rm = pctl->regmap; 1435 1436 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); 1437 if (ret) 1438 return ret; 1439 1440 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask); 1441 if (ret) 1442 mask = SYSCFG_IRQMUX_MASK; 1443 1444 mask_width = fls(mask); 1445 1446 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { 1447 struct reg_field mux; 1448 1449 mux.reg = offset + (i / 4) * 4; 1450 mux.lsb = (i % 4) * mask_width; 1451 mux.msb = mux.lsb + mask_width - 1; 1452 1453 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n", 1454 i, mux.reg, mux.lsb, mux.msb); 1455 1456 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); 1457 if (IS_ERR(pctl->irqmux[i])) 1458 return PTR_ERR(pctl->irqmux[i]); 1459 } 1460 1461 return 0; 1462 } 1463 1464 static int stm32_pctrl_build_state(struct platform_device *pdev) 1465 { 1466 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); 1467 int i; 1468 1469 pctl->ngroups = pctl->npins; 1470 1471 /* Allocate groups */ 1472 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1473 sizeof(*pctl->groups), GFP_KERNEL); 1474 if (!pctl->groups) 1475 return -ENOMEM; 1476 1477 /* We assume that one pin is one group, use pin name as group name. */ 1478 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, 1479 sizeof(*pctl->grp_names), GFP_KERNEL); 1480 if (!pctl->grp_names) 1481 return -ENOMEM; 1482 1483 for (i = 0; i < pctl->npins; i++) { 1484 const struct stm32_desc_pin *pin = pctl->pins + i; 1485 struct stm32_pinctrl_group *group = pctl->groups + i; 1486 1487 group->name = pin->pin.name; 1488 group->pin = pin->pin.number; 1489 pctl->grp_names[i] = pin->pin.name; 1490 } 1491 1492 return 0; 1493 } 1494 1495 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl, 1496 struct stm32_desc_pin *pins) 1497 { 1498 const struct stm32_desc_pin *p; 1499 int i, nb_pins_available = 0; 1500 1501 for (i = 0; i < pctl->match_data->npins; i++) { 1502 p = pctl->match_data->pins + i; 1503 if (pctl->pkg && !(pctl->pkg & p->pkg)) 1504 continue; 1505 pins->pin = p->pin; 1506 memcpy((struct stm32_desc_pin *)pins->functions, p->functions, 1507 STM32_CONFIG_NUM * sizeof(struct stm32_desc_function)); 1508 pins++; 1509 nb_pins_available++; 1510 } 1511 1512 pctl->npins = nb_pins_available; 1513 1514 return 0; 1515 } 1516 1517 int stm32_pctl_probe(struct platform_device *pdev) 1518 { 1519 const struct stm32_pinctrl_match_data *match_data; 1520 struct fwnode_handle *child; 1521 struct device *dev = &pdev->dev; 1522 struct stm32_pinctrl *pctl; 1523 struct pinctrl_pin_desc *pins; 1524 int i, ret, hwlock_id; 1525 unsigned int banks; 1526 1527 match_data = device_get_match_data(dev); 1528 if (!match_data) 1529 return -EINVAL; 1530 1531 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); 1532 if (!pctl) 1533 return -ENOMEM; 1534 1535 platform_set_drvdata(pdev, pctl); 1536 1537 /* check for IRQ controller (may require deferred probe) */ 1538 pctl->domain = stm32_pctrl_get_irq_domain(pdev); 1539 if (IS_ERR(pctl->domain)) 1540 return PTR_ERR(pctl->domain); 1541 if (!pctl->domain) 1542 dev_warn(dev, "pinctrl without interrupt support\n"); 1543 1544 /* hwspinlock is optional */ 1545 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); 1546 if (hwlock_id < 0) { 1547 if (hwlock_id == -EPROBE_DEFER) 1548 return hwlock_id; 1549 } else { 1550 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); 1551 } 1552 1553 spin_lock_init(&pctl->irqmux_lock); 1554 1555 pctl->dev = dev; 1556 pctl->match_data = match_data; 1557 1558 /* get optional package information */ 1559 if (!device_property_read_u32(dev, "st,package", &pctl->pkg)) 1560 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg); 1561 1562 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins, 1563 sizeof(*pctl->pins), GFP_KERNEL); 1564 if (!pctl->pins) 1565 return -ENOMEM; 1566 1567 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins); 1568 if (ret) 1569 return ret; 1570 1571 ret = stm32_pctrl_build_state(pdev); 1572 if (ret) { 1573 dev_err(dev, "build state failed: %d\n", ret); 1574 return -EINVAL; 1575 } 1576 1577 if (pctl->domain) { 1578 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1579 if (ret) 1580 return ret; 1581 } 1582 1583 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins), 1584 GFP_KERNEL); 1585 if (!pins) 1586 return -ENOMEM; 1587 1588 for (i = 0; i < pctl->npins; i++) 1589 pins[i] = pctl->pins[i].pin; 1590 1591 pctl->pctl_desc.name = dev_name(&pdev->dev); 1592 pctl->pctl_desc.owner = THIS_MODULE; 1593 pctl->pctl_desc.pins = pins; 1594 pctl->pctl_desc.npins = pctl->npins; 1595 pctl->pctl_desc.link_consumers = true; 1596 pctl->pctl_desc.confops = &stm32_pconf_ops; 1597 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; 1598 pctl->pctl_desc.pmxops = &stm32_pmx_ops; 1599 pctl->dev = &pdev->dev; 1600 1601 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, 1602 pctl); 1603 1604 if (IS_ERR(pctl->pctl_dev)) { 1605 dev_err(&pdev->dev, "Failed pinctrl registration\n"); 1606 return PTR_ERR(pctl->pctl_dev); 1607 } 1608 1609 banks = gpiochip_node_count(dev); 1610 if (!banks) { 1611 dev_err(dev, "at least one GPIO bank is required\n"); 1612 return -EINVAL; 1613 } 1614 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), 1615 GFP_KERNEL); 1616 if (!pctl->banks) 1617 return -ENOMEM; 1618 1619 i = 0; 1620 for_each_gpiochip_node(dev, child) { 1621 struct stm32_gpio_bank *bank = &pctl->banks[i]; 1622 struct device_node *np = to_of_node(child); 1623 1624 bank->rstc = of_reset_control_get_exclusive(np, NULL); 1625 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) { 1626 fwnode_handle_put(child); 1627 return -EPROBE_DEFER; 1628 } 1629 1630 bank->clk = of_clk_get_by_name(np, NULL); 1631 if (IS_ERR(bank->clk)) { 1632 fwnode_handle_put(child); 1633 return dev_err_probe(dev, PTR_ERR(bank->clk), 1634 "failed to get clk\n"); 1635 } 1636 i++; 1637 } 1638 1639 for_each_gpiochip_node(dev, child) { 1640 ret = stm32_gpiolib_register_bank(pctl, child); 1641 if (ret) { 1642 fwnode_handle_put(child); 1643 1644 for (i = 0; i < pctl->nbanks; i++) 1645 clk_disable_unprepare(pctl->banks[i].clk); 1646 1647 return ret; 1648 } 1649 1650 pctl->nbanks++; 1651 } 1652 1653 dev_info(dev, "Pinctrl STM32 initialized\n"); 1654 1655 return 0; 1656 } 1657 1658 static int __maybe_unused stm32_pinctrl_restore_gpio_regs( 1659 struct stm32_pinctrl *pctl, u32 pin) 1660 { 1661 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); 1662 u32 val, alt, mode, offset = stm32_gpio_pin(pin); 1663 struct pinctrl_gpio_range *range; 1664 struct stm32_gpio_bank *bank; 1665 bool pin_is_irq; 1666 int ret; 1667 1668 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin); 1669 if (!range) 1670 return 0; 1671 1672 if (!gpiochip_line_is_valid(range->gc, offset)) 1673 return 0; 1674 1675 pin_is_irq = gpiochip_line_is_irq(range->gc, offset); 1676 1677 if (!desc || (!pin_is_irq && !desc->gpio_owner)) 1678 return 0; 1679 1680 bank = gpiochip_get_data(range->gc); 1681 1682 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; 1683 alt >>= STM32_GPIO_BKP_ALT_SHIFT; 1684 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; 1685 mode >>= STM32_GPIO_BKP_MODE_SHIFT; 1686 1687 ret = stm32_pmx_set_mode(bank, offset, mode, alt); 1688 if (ret) 1689 return ret; 1690 1691 if (mode == 1) { 1692 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); 1693 val = val >> STM32_GPIO_BKP_VAL; 1694 __stm32_gpio_set(bank, offset, val); 1695 } 1696 1697 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); 1698 val >>= STM32_GPIO_BKP_TYPE; 1699 ret = stm32_pconf_set_driving(bank, offset, val); 1700 if (ret) 1701 return ret; 1702 1703 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; 1704 val >>= STM32_GPIO_BKP_SPEED_SHIFT; 1705 ret = stm32_pconf_set_speed(bank, offset, val); 1706 if (ret) 1707 return ret; 1708 1709 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; 1710 val >>= STM32_GPIO_BKP_PUPD_SHIFT; 1711 ret = stm32_pconf_set_bias(bank, offset, val); 1712 if (ret) 1713 return ret; 1714 1715 if (pin_is_irq) 1716 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); 1717 1718 return 0; 1719 } 1720 1721 int __maybe_unused stm32_pinctrl_suspend(struct device *dev) 1722 { 1723 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); 1724 int i; 1725 1726 for (i = 0; i < pctl->nbanks; i++) 1727 clk_disable(pctl->banks[i].clk); 1728 1729 return 0; 1730 } 1731 1732 int __maybe_unused stm32_pinctrl_resume(struct device *dev) 1733 { 1734 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); 1735 struct stm32_pinctrl_group *g = pctl->groups; 1736 int i; 1737 1738 for (i = 0; i < pctl->nbanks; i++) 1739 clk_enable(pctl->banks[i].clk); 1740 1741 for (i = 0; i < pctl->ngroups; i++, g++) 1742 stm32_pinctrl_restore_gpio_regs(pctl, g->pin); 1743 1744 return 0; 1745 } 1746