1*447976abSJianlong Huang /* SPDX-License-Identifier: GPL-2.0 */ 2*447976abSJianlong Huang /* 3*447976abSJianlong Huang * Pinctrl / GPIO driver for StarFive JH7110 SoC 4*447976abSJianlong Huang * 5*447976abSJianlong Huang * Copyright (C) 2022 StarFive Technology Co., Ltd. 6*447976abSJianlong Huang */ 7*447976abSJianlong Huang 8*447976abSJianlong Huang #ifndef __PINCTRL_STARFIVE_JH7110_H__ 9*447976abSJianlong Huang #define __PINCTRL_STARFIVE_JH7110_H__ 10*447976abSJianlong Huang 11*447976abSJianlong Huang #include <linux/pinctrl/pinconf-generic.h> 12*447976abSJianlong Huang #include <linux/pinctrl/pinmux.h> 13*447976abSJianlong Huang 14*447976abSJianlong Huang struct jh7110_pinctrl { 15*447976abSJianlong Huang struct device *dev; 16*447976abSJianlong Huang struct gpio_chip gc; 17*447976abSJianlong Huang struct pinctrl_gpio_range gpios; 18*447976abSJianlong Huang raw_spinlock_t lock; 19*447976abSJianlong Huang void __iomem *base; 20*447976abSJianlong Huang struct pinctrl_dev *pctl; 21*447976abSJianlong Huang /* register read/write mutex */ 22*447976abSJianlong Huang struct mutex mutex; 23*447976abSJianlong Huang const struct jh7110_pinctrl_soc_info *info; 24*447976abSJianlong Huang }; 25*447976abSJianlong Huang 26*447976abSJianlong Huang struct jh7110_gpio_irq_reg { 27*447976abSJianlong Huang unsigned int is_reg_base; 28*447976abSJianlong Huang unsigned int ic_reg_base; 29*447976abSJianlong Huang unsigned int ibe_reg_base; 30*447976abSJianlong Huang unsigned int iev_reg_base; 31*447976abSJianlong Huang unsigned int ie_reg_base; 32*447976abSJianlong Huang unsigned int ris_reg_base; 33*447976abSJianlong Huang unsigned int mis_reg_base; 34*447976abSJianlong Huang }; 35*447976abSJianlong Huang 36*447976abSJianlong Huang struct jh7110_pinctrl_soc_info { 37*447976abSJianlong Huang const struct pinctrl_pin_desc *pins; 38*447976abSJianlong Huang unsigned int npins; 39*447976abSJianlong Huang unsigned int ngpios; 40*447976abSJianlong Huang unsigned int gc_base; 41*447976abSJianlong Huang 42*447976abSJianlong Huang /* gpio dout/doen/din/gpioinput register */ 43*447976abSJianlong Huang unsigned int dout_reg_base; 44*447976abSJianlong Huang unsigned int dout_mask; 45*447976abSJianlong Huang unsigned int doen_reg_base; 46*447976abSJianlong Huang unsigned int doen_mask; 47*447976abSJianlong Huang unsigned int gpi_reg_base; 48*447976abSJianlong Huang unsigned int gpi_mask; 49*447976abSJianlong Huang unsigned int gpioin_reg_base; 50*447976abSJianlong Huang 51*447976abSJianlong Huang const struct jh7110_gpio_irq_reg *irq_reg; 52*447976abSJianlong Huang 53*447976abSJianlong Huang /* generic pinmux */ 54*447976abSJianlong Huang int (*jh7110_set_one_pin_mux)(struct jh7110_pinctrl *sfp, 55*447976abSJianlong Huang unsigned int pin, 56*447976abSJianlong Huang unsigned int din, u32 dout, 57*447976abSJianlong Huang u32 doen, u32 func); 58*447976abSJianlong Huang /* gpio chip */ 59*447976abSJianlong Huang int (*jh7110_get_padcfg_base)(struct jh7110_pinctrl *sfp, 60*447976abSJianlong Huang unsigned int pin); 61*447976abSJianlong Huang void (*jh7110_gpio_irq_handler)(struct irq_desc *desc); 62*447976abSJianlong Huang int (*jh7110_gpio_init_hw)(struct gpio_chip *gc); 63*447976abSJianlong Huang }; 64*447976abSJianlong Huang 65*447976abSJianlong Huang void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin, 66*447976abSJianlong Huang unsigned int din, u32 dout, u32 doen); 67*447976abSJianlong Huang int jh7110_pinctrl_probe(struct platform_device *pdev); 68*447976abSJianlong Huang struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc); 69*447976abSJianlong Huang 70*447976abSJianlong Huang #endif /* __PINCTRL_STARFIVE_JH7110_H__ */ 71