1447976abSJianlong Huang /* SPDX-License-Identifier: GPL-2.0 */ 2447976abSJianlong Huang /* 3447976abSJianlong Huang * Pinctrl / GPIO driver for StarFive JH7110 SoC 4447976abSJianlong Huang * 5447976abSJianlong Huang * Copyright (C) 2022 StarFive Technology Co., Ltd. 6447976abSJianlong Huang */ 7447976abSJianlong Huang 8447976abSJianlong Huang #ifndef __PINCTRL_STARFIVE_JH7110_H__ 9447976abSJianlong Huang #define __PINCTRL_STARFIVE_JH7110_H__ 10447976abSJianlong Huang 11447976abSJianlong Huang #include <linux/pinctrl/pinconf-generic.h> 12447976abSJianlong Huang #include <linux/pinctrl/pinmux.h> 13447976abSJianlong Huang 14447976abSJianlong Huang struct jh7110_pinctrl { 15447976abSJianlong Huang struct device *dev; 16447976abSJianlong Huang struct gpio_chip gc; 17447976abSJianlong Huang struct pinctrl_gpio_range gpios; 18447976abSJianlong Huang raw_spinlock_t lock; 19447976abSJianlong Huang void __iomem *base; 20447976abSJianlong Huang struct pinctrl_dev *pctl; 21447976abSJianlong Huang /* register read/write mutex */ 22447976abSJianlong Huang struct mutex mutex; 23447976abSJianlong Huang const struct jh7110_pinctrl_soc_info *info; 24*64061b67SHal Feng u32 *saved_regs; 25447976abSJianlong Huang }; 26447976abSJianlong Huang 27447976abSJianlong Huang struct jh7110_gpio_irq_reg { 28447976abSJianlong Huang unsigned int is_reg_base; 29447976abSJianlong Huang unsigned int ic_reg_base; 30447976abSJianlong Huang unsigned int ibe_reg_base; 31447976abSJianlong Huang unsigned int iev_reg_base; 32447976abSJianlong Huang unsigned int ie_reg_base; 33447976abSJianlong Huang unsigned int ris_reg_base; 34447976abSJianlong Huang unsigned int mis_reg_base; 35447976abSJianlong Huang }; 36447976abSJianlong Huang 37447976abSJianlong Huang struct jh7110_pinctrl_soc_info { 38447976abSJianlong Huang const struct pinctrl_pin_desc *pins; 39447976abSJianlong Huang unsigned int npins; 40447976abSJianlong Huang unsigned int ngpios; 41447976abSJianlong Huang unsigned int gc_base; 42447976abSJianlong Huang 43447976abSJianlong Huang /* gpio dout/doen/din/gpioinput register */ 44447976abSJianlong Huang unsigned int dout_reg_base; 45447976abSJianlong Huang unsigned int dout_mask; 46447976abSJianlong Huang unsigned int doen_reg_base; 47447976abSJianlong Huang unsigned int doen_mask; 48447976abSJianlong Huang unsigned int gpi_reg_base; 49447976abSJianlong Huang unsigned int gpi_mask; 50447976abSJianlong Huang unsigned int gpioin_reg_base; 51447976abSJianlong Huang 52447976abSJianlong Huang const struct jh7110_gpio_irq_reg *irq_reg; 53447976abSJianlong Huang 54*64061b67SHal Feng unsigned int nsaved_regs; 55*64061b67SHal Feng 56447976abSJianlong Huang /* generic pinmux */ 57447976abSJianlong Huang int (*jh7110_set_one_pin_mux)(struct jh7110_pinctrl *sfp, 58447976abSJianlong Huang unsigned int pin, 59447976abSJianlong Huang unsigned int din, u32 dout, 60447976abSJianlong Huang u32 doen, u32 func); 61447976abSJianlong Huang /* gpio chip */ 62447976abSJianlong Huang int (*jh7110_get_padcfg_base)(struct jh7110_pinctrl *sfp, 63447976abSJianlong Huang unsigned int pin); 64447976abSJianlong Huang void (*jh7110_gpio_irq_handler)(struct irq_desc *desc); 65447976abSJianlong Huang int (*jh7110_gpio_init_hw)(struct gpio_chip *gc); 66447976abSJianlong Huang }; 67447976abSJianlong Huang 68447976abSJianlong Huang void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin, 69447976abSJianlong Huang unsigned int din, u32 dout, u32 doen); 70447976abSJianlong Huang int jh7110_pinctrl_probe(struct platform_device *pdev); 71447976abSJianlong Huang struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc); 72*64061b67SHal Feng extern const struct dev_pm_ops jh7110_pinctrl_pm_ops; 73447976abSJianlong Huang 74447976abSJianlong Huang #endif /* __PINCTRL_STARFIVE_JH7110_H__ */ 75