1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pinctrl / GPIO driver for StarFive JH7110 SoC sys controller 4 * 5 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 6 * Copyright (C) 2022 StarFive Technology Co., Ltd. 7 */ 8 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/io.h> 13 #include <linux/mod_devicetable.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/platform_device.h> 17 #include <linux/reset.h> 18 #include <linux/spinlock.h> 19 20 #include <linux/pinctrl/pinctrl.h> 21 #include <linux/pinctrl/pinmux.h> 22 23 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h> 24 25 #include "../core.h" 26 #include "../pinctrl-utils.h" 27 #include "../pinmux.h" 28 #include "../pinconf.h" 29 #include "pinctrl-starfive-jh7110.h" 30 31 #define JH7110_SYS_NGPIO 64 32 #define JH7110_SYS_GC_BASE 0 33 34 #define JH7110_SYS_REGS_NUM 174 35 36 /* registers */ 37 #define JH7110_SYS_DOEN 0x000 38 #define JH7110_SYS_DOUT 0x040 39 #define JH7110_SYS_GPI 0x080 40 #define JH7110_SYS_GPIOIN 0x118 41 42 #define JH7110_SYS_GPIOEN 0x0dc 43 #define JH7110_SYS_GPIOIS0 0x0e0 44 #define JH7110_SYS_GPIOIS1 0x0e4 45 #define JH7110_SYS_GPIOIC0 0x0e8 46 #define JH7110_SYS_GPIOIC1 0x0ec 47 #define JH7110_SYS_GPIOIBE0 0x0f0 48 #define JH7110_SYS_GPIOIBE1 0x0f4 49 #define JH7110_SYS_GPIOIEV0 0x0f8 50 #define JH7110_SYS_GPIOIEV1 0x0fc 51 #define JH7110_SYS_GPIOIE0 0x100 52 #define JH7110_SYS_GPIOIE1 0x104 53 #define JH7110_SYS_GPIORIS0 0x108 54 #define JH7110_SYS_GPIORIS1 0x10c 55 #define JH7110_SYS_GPIOMIS0 0x110 56 #define JH7110_SYS_GPIOMIS1 0x114 57 58 #define JH7110_SYS_GPO_PDA_0_74_CFG 0x120 59 #define JH7110_SYS_GPO_PDA_89_94_CFG 0x284 60 61 static const struct pinctrl_pin_desc jh7110_sys_pins[] = { 62 PINCTRL_PIN(PAD_GPIO0, "GPIO0"), 63 PINCTRL_PIN(PAD_GPIO1, "GPIO1"), 64 PINCTRL_PIN(PAD_GPIO2, "GPIO2"), 65 PINCTRL_PIN(PAD_GPIO3, "GPIO3"), 66 PINCTRL_PIN(PAD_GPIO4, "GPIO4"), 67 PINCTRL_PIN(PAD_GPIO5, "GPIO5"), 68 PINCTRL_PIN(PAD_GPIO6, "GPIO6"), 69 PINCTRL_PIN(PAD_GPIO7, "GPIO7"), 70 PINCTRL_PIN(PAD_GPIO8, "GPIO8"), 71 PINCTRL_PIN(PAD_GPIO9, "GPIO9"), 72 PINCTRL_PIN(PAD_GPIO10, "GPIO10"), 73 PINCTRL_PIN(PAD_GPIO11, "GPIO11"), 74 PINCTRL_PIN(PAD_GPIO12, "GPIO12"), 75 PINCTRL_PIN(PAD_GPIO13, "GPIO13"), 76 PINCTRL_PIN(PAD_GPIO14, "GPIO14"), 77 PINCTRL_PIN(PAD_GPIO15, "GPIO15"), 78 PINCTRL_PIN(PAD_GPIO16, "GPIO16"), 79 PINCTRL_PIN(PAD_GPIO17, "GPIO17"), 80 PINCTRL_PIN(PAD_GPIO18, "GPIO18"), 81 PINCTRL_PIN(PAD_GPIO19, "GPIO19"), 82 PINCTRL_PIN(PAD_GPIO20, "GPIO20"), 83 PINCTRL_PIN(PAD_GPIO21, "GPIO21"), 84 PINCTRL_PIN(PAD_GPIO22, "GPIO22"), 85 PINCTRL_PIN(PAD_GPIO23, "GPIO23"), 86 PINCTRL_PIN(PAD_GPIO24, "GPIO24"), 87 PINCTRL_PIN(PAD_GPIO25, "GPIO25"), 88 PINCTRL_PIN(PAD_GPIO26, "GPIO26"), 89 PINCTRL_PIN(PAD_GPIO27, "GPIO27"), 90 PINCTRL_PIN(PAD_GPIO28, "GPIO28"), 91 PINCTRL_PIN(PAD_GPIO29, "GPIO29"), 92 PINCTRL_PIN(PAD_GPIO30, "GPIO30"), 93 PINCTRL_PIN(PAD_GPIO31, "GPIO31"), 94 PINCTRL_PIN(PAD_GPIO32, "GPIO32"), 95 PINCTRL_PIN(PAD_GPIO33, "GPIO33"), 96 PINCTRL_PIN(PAD_GPIO34, "GPIO34"), 97 PINCTRL_PIN(PAD_GPIO35, "GPIO35"), 98 PINCTRL_PIN(PAD_GPIO36, "GPIO36"), 99 PINCTRL_PIN(PAD_GPIO37, "GPIO37"), 100 PINCTRL_PIN(PAD_GPIO38, "GPIO38"), 101 PINCTRL_PIN(PAD_GPIO39, "GPIO39"), 102 PINCTRL_PIN(PAD_GPIO40, "GPIO40"), 103 PINCTRL_PIN(PAD_GPIO41, "GPIO41"), 104 PINCTRL_PIN(PAD_GPIO42, "GPIO42"), 105 PINCTRL_PIN(PAD_GPIO43, "GPIO43"), 106 PINCTRL_PIN(PAD_GPIO44, "GPIO44"), 107 PINCTRL_PIN(PAD_GPIO45, "GPIO45"), 108 PINCTRL_PIN(PAD_GPIO46, "GPIO46"), 109 PINCTRL_PIN(PAD_GPIO47, "GPIO47"), 110 PINCTRL_PIN(PAD_GPIO48, "GPIO48"), 111 PINCTRL_PIN(PAD_GPIO49, "GPIO49"), 112 PINCTRL_PIN(PAD_GPIO50, "GPIO50"), 113 PINCTRL_PIN(PAD_GPIO51, "GPIO51"), 114 PINCTRL_PIN(PAD_GPIO52, "GPIO52"), 115 PINCTRL_PIN(PAD_GPIO53, "GPIO53"), 116 PINCTRL_PIN(PAD_GPIO54, "GPIO54"), 117 PINCTRL_PIN(PAD_GPIO55, "GPIO55"), 118 PINCTRL_PIN(PAD_GPIO56, "GPIO56"), 119 PINCTRL_PIN(PAD_GPIO57, "GPIO57"), 120 PINCTRL_PIN(PAD_GPIO58, "GPIO58"), 121 PINCTRL_PIN(PAD_GPIO59, "GPIO59"), 122 PINCTRL_PIN(PAD_GPIO60, "GPIO60"), 123 PINCTRL_PIN(PAD_GPIO61, "GPIO61"), 124 PINCTRL_PIN(PAD_GPIO62, "GPIO62"), 125 PINCTRL_PIN(PAD_GPIO63, "GPIO63"), 126 PINCTRL_PIN(PAD_SD0_CLK, "SD0_CLK"), 127 PINCTRL_PIN(PAD_SD0_CMD, "SD0_CMD"), 128 PINCTRL_PIN(PAD_SD0_DATA0, "SD0_DATA0"), 129 PINCTRL_PIN(PAD_SD0_DATA1, "SD0_DATA1"), 130 PINCTRL_PIN(PAD_SD0_DATA2, "SD0_DATA2"), 131 PINCTRL_PIN(PAD_SD0_DATA3, "SD0_DATA3"), 132 PINCTRL_PIN(PAD_SD0_DATA4, "SD0_DATA4"), 133 PINCTRL_PIN(PAD_SD0_DATA5, "SD0_DATA5"), 134 PINCTRL_PIN(PAD_SD0_DATA6, "SD0_DATA6"), 135 PINCTRL_PIN(PAD_SD0_DATA7, "SD0_DATA7"), 136 PINCTRL_PIN(PAD_SD0_STRB, "SD0_STRB"), 137 PINCTRL_PIN(PAD_GMAC1_MDC, "GMAC1_MDC"), 138 PINCTRL_PIN(PAD_GMAC1_MDIO, "GMAC1_MDIO"), 139 PINCTRL_PIN(PAD_GMAC1_RXD0, "GMAC1_RXD0"), 140 PINCTRL_PIN(PAD_GMAC1_RXD1, "GMAC1_RXD1"), 141 PINCTRL_PIN(PAD_GMAC1_RXD2, "GMAC1_RXD2"), 142 PINCTRL_PIN(PAD_GMAC1_RXD3, "GMAC1_RXD3"), 143 PINCTRL_PIN(PAD_GMAC1_RXDV, "GMAC1_RXDV"), 144 PINCTRL_PIN(PAD_GMAC1_RXC, "GMAC1_RXC"), 145 PINCTRL_PIN(PAD_GMAC1_TXD0, "GMAC1_TXD0"), 146 PINCTRL_PIN(PAD_GMAC1_TXD1, "GMAC1_TXD1"), 147 PINCTRL_PIN(PAD_GMAC1_TXD2, "GMAC1_TXD2"), 148 PINCTRL_PIN(PAD_GMAC1_TXD3, "GMAC1_TXD3"), 149 PINCTRL_PIN(PAD_GMAC1_TXEN, "GMAC1_TXEN"), 150 PINCTRL_PIN(PAD_GMAC1_TXC, "GMAC1_TXC"), 151 PINCTRL_PIN(PAD_QSPI_SCLK, "QSPI_SCLK"), 152 PINCTRL_PIN(PAD_QSPI_CS0, "QSPI_CS0"), 153 PINCTRL_PIN(PAD_QSPI_DATA0, "QSPI_DATA0"), 154 PINCTRL_PIN(PAD_QSPI_DATA1, "QSPI_DATA1"), 155 PINCTRL_PIN(PAD_QSPI_DATA2, "QSPI_DATA2"), 156 PINCTRL_PIN(PAD_QSPI_DATA3, "QSPI_DATA3"), 157 }; 158 159 struct jh7110_func_sel { 160 u16 offset; 161 u8 shift; 162 u8 max; 163 }; 164 165 static const struct jh7110_func_sel 166 jh7110_sys_func_sel[ARRAY_SIZE(jh7110_sys_pins)] = { 167 [PAD_GMAC1_RXC] = { 0x29c, 0, 1 }, 168 [PAD_GPIO10] = { 0x29c, 2, 3 }, 169 [PAD_GPIO11] = { 0x29c, 5, 3 }, 170 [PAD_GPIO12] = { 0x29c, 8, 3 }, 171 [PAD_GPIO13] = { 0x29c, 11, 3 }, 172 [PAD_GPIO14] = { 0x29c, 14, 3 }, 173 [PAD_GPIO15] = { 0x29c, 17, 3 }, 174 [PAD_GPIO16] = { 0x29c, 20, 3 }, 175 [PAD_GPIO17] = { 0x29c, 23, 3 }, 176 [PAD_GPIO18] = { 0x29c, 26, 3 }, 177 [PAD_GPIO19] = { 0x29c, 29, 3 }, 178 179 [PAD_GPIO20] = { 0x2a0, 0, 3 }, 180 [PAD_GPIO21] = { 0x2a0, 3, 3 }, 181 [PAD_GPIO22] = { 0x2a0, 6, 3 }, 182 [PAD_GPIO23] = { 0x2a0, 9, 3 }, 183 [PAD_GPIO24] = { 0x2a0, 12, 3 }, 184 [PAD_GPIO25] = { 0x2a0, 15, 3 }, 185 [PAD_GPIO26] = { 0x2a0, 18, 3 }, 186 [PAD_GPIO27] = { 0x2a0, 21, 3 }, 187 [PAD_GPIO28] = { 0x2a0, 24, 3 }, 188 [PAD_GPIO29] = { 0x2a0, 27, 3 }, 189 190 [PAD_GPIO30] = { 0x2a4, 0, 3 }, 191 [PAD_GPIO31] = { 0x2a4, 3, 3 }, 192 [PAD_GPIO32] = { 0x2a4, 6, 3 }, 193 [PAD_GPIO33] = { 0x2a4, 9, 3 }, 194 [PAD_GPIO34] = { 0x2a4, 12, 3 }, 195 [PAD_GPIO35] = { 0x2a4, 15, 3 }, 196 [PAD_GPIO36] = { 0x2a4, 17, 3 }, 197 [PAD_GPIO37] = { 0x2a4, 20, 3 }, 198 [PAD_GPIO38] = { 0x2a4, 23, 3 }, 199 [PAD_GPIO39] = { 0x2a4, 26, 3 }, 200 [PAD_GPIO40] = { 0x2a4, 29, 3 }, 201 202 [PAD_GPIO41] = { 0x2a8, 0, 3 }, 203 [PAD_GPIO42] = { 0x2a8, 3, 3 }, 204 [PAD_GPIO43] = { 0x2a8, 6, 3 }, 205 [PAD_GPIO44] = { 0x2a8, 9, 3 }, 206 [PAD_GPIO45] = { 0x2a8, 12, 3 }, 207 [PAD_GPIO46] = { 0x2a8, 15, 3 }, 208 [PAD_GPIO47] = { 0x2a8, 18, 3 }, 209 [PAD_GPIO48] = { 0x2a8, 21, 3 }, 210 [PAD_GPIO49] = { 0x2a8, 24, 3 }, 211 [PAD_GPIO50] = { 0x2a8, 27, 3 }, 212 [PAD_GPIO51] = { 0x2a8, 30, 3 }, 213 214 [PAD_GPIO52] = { 0x2ac, 0, 3 }, 215 [PAD_GPIO53] = { 0x2ac, 2, 3 }, 216 [PAD_GPIO54] = { 0x2ac, 4, 3 }, 217 [PAD_GPIO55] = { 0x2ac, 6, 3 }, 218 [PAD_GPIO56] = { 0x2ac, 9, 3 }, 219 [PAD_GPIO57] = { 0x2ac, 12, 3 }, 220 [PAD_GPIO58] = { 0x2ac, 15, 3 }, 221 [PAD_GPIO59] = { 0x2ac, 18, 3 }, 222 [PAD_GPIO60] = { 0x2ac, 21, 3 }, 223 [PAD_GPIO61] = { 0x2ac, 24, 3 }, 224 [PAD_GPIO62] = { 0x2ac, 27, 3 }, 225 [PAD_GPIO63] = { 0x2ac, 30, 3 }, 226 227 [PAD_GPIO6] = { 0x2b0, 0, 3 }, 228 [PAD_GPIO7] = { 0x2b0, 2, 3 }, 229 [PAD_GPIO8] = { 0x2b0, 5, 3 }, 230 [PAD_GPIO9] = { 0x2b0, 8, 3 }, 231 }; 232 233 struct jh7110_vin_group_sel { 234 u16 offset; 235 u8 shift; 236 u8 group; 237 }; 238 239 static const struct jh7110_vin_group_sel 240 jh7110_sys_vin_group_sel[ARRAY_SIZE(jh7110_sys_pins)] = { 241 [PAD_GPIO6] = { 0x2b4, 21, 0 }, 242 [PAD_GPIO7] = { 0x2b4, 18, 0 }, 243 [PAD_GPIO8] = { 0x2b4, 15, 0 }, 244 [PAD_GPIO9] = { 0x2b0, 11, 0 }, 245 [PAD_GPIO10] = { 0x2b0, 20, 0 }, 246 [PAD_GPIO11] = { 0x2b0, 23, 0 }, 247 [PAD_GPIO12] = { 0x2b0, 26, 0 }, 248 [PAD_GPIO13] = { 0x2b0, 29, 0 }, 249 [PAD_GPIO14] = { 0x2b4, 0, 0 }, 250 [PAD_GPIO15] = { 0x2b4, 3, 0 }, 251 [PAD_GPIO16] = { 0x2b4, 6, 0 }, 252 [PAD_GPIO17] = { 0x2b4, 9, 0 }, 253 [PAD_GPIO18] = { 0x2b4, 12, 0 }, 254 [PAD_GPIO19] = { 0x2b0, 14, 0 }, 255 [PAD_GPIO20] = { 0x2b0, 17, 0 }, 256 257 [PAD_GPIO21] = { 0x2b4, 21, 1 }, 258 [PAD_GPIO22] = { 0x2b4, 18, 1 }, 259 [PAD_GPIO23] = { 0x2b4, 15, 1 }, 260 [PAD_GPIO24] = { 0x2b0, 11, 1 }, 261 [PAD_GPIO25] = { 0x2b0, 20, 1 }, 262 [PAD_GPIO26] = { 0x2b0, 23, 1 }, 263 [PAD_GPIO27] = { 0x2b0, 26, 1 }, 264 [PAD_GPIO28] = { 0x2b0, 29, 1 }, 265 [PAD_GPIO29] = { 0x2b4, 0, 1 }, 266 [PAD_GPIO30] = { 0x2b4, 3, 1 }, 267 [PAD_GPIO31] = { 0x2b4, 6, 1 }, 268 [PAD_GPIO32] = { 0x2b4, 9, 1 }, 269 [PAD_GPIO33] = { 0x2b4, 12, 1 }, 270 [PAD_GPIO34] = { 0x2b0, 14, 1 }, 271 [PAD_GPIO35] = { 0x2b0, 17, 1 }, 272 273 [PAD_GPIO36] = { 0x2b4, 21, 2 }, 274 [PAD_GPIO37] = { 0x2b4, 18, 2 }, 275 [PAD_GPIO38] = { 0x2b4, 15, 2 }, 276 [PAD_GPIO39] = { 0x2b0, 11, 2 }, 277 [PAD_GPIO40] = { 0x2b0, 20, 2 }, 278 [PAD_GPIO41] = { 0x2b0, 23, 2 }, 279 [PAD_GPIO42] = { 0x2b0, 26, 2 }, 280 [PAD_GPIO43] = { 0x2b0, 29, 2 }, 281 [PAD_GPIO44] = { 0x2b4, 0, 2 }, 282 [PAD_GPIO45] = { 0x2b4, 3, 2 }, 283 [PAD_GPIO46] = { 0x2b4, 6, 2 }, 284 [PAD_GPIO47] = { 0x2b4, 9, 2 }, 285 [PAD_GPIO48] = { 0x2b4, 12, 2 }, 286 [PAD_GPIO49] = { 0x2b0, 14, 2 }, 287 [PAD_GPIO50] = { 0x2b0, 17, 2 }, 288 }; 289 290 static void jh7110_set_function(struct jh7110_pinctrl *sfp, 291 unsigned int pin, u32 func) 292 { 293 const struct jh7110_func_sel *fs = &jh7110_sys_func_sel[pin]; 294 unsigned long flags; 295 void __iomem *reg; 296 u32 mask; 297 298 if (!fs->offset) 299 return; 300 301 if (func > fs->max) 302 return; 303 304 reg = sfp->base + fs->offset; 305 func = func << fs->shift; 306 mask = 0x3U << fs->shift; 307 308 raw_spin_lock_irqsave(&sfp->lock, flags); 309 func |= readl_relaxed(reg) & ~mask; 310 writel_relaxed(func, reg); 311 raw_spin_unlock_irqrestore(&sfp->lock, flags); 312 } 313 314 static void jh7110_set_vin_group(struct jh7110_pinctrl *sfp, 315 unsigned int pin) 316 { 317 const struct jh7110_vin_group_sel *gs = &jh7110_sys_vin_group_sel[pin]; 318 unsigned long flags; 319 void __iomem *reg; 320 u32 mask; 321 u32 grp; 322 323 if (!gs->offset) 324 return; 325 326 reg = sfp->base + gs->offset; 327 grp = gs->group << gs->shift; 328 mask = 0x3U << gs->shift; 329 330 raw_spin_lock_irqsave(&sfp->lock, flags); 331 grp |= readl_relaxed(reg) & ~mask; 332 writel_relaxed(grp, reg); 333 raw_spin_unlock_irqrestore(&sfp->lock, flags); 334 } 335 336 static int jh7110_sys_set_one_pin_mux(struct jh7110_pinctrl *sfp, 337 unsigned int pin, 338 unsigned int din, u32 dout, 339 u32 doen, u32 func) 340 { 341 if (pin < sfp->gc.ngpio && func == 0) 342 jh7110_set_gpiomux(sfp, pin, din, dout, doen); 343 344 jh7110_set_function(sfp, pin, func); 345 346 if (pin < sfp->gc.ngpio && func == 2) 347 jh7110_set_vin_group(sfp, pin); 348 349 return 0; 350 } 351 352 static int jh7110_sys_get_padcfg_base(struct jh7110_pinctrl *sfp, 353 unsigned int pin) 354 { 355 if (pin < PAD_GMAC1_MDC) 356 return JH7110_SYS_GPO_PDA_0_74_CFG; 357 else if (pin > PAD_GMAC1_TXC && pin <= PAD_QSPI_DATA3) 358 return JH7110_SYS_GPO_PDA_89_94_CFG; 359 else 360 return -1; 361 } 362 363 static void jh7110_sys_irq_handler(struct irq_desc *desc) 364 { 365 struct jh7110_pinctrl *sfp = jh7110_from_irq_desc(desc); 366 struct irq_chip *chip = irq_desc_get_chip(desc); 367 unsigned long mis; 368 unsigned int pin; 369 370 chained_irq_enter(chip, desc); 371 372 mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS0); 373 for_each_set_bit(pin, &mis, 32) 374 generic_handle_domain_irq(sfp->gc.irq.domain, pin); 375 376 mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS1); 377 for_each_set_bit(pin, &mis, 32) 378 generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32); 379 380 chained_irq_exit(chip, desc); 381 } 382 383 static int jh7110_sys_init_hw(struct gpio_chip *gc) 384 { 385 struct jh7110_pinctrl *sfp = container_of(gc, 386 struct jh7110_pinctrl, gc); 387 388 /* mask all GPIO interrupts */ 389 writel(0U, sfp->base + JH7110_SYS_GPIOIE0); 390 writel(0U, sfp->base + JH7110_SYS_GPIOIE1); 391 /* clear edge interrupt flags */ 392 writel(~0U, sfp->base + JH7110_SYS_GPIOIC0); 393 writel(~0U, sfp->base + JH7110_SYS_GPIOIC1); 394 /* enable GPIO interrupts */ 395 writel(1U, sfp->base + JH7110_SYS_GPIOEN); 396 return 0; 397 } 398 399 static const struct jh7110_gpio_irq_reg jh7110_sys_irq_reg = { 400 .is_reg_base = JH7110_SYS_GPIOIS0, 401 .ic_reg_base = JH7110_SYS_GPIOIC0, 402 .ibe_reg_base = JH7110_SYS_GPIOIBE0, 403 .iev_reg_base = JH7110_SYS_GPIOIEV0, 404 .ie_reg_base = JH7110_SYS_GPIOIE0, 405 .ris_reg_base = JH7110_SYS_GPIORIS0, 406 .mis_reg_base = JH7110_SYS_GPIOMIS0, 407 }; 408 409 static const struct jh7110_pinctrl_soc_info jh7110_sys_pinctrl_info = { 410 .pins = jh7110_sys_pins, 411 .npins = ARRAY_SIZE(jh7110_sys_pins), 412 .ngpios = JH7110_SYS_NGPIO, 413 .gc_base = JH7110_SYS_GC_BASE, 414 .dout_reg_base = JH7110_SYS_DOUT, 415 .dout_mask = GENMASK(6, 0), 416 .doen_reg_base = JH7110_SYS_DOEN, 417 .doen_mask = GENMASK(5, 0), 418 .gpi_reg_base = JH7110_SYS_GPI, 419 .gpi_mask = GENMASK(6, 0), 420 .gpioin_reg_base = JH7110_SYS_GPIOIN, 421 .irq_reg = &jh7110_sys_irq_reg, 422 .nsaved_regs = JH7110_SYS_REGS_NUM, 423 .jh7110_set_one_pin_mux = jh7110_sys_set_one_pin_mux, 424 .jh7110_get_padcfg_base = jh7110_sys_get_padcfg_base, 425 .jh7110_gpio_irq_handler = jh7110_sys_irq_handler, 426 .jh7110_gpio_init_hw = jh7110_sys_init_hw, 427 }; 428 429 static const struct of_device_id jh7110_sys_pinctrl_of_match[] = { 430 { 431 .compatible = "starfive,jh7110-sys-pinctrl", 432 .data = &jh7110_sys_pinctrl_info, 433 }, 434 { /* sentinel */ } 435 }; 436 MODULE_DEVICE_TABLE(of, jh7110_sys_pinctrl_of_match); 437 438 static struct platform_driver jh7110_sys_pinctrl_driver = { 439 .probe = jh7110_pinctrl_probe, 440 .driver = { 441 .name = "starfive-jh7110-sys-pinctrl", 442 .of_match_table = jh7110_sys_pinctrl_of_match, 443 .pm = pm_sleep_ptr(&jh7110_pinctrl_pm_ops), 444 }, 445 }; 446 module_platform_driver(jh7110_sys_pinctrl_driver); 447 448 MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC sys controller"); 449 MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>"); 450 MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>"); 451 MODULE_LICENSE("GPL"); 452