1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pinctrl / GPIO driver for StarFive JH7110 SoC sys controller 4 * 5 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 6 * Copyright (C) 2022 StarFive Technology Co., Ltd. 7 */ 8 9 #include <linux/bits.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/io.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/spinlock.h> 16 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinmux.h> 19 20 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h> 21 22 #include "../core.h" 23 #include "../pinctrl-utils.h" 24 #include "../pinmux.h" 25 #include "../pinconf.h" 26 #include "pinctrl-starfive-jh7110.h" 27 28 #define JH7110_SYS_NGPIO 64 29 30 #define JH7110_SYS_REGS_NUM 174 31 32 /* registers */ 33 #define JH7110_SYS_DOEN 0x000 34 #define JH7110_SYS_DOUT 0x040 35 #define JH7110_SYS_GPI 0x080 36 #define JH7110_SYS_GPIOIN 0x118 37 38 #define JH7110_SYS_GPIOEN 0x0dc 39 #define JH7110_SYS_GPIOIS0 0x0e0 40 #define JH7110_SYS_GPIOIS1 0x0e4 41 #define JH7110_SYS_GPIOIC0 0x0e8 42 #define JH7110_SYS_GPIOIC1 0x0ec 43 #define JH7110_SYS_GPIOIBE0 0x0f0 44 #define JH7110_SYS_GPIOIBE1 0x0f4 45 #define JH7110_SYS_GPIOIEV0 0x0f8 46 #define JH7110_SYS_GPIOIEV1 0x0fc 47 #define JH7110_SYS_GPIOIE0 0x100 48 #define JH7110_SYS_GPIOIE1 0x104 49 #define JH7110_SYS_GPIORIS0 0x108 50 #define JH7110_SYS_GPIORIS1 0x10c 51 #define JH7110_SYS_GPIOMIS0 0x110 52 #define JH7110_SYS_GPIOMIS1 0x114 53 54 #define JH7110_SYS_GPO_PDA_0_74_CFG 0x120 55 #define JH7110_SYS_GPO_PDA_89_94_CFG 0x284 56 57 static const struct pinctrl_pin_desc jh7110_sys_pins[] = { 58 PINCTRL_PIN(PAD_GPIO0, "GPIO0"), 59 PINCTRL_PIN(PAD_GPIO1, "GPIO1"), 60 PINCTRL_PIN(PAD_GPIO2, "GPIO2"), 61 PINCTRL_PIN(PAD_GPIO3, "GPIO3"), 62 PINCTRL_PIN(PAD_GPIO4, "GPIO4"), 63 PINCTRL_PIN(PAD_GPIO5, "GPIO5"), 64 PINCTRL_PIN(PAD_GPIO6, "GPIO6"), 65 PINCTRL_PIN(PAD_GPIO7, "GPIO7"), 66 PINCTRL_PIN(PAD_GPIO8, "GPIO8"), 67 PINCTRL_PIN(PAD_GPIO9, "GPIO9"), 68 PINCTRL_PIN(PAD_GPIO10, "GPIO10"), 69 PINCTRL_PIN(PAD_GPIO11, "GPIO11"), 70 PINCTRL_PIN(PAD_GPIO12, "GPIO12"), 71 PINCTRL_PIN(PAD_GPIO13, "GPIO13"), 72 PINCTRL_PIN(PAD_GPIO14, "GPIO14"), 73 PINCTRL_PIN(PAD_GPIO15, "GPIO15"), 74 PINCTRL_PIN(PAD_GPIO16, "GPIO16"), 75 PINCTRL_PIN(PAD_GPIO17, "GPIO17"), 76 PINCTRL_PIN(PAD_GPIO18, "GPIO18"), 77 PINCTRL_PIN(PAD_GPIO19, "GPIO19"), 78 PINCTRL_PIN(PAD_GPIO20, "GPIO20"), 79 PINCTRL_PIN(PAD_GPIO21, "GPIO21"), 80 PINCTRL_PIN(PAD_GPIO22, "GPIO22"), 81 PINCTRL_PIN(PAD_GPIO23, "GPIO23"), 82 PINCTRL_PIN(PAD_GPIO24, "GPIO24"), 83 PINCTRL_PIN(PAD_GPIO25, "GPIO25"), 84 PINCTRL_PIN(PAD_GPIO26, "GPIO26"), 85 PINCTRL_PIN(PAD_GPIO27, "GPIO27"), 86 PINCTRL_PIN(PAD_GPIO28, "GPIO28"), 87 PINCTRL_PIN(PAD_GPIO29, "GPIO29"), 88 PINCTRL_PIN(PAD_GPIO30, "GPIO30"), 89 PINCTRL_PIN(PAD_GPIO31, "GPIO31"), 90 PINCTRL_PIN(PAD_GPIO32, "GPIO32"), 91 PINCTRL_PIN(PAD_GPIO33, "GPIO33"), 92 PINCTRL_PIN(PAD_GPIO34, "GPIO34"), 93 PINCTRL_PIN(PAD_GPIO35, "GPIO35"), 94 PINCTRL_PIN(PAD_GPIO36, "GPIO36"), 95 PINCTRL_PIN(PAD_GPIO37, "GPIO37"), 96 PINCTRL_PIN(PAD_GPIO38, "GPIO38"), 97 PINCTRL_PIN(PAD_GPIO39, "GPIO39"), 98 PINCTRL_PIN(PAD_GPIO40, "GPIO40"), 99 PINCTRL_PIN(PAD_GPIO41, "GPIO41"), 100 PINCTRL_PIN(PAD_GPIO42, "GPIO42"), 101 PINCTRL_PIN(PAD_GPIO43, "GPIO43"), 102 PINCTRL_PIN(PAD_GPIO44, "GPIO44"), 103 PINCTRL_PIN(PAD_GPIO45, "GPIO45"), 104 PINCTRL_PIN(PAD_GPIO46, "GPIO46"), 105 PINCTRL_PIN(PAD_GPIO47, "GPIO47"), 106 PINCTRL_PIN(PAD_GPIO48, "GPIO48"), 107 PINCTRL_PIN(PAD_GPIO49, "GPIO49"), 108 PINCTRL_PIN(PAD_GPIO50, "GPIO50"), 109 PINCTRL_PIN(PAD_GPIO51, "GPIO51"), 110 PINCTRL_PIN(PAD_GPIO52, "GPIO52"), 111 PINCTRL_PIN(PAD_GPIO53, "GPIO53"), 112 PINCTRL_PIN(PAD_GPIO54, "GPIO54"), 113 PINCTRL_PIN(PAD_GPIO55, "GPIO55"), 114 PINCTRL_PIN(PAD_GPIO56, "GPIO56"), 115 PINCTRL_PIN(PAD_GPIO57, "GPIO57"), 116 PINCTRL_PIN(PAD_GPIO58, "GPIO58"), 117 PINCTRL_PIN(PAD_GPIO59, "GPIO59"), 118 PINCTRL_PIN(PAD_GPIO60, "GPIO60"), 119 PINCTRL_PIN(PAD_GPIO61, "GPIO61"), 120 PINCTRL_PIN(PAD_GPIO62, "GPIO62"), 121 PINCTRL_PIN(PAD_GPIO63, "GPIO63"), 122 PINCTRL_PIN(PAD_SD0_CLK, "SD0_CLK"), 123 PINCTRL_PIN(PAD_SD0_CMD, "SD0_CMD"), 124 PINCTRL_PIN(PAD_SD0_DATA0, "SD0_DATA0"), 125 PINCTRL_PIN(PAD_SD0_DATA1, "SD0_DATA1"), 126 PINCTRL_PIN(PAD_SD0_DATA2, "SD0_DATA2"), 127 PINCTRL_PIN(PAD_SD0_DATA3, "SD0_DATA3"), 128 PINCTRL_PIN(PAD_SD0_DATA4, "SD0_DATA4"), 129 PINCTRL_PIN(PAD_SD0_DATA5, "SD0_DATA5"), 130 PINCTRL_PIN(PAD_SD0_DATA6, "SD0_DATA6"), 131 PINCTRL_PIN(PAD_SD0_DATA7, "SD0_DATA7"), 132 PINCTRL_PIN(PAD_SD0_STRB, "SD0_STRB"), 133 PINCTRL_PIN(PAD_GMAC1_MDC, "GMAC1_MDC"), 134 PINCTRL_PIN(PAD_GMAC1_MDIO, "GMAC1_MDIO"), 135 PINCTRL_PIN(PAD_GMAC1_RXD0, "GMAC1_RXD0"), 136 PINCTRL_PIN(PAD_GMAC1_RXD1, "GMAC1_RXD1"), 137 PINCTRL_PIN(PAD_GMAC1_RXD2, "GMAC1_RXD2"), 138 PINCTRL_PIN(PAD_GMAC1_RXD3, "GMAC1_RXD3"), 139 PINCTRL_PIN(PAD_GMAC1_RXDV, "GMAC1_RXDV"), 140 PINCTRL_PIN(PAD_GMAC1_RXC, "GMAC1_RXC"), 141 PINCTRL_PIN(PAD_GMAC1_TXD0, "GMAC1_TXD0"), 142 PINCTRL_PIN(PAD_GMAC1_TXD1, "GMAC1_TXD1"), 143 PINCTRL_PIN(PAD_GMAC1_TXD2, "GMAC1_TXD2"), 144 PINCTRL_PIN(PAD_GMAC1_TXD3, "GMAC1_TXD3"), 145 PINCTRL_PIN(PAD_GMAC1_TXEN, "GMAC1_TXEN"), 146 PINCTRL_PIN(PAD_GMAC1_TXC, "GMAC1_TXC"), 147 PINCTRL_PIN(PAD_QSPI_SCLK, "QSPI_SCLK"), 148 PINCTRL_PIN(PAD_QSPI_CS0, "QSPI_CS0"), 149 PINCTRL_PIN(PAD_QSPI_DATA0, "QSPI_DATA0"), 150 PINCTRL_PIN(PAD_QSPI_DATA1, "QSPI_DATA1"), 151 PINCTRL_PIN(PAD_QSPI_DATA2, "QSPI_DATA2"), 152 PINCTRL_PIN(PAD_QSPI_DATA3, "QSPI_DATA3"), 153 }; 154 155 struct jh7110_func_sel { 156 u16 offset; 157 u8 shift; 158 u8 max; 159 }; 160 161 static const struct jh7110_func_sel 162 jh7110_sys_func_sel[ARRAY_SIZE(jh7110_sys_pins)] = { 163 [PAD_GMAC1_RXC] = { 0x29c, 0, 1 }, 164 [PAD_GPIO10] = { 0x29c, 2, 3 }, 165 [PAD_GPIO11] = { 0x29c, 5, 3 }, 166 [PAD_GPIO12] = { 0x29c, 8, 3 }, 167 [PAD_GPIO13] = { 0x29c, 11, 3 }, 168 [PAD_GPIO14] = { 0x29c, 14, 3 }, 169 [PAD_GPIO15] = { 0x29c, 17, 3 }, 170 [PAD_GPIO16] = { 0x29c, 20, 3 }, 171 [PAD_GPIO17] = { 0x29c, 23, 3 }, 172 [PAD_GPIO18] = { 0x29c, 26, 3 }, 173 [PAD_GPIO19] = { 0x29c, 29, 3 }, 174 175 [PAD_GPIO20] = { 0x2a0, 0, 3 }, 176 [PAD_GPIO21] = { 0x2a0, 3, 3 }, 177 [PAD_GPIO22] = { 0x2a0, 6, 3 }, 178 [PAD_GPIO23] = { 0x2a0, 9, 3 }, 179 [PAD_GPIO24] = { 0x2a0, 12, 3 }, 180 [PAD_GPIO25] = { 0x2a0, 15, 3 }, 181 [PAD_GPIO26] = { 0x2a0, 18, 3 }, 182 [PAD_GPIO27] = { 0x2a0, 21, 3 }, 183 [PAD_GPIO28] = { 0x2a0, 24, 3 }, 184 [PAD_GPIO29] = { 0x2a0, 27, 3 }, 185 186 [PAD_GPIO30] = { 0x2a4, 0, 3 }, 187 [PAD_GPIO31] = { 0x2a4, 3, 3 }, 188 [PAD_GPIO32] = { 0x2a4, 6, 3 }, 189 [PAD_GPIO33] = { 0x2a4, 9, 3 }, 190 [PAD_GPIO34] = { 0x2a4, 12, 3 }, 191 [PAD_GPIO35] = { 0x2a4, 15, 3 }, 192 [PAD_GPIO36] = { 0x2a4, 17, 3 }, 193 [PAD_GPIO37] = { 0x2a4, 20, 3 }, 194 [PAD_GPIO38] = { 0x2a4, 23, 3 }, 195 [PAD_GPIO39] = { 0x2a4, 26, 3 }, 196 [PAD_GPIO40] = { 0x2a4, 29, 3 }, 197 198 [PAD_GPIO41] = { 0x2a8, 0, 3 }, 199 [PAD_GPIO42] = { 0x2a8, 3, 3 }, 200 [PAD_GPIO43] = { 0x2a8, 6, 3 }, 201 [PAD_GPIO44] = { 0x2a8, 9, 3 }, 202 [PAD_GPIO45] = { 0x2a8, 12, 3 }, 203 [PAD_GPIO46] = { 0x2a8, 15, 3 }, 204 [PAD_GPIO47] = { 0x2a8, 18, 3 }, 205 [PAD_GPIO48] = { 0x2a8, 21, 3 }, 206 [PAD_GPIO49] = { 0x2a8, 24, 3 }, 207 [PAD_GPIO50] = { 0x2a8, 27, 3 }, 208 [PAD_GPIO51] = { 0x2a8, 30, 3 }, 209 210 [PAD_GPIO52] = { 0x2ac, 0, 3 }, 211 [PAD_GPIO53] = { 0x2ac, 2, 3 }, 212 [PAD_GPIO54] = { 0x2ac, 4, 3 }, 213 [PAD_GPIO55] = { 0x2ac, 6, 3 }, 214 [PAD_GPIO56] = { 0x2ac, 9, 3 }, 215 [PAD_GPIO57] = { 0x2ac, 12, 3 }, 216 [PAD_GPIO58] = { 0x2ac, 15, 3 }, 217 [PAD_GPIO59] = { 0x2ac, 18, 3 }, 218 [PAD_GPIO60] = { 0x2ac, 21, 3 }, 219 [PAD_GPIO61] = { 0x2ac, 24, 3 }, 220 [PAD_GPIO62] = { 0x2ac, 27, 3 }, 221 [PAD_GPIO63] = { 0x2ac, 30, 3 }, 222 223 [PAD_GPIO6] = { 0x2b0, 0, 3 }, 224 [PAD_GPIO7] = { 0x2b0, 2, 3 }, 225 [PAD_GPIO8] = { 0x2b0, 5, 3 }, 226 [PAD_GPIO9] = { 0x2b0, 8, 3 }, 227 }; 228 229 struct jh7110_vin_group_sel { 230 u16 offset; 231 u8 shift; 232 u8 group; 233 }; 234 235 static const struct jh7110_vin_group_sel 236 jh7110_sys_vin_group_sel[ARRAY_SIZE(jh7110_sys_pins)] = { 237 [PAD_GPIO6] = { 0x2b4, 21, 0 }, 238 [PAD_GPIO7] = { 0x2b4, 18, 0 }, 239 [PAD_GPIO8] = { 0x2b4, 15, 0 }, 240 [PAD_GPIO9] = { 0x2b0, 11, 0 }, 241 [PAD_GPIO10] = { 0x2b0, 20, 0 }, 242 [PAD_GPIO11] = { 0x2b0, 23, 0 }, 243 [PAD_GPIO12] = { 0x2b0, 26, 0 }, 244 [PAD_GPIO13] = { 0x2b0, 29, 0 }, 245 [PAD_GPIO14] = { 0x2b4, 0, 0 }, 246 [PAD_GPIO15] = { 0x2b4, 3, 0 }, 247 [PAD_GPIO16] = { 0x2b4, 6, 0 }, 248 [PAD_GPIO17] = { 0x2b4, 9, 0 }, 249 [PAD_GPIO18] = { 0x2b4, 12, 0 }, 250 [PAD_GPIO19] = { 0x2b0, 14, 0 }, 251 [PAD_GPIO20] = { 0x2b0, 17, 0 }, 252 253 [PAD_GPIO21] = { 0x2b4, 21, 1 }, 254 [PAD_GPIO22] = { 0x2b4, 18, 1 }, 255 [PAD_GPIO23] = { 0x2b4, 15, 1 }, 256 [PAD_GPIO24] = { 0x2b0, 11, 1 }, 257 [PAD_GPIO25] = { 0x2b0, 20, 1 }, 258 [PAD_GPIO26] = { 0x2b0, 23, 1 }, 259 [PAD_GPIO27] = { 0x2b0, 26, 1 }, 260 [PAD_GPIO28] = { 0x2b0, 29, 1 }, 261 [PAD_GPIO29] = { 0x2b4, 0, 1 }, 262 [PAD_GPIO30] = { 0x2b4, 3, 1 }, 263 [PAD_GPIO31] = { 0x2b4, 6, 1 }, 264 [PAD_GPIO32] = { 0x2b4, 9, 1 }, 265 [PAD_GPIO33] = { 0x2b4, 12, 1 }, 266 [PAD_GPIO34] = { 0x2b0, 14, 1 }, 267 [PAD_GPIO35] = { 0x2b0, 17, 1 }, 268 269 [PAD_GPIO36] = { 0x2b4, 21, 2 }, 270 [PAD_GPIO37] = { 0x2b4, 18, 2 }, 271 [PAD_GPIO38] = { 0x2b4, 15, 2 }, 272 [PAD_GPIO39] = { 0x2b0, 11, 2 }, 273 [PAD_GPIO40] = { 0x2b0, 20, 2 }, 274 [PAD_GPIO41] = { 0x2b0, 23, 2 }, 275 [PAD_GPIO42] = { 0x2b0, 26, 2 }, 276 [PAD_GPIO43] = { 0x2b0, 29, 2 }, 277 [PAD_GPIO44] = { 0x2b4, 0, 2 }, 278 [PAD_GPIO45] = { 0x2b4, 3, 2 }, 279 [PAD_GPIO46] = { 0x2b4, 6, 2 }, 280 [PAD_GPIO47] = { 0x2b4, 9, 2 }, 281 [PAD_GPIO48] = { 0x2b4, 12, 2 }, 282 [PAD_GPIO49] = { 0x2b0, 14, 2 }, 283 [PAD_GPIO50] = { 0x2b0, 17, 2 }, 284 }; 285 286 static void jh7110_set_function(struct jh7110_pinctrl *sfp, 287 unsigned int pin, u32 func) 288 { 289 const struct jh7110_func_sel *fs = &jh7110_sys_func_sel[pin]; 290 unsigned long flags; 291 void __iomem *reg; 292 u32 mask; 293 294 if (!fs->offset) 295 return; 296 297 if (func > fs->max) 298 return; 299 300 reg = sfp->base + fs->offset; 301 func = func << fs->shift; 302 mask = 0x3U << fs->shift; 303 304 raw_spin_lock_irqsave(&sfp->lock, flags); 305 func |= readl_relaxed(reg) & ~mask; 306 writel_relaxed(func, reg); 307 raw_spin_unlock_irqrestore(&sfp->lock, flags); 308 } 309 310 static void jh7110_set_vin_group(struct jh7110_pinctrl *sfp, 311 unsigned int pin) 312 { 313 const struct jh7110_vin_group_sel *gs = &jh7110_sys_vin_group_sel[pin]; 314 unsigned long flags; 315 void __iomem *reg; 316 u32 mask; 317 u32 grp; 318 319 if (!gs->offset) 320 return; 321 322 reg = sfp->base + gs->offset; 323 grp = gs->group << gs->shift; 324 mask = 0x3U << gs->shift; 325 326 raw_spin_lock_irqsave(&sfp->lock, flags); 327 grp |= readl_relaxed(reg) & ~mask; 328 writel_relaxed(grp, reg); 329 raw_spin_unlock_irqrestore(&sfp->lock, flags); 330 } 331 332 static int jh7110_sys_set_one_pin_mux(struct jh7110_pinctrl *sfp, 333 unsigned int pin, 334 unsigned int din, u32 dout, 335 u32 doen, u32 func) 336 { 337 if (pin < sfp->gc.ngpio && func == 0) 338 jh7110_set_gpiomux(sfp, pin, din, dout, doen); 339 340 jh7110_set_function(sfp, pin, func); 341 342 if (pin < sfp->gc.ngpio && func == 2) 343 jh7110_set_vin_group(sfp, pin); 344 345 return 0; 346 } 347 348 static int jh7110_sys_get_padcfg_base(struct jh7110_pinctrl *sfp, 349 unsigned int pin) 350 { 351 if (pin < PAD_GMAC1_MDC) 352 return JH7110_SYS_GPO_PDA_0_74_CFG; 353 else if (pin > PAD_GMAC1_TXC && pin <= PAD_QSPI_DATA3) 354 return JH7110_SYS_GPO_PDA_89_94_CFG; 355 else 356 return -1; 357 } 358 359 static void jh7110_sys_irq_handler(struct irq_desc *desc) 360 { 361 struct jh7110_pinctrl *sfp = jh7110_from_irq_desc(desc); 362 struct irq_chip *chip = irq_desc_get_chip(desc); 363 unsigned long mis; 364 unsigned int pin; 365 366 chained_irq_enter(chip, desc); 367 368 mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS0); 369 for_each_set_bit(pin, &mis, 32) 370 generic_handle_domain_irq(sfp->gc.irq.domain, pin); 371 372 mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS1); 373 for_each_set_bit(pin, &mis, 32) 374 generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32); 375 376 chained_irq_exit(chip, desc); 377 } 378 379 static int jh7110_sys_init_hw(struct gpio_chip *gc) 380 { 381 struct jh7110_pinctrl *sfp = container_of(gc, 382 struct jh7110_pinctrl, gc); 383 384 /* mask all GPIO interrupts */ 385 writel(0U, sfp->base + JH7110_SYS_GPIOIE0); 386 writel(0U, sfp->base + JH7110_SYS_GPIOIE1); 387 /* clear edge interrupt flags */ 388 writel(~0U, sfp->base + JH7110_SYS_GPIOIC0); 389 writel(~0U, sfp->base + JH7110_SYS_GPIOIC1); 390 /* enable GPIO interrupts */ 391 writel(1U, sfp->base + JH7110_SYS_GPIOEN); 392 return 0; 393 } 394 395 static const struct jh7110_gpio_irq_reg jh7110_sys_irq_reg = { 396 .is_reg_base = JH7110_SYS_GPIOIS0, 397 .ic_reg_base = JH7110_SYS_GPIOIC0, 398 .ibe_reg_base = JH7110_SYS_GPIOIBE0, 399 .iev_reg_base = JH7110_SYS_GPIOIEV0, 400 .ie_reg_base = JH7110_SYS_GPIOIE0, 401 .ris_reg_base = JH7110_SYS_GPIORIS0, 402 .mis_reg_base = JH7110_SYS_GPIOMIS0, 403 }; 404 405 static const struct jh7110_pinctrl_soc_info jh7110_sys_pinctrl_info = { 406 .pins = jh7110_sys_pins, 407 .npins = ARRAY_SIZE(jh7110_sys_pins), 408 .ngpios = JH7110_SYS_NGPIO, 409 .dout_reg_base = JH7110_SYS_DOUT, 410 .dout_mask = GENMASK(6, 0), 411 .doen_reg_base = JH7110_SYS_DOEN, 412 .doen_mask = GENMASK(5, 0), 413 .gpi_reg_base = JH7110_SYS_GPI, 414 .gpi_mask = GENMASK(6, 0), 415 .gpioin_reg_base = JH7110_SYS_GPIOIN, 416 .irq_reg = &jh7110_sys_irq_reg, 417 .nsaved_regs = JH7110_SYS_REGS_NUM, 418 .jh7110_set_one_pin_mux = jh7110_sys_set_one_pin_mux, 419 .jh7110_get_padcfg_base = jh7110_sys_get_padcfg_base, 420 .jh7110_gpio_irq_handler = jh7110_sys_irq_handler, 421 .jh7110_gpio_init_hw = jh7110_sys_init_hw, 422 }; 423 424 static const struct of_device_id jh7110_sys_pinctrl_of_match[] = { 425 { 426 .compatible = "starfive,jh7110-sys-pinctrl", 427 .data = &jh7110_sys_pinctrl_info, 428 }, 429 { /* sentinel */ } 430 }; 431 MODULE_DEVICE_TABLE(of, jh7110_sys_pinctrl_of_match); 432 433 static struct platform_driver jh7110_sys_pinctrl_driver = { 434 .probe = jh7110_pinctrl_probe, 435 .driver = { 436 .name = "starfive-jh7110-sys-pinctrl", 437 .of_match_table = jh7110_sys_pinctrl_of_match, 438 .pm = pm_sleep_ptr(&jh7110_pinctrl_pm_ops), 439 }, 440 }; 441 module_platform_driver(jh7110_sys_pinctrl_driver); 442 443 MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC sys controller"); 444 MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>"); 445 MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>"); 446 MODULE_LICENSE("GPL"); 447