1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2024 Yixun Lan <dlan@gentoo.org> */ 3 4 #include <linux/bits.h> 5 #include <linux/clk.h> 6 #include <linux/cleanup.h> 7 #include <linux/io.h> 8 #include <linux/of.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 #include <linux/seq_file.h> 12 #include <linux/spinlock.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 17 #include <linux/pinctrl/pinconf-generic.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinctrl.h> 20 #include <linux/pinctrl/pinmux.h> 21 22 #include "../core.h" 23 #include "../pinctrl-utils.h" 24 #include "../pinconf.h" 25 #include "../pinmux.h" 26 #include "pinctrl-k1.h" 27 28 /* 29 * | pull | drive | schmitter | slew | edge | strong | mux | 30 * SoC | up/down | strength | trigger | rate | detect | pull | mode | 31 *-----+---------+----------+-----------+-------+--------+--------+--------+ 32 * K1 | 3 bits | 3 bits | 2 bits | 1 bit | 3 bits | 1 bit | 3 bits | 33 *-----+---------+----------+-----------+-------+--------+--------+--------+ 34 * K3 | 3 bits | 4 bits | 1 bits | 1 bit | 3 bits | 1 bit | 3 bits | 35 */ 36 37 #define PAD_MUX GENMASK(2, 0) 38 #define PAD_STRONG_PULL BIT(3) 39 #define PAD_EDGE_RISE BIT(4) 40 #define PAD_EDGE_FALL BIT(5) 41 #define PAD_EDGE_CLEAR BIT(6) 42 #define PAD_SLEW_RATE GENMASK(12, 11) 43 #define PAD_SLEW_RATE_EN BIT(7) 44 #define PAD_SCHMITT_K1 GENMASK(9, 8) 45 #define PAD_DRIVE_K1 GENMASK(12, 10) 46 #define PAD_SCHMITT_K3 BIT(8) 47 #define PAD_DRIVE_K3 GENMASK(12, 9) 48 #define PAD_PULLDOWN BIT(13) 49 #define PAD_PULLUP BIT(14) 50 #define PAD_PULL_EN BIT(15) 51 52 #define IO_PWR_DOMAIN_OFFSET 0x800 53 54 #define IO_PWR_DOMAIN_GPIO2_Kx 0x0c 55 #define IO_PWR_DOMAIN_MMC_Kx 0x1c 56 57 #define IO_PWR_DOMAIN_GPIO3_K1 0x10 58 #define IO_PWR_DOMAIN_QSPI_K1 0x20 59 60 #define IO_PWR_DOMAIN_GPIO1_K3 0x04 61 #define IO_PWR_DOMAIN_GPIO5_K3 0x10 62 #define IO_PWR_DOMAIN_GPIO4_K3 0x20 63 #define IO_PWR_DOMAIN_QSPI_K3 0x2c 64 65 #define IO_PWR_DOMAIN_V18EN BIT(2) 66 67 #define APBC_ASFAR 0x50 68 #define APBC_ASSAR 0x54 69 70 #define APBC_ASFAR_AKEY 0xbaba 71 #define APBC_ASSAR_AKEY 0xeb10 72 73 struct spacemit_pin_drv_strength { 74 u8 val; 75 u32 mA; 76 }; 77 78 struct spacemit_pinctrl_dconf { 79 u64 schmitt_mask; 80 u64 drive_mask; 81 82 struct spacemit_pin_drv_strength *ds_1v8_tbl; 83 size_t ds_1v8_tbl_num; 84 struct spacemit_pin_drv_strength *ds_3v3_tbl; 85 size_t ds_3v3_tbl_num; 86 }; 87 88 struct spacemit_pin { 89 u16 pin; 90 u16 flags; 91 u8 gpiofunc; 92 }; 93 94 struct spacemit_pinctrl { 95 struct device *dev; 96 struct pinctrl_dev *pctl_dev; 97 const struct spacemit_pinctrl_data *data; 98 struct pinctrl_desc pdesc; 99 100 struct mutex mutex; 101 raw_spinlock_t lock; 102 103 void __iomem *regs; 104 105 struct regmap *regmap_apbc; 106 }; 107 108 struct spacemit_pinctrl_data { 109 const struct pinctrl_pin_desc *pins; 110 const struct spacemit_pin *data; 111 u16 npins; 112 unsigned int (*pin_to_offset)(unsigned int pin); 113 unsigned int (*pin_to_io_pd_offset)(unsigned int pin); 114 const struct spacemit_pinctrl_dconf *dconf; 115 }; 116 117 struct spacemit_pin_mux_config { 118 const struct spacemit_pin *pin; 119 u32 config; 120 }; 121 122 /* map pin id to pinctrl register offset, refer MFPR definition */ 123 static unsigned int spacemit_k1_pin_to_offset(unsigned int pin) 124 { 125 unsigned int offset = 0; 126 127 switch (pin) { 128 case 0 ... 85: 129 offset = pin + 1; 130 break; 131 case 86 ... 92: 132 offset = pin + 37; 133 break; 134 case 93 ... 97: 135 offset = pin + 24; 136 break; 137 case 98: 138 offset = 93; 139 break; 140 case 99: 141 offset = 92; 142 break; 143 case 100: 144 offset = 91; 145 break; 146 case 101: 147 offset = 90; 148 break; 149 case 102: 150 offset = 95; 151 break; 152 case 103: 153 offset = 94; 154 break; 155 case 104 ... 110: 156 offset = pin + 6; 157 break; 158 case 111 ... 127: 159 offset = pin + 20; 160 break; 161 default: 162 break; 163 } 164 165 return offset << 2; 166 } 167 168 static unsigned int spacemit_k3_pin_to_offset(unsigned int pin) 169 { 170 unsigned int offset = pin > 130 ? (pin + 2) : pin; 171 172 return offset << 2; 173 } 174 175 static unsigned int spacemit_k1_pin_to_io_pd_offset(unsigned int pin) 176 { 177 unsigned int offset = 0; 178 179 switch (pin) { 180 case 47 ... 52: 181 offset = IO_PWR_DOMAIN_GPIO3_K1; 182 break; 183 case 75 ... 80: 184 offset = IO_PWR_DOMAIN_GPIO2_Kx; 185 break; 186 case 98 ... 103: 187 offset = IO_PWR_DOMAIN_QSPI_K1; 188 break; 189 case 104 ... 109: 190 offset = IO_PWR_DOMAIN_MMC_Kx; 191 break; 192 } 193 194 return offset; 195 } 196 197 static unsigned int spacemit_k3_pin_to_io_pd_offset(unsigned int pin) 198 { 199 unsigned int offset = 0; 200 201 switch (pin) { 202 case 0 ... 20: 203 offset = IO_PWR_DOMAIN_GPIO1_K3; 204 break; 205 case 21 ... 41: 206 offset = IO_PWR_DOMAIN_GPIO2_Kx; 207 break; 208 case 76 ... 98: 209 offset = IO_PWR_DOMAIN_GPIO4_K3; 210 break; 211 case 99 ... 127: 212 offset = IO_PWR_DOMAIN_GPIO5_K3; 213 break; 214 case 132 ... 137: 215 offset = IO_PWR_DOMAIN_MMC_Kx; 216 break; 217 case 138 ... 144: 218 offset = IO_PWR_DOMAIN_QSPI_K3; 219 break; 220 } 221 222 return offset; 223 } 224 225 static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl, 226 unsigned int pin) 227 { 228 return pctrl->regs + pctrl->data->pin_to_offset(pin); 229 } 230 231 static u16 spacemit_dt_get_pin(u32 value) 232 { 233 return value >> 16; 234 } 235 236 static u16 spacemit_dt_get_pin_mux(u32 value) 237 { 238 return value & GENMASK(15, 0); 239 } 240 241 static const struct spacemit_pin *spacemit_get_pin(struct spacemit_pinctrl *pctrl, 242 unsigned long pin) 243 { 244 const struct spacemit_pin *pdata = pctrl->data->data; 245 int i; 246 247 for (i = 0; i < pctrl->data->npins; i++) { 248 if (pin == pdata[i].pin) 249 return &pdata[i]; 250 } 251 252 return NULL; 253 } 254 255 static inline enum spacemit_pin_io_type spacemit_to_pin_io_type( 256 const struct spacemit_pin *pin) 257 { 258 return K1_PIN_GET_IO_TYPE(pin->flags); 259 } 260 261 /* External: IO voltage via external source, can be 1.8V or 3.3V */ 262 static const char * const io_type_desc[] = { 263 "None", 264 "Fixed/1V8", 265 "Fixed/3V3", 266 "External", 267 }; 268 269 static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev, 270 struct seq_file *seq, unsigned int pin) 271 { 272 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 273 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); 274 enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin); 275 void __iomem *reg; 276 u32 value; 277 278 seq_printf(seq, "offset: 0x%04x ", pctrl->data->pin_to_offset(pin)); 279 seq_printf(seq, "type: %s ", io_type_desc[type]); 280 281 reg = spacemit_pin_to_reg(pctrl, pin); 282 value = readl(reg); 283 seq_printf(seq, "mux: %ld reg: 0x%04x", (value & PAD_MUX), value); 284 } 285 286 static const struct spacemit_pinctrl_dconf k1_drive_conf = { 287 .drive_mask = PAD_DRIVE_K1, 288 .schmitt_mask = PAD_SCHMITT_K1, 289 .ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) { 290 { 0, 11 }, 291 { 2, 21 }, 292 { 4, 32 }, 293 { 6, 42 }, 294 }, 295 .ds_1v8_tbl_num = 4, 296 .ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) { 297 { 0, 7 }, 298 { 2, 10 }, 299 { 4, 13 }, 300 { 6, 16 }, 301 { 1, 19 }, 302 { 3, 23 }, 303 { 5, 26 }, 304 { 7, 29 }, 305 }, 306 .ds_3v3_tbl_num = 8, 307 }; 308 309 static const struct spacemit_pinctrl_dconf k3_drive_conf = { 310 .drive_mask = PAD_DRIVE_K3, 311 .schmitt_mask = PAD_SCHMITT_K3, 312 .ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) { 313 { 0, 2 }, 314 { 1, 4 }, 315 { 2, 6 }, 316 { 3, 7 }, 317 { 4, 9 }, 318 { 5, 11 }, 319 { 6, 13 }, 320 { 7, 14 }, 321 { 8, 21 }, 322 { 9, 23 }, 323 { 10, 25 }, 324 { 11, 26 }, 325 { 12, 28 }, 326 { 13, 30 }, 327 { 14, 31 }, 328 { 15, 33 }, 329 }, 330 .ds_1v8_tbl_num = 16, 331 .ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) { 332 { 0, 3 }, 333 { 1, 5 }, 334 { 2, 7 }, 335 { 3, 9 }, 336 { 4, 11 }, 337 { 5, 13 }, 338 { 6, 15 }, 339 { 7, 17 }, 340 { 8, 25 }, 341 { 9, 27 }, 342 { 10, 29 }, 343 { 11, 31 }, 344 { 12, 33 }, 345 { 13, 35 }, 346 { 14, 37 }, 347 { 15, 38 }, 348 }, 349 .ds_3v3_tbl_num = 16, 350 }; 351 352 static inline u8 spacemit_get_ds_value(struct spacemit_pin_drv_strength *tbl, 353 u32 num, u32 mA) 354 { 355 int i; 356 357 for (i = 0; i < num; i++) 358 if (mA <= tbl[i].mA) 359 return tbl[i].val; 360 361 return tbl[num - 1].val; 362 } 363 364 static inline u32 spacemit_get_ds_mA(struct spacemit_pin_drv_strength *tbl, 365 u32 num, u32 val) 366 { 367 int i; 368 369 for (i = 0; i < num; i++) 370 if (val == tbl[i].val) 371 return tbl[i].mA; 372 373 return 0; 374 } 375 376 static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type, 377 const struct spacemit_pinctrl_dconf *dconf, 378 u32 mA) 379 { 380 switch (type) { 381 case IO_TYPE_1V8: 382 return spacemit_get_ds_value(dconf->ds_1v8_tbl, 383 dconf->ds_1v8_tbl_num, 384 mA); 385 case IO_TYPE_3V3: 386 return spacemit_get_ds_value(dconf->ds_3v3_tbl, 387 dconf->ds_3v3_tbl_num, 388 mA); 389 default: 390 return 0; 391 } 392 } 393 394 static inline u32 spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type, 395 const struct spacemit_pinctrl_dconf *dconf, 396 u32 value) 397 { 398 switch (type) { 399 case IO_TYPE_1V8: 400 return spacemit_get_ds_mA(dconf->ds_1v8_tbl, 401 dconf->ds_1v8_tbl_num, 402 value); 403 case IO_TYPE_3V3: 404 return spacemit_get_ds_mA(dconf->ds_3v3_tbl, 405 dconf->ds_3v3_tbl_num, 406 value); 407 default: 408 return 0; 409 } 410 } 411 412 static int spacemit_pctrl_check_power(struct pinctrl_dev *pctldev, 413 struct device_node *dn, 414 struct spacemit_pin_mux_config *pinmuxs, 415 int num_pins, const char *grpname) 416 { 417 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 418 struct device *dev = pctrl->dev; 419 enum spacemit_pin_io_type type; 420 u32 power = 0, i; 421 422 of_property_read_u32(dn, "power-source", &power); 423 424 for (i = 0; i < num_pins; i++) { 425 type = spacemit_to_pin_io_type(pinmuxs[i].pin); 426 427 if (type != IO_TYPE_EXTERNAL) 428 continue; 429 430 switch (power) { 431 case PIN_POWER_STATE_1V8: 432 case PIN_POWER_STATE_3V3: 433 break; 434 default: 435 dev_err(dev, "group %s has unsupported power\n", 436 grpname); 437 return -ENOTSUPP; 438 } 439 } 440 441 return 0; 442 } 443 444 static void spacemit_set_io_pwr_domain(struct spacemit_pinctrl *pctrl, 445 const struct spacemit_pin *spin, 446 const enum spacemit_pin_io_type type) 447 { 448 u32 offset, val = 0; 449 450 if (!pctrl->regmap_apbc) 451 return; 452 453 offset = pctrl->data->pin_to_io_pd_offset(spin->pin); 454 455 /* Other bits are reserved so don't need to save them */ 456 if (type == IO_TYPE_1V8) 457 val = IO_PWR_DOMAIN_V18EN; 458 459 /* 460 * IO power domain registers are protected and cannot be accessed 461 * directly. Before performing any read or write to the IO power 462 * domain registers, an explicit unlock sequence must be issued 463 * via the AIB Secure Access Register (ASAR). 464 * 465 * The unlock sequence allows exactly one subsequent access to the 466 * IO power domain registers. After that access completes, the ASAR 467 * keys are automatically cleared, and the registers become locked 468 * again. 469 * 470 * This mechanism ensures that IO power domain configuration is 471 * performed intentionally, as incorrect voltage settings may 472 * result in functional failures or hardware damage. 473 */ 474 regmap_write(pctrl->regmap_apbc, APBC_ASFAR, APBC_ASFAR_AKEY); 475 regmap_write(pctrl->regmap_apbc, APBC_ASSAR, APBC_ASSAR_AKEY); 476 477 writel_relaxed(val, pctrl->regs + IO_PWR_DOMAIN_OFFSET + offset); 478 } 479 480 static int spacemit_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 481 struct device_node *np, 482 struct pinctrl_map **maps, 483 unsigned int *num_maps) 484 { 485 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 486 struct device *dev = pctrl->dev; 487 struct device_node *child; 488 struct pinctrl_map *map; 489 const char **grpnames; 490 const char *grpname; 491 int ngroups = 0; 492 int nmaps = 0; 493 int ret; 494 495 for_each_available_child_of_node(np, child) 496 ngroups += 1; 497 498 grpnames = devm_kcalloc(dev, ngroups, sizeof(*grpnames), GFP_KERNEL); 499 if (!grpnames) 500 return -ENOMEM; 501 502 map = kzalloc_objs(*map, ngroups * 2); 503 if (!map) 504 return -ENOMEM; 505 506 ngroups = 0; 507 guard(mutex)(&pctrl->mutex); 508 for_each_available_child_of_node_scoped(np, child) { 509 struct spacemit_pin_mux_config *pinmuxs; 510 unsigned int config, *pins; 511 int i, npins; 512 513 npins = of_property_count_u32_elems(child, "pinmux"); 514 515 if (npins < 1) { 516 dev_err(dev, "invalid pinctrl group %pOFn.%pOFn\n", 517 np, child); 518 return -EINVAL; 519 } 520 521 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", 522 np, child); 523 if (!grpname) 524 return -ENOMEM; 525 526 grpnames[ngroups++] = grpname; 527 528 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); 529 if (!pins) 530 return -ENOMEM; 531 532 pinmuxs = devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL); 533 if (!pinmuxs) 534 return -ENOMEM; 535 536 for (i = 0; i < npins; i++) { 537 ret = of_property_read_u32_index(child, "pinmux", 538 i, &config); 539 540 if (ret) 541 return -EINVAL; 542 543 pins[i] = spacemit_dt_get_pin(config); 544 pinmuxs[i].config = config; 545 pinmuxs[i].pin = spacemit_get_pin(pctrl, pins[i]); 546 547 if (!pinmuxs[i].pin) 548 return dev_err_probe(dev, -ENODEV, "failed to get pin %d\n", pins[i]); 549 } 550 551 ret = spacemit_pctrl_check_power(pctldev, child, pinmuxs, 552 npins, grpname); 553 if (ret < 0) 554 return ret; 555 556 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; 557 map[nmaps].data.mux.function = np->name; 558 map[nmaps].data.mux.group = grpname; 559 nmaps += 1; 560 561 ret = pinctrl_generic_add_group(pctldev, grpname, 562 pins, npins, pinmuxs); 563 if (ret < 0) 564 return dev_err_probe(dev, ret, "failed to add group %s: %d\n", grpname, ret); 565 566 ret = pinconf_generic_parse_dt_config(child, pctldev, 567 &map[nmaps].data.configs.configs, 568 &map[nmaps].data.configs.num_configs); 569 if (ret) 570 return dev_err_probe(dev, ret, "failed to parse pin config of group %s\n", 571 grpname); 572 573 if (map[nmaps].data.configs.num_configs == 0) 574 continue; 575 576 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; 577 map[nmaps].data.configs.group_or_pin = grpname; 578 nmaps += 1; 579 } 580 581 ret = pinmux_generic_add_function(pctldev, np->name, 582 grpnames, ngroups, NULL); 583 if (ret < 0) { 584 pinctrl_utils_free_map(pctldev, map, nmaps); 585 return dev_err_probe(dev, ret, "error adding function %s\n", np->name); 586 } 587 588 *maps = map; 589 *num_maps = nmaps; 590 591 return 0; 592 } 593 594 static const struct pinctrl_ops spacemit_pctrl_ops = { 595 .get_groups_count = pinctrl_generic_get_group_count, 596 .get_group_name = pinctrl_generic_get_group_name, 597 .get_group_pins = pinctrl_generic_get_group_pins, 598 .pin_dbg_show = spacemit_pctrl_dbg_show, 599 .dt_node_to_map = spacemit_pctrl_dt_node_to_map, 600 .dt_free_map = pinctrl_utils_free_map, 601 }; 602 603 static int spacemit_pmx_set_mux(struct pinctrl_dev *pctldev, 604 unsigned int fsel, unsigned int gsel) 605 { 606 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 607 const struct group_desc *group; 608 const struct spacemit_pin_mux_config *configs; 609 unsigned int i, mux; 610 void __iomem *reg; 611 612 group = pinctrl_generic_get_group(pctldev, gsel); 613 if (!group) 614 return -EINVAL; 615 616 configs = group->data; 617 618 for (i = 0; i < group->grp.npins; i++) { 619 const struct spacemit_pin *spin = configs[i].pin; 620 u32 value = configs[i].config; 621 622 reg = spacemit_pin_to_reg(pctrl, spin->pin); 623 mux = spacemit_dt_get_pin_mux(value); 624 625 guard(raw_spinlock_irqsave)(&pctrl->lock); 626 value = readl_relaxed(reg) & ~PAD_MUX; 627 writel_relaxed(mux | value, reg); 628 } 629 630 return 0; 631 } 632 633 static int spacemit_request_gpio(struct pinctrl_dev *pctldev, 634 struct pinctrl_gpio_range *range, 635 unsigned int pin) 636 { 637 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 638 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); 639 void __iomem *reg; 640 641 reg = spacemit_pin_to_reg(pctrl, pin); 642 guard(raw_spinlock_irqsave)(&pctrl->lock); 643 writel_relaxed(spin->gpiofunc, reg); 644 645 return 0; 646 } 647 648 static const struct pinmux_ops spacemit_pmx_ops = { 649 .get_functions_count = pinmux_generic_get_function_count, 650 .get_function_name = pinmux_generic_get_function_name, 651 .get_function_groups = pinmux_generic_get_function_groups, 652 .set_mux = spacemit_pmx_set_mux, 653 .gpio_request_enable = spacemit_request_gpio, 654 .strict = true, 655 }; 656 657 static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, 658 unsigned int pin, unsigned long *config) 659 { 660 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 661 int param = pinconf_to_config_param(*config); 662 u32 value, arg = 0; 663 664 if (!pin) 665 return -EINVAL; 666 667 value = readl(spacemit_pin_to_reg(pctrl, pin)); 668 669 switch (param) { 670 case PIN_CONFIG_SLEW_RATE: 671 if (FIELD_GET(PAD_SLEW_RATE_EN, value)) 672 arg = FIELD_GET(PAD_SLEW_RATE, value) + 2; 673 else 674 arg = 0; 675 break; 676 default: 677 return -EINVAL; 678 } 679 680 *config = pinconf_to_config_packed(param, arg); 681 682 return 0; 683 } 684 685 #define ENABLE_DRV_STRENGTH BIT(1) 686 #define ENABLE_SLEW_RATE BIT(2) 687 static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl, 688 const struct spacemit_pin *spin, 689 const struct spacemit_pinctrl_dconf *dconf, 690 unsigned long *configs, 691 unsigned int num_configs, 692 u32 *value) 693 { 694 enum spacemit_pin_io_type type; 695 int i, param; 696 u32 v = 0, voltage = 0, arg, val; 697 u32 flag = 0, drv_strength, slew_rate; 698 699 if (!spin) 700 return -EINVAL; 701 702 for (i = 0; i < num_configs; i++) { 703 param = pinconf_to_config_param(configs[i]); 704 arg = pinconf_to_config_argument(configs[i]); 705 706 switch (param) { 707 case PIN_CONFIG_BIAS_DISABLE: 708 v &= ~(PAD_PULL_EN | PAD_PULLDOWN | PAD_PULLUP); 709 v &= ~PAD_STRONG_PULL; 710 break; 711 case PIN_CONFIG_BIAS_PULL_DOWN: 712 v &= ~(PAD_PULLUP | PAD_STRONG_PULL); 713 v |= (PAD_PULL_EN | PAD_PULLDOWN); 714 break; 715 case PIN_CONFIG_BIAS_PULL_UP: 716 v &= ~PAD_PULLDOWN; 717 v |= (PAD_PULL_EN | PAD_PULLUP); 718 719 if (arg == 1) 720 v |= PAD_STRONG_PULL; 721 break; 722 case PIN_CONFIG_DRIVE_STRENGTH: 723 flag |= ENABLE_DRV_STRENGTH; 724 drv_strength = arg; 725 break; 726 case PIN_CONFIG_INPUT_SCHMITT: 727 v &= ~dconf->schmitt_mask; 728 v |= (arg << __ffs(dconf->schmitt_mask)) & dconf->schmitt_mask; 729 break; 730 case PIN_CONFIG_POWER_SOURCE: 731 voltage = arg; 732 break; 733 case PIN_CONFIG_SLEW_RATE: 734 if (arg) { 735 flag |= ENABLE_SLEW_RATE; 736 v |= PAD_SLEW_RATE_EN; 737 slew_rate = arg; 738 } else { 739 v &= ~PAD_SLEW_RATE_EN; 740 } 741 break; 742 default: 743 return -EINVAL; 744 } 745 } 746 747 if (flag & ENABLE_DRV_STRENGTH) { 748 type = spacemit_to_pin_io_type(spin); 749 750 /* fix external io type */ 751 if (type == IO_TYPE_EXTERNAL) { 752 switch (voltage) { 753 case 1800: 754 type = IO_TYPE_1V8; 755 break; 756 case 3300: 757 type = IO_TYPE_3V3; 758 break; 759 default: 760 return -EINVAL; 761 } 762 spacemit_set_io_pwr_domain(pctrl, spin, type); 763 } 764 765 val = spacemit_get_driver_strength(type, dconf, drv_strength); 766 767 v &= ~dconf->drive_mask; 768 v |= (val << __ffs(dconf->drive_mask)) & dconf->drive_mask; 769 } 770 771 if (flag & ENABLE_SLEW_RATE) { 772 /* check, driver strength & slew rate */ 773 if (flag & ENABLE_DRV_STRENGTH) { 774 val = FIELD_GET(PAD_SLEW_RATE, v) + 2; 775 if (slew_rate > 1 && slew_rate != val) { 776 pr_err("slew rate conflict with drive strength\n"); 777 return -EINVAL; 778 } 779 } else { 780 v &= ~PAD_SLEW_RATE; 781 slew_rate = slew_rate > 1 ? (slew_rate - 2) : 0; 782 v |= FIELD_PREP(PAD_SLEW_RATE, slew_rate); 783 } 784 } 785 786 *value = v; 787 788 return 0; 789 } 790 791 static int spacemit_pin_set_config(struct spacemit_pinctrl *pctrl, 792 unsigned int pin, u32 value) 793 { 794 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); 795 void __iomem *reg; 796 unsigned int mux; 797 798 if (!pin) 799 return -EINVAL; 800 801 reg = spacemit_pin_to_reg(pctrl, spin->pin); 802 803 guard(raw_spinlock_irqsave)(&pctrl->lock); 804 mux = readl_relaxed(reg) & PAD_MUX; 805 writel_relaxed(mux | value, reg); 806 807 return 0; 808 } 809 810 static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, 811 unsigned int pin, unsigned long *configs, 812 unsigned int num_configs) 813 { 814 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 815 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); 816 u32 value; 817 818 if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, 819 configs, num_configs, &value)) 820 return -EINVAL; 821 822 return spacemit_pin_set_config(pctrl, pin, value); 823 } 824 825 static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, 826 unsigned int gsel, 827 unsigned long *configs, 828 unsigned int num_configs) 829 { 830 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 831 const struct spacemit_pin *spin; 832 const struct group_desc *group; 833 u32 value; 834 int i; 835 836 group = pinctrl_generic_get_group(pctldev, gsel); 837 if (!group) 838 return -EINVAL; 839 840 spin = spacemit_get_pin(pctrl, group->grp.pins[0]); 841 if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, 842 configs, num_configs, &value)) 843 return -EINVAL; 844 845 for (i = 0; i < group->grp.npins; i++) 846 spacemit_pin_set_config(pctrl, group->grp.pins[i], value); 847 848 return 0; 849 } 850 851 static void spacemit_pinconf_dbg_pull(struct seq_file *seq, unsigned int value) 852 { 853 u32 normal, strong; 854 855 if (!FIELD_GET(PAD_PULL_EN, value)) { 856 seq_puts(seq, ", bias pull disabled"); 857 return; 858 } 859 860 if (FIELD_GET(PAD_PULLDOWN, value)) 861 seq_puts(seq, ", bias pull down"); 862 863 normal = FIELD_GET(PAD_PULLUP, value); 864 strong = FIELD_GET(PAD_STRONG_PULL, value); 865 866 if (normal && strong) 867 seq_puts(seq, ", bias strong pull up"); 868 else if (normal) 869 seq_puts(seq, ", bias normal pull up"); 870 } 871 872 static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev, 873 struct seq_file *seq, unsigned int pin) 874 { 875 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 876 const struct spacemit_pinctrl_dconf *dconf = pctrl->data->dconf; 877 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); 878 enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin); 879 void __iomem *reg = spacemit_pin_to_reg(pctrl, pin); 880 u32 value, tmp, mA; 881 882 value = readl(reg); 883 spacemit_pinconf_dbg_pull(seq, value); 884 885 seq_printf(seq, ", io type (%s)", io_type_desc[type]); 886 887 tmp = (value & dconf->drive_mask) >> __ffs(dconf->drive_mask); 888 if (type == IO_TYPE_1V8 || type == IO_TYPE_3V3) { 889 mA = spacemit_get_drive_strength_mA(type, dconf, tmp); 890 seq_printf(seq, ", drive strength (%d mA)", mA); 891 } 892 893 /* drive strength depend on power source, so show all values */ 894 if (type == IO_TYPE_EXTERNAL) 895 seq_printf(seq, ", drive strength (%d or %d mA)", 896 spacemit_get_drive_strength_mA(IO_TYPE_1V8, dconf, tmp), 897 spacemit_get_drive_strength_mA(IO_TYPE_3V3, dconf, tmp)); 898 899 seq_printf(seq, ", register (0x%04x)", value); 900 } 901 902 static const struct pinconf_ops spacemit_pinconf_ops = { 903 .pin_config_get = spacemit_pinconf_get, 904 .pin_config_set = spacemit_pinconf_set, 905 .pin_config_group_set = spacemit_pinconf_group_set, 906 .pin_config_dbg_show = spacemit_pinconf_dbg_show, 907 .is_generic = true, 908 }; 909 910 static int spacemit_pinctrl_probe(struct platform_device *pdev) 911 { 912 struct device_node *np = pdev->dev.of_node; 913 struct device *dev = &pdev->dev; 914 struct spacemit_pinctrl *pctrl; 915 struct clk *func_clk, *bus_clk; 916 const struct spacemit_pinctrl_data *pctrl_data; 917 int ret; 918 919 pctrl_data = device_get_match_data(dev); 920 if (!pctrl_data) 921 return -ENODEV; 922 923 if (pctrl_data->npins == 0) 924 return dev_err_probe(dev, -EINVAL, "invalid pin data\n"); 925 926 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 927 if (!pctrl) 928 return -ENOMEM; 929 930 pctrl->regs = devm_platform_ioremap_resource(pdev, 0); 931 if (IS_ERR(pctrl->regs)) 932 return PTR_ERR(pctrl->regs); 933 934 pctrl->regmap_apbc = syscon_regmap_lookup_by_phandle(np, "spacemit,apbc"); 935 if (IS_ERR(pctrl->regmap_apbc)) { 936 dev_warn(dev, "no syscon found, disable power voltage switch functionality\n"); 937 pctrl->regmap_apbc = NULL; 938 } 939 940 func_clk = devm_clk_get_enabled(dev, "func"); 941 if (IS_ERR(func_clk)) 942 return dev_err_probe(dev, PTR_ERR(func_clk), "failed to get func clock\n"); 943 944 bus_clk = devm_clk_get_enabled(dev, "bus"); 945 if (IS_ERR(bus_clk)) 946 return dev_err_probe(dev, PTR_ERR(bus_clk), "failed to get bus clock\n"); 947 948 pctrl->pdesc.name = dev_name(dev); 949 pctrl->pdesc.pins = pctrl_data->pins; 950 pctrl->pdesc.npins = pctrl_data->npins; 951 pctrl->pdesc.pctlops = &spacemit_pctrl_ops; 952 pctrl->pdesc.pmxops = &spacemit_pmx_ops; 953 pctrl->pdesc.confops = &spacemit_pinconf_ops; 954 pctrl->pdesc.owner = THIS_MODULE; 955 956 pctrl->data = pctrl_data; 957 pctrl->dev = dev; 958 raw_spin_lock_init(&pctrl->lock); 959 960 ret = devm_mutex_init(dev, &pctrl->mutex); 961 if (ret) 962 return ret; 963 964 platform_set_drvdata(pdev, pctrl); 965 966 ret = devm_pinctrl_register_and_init(dev, &pctrl->pdesc, 967 pctrl, &pctrl->pctl_dev); 968 if (ret) 969 return dev_err_probe(dev, ret, 970 "fail to register pinctrl driver\n"); 971 972 return pinctrl_enable(pctrl->pctl_dev); 973 } 974 975 static const struct pinctrl_pin_desc k1_pin_desc[] = { 976 PINCTRL_PIN(0, "GPIO_00"), 977 PINCTRL_PIN(1, "GPIO_01"), 978 PINCTRL_PIN(2, "GPIO_02"), 979 PINCTRL_PIN(3, "GPIO_03"), 980 PINCTRL_PIN(4, "GPIO_04"), 981 PINCTRL_PIN(5, "GPIO_05"), 982 PINCTRL_PIN(6, "GPIO_06"), 983 PINCTRL_PIN(7, "GPIO_07"), 984 PINCTRL_PIN(8, "GPIO_08"), 985 PINCTRL_PIN(9, "GPIO_09"), 986 PINCTRL_PIN(10, "GPIO_10"), 987 PINCTRL_PIN(11, "GPIO_11"), 988 PINCTRL_PIN(12, "GPIO_12"), 989 PINCTRL_PIN(13, "GPIO_13"), 990 PINCTRL_PIN(14, "GPIO_14"), 991 PINCTRL_PIN(15, "GPIO_15"), 992 PINCTRL_PIN(16, "GPIO_16"), 993 PINCTRL_PIN(17, "GPIO_17"), 994 PINCTRL_PIN(18, "GPIO_18"), 995 PINCTRL_PIN(19, "GPIO_19"), 996 PINCTRL_PIN(20, "GPIO_20"), 997 PINCTRL_PIN(21, "GPIO_21"), 998 PINCTRL_PIN(22, "GPIO_22"), 999 PINCTRL_PIN(23, "GPIO_23"), 1000 PINCTRL_PIN(24, "GPIO_24"), 1001 PINCTRL_PIN(25, "GPIO_25"), 1002 PINCTRL_PIN(26, "GPIO_26"), 1003 PINCTRL_PIN(27, "GPIO_27"), 1004 PINCTRL_PIN(28, "GPIO_28"), 1005 PINCTRL_PIN(29, "GPIO_29"), 1006 PINCTRL_PIN(30, "GPIO_30"), 1007 PINCTRL_PIN(31, "GPIO_31"), 1008 PINCTRL_PIN(32, "GPIO_32"), 1009 PINCTRL_PIN(33, "GPIO_33"), 1010 PINCTRL_PIN(34, "GPIO_34"), 1011 PINCTRL_PIN(35, "GPIO_35"), 1012 PINCTRL_PIN(36, "GPIO_36"), 1013 PINCTRL_PIN(37, "GPIO_37"), 1014 PINCTRL_PIN(38, "GPIO_38"), 1015 PINCTRL_PIN(39, "GPIO_39"), 1016 PINCTRL_PIN(40, "GPIO_40"), 1017 PINCTRL_PIN(41, "GPIO_41"), 1018 PINCTRL_PIN(42, "GPIO_42"), 1019 PINCTRL_PIN(43, "GPIO_43"), 1020 PINCTRL_PIN(44, "GPIO_44"), 1021 PINCTRL_PIN(45, "GPIO_45"), 1022 PINCTRL_PIN(46, "GPIO_46"), 1023 PINCTRL_PIN(47, "GPIO_47"), 1024 PINCTRL_PIN(48, "GPIO_48"), 1025 PINCTRL_PIN(49, "GPIO_49"), 1026 PINCTRL_PIN(50, "GPIO_50"), 1027 PINCTRL_PIN(51, "GPIO_51"), 1028 PINCTRL_PIN(52, "GPIO_52"), 1029 PINCTRL_PIN(53, "GPIO_53"), 1030 PINCTRL_PIN(54, "GPIO_54"), 1031 PINCTRL_PIN(55, "GPIO_55"), 1032 PINCTRL_PIN(56, "GPIO_56"), 1033 PINCTRL_PIN(57, "GPIO_57"), 1034 PINCTRL_PIN(58, "GPIO_58"), 1035 PINCTRL_PIN(59, "GPIO_59"), 1036 PINCTRL_PIN(60, "GPIO_60"), 1037 PINCTRL_PIN(61, "GPIO_61"), 1038 PINCTRL_PIN(62, "GPIO_62"), 1039 PINCTRL_PIN(63, "GPIO_63"), 1040 PINCTRL_PIN(64, "GPIO_64"), 1041 PINCTRL_PIN(65, "GPIO_65"), 1042 PINCTRL_PIN(66, "GPIO_66"), 1043 PINCTRL_PIN(67, "GPIO_67"), 1044 PINCTRL_PIN(68, "GPIO_68"), 1045 PINCTRL_PIN(69, "GPIO_69"), 1046 PINCTRL_PIN(70, "GPIO_70/PRI_TDI"), 1047 PINCTRL_PIN(71, "GPIO_71/PRI_TMS"), 1048 PINCTRL_PIN(72, "GPIO_72/PRI_TCK"), 1049 PINCTRL_PIN(73, "GPIO_73/PRI_TDO"), 1050 PINCTRL_PIN(74, "GPIO_74"), 1051 PINCTRL_PIN(75, "GPIO_75"), 1052 PINCTRL_PIN(76, "GPIO_76"), 1053 PINCTRL_PIN(77, "GPIO_77"), 1054 PINCTRL_PIN(78, "GPIO_78"), 1055 PINCTRL_PIN(79, "GPIO_79"), 1056 PINCTRL_PIN(80, "GPIO_80"), 1057 PINCTRL_PIN(81, "GPIO_81"), 1058 PINCTRL_PIN(82, "GPIO_82"), 1059 PINCTRL_PIN(83, "GPIO_83"), 1060 PINCTRL_PIN(84, "GPIO_84"), 1061 PINCTRL_PIN(85, "GPIO_85"), 1062 PINCTRL_PIN(86, "GPIO_86"), 1063 PINCTRL_PIN(87, "GPIO_87"), 1064 PINCTRL_PIN(88, "GPIO_88"), 1065 PINCTRL_PIN(89, "GPIO_89"), 1066 PINCTRL_PIN(90, "GPIO_90"), 1067 PINCTRL_PIN(91, "GPIO_91"), 1068 PINCTRL_PIN(92, "GPIO_92"), 1069 PINCTRL_PIN(93, "GPIO_93/PWR_SCL"), 1070 PINCTRL_PIN(94, "GPIO_94/PWR_SDA"), 1071 PINCTRL_PIN(95, "GPIO_95/VCX0_EN"), 1072 PINCTRL_PIN(96, "GPIO_96/DVL0"), 1073 PINCTRL_PIN(97, "GPIO_97/DVL1"), 1074 PINCTRL_PIN(98, "GPIO_98/QSPI_DAT3"), 1075 PINCTRL_PIN(99, "GPIO_99/QSPI_DAT2"), 1076 PINCTRL_PIN(100, "GPIO_100/QSPI_DAT1"), 1077 PINCTRL_PIN(101, "GPIO_101/QSPI_DAT0"), 1078 PINCTRL_PIN(102, "GPIO_102/QSPI_CLK"), 1079 PINCTRL_PIN(103, "GPIO_103/QSPI_CS1"), 1080 PINCTRL_PIN(104, "GPIO_104/MMC1_DAT3"), 1081 PINCTRL_PIN(105, "GPIO_105/MMC1_DAT2"), 1082 PINCTRL_PIN(106, "GPIO_106/MMC1_DAT1"), 1083 PINCTRL_PIN(107, "GPIO_107/MMC1_DAT0"), 1084 PINCTRL_PIN(108, "GPIO_108/MMC1_CMD"), 1085 PINCTRL_PIN(109, "GPIO_109/MMC1_CLK"), 1086 PINCTRL_PIN(110, "GPIO_110"), 1087 PINCTRL_PIN(111, "GPIO_111"), 1088 PINCTRL_PIN(112, "GPIO_112"), 1089 PINCTRL_PIN(113, "GPIO_113"), 1090 PINCTRL_PIN(114, "GPIO_114"), 1091 PINCTRL_PIN(115, "GPIO_115"), 1092 PINCTRL_PIN(116, "GPIO_116"), 1093 PINCTRL_PIN(117, "GPIO_117"), 1094 PINCTRL_PIN(118, "GPIO_118"), 1095 PINCTRL_PIN(119, "GPIO_119"), 1096 PINCTRL_PIN(120, "GPIO_120"), 1097 PINCTRL_PIN(121, "GPIO_121"), 1098 PINCTRL_PIN(122, "GPIO_122"), 1099 PINCTRL_PIN(123, "GPIO_123"), 1100 PINCTRL_PIN(124, "GPIO_124"), 1101 PINCTRL_PIN(125, "GPIO_125"), 1102 PINCTRL_PIN(126, "GPIO_126"), 1103 PINCTRL_PIN(127, "GPIO_127"), 1104 }; 1105 1106 static const struct spacemit_pin k1_pin_data[ARRAY_SIZE(k1_pin_desc)] = { 1107 K1_FUNC_PIN(0, 0, IO_TYPE_1V8), 1108 K1_FUNC_PIN(1, 0, IO_TYPE_1V8), 1109 K1_FUNC_PIN(2, 0, IO_TYPE_1V8), 1110 K1_FUNC_PIN(3, 0, IO_TYPE_1V8), 1111 K1_FUNC_PIN(4, 0, IO_TYPE_1V8), 1112 K1_FUNC_PIN(5, 0, IO_TYPE_1V8), 1113 K1_FUNC_PIN(6, 0, IO_TYPE_1V8), 1114 K1_FUNC_PIN(7, 0, IO_TYPE_1V8), 1115 K1_FUNC_PIN(8, 0, IO_TYPE_1V8), 1116 K1_FUNC_PIN(9, 0, IO_TYPE_1V8), 1117 K1_FUNC_PIN(10, 0, IO_TYPE_1V8), 1118 K1_FUNC_PIN(11, 0, IO_TYPE_1V8), 1119 K1_FUNC_PIN(12, 0, IO_TYPE_1V8), 1120 K1_FUNC_PIN(13, 0, IO_TYPE_1V8), 1121 K1_FUNC_PIN(14, 0, IO_TYPE_1V8), 1122 K1_FUNC_PIN(15, 0, IO_TYPE_1V8), 1123 K1_FUNC_PIN(16, 0, IO_TYPE_1V8), 1124 K1_FUNC_PIN(17, 0, IO_TYPE_1V8), 1125 K1_FUNC_PIN(18, 0, IO_TYPE_1V8), 1126 K1_FUNC_PIN(19, 0, IO_TYPE_1V8), 1127 K1_FUNC_PIN(20, 0, IO_TYPE_1V8), 1128 K1_FUNC_PIN(21, 0, IO_TYPE_1V8), 1129 K1_FUNC_PIN(22, 0, IO_TYPE_1V8), 1130 K1_FUNC_PIN(23, 0, IO_TYPE_1V8), 1131 K1_FUNC_PIN(24, 0, IO_TYPE_1V8), 1132 K1_FUNC_PIN(25, 0, IO_TYPE_1V8), 1133 K1_FUNC_PIN(26, 0, IO_TYPE_1V8), 1134 K1_FUNC_PIN(27, 0, IO_TYPE_1V8), 1135 K1_FUNC_PIN(28, 0, IO_TYPE_1V8), 1136 K1_FUNC_PIN(29, 0, IO_TYPE_1V8), 1137 K1_FUNC_PIN(30, 0, IO_TYPE_1V8), 1138 K1_FUNC_PIN(31, 0, IO_TYPE_1V8), 1139 K1_FUNC_PIN(32, 0, IO_TYPE_1V8), 1140 K1_FUNC_PIN(33, 0, IO_TYPE_1V8), 1141 K1_FUNC_PIN(34, 0, IO_TYPE_1V8), 1142 K1_FUNC_PIN(35, 0, IO_TYPE_1V8), 1143 K1_FUNC_PIN(36, 0, IO_TYPE_1V8), 1144 K1_FUNC_PIN(37, 0, IO_TYPE_1V8), 1145 K1_FUNC_PIN(38, 0, IO_TYPE_1V8), 1146 K1_FUNC_PIN(39, 0, IO_TYPE_1V8), 1147 K1_FUNC_PIN(40, 0, IO_TYPE_1V8), 1148 K1_FUNC_PIN(41, 0, IO_TYPE_1V8), 1149 K1_FUNC_PIN(42, 0, IO_TYPE_1V8), 1150 K1_FUNC_PIN(43, 0, IO_TYPE_1V8), 1151 K1_FUNC_PIN(44, 0, IO_TYPE_1V8), 1152 K1_FUNC_PIN(45, 0, IO_TYPE_1V8), 1153 K1_FUNC_PIN(46, 0, IO_TYPE_1V8), 1154 K1_FUNC_PIN(47, 0, IO_TYPE_EXTERNAL), 1155 K1_FUNC_PIN(48, 0, IO_TYPE_EXTERNAL), 1156 K1_FUNC_PIN(49, 0, IO_TYPE_EXTERNAL), 1157 K1_FUNC_PIN(50, 0, IO_TYPE_EXTERNAL), 1158 K1_FUNC_PIN(51, 0, IO_TYPE_EXTERNAL), 1159 K1_FUNC_PIN(52, 0, IO_TYPE_EXTERNAL), 1160 K1_FUNC_PIN(53, 0, IO_TYPE_1V8), 1161 K1_FUNC_PIN(54, 0, IO_TYPE_1V8), 1162 K1_FUNC_PIN(55, 0, IO_TYPE_1V8), 1163 K1_FUNC_PIN(56, 0, IO_TYPE_1V8), 1164 K1_FUNC_PIN(57, 0, IO_TYPE_1V8), 1165 K1_FUNC_PIN(58, 0, IO_TYPE_1V8), 1166 K1_FUNC_PIN(59, 0, IO_TYPE_1V8), 1167 K1_FUNC_PIN(60, 0, IO_TYPE_1V8), 1168 K1_FUNC_PIN(61, 0, IO_TYPE_1V8), 1169 K1_FUNC_PIN(62, 0, IO_TYPE_1V8), 1170 K1_FUNC_PIN(63, 0, IO_TYPE_1V8), 1171 K1_FUNC_PIN(64, 0, IO_TYPE_1V8), 1172 K1_FUNC_PIN(65, 0, IO_TYPE_1V8), 1173 K1_FUNC_PIN(66, 0, IO_TYPE_1V8), 1174 K1_FUNC_PIN(67, 0, IO_TYPE_1V8), 1175 K1_FUNC_PIN(68, 0, IO_TYPE_1V8), 1176 K1_FUNC_PIN(69, 0, IO_TYPE_1V8), 1177 K1_FUNC_PIN(70, 1, IO_TYPE_1V8), 1178 K1_FUNC_PIN(71, 1, IO_TYPE_1V8), 1179 K1_FUNC_PIN(72, 1, IO_TYPE_1V8), 1180 K1_FUNC_PIN(73, 1, IO_TYPE_1V8), 1181 K1_FUNC_PIN(74, 0, IO_TYPE_1V8), 1182 K1_FUNC_PIN(75, 0, IO_TYPE_EXTERNAL), 1183 K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL), 1184 K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL), 1185 K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL), 1186 K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL), 1187 K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL), 1188 K1_FUNC_PIN(81, 0, IO_TYPE_1V8), 1189 K1_FUNC_PIN(82, 0, IO_TYPE_1V8), 1190 K1_FUNC_PIN(83, 0, IO_TYPE_1V8), 1191 K1_FUNC_PIN(84, 0, IO_TYPE_1V8), 1192 K1_FUNC_PIN(85, 0, IO_TYPE_1V8), 1193 K1_FUNC_PIN(86, 0, IO_TYPE_1V8), 1194 K1_FUNC_PIN(87, 0, IO_TYPE_1V8), 1195 K1_FUNC_PIN(88, 0, IO_TYPE_1V8), 1196 K1_FUNC_PIN(89, 0, IO_TYPE_1V8), 1197 K1_FUNC_PIN(90, 0, IO_TYPE_1V8), 1198 K1_FUNC_PIN(91, 0, IO_TYPE_1V8), 1199 K1_FUNC_PIN(92, 0, IO_TYPE_1V8), 1200 K1_FUNC_PIN(93, 1, IO_TYPE_1V8), 1201 K1_FUNC_PIN(94, 1, IO_TYPE_1V8), 1202 K1_FUNC_PIN(95, 1, IO_TYPE_1V8), 1203 K1_FUNC_PIN(96, 1, IO_TYPE_1V8), 1204 K1_FUNC_PIN(97, 1, IO_TYPE_1V8), 1205 K1_FUNC_PIN(98, 1, IO_TYPE_EXTERNAL), 1206 K1_FUNC_PIN(99, 1, IO_TYPE_EXTERNAL), 1207 K1_FUNC_PIN(100, 1, IO_TYPE_EXTERNAL), 1208 K1_FUNC_PIN(101, 1, IO_TYPE_EXTERNAL), 1209 K1_FUNC_PIN(102, 1, IO_TYPE_EXTERNAL), 1210 K1_FUNC_PIN(103, 1, IO_TYPE_EXTERNAL), 1211 K1_FUNC_PIN(104, 4, IO_TYPE_EXTERNAL), 1212 K1_FUNC_PIN(105, 4, IO_TYPE_EXTERNAL), 1213 K1_FUNC_PIN(106, 4, IO_TYPE_EXTERNAL), 1214 K1_FUNC_PIN(107, 4, IO_TYPE_EXTERNAL), 1215 K1_FUNC_PIN(108, 4, IO_TYPE_EXTERNAL), 1216 K1_FUNC_PIN(109, 4, IO_TYPE_EXTERNAL), 1217 K1_FUNC_PIN(110, 0, IO_TYPE_1V8), 1218 K1_FUNC_PIN(111, 0, IO_TYPE_1V8), 1219 K1_FUNC_PIN(112, 0, IO_TYPE_1V8), 1220 K1_FUNC_PIN(113, 0, IO_TYPE_1V8), 1221 K1_FUNC_PIN(114, 0, IO_TYPE_1V8), 1222 K1_FUNC_PIN(115, 0, IO_TYPE_1V8), 1223 K1_FUNC_PIN(116, 0, IO_TYPE_1V8), 1224 K1_FUNC_PIN(117, 0, IO_TYPE_1V8), 1225 K1_FUNC_PIN(118, 0, IO_TYPE_1V8), 1226 K1_FUNC_PIN(119, 0, IO_TYPE_1V8), 1227 K1_FUNC_PIN(120, 0, IO_TYPE_1V8), 1228 K1_FUNC_PIN(121, 0, IO_TYPE_1V8), 1229 K1_FUNC_PIN(122, 0, IO_TYPE_1V8), 1230 K1_FUNC_PIN(123, 0, IO_TYPE_1V8), 1231 K1_FUNC_PIN(124, 0, IO_TYPE_1V8), 1232 K1_FUNC_PIN(125, 0, IO_TYPE_1V8), 1233 K1_FUNC_PIN(126, 0, IO_TYPE_1V8), 1234 K1_FUNC_PIN(127, 0, IO_TYPE_1V8), 1235 }; 1236 1237 static const struct spacemit_pinctrl_data k1_pinctrl_data = { 1238 .pins = k1_pin_desc, 1239 .data = k1_pin_data, 1240 .npins = ARRAY_SIZE(k1_pin_desc), 1241 .pin_to_offset = spacemit_k1_pin_to_offset, 1242 .pin_to_io_pd_offset = spacemit_k1_pin_to_io_pd_offset, 1243 .dconf = &k1_drive_conf, 1244 }; 1245 1246 static const struct pinctrl_pin_desc k3_pin_desc[] = { 1247 PINCTRL_PIN(0, "GPIO_00"), 1248 PINCTRL_PIN(1, "GPIO_01"), 1249 PINCTRL_PIN(2, "GPIO_02"), 1250 PINCTRL_PIN(3, "GPIO_03"), 1251 PINCTRL_PIN(4, "GPIO_04"), 1252 PINCTRL_PIN(5, "GPIO_05"), 1253 PINCTRL_PIN(6, "GPIO_06"), 1254 PINCTRL_PIN(7, "GPIO_07"), 1255 PINCTRL_PIN(8, "GPIO_08"), 1256 PINCTRL_PIN(9, "GPIO_09"), 1257 PINCTRL_PIN(10, "GPIO_10"), 1258 PINCTRL_PIN(11, "GPIO_11"), 1259 PINCTRL_PIN(12, "GPIO_12"), 1260 PINCTRL_PIN(13, "GPIO_13"), 1261 PINCTRL_PIN(14, "GPIO_14"), 1262 PINCTRL_PIN(15, "GPIO_15"), 1263 PINCTRL_PIN(16, "GPIO_16"), 1264 PINCTRL_PIN(17, "GPIO_17"), 1265 PINCTRL_PIN(18, "GPIO_18"), 1266 PINCTRL_PIN(19, "GPIO_19"), 1267 PINCTRL_PIN(20, "GPIO_20"), 1268 PINCTRL_PIN(21, "GPIO_21"), 1269 PINCTRL_PIN(22, "GPIO_22"), 1270 PINCTRL_PIN(23, "GPIO_23"), 1271 PINCTRL_PIN(24, "GPIO_24"), 1272 PINCTRL_PIN(25, "GPIO_25"), 1273 PINCTRL_PIN(26, "GPIO_26"), 1274 PINCTRL_PIN(27, "GPIO_27"), 1275 PINCTRL_PIN(28, "GPIO_28"), 1276 PINCTRL_PIN(29, "GPIO_29"), 1277 PINCTRL_PIN(30, "GPIO_30"), 1278 PINCTRL_PIN(31, "GPIO_31"), 1279 PINCTRL_PIN(32, "GPIO_32"), 1280 PINCTRL_PIN(33, "GPIO_33"), 1281 PINCTRL_PIN(34, "GPIO_34"), 1282 PINCTRL_PIN(35, "GPIO_35"), 1283 PINCTRL_PIN(36, "GPIO_36"), 1284 PINCTRL_PIN(37, "GPIO_37"), 1285 PINCTRL_PIN(38, "GPIO_38"), 1286 PINCTRL_PIN(39, "GPIO_39"), 1287 PINCTRL_PIN(40, "GPIO_40"), 1288 PINCTRL_PIN(41, "GPIO_41"), 1289 PINCTRL_PIN(42, "GPIO_42"), 1290 PINCTRL_PIN(43, "GPIO_43"), 1291 PINCTRL_PIN(44, "GPIO_44"), 1292 PINCTRL_PIN(45, "GPIO_45"), 1293 PINCTRL_PIN(46, "GPIO_46"), 1294 PINCTRL_PIN(47, "GPIO_47"), 1295 PINCTRL_PIN(48, "GPIO_48"), 1296 PINCTRL_PIN(49, "GPIO_49"), 1297 PINCTRL_PIN(50, "GPIO_50"), 1298 PINCTRL_PIN(51, "GPIO_51"), 1299 PINCTRL_PIN(52, "GPIO_52"), 1300 PINCTRL_PIN(53, "GPIO_53"), 1301 PINCTRL_PIN(54, "GPIO_54"), 1302 PINCTRL_PIN(55, "GPIO_55"), 1303 PINCTRL_PIN(56, "GPIO_56"), 1304 PINCTRL_PIN(57, "GPIO_57"), 1305 PINCTRL_PIN(58, "GPIO_58"), 1306 PINCTRL_PIN(59, "GPIO_59"), 1307 PINCTRL_PIN(60, "GPIO_60"), 1308 PINCTRL_PIN(61, "GPIO_61"), 1309 PINCTRL_PIN(62, "GPIO_62"), 1310 PINCTRL_PIN(63, "GPIO_63"), 1311 PINCTRL_PIN(64, "GPIO_64"), 1312 PINCTRL_PIN(65, "GPIO_65"), 1313 PINCTRL_PIN(66, "GPIO_66"), 1314 PINCTRL_PIN(67, "GPIO_67"), 1315 PINCTRL_PIN(68, "GPIO_68"), 1316 PINCTRL_PIN(69, "GPIO_69"), 1317 PINCTRL_PIN(70, "GPIO_70"), 1318 PINCTRL_PIN(71, "GPIO_71"), 1319 PINCTRL_PIN(72, "GPIO_72"), 1320 PINCTRL_PIN(73, "GPIO_73"), 1321 PINCTRL_PIN(74, "GPIO_74"), 1322 PINCTRL_PIN(75, "GPIO_75"), 1323 PINCTRL_PIN(76, "GPIO_76"), 1324 PINCTRL_PIN(77, "GPIO_77"), 1325 PINCTRL_PIN(78, "GPIO_78"), 1326 PINCTRL_PIN(79, "GPIO_79"), 1327 PINCTRL_PIN(80, "GPIO_80"), 1328 PINCTRL_PIN(81, "GPIO_81"), 1329 PINCTRL_PIN(82, "GPIO_82"), 1330 PINCTRL_PIN(83, "GPIO_83"), 1331 PINCTRL_PIN(84, "GPIO_84"), 1332 PINCTRL_PIN(85, "GPIO_85"), 1333 PINCTRL_PIN(86, "GPIO_86"), 1334 PINCTRL_PIN(87, "GPIO_87"), 1335 PINCTRL_PIN(88, "GPIO_88"), 1336 PINCTRL_PIN(89, "GPIO_89"), 1337 PINCTRL_PIN(90, "GPIO_90"), 1338 PINCTRL_PIN(91, "GPIO_91"), 1339 PINCTRL_PIN(92, "GPIO_92"), 1340 PINCTRL_PIN(93, "GPIO_93"), 1341 PINCTRL_PIN(94, "GPIO_94"), 1342 PINCTRL_PIN(95, "GPIO_95"), 1343 PINCTRL_PIN(96, "GPIO_96"), 1344 PINCTRL_PIN(97, "GPIO_97"), 1345 PINCTRL_PIN(98, "GPIO_98"), 1346 PINCTRL_PIN(99, "GPIO_99"), 1347 PINCTRL_PIN(100, "GPIO_100"), 1348 PINCTRL_PIN(101, "GPIO_101"), 1349 PINCTRL_PIN(102, "GPIO_102"), 1350 PINCTRL_PIN(103, "GPIO_103"), 1351 PINCTRL_PIN(104, "GPIO_104"), 1352 PINCTRL_PIN(105, "GPIO_105"), 1353 PINCTRL_PIN(106, "GPIO_106"), 1354 PINCTRL_PIN(107, "GPIO_107"), 1355 PINCTRL_PIN(108, "GPIO_108"), 1356 PINCTRL_PIN(109, "GPIO_109"), 1357 PINCTRL_PIN(110, "GPIO_110"), 1358 PINCTRL_PIN(111, "GPIO_111"), 1359 PINCTRL_PIN(112, "GPIO_112"), 1360 PINCTRL_PIN(113, "GPIO_113"), 1361 PINCTRL_PIN(114, "GPIO_114"), 1362 PINCTRL_PIN(115, "GPIO_115"), 1363 PINCTRL_PIN(116, "GPIO_116"), 1364 PINCTRL_PIN(117, "GPIO_117"), 1365 PINCTRL_PIN(118, "GPIO_118"), 1366 PINCTRL_PIN(119, "GPIO_119"), 1367 PINCTRL_PIN(120, "GPIO_120"), 1368 PINCTRL_PIN(121, "GPIO_121"), 1369 PINCTRL_PIN(122, "GPIO_122"), 1370 PINCTRL_PIN(123, "GPIO_123"), 1371 PINCTRL_PIN(124, "GPIO_124"), 1372 PINCTRL_PIN(125, "GPIO_125"), 1373 PINCTRL_PIN(126, "GPIO_126"), 1374 PINCTRL_PIN(127, "GPIO_127"), 1375 PINCTRL_PIN(128, "PWR_SCL"), 1376 PINCTRL_PIN(129, "PWR_SDA"), 1377 PINCTRL_PIN(130, "VCXO_EN"), 1378 PINCTRL_PIN(131, "PMIC_INT_N"), 1379 PINCTRL_PIN(132, "MMC1_DAT3"), 1380 PINCTRL_PIN(133, "MMC1_DAT2"), 1381 PINCTRL_PIN(134, "MMC1_DAT1"), 1382 PINCTRL_PIN(135, "MMC1_DAT0"), 1383 PINCTRL_PIN(136, "MMC1_CMD"), 1384 PINCTRL_PIN(137, "MMC1_CLK"), 1385 PINCTRL_PIN(138, "QSPI_DAT0"), 1386 PINCTRL_PIN(139, "QSPI_DAT1"), 1387 PINCTRL_PIN(140, "QSPI_DAT2"), 1388 PINCTRL_PIN(141, "QSPI_DAT3"), 1389 PINCTRL_PIN(142, "QSPI_CS0"), 1390 PINCTRL_PIN(143, "QSPI_CS1"), 1391 PINCTRL_PIN(144, "QSPI_CLK"), 1392 PINCTRL_PIN(145, "PRI_TDI"), 1393 PINCTRL_PIN(146, "PRI_TMS"), 1394 PINCTRL_PIN(147, "PRI_TCK"), 1395 PINCTRL_PIN(148, "PRI_TDO"), 1396 PINCTRL_PIN(149, "PWR_SSP_SCLK"), 1397 PINCTRL_PIN(150, "PWR_SSP_FRM"), 1398 PINCTRL_PIN(151, "PWR_SSP_TXD"), 1399 PINCTRL_PIN(152, "PWR_SSP_RXD"), 1400 }; 1401 1402 static const struct spacemit_pin k3_pin_data[ARRAY_SIZE(k3_pin_desc)] = { 1403 /* GPIO1 bank */ 1404 K1_FUNC_PIN(0, 0, IO_TYPE_EXTERNAL), 1405 K1_FUNC_PIN(1, 0, IO_TYPE_EXTERNAL), 1406 K1_FUNC_PIN(2, 0, IO_TYPE_EXTERNAL), 1407 K1_FUNC_PIN(3, 0, IO_TYPE_EXTERNAL), 1408 K1_FUNC_PIN(4, 0, IO_TYPE_EXTERNAL), 1409 K1_FUNC_PIN(5, 0, IO_TYPE_EXTERNAL), 1410 K1_FUNC_PIN(6, 0, IO_TYPE_EXTERNAL), 1411 K1_FUNC_PIN(7, 0, IO_TYPE_EXTERNAL), 1412 K1_FUNC_PIN(8, 0, IO_TYPE_EXTERNAL), 1413 K1_FUNC_PIN(9, 0, IO_TYPE_EXTERNAL), 1414 K1_FUNC_PIN(10, 0, IO_TYPE_EXTERNAL), 1415 K1_FUNC_PIN(11, 0, IO_TYPE_EXTERNAL), 1416 K1_FUNC_PIN(12, 0, IO_TYPE_EXTERNAL), 1417 K1_FUNC_PIN(13, 0, IO_TYPE_EXTERNAL), 1418 K1_FUNC_PIN(14, 0, IO_TYPE_EXTERNAL), 1419 K1_FUNC_PIN(15, 0, IO_TYPE_EXTERNAL), 1420 K1_FUNC_PIN(16, 0, IO_TYPE_EXTERNAL), 1421 K1_FUNC_PIN(17, 0, IO_TYPE_EXTERNAL), 1422 K1_FUNC_PIN(18, 0, IO_TYPE_EXTERNAL), 1423 K1_FUNC_PIN(19, 0, IO_TYPE_EXTERNAL), 1424 K1_FUNC_PIN(20, 0, IO_TYPE_EXTERNAL), 1425 1426 /* GPIO2 bank */ 1427 K1_FUNC_PIN(21, 0, IO_TYPE_EXTERNAL), 1428 K1_FUNC_PIN(22, 0, IO_TYPE_EXTERNAL), 1429 K1_FUNC_PIN(23, 0, IO_TYPE_EXTERNAL), 1430 K1_FUNC_PIN(24, 0, IO_TYPE_EXTERNAL), 1431 K1_FUNC_PIN(25, 0, IO_TYPE_EXTERNAL), 1432 K1_FUNC_PIN(26, 0, IO_TYPE_EXTERNAL), 1433 K1_FUNC_PIN(27, 0, IO_TYPE_EXTERNAL), 1434 K1_FUNC_PIN(28, 0, IO_TYPE_EXTERNAL), 1435 K1_FUNC_PIN(29, 0, IO_TYPE_EXTERNAL), 1436 K1_FUNC_PIN(30, 0, IO_TYPE_EXTERNAL), 1437 K1_FUNC_PIN(31, 0, IO_TYPE_EXTERNAL), 1438 K1_FUNC_PIN(32, 0, IO_TYPE_EXTERNAL), 1439 K1_FUNC_PIN(33, 0, IO_TYPE_EXTERNAL), 1440 K1_FUNC_PIN(34, 0, IO_TYPE_EXTERNAL), 1441 K1_FUNC_PIN(35, 0, IO_TYPE_EXTERNAL), 1442 K1_FUNC_PIN(36, 0, IO_TYPE_EXTERNAL), 1443 K1_FUNC_PIN(37, 0, IO_TYPE_EXTERNAL), 1444 K1_FUNC_PIN(38, 0, IO_TYPE_EXTERNAL), 1445 K1_FUNC_PIN(39, 0, IO_TYPE_EXTERNAL), 1446 K1_FUNC_PIN(40, 0, IO_TYPE_EXTERNAL), 1447 K1_FUNC_PIN(41, 0, IO_TYPE_EXTERNAL), 1448 1449 /* GPIO3 bank */ 1450 K1_FUNC_PIN(42, 0, IO_TYPE_1V8), 1451 K1_FUNC_PIN(43, 0, IO_TYPE_1V8), 1452 K1_FUNC_PIN(44, 0, IO_TYPE_1V8), 1453 K1_FUNC_PIN(45, 0, IO_TYPE_1V8), 1454 K1_FUNC_PIN(46, 0, IO_TYPE_1V8), 1455 K1_FUNC_PIN(47, 0, IO_TYPE_1V8), 1456 K1_FUNC_PIN(48, 0, IO_TYPE_1V8), 1457 K1_FUNC_PIN(49, 0, IO_TYPE_1V8), 1458 K1_FUNC_PIN(50, 0, IO_TYPE_1V8), 1459 K1_FUNC_PIN(51, 0, IO_TYPE_1V8), 1460 K1_FUNC_PIN(52, 0, IO_TYPE_1V8), 1461 K1_FUNC_PIN(53, 0, IO_TYPE_1V8), 1462 K1_FUNC_PIN(54, 0, IO_TYPE_1V8), 1463 K1_FUNC_PIN(55, 0, IO_TYPE_1V8), 1464 K1_FUNC_PIN(56, 0, IO_TYPE_1V8), 1465 K1_FUNC_PIN(57, 0, IO_TYPE_1V8), 1466 K1_FUNC_PIN(58, 0, IO_TYPE_1V8), 1467 K1_FUNC_PIN(59, 0, IO_TYPE_1V8), 1468 K1_FUNC_PIN(60, 0, IO_TYPE_1V8), 1469 K1_FUNC_PIN(61, 0, IO_TYPE_1V8), 1470 K1_FUNC_PIN(62, 0, IO_TYPE_1V8), 1471 K1_FUNC_PIN(63, 0, IO_TYPE_1V8), 1472 K1_FUNC_PIN(64, 0, IO_TYPE_1V8), 1473 K1_FUNC_PIN(65, 0, IO_TYPE_1V8), 1474 K1_FUNC_PIN(66, 0, IO_TYPE_1V8), 1475 K1_FUNC_PIN(67, 0, IO_TYPE_1V8), 1476 K1_FUNC_PIN(68, 0, IO_TYPE_1V8), 1477 K1_FUNC_PIN(69, 0, IO_TYPE_1V8), 1478 K1_FUNC_PIN(70, 0, IO_TYPE_1V8), 1479 K1_FUNC_PIN(71, 0, IO_TYPE_1V8), 1480 K1_FUNC_PIN(72, 0, IO_TYPE_1V8), 1481 K1_FUNC_PIN(73, 0, IO_TYPE_1V8), 1482 K1_FUNC_PIN(74, 0, IO_TYPE_1V8), 1483 K1_FUNC_PIN(75, 0, IO_TYPE_1V8), 1484 1485 /* GPIO4 bank */ 1486 K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL), 1487 K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL), 1488 K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL), 1489 K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL), 1490 K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL), 1491 K1_FUNC_PIN(81, 0, IO_TYPE_EXTERNAL), 1492 K1_FUNC_PIN(82, 0, IO_TYPE_EXTERNAL), 1493 K1_FUNC_PIN(83, 0, IO_TYPE_EXTERNAL), 1494 K1_FUNC_PIN(84, 0, IO_TYPE_EXTERNAL), 1495 K1_FUNC_PIN(85, 0, IO_TYPE_EXTERNAL), 1496 K1_FUNC_PIN(86, 0, IO_TYPE_EXTERNAL), 1497 K1_FUNC_PIN(87, 0, IO_TYPE_EXTERNAL), 1498 K1_FUNC_PIN(88, 0, IO_TYPE_EXTERNAL), 1499 K1_FUNC_PIN(89, 0, IO_TYPE_EXTERNAL), 1500 K1_FUNC_PIN(90, 0, IO_TYPE_EXTERNAL), 1501 K1_FUNC_PIN(91, 0, IO_TYPE_EXTERNAL), 1502 K1_FUNC_PIN(92, 0, IO_TYPE_EXTERNAL), 1503 K1_FUNC_PIN(93, 0, IO_TYPE_EXTERNAL), 1504 K1_FUNC_PIN(94, 0, IO_TYPE_EXTERNAL), 1505 K1_FUNC_PIN(95, 0, IO_TYPE_EXTERNAL), 1506 K1_FUNC_PIN(96, 0, IO_TYPE_EXTERNAL), 1507 K1_FUNC_PIN(97, 0, IO_TYPE_EXTERNAL), 1508 K1_FUNC_PIN(98, 0, IO_TYPE_EXTERNAL), 1509 1510 /* GPIO5 bank */ 1511 K1_FUNC_PIN(99, 0, IO_TYPE_EXTERNAL), 1512 K1_FUNC_PIN(100, 0, IO_TYPE_EXTERNAL), 1513 K1_FUNC_PIN(101, 0, IO_TYPE_EXTERNAL), 1514 K1_FUNC_PIN(102, 0, IO_TYPE_EXTERNAL), 1515 K1_FUNC_PIN(103, 0, IO_TYPE_EXTERNAL), 1516 K1_FUNC_PIN(104, 0, IO_TYPE_EXTERNAL), 1517 K1_FUNC_PIN(105, 0, IO_TYPE_EXTERNAL), 1518 K1_FUNC_PIN(106, 0, IO_TYPE_EXTERNAL), 1519 K1_FUNC_PIN(107, 0, IO_TYPE_EXTERNAL), 1520 K1_FUNC_PIN(108, 0, IO_TYPE_EXTERNAL), 1521 K1_FUNC_PIN(109, 0, IO_TYPE_EXTERNAL), 1522 K1_FUNC_PIN(110, 0, IO_TYPE_EXTERNAL), 1523 K1_FUNC_PIN(111, 0, IO_TYPE_EXTERNAL), 1524 K1_FUNC_PIN(112, 0, IO_TYPE_EXTERNAL), 1525 K1_FUNC_PIN(113, 0, IO_TYPE_EXTERNAL), 1526 K1_FUNC_PIN(114, 0, IO_TYPE_EXTERNAL), 1527 K1_FUNC_PIN(115, 0, IO_TYPE_EXTERNAL), 1528 K1_FUNC_PIN(116, 0, IO_TYPE_EXTERNAL), 1529 K1_FUNC_PIN(117, 0, IO_TYPE_EXTERNAL), 1530 K1_FUNC_PIN(118, 0, IO_TYPE_EXTERNAL), 1531 K1_FUNC_PIN(119, 0, IO_TYPE_EXTERNAL), 1532 K1_FUNC_PIN(120, 0, IO_TYPE_EXTERNAL), 1533 K1_FUNC_PIN(121, 0, IO_TYPE_EXTERNAL), 1534 K1_FUNC_PIN(122, 0, IO_TYPE_EXTERNAL), 1535 K1_FUNC_PIN(123, 0, IO_TYPE_EXTERNAL), 1536 K1_FUNC_PIN(124, 0, IO_TYPE_EXTERNAL), 1537 K1_FUNC_PIN(125, 0, IO_TYPE_EXTERNAL), 1538 K1_FUNC_PIN(126, 0, IO_TYPE_EXTERNAL), 1539 K1_FUNC_PIN(127, 0, IO_TYPE_EXTERNAL), 1540 1541 /* PMIC */ 1542 K1_FUNC_PIN(128, 0, IO_TYPE_1V8), 1543 K1_FUNC_PIN(129, 0, IO_TYPE_1V8), 1544 K1_FUNC_PIN(130, 0, IO_TYPE_1V8), 1545 K1_FUNC_PIN(131, 0, IO_TYPE_1V8), 1546 1547 /* SD/MMC1 */ 1548 K1_FUNC_PIN(132, 1, IO_TYPE_EXTERNAL), 1549 K1_FUNC_PIN(133, 1, IO_TYPE_EXTERNAL), 1550 K1_FUNC_PIN(134, 1, IO_TYPE_EXTERNAL), 1551 K1_FUNC_PIN(135, 1, IO_TYPE_EXTERNAL), 1552 K1_FUNC_PIN(136, 1, IO_TYPE_EXTERNAL), 1553 K1_FUNC_PIN(137, 1, IO_TYPE_EXTERNAL), 1554 1555 /* QSPI */ 1556 K1_FUNC_PIN(138, 1, IO_TYPE_EXTERNAL), 1557 K1_FUNC_PIN(139, 1, IO_TYPE_EXTERNAL), 1558 K1_FUNC_PIN(140, 1, IO_TYPE_EXTERNAL), 1559 K1_FUNC_PIN(141, 1, IO_TYPE_EXTERNAL), 1560 K1_FUNC_PIN(142, 1, IO_TYPE_EXTERNAL), 1561 K1_FUNC_PIN(143, 1, IO_TYPE_EXTERNAL), 1562 K1_FUNC_PIN(144, 1, IO_TYPE_EXTERNAL), 1563 1564 /* PMIC */ 1565 K1_FUNC_PIN(145, 1, IO_TYPE_1V8), 1566 K1_FUNC_PIN(146, 1, IO_TYPE_1V8), 1567 K1_FUNC_PIN(147, 1, IO_TYPE_1V8), 1568 K1_FUNC_PIN(148, 1, IO_TYPE_1V8), 1569 K1_FUNC_PIN(149, 1, IO_TYPE_1V8), 1570 K1_FUNC_PIN(150, 1, IO_TYPE_1V8), 1571 K1_FUNC_PIN(151, 1, IO_TYPE_1V8), 1572 K1_FUNC_PIN(152, 1, IO_TYPE_1V8), 1573 }; 1574 1575 static const struct spacemit_pinctrl_data k3_pinctrl_data = { 1576 .pins = k3_pin_desc, 1577 .data = k3_pin_data, 1578 .npins = ARRAY_SIZE(k3_pin_desc), 1579 .pin_to_offset = spacemit_k3_pin_to_offset, 1580 .pin_to_io_pd_offset = spacemit_k3_pin_to_io_pd_offset, 1581 .dconf = &k3_drive_conf, 1582 }; 1583 1584 static const struct of_device_id k1_pinctrl_ids[] = { 1585 { .compatible = "spacemit,k1-pinctrl", .data = &k1_pinctrl_data }, 1586 { .compatible = "spacemit,k3-pinctrl", .data = &k3_pinctrl_data }, 1587 { /* sentinel */ } 1588 }; 1589 MODULE_DEVICE_TABLE(of, k1_pinctrl_ids); 1590 1591 static struct platform_driver k1_pinctrl_driver = { 1592 .probe = spacemit_pinctrl_probe, 1593 .driver = { 1594 .name = "k1-pinctrl", 1595 .suppress_bind_attrs = true, 1596 .of_match_table = k1_pinctrl_ids, 1597 }, 1598 }; 1599 builtin_platform_driver(k1_pinctrl_driver); 1600 1601 MODULE_AUTHOR("Yixun Lan <dlan@gentoo.org>"); 1602 MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1/K3 SoC"); 1603 MODULE_LICENSE("GPL"); 1604