1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Exynos specific definitions for Samsung pinctrl and gpiolib driver. 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * Copyright (c) 2012 Linaro Ltd 8 * http://www.linaro.org 9 * 10 * This file contains the Exynos specific definitions for the Samsung 11 * pinctrl/gpiolib interface drivers. 12 * 13 * Author: Thomas Abraham <thomas.ab@samsung.com> 14 */ 15 16 #ifndef __PINCTRL_SAMSUNG_EXYNOS_H 17 #define __PINCTRL_SAMSUNG_EXYNOS_H 18 19 /* Values for the pin CON register */ 20 #define EXYNOS_PIN_CON_FUNC_EINT 0xf 21 22 /* External GPIO and wakeup interrupt related definitions */ 23 #define EXYNOS_GPIO_ECON_OFFSET 0x700 24 #define EXYNOS_GPIO_EFLTCON_OFFSET 0x800 25 #define EXYNOS_GPIO_EMASK_OFFSET 0x900 26 #define EXYNOS_GPIO_EPEND_OFFSET 0xA00 27 #define EXYNOS_WKUP_ECON_OFFSET 0xE00 28 #define EXYNOS_WKUP_EMASK_OFFSET 0xF00 29 #define EXYNOS_WKUP_EPEND_OFFSET 0xF40 30 #define EXYNOS7_WKUP_ECON_OFFSET 0x700 31 #define EXYNOS7_WKUP_EMASK_OFFSET 0x900 32 #define EXYNOS7_WKUP_EPEND_OFFSET 0xA00 33 #define EXYNOS_SVC_OFFSET 0xB08 34 35 /* helpers to access interrupt service register */ 36 #define EXYNOS_SVC_GROUP_SHIFT 3 37 #define EXYNOS_SVC_GROUP_MASK 0x1f 38 #define EXYNOS_SVC_NUM_MASK 7 39 #define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \ 40 EXYNOS_SVC_GROUP_MASK) 41 42 /* Exynos specific external interrupt trigger types */ 43 #define EXYNOS_EINT_LEVEL_LOW 0 44 #define EXYNOS_EINT_LEVEL_HIGH 1 45 #define EXYNOS_EINT_EDGE_FALLING 2 46 #define EXYNOS_EINT_EDGE_RISING 3 47 #define EXYNOS_EINT_EDGE_BOTH 4 48 #define EXYNOS_EINT_CON_MASK 0xF 49 #define EXYNOS_EINT_CON_LEN 4 50 51 #define EXYNOS_EINT_MAX_PER_BANK 8 52 #define EXYNOS_EINT_NR_WKUP_EINT 53 54 #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ 55 { \ 56 .type = &bank_type_off, \ 57 .pctl_offset = reg, \ 58 .nr_pins = pins, \ 59 .eint_type = EINT_TYPE_NONE, \ 60 .name = id \ 61 } 62 63 #define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ 64 { \ 65 .type = &bank_type_off, \ 66 .pctl_offset = reg, \ 67 .nr_pins = pins, \ 68 .eint_type = EINT_TYPE_GPIO, \ 69 .eint_offset = offs, \ 70 .name = id \ 71 } 72 73 #define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ 74 { \ 75 .type = &bank_type_alive, \ 76 .pctl_offset = reg, \ 77 .nr_pins = pins, \ 78 .eint_type = EINT_TYPE_WKUP, \ 79 .eint_offset = offs, \ 80 .name = id \ 81 } 82 83 #define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \ 84 { \ 85 .type = &exynos5433_bank_type_off, \ 86 .pctl_offset = reg, \ 87 .nr_pins = pins, \ 88 .eint_type = EINT_TYPE_GPIO, \ 89 .eint_offset = offs, \ 90 .name = id \ 91 } 92 93 #define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \ 94 { \ 95 .type = &exynos5433_bank_type_alive, \ 96 .pctl_offset = reg, \ 97 .nr_pins = pins, \ 98 .eint_type = EINT_TYPE_WKUP, \ 99 .eint_offset = offs, \ 100 .name = id \ 101 } 102 103 #define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \ 104 { \ 105 .type = &exynos5433_bank_type_off, \ 106 .pctl_offset = reg, \ 107 .nr_pins = pins, \ 108 .eint_type = EINT_TYPE_WKUP, \ 109 .eint_offset = offs, \ 110 .name = id, \ 111 .pctl_res_idx = pctl_idx, \ 112 } \ 113 114 #define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \ 115 { \ 116 .type = &exynos850_bank_type_alive, \ 117 .pctl_offset = reg, \ 118 .nr_pins = pins, \ 119 .eint_type = EINT_TYPE_NONE, \ 120 .name = id \ 121 } 122 123 #define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs) \ 124 { \ 125 .type = &exynos850_bank_type_off, \ 126 .pctl_offset = reg, \ 127 .nr_pins = pins, \ 128 .eint_type = EINT_TYPE_GPIO, \ 129 .eint_offset = offs, \ 130 .name = id \ 131 } 132 133 #define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs) \ 134 { \ 135 .type = &exynos850_bank_type_alive, \ 136 .pctl_offset = reg, \ 137 .nr_pins = pins, \ 138 .eint_type = EINT_TYPE_WKUP, \ 139 .eint_offset = offs, \ 140 .name = id \ 141 } 142 143 /** 144 * struct exynos_weint_data: irq specific data for all the wakeup interrupts 145 * generated by the external wakeup interrupt controller. 146 * @irq: interrupt number within the domain. 147 * @bank: bank responsible for this interrupt 148 */ 149 struct exynos_weint_data { 150 unsigned int irq; 151 struct samsung_pin_bank *bank; 152 }; 153 154 /** 155 * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts 156 * generated by the external wakeup interrupt controller. 157 * @nr_banks: count of banks being part of the mux 158 * @banks: array of banks being part of the mux 159 */ 160 struct exynos_muxed_weint_data { 161 unsigned int nr_banks; 162 struct samsung_pin_bank *banks[] __counted_by(nr_banks); 163 }; 164 165 int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d); 166 int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d); 167 void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata); 168 void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata); 169 struct samsung_retention_ctrl * 170 exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, 171 const struct samsung_retention_data *data); 172 173 #endif /* __PINCTRL_SAMSUNG_EXYNOS_H */ 174