1 /* 2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. 3 * 4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * Copyright (c) 2012 Linaro Ltd 7 * http://www.linaro.org 8 * 9 * Author: Thomas Abraham <thomas.ab@samsung.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This file contains the Samsung Exynos specific information required by the 17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of 18 * external gpio and wakeup interrupt support. 19 */ 20 21 #include <linux/module.h> 22 #include <linux/device.h> 23 #include <linux/interrupt.h> 24 #include <linux/irqdomain.h> 25 #include <linux/irq.h> 26 #include <linux/irqchip/chained_irq.h> 27 #include <linux/of_irq.h> 28 #include <linux/io.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/err.h> 32 33 #include "pinctrl-samsung.h" 34 #include "pinctrl-exynos.h" 35 36 struct exynos_irq_chip { 37 struct irq_chip chip; 38 39 u32 eint_con; 40 u32 eint_mask; 41 u32 eint_pend; 42 }; 43 44 static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip) 45 { 46 return container_of(chip, struct exynos_irq_chip, chip); 47 } 48 49 static const struct samsung_pin_bank_type bank_type_off = { 50 .fld_width = { 4, 1, 2, 2, 2, 2, }, 51 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 52 }; 53 54 static const struct samsung_pin_bank_type bank_type_alive = { 55 .fld_width = { 4, 1, 2, 2, }, 56 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 57 }; 58 59 static void exynos_irq_mask(struct irq_data *irqd) 60 { 61 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 62 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 63 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 64 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; 65 unsigned long mask; 66 unsigned long flags; 67 68 spin_lock_irqsave(&bank->slock, flags); 69 70 mask = readl(bank->eint_base + reg_mask); 71 mask |= 1 << irqd->hwirq; 72 writel(mask, bank->eint_base + reg_mask); 73 74 spin_unlock_irqrestore(&bank->slock, flags); 75 } 76 77 static void exynos_irq_ack(struct irq_data *irqd) 78 { 79 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 80 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 81 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 82 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; 83 84 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); 85 } 86 87 static void exynos_irq_unmask(struct irq_data *irqd) 88 { 89 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 90 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 91 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 92 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; 93 unsigned long mask; 94 unsigned long flags; 95 96 /* 97 * Ack level interrupts right before unmask 98 * 99 * If we don't do this we'll get a double-interrupt. Level triggered 100 * interrupts must not fire an interrupt if the level is not 101 * _currently_ active, even if it was active while the interrupt was 102 * masked. 103 */ 104 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) 105 exynos_irq_ack(irqd); 106 107 spin_lock_irqsave(&bank->slock, flags); 108 109 mask = readl(bank->eint_base + reg_mask); 110 mask &= ~(1 << irqd->hwirq); 111 writel(mask, bank->eint_base + reg_mask); 112 113 spin_unlock_irqrestore(&bank->slock, flags); 114 } 115 116 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) 117 { 118 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 119 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 120 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 121 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; 122 unsigned int con, trig_type; 123 unsigned long reg_con = our_chip->eint_con + bank->eint_offset; 124 125 switch (type) { 126 case IRQ_TYPE_EDGE_RISING: 127 trig_type = EXYNOS_EINT_EDGE_RISING; 128 break; 129 case IRQ_TYPE_EDGE_FALLING: 130 trig_type = EXYNOS_EINT_EDGE_FALLING; 131 break; 132 case IRQ_TYPE_EDGE_BOTH: 133 trig_type = EXYNOS_EINT_EDGE_BOTH; 134 break; 135 case IRQ_TYPE_LEVEL_HIGH: 136 trig_type = EXYNOS_EINT_LEVEL_HIGH; 137 break; 138 case IRQ_TYPE_LEVEL_LOW: 139 trig_type = EXYNOS_EINT_LEVEL_LOW; 140 break; 141 default: 142 pr_err("unsupported external interrupt type\n"); 143 return -EINVAL; 144 } 145 146 if (type & IRQ_TYPE_EDGE_BOTH) 147 irq_set_handler_locked(irqd, handle_edge_irq); 148 else 149 irq_set_handler_locked(irqd, handle_level_irq); 150 151 con = readl(bank->eint_base + reg_con); 152 con &= ~(EXYNOS_EINT_CON_MASK << shift); 153 con |= trig_type << shift; 154 writel(con, bank->eint_base + reg_con); 155 156 return 0; 157 } 158 159 static int exynos_irq_request_resources(struct irq_data *irqd) 160 { 161 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 162 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 163 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 164 const struct samsung_pin_bank_type *bank_type = bank->type; 165 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; 166 unsigned long reg_con = our_chip->eint_con + bank->eint_offset; 167 unsigned long flags; 168 unsigned int mask; 169 unsigned int con; 170 int ret; 171 172 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); 173 if (ret) { 174 dev_err(bank->gpio_chip.parent, 175 "unable to lock pin %s-%lu IRQ\n", 176 bank->name, irqd->hwirq); 177 return ret; 178 } 179 180 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; 181 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; 182 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; 183 184 spin_lock_irqsave(&bank->slock, flags); 185 186 con = readl(bank->eint_base + reg_con); 187 con &= ~(mask << shift); 188 con |= EXYNOS_EINT_FUNC << shift; 189 writel(con, bank->eint_base + reg_con); 190 191 spin_unlock_irqrestore(&bank->slock, flags); 192 193 exynos_irq_unmask(irqd); 194 195 return 0; 196 } 197 198 static void exynos_irq_release_resources(struct irq_data *irqd) 199 { 200 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 201 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 202 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 203 const struct samsung_pin_bank_type *bank_type = bank->type; 204 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; 205 unsigned long reg_con = our_chip->eint_con + bank->eint_offset; 206 unsigned long flags; 207 unsigned int mask; 208 unsigned int con; 209 210 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; 211 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; 212 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; 213 214 exynos_irq_mask(irqd); 215 216 spin_lock_irqsave(&bank->slock, flags); 217 218 con = readl(bank->eint_base + reg_con); 219 con &= ~(mask << shift); 220 con |= FUNC_INPUT << shift; 221 writel(con, bank->eint_base + reg_con); 222 223 spin_unlock_irqrestore(&bank->slock, flags); 224 225 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); 226 } 227 228 /* 229 * irq_chip for gpio interrupts. 230 */ 231 static struct exynos_irq_chip exynos_gpio_irq_chip = { 232 .chip = { 233 .name = "exynos_gpio_irq_chip", 234 .irq_unmask = exynos_irq_unmask, 235 .irq_mask = exynos_irq_mask, 236 .irq_ack = exynos_irq_ack, 237 .irq_set_type = exynos_irq_set_type, 238 .irq_request_resources = exynos_irq_request_resources, 239 .irq_release_resources = exynos_irq_release_resources, 240 }, 241 .eint_con = EXYNOS_GPIO_ECON_OFFSET, 242 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET, 243 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET, 244 }; 245 246 static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq, 247 irq_hw_number_t hw) 248 { 249 struct samsung_pin_bank *b = h->host_data; 250 251 irq_set_chip_data(virq, b); 252 irq_set_chip_and_handler(virq, &b->irq_chip->chip, 253 handle_level_irq); 254 return 0; 255 } 256 257 /* 258 * irq domain callbacks for external gpio and wakeup interrupt controllers. 259 */ 260 static const struct irq_domain_ops exynos_eint_irqd_ops = { 261 .map = exynos_eint_irq_map, 262 .xlate = irq_domain_xlate_twocell, 263 }; 264 265 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) 266 { 267 struct samsung_pinctrl_drv_data *d = data; 268 struct samsung_pin_bank *bank = d->pin_banks; 269 unsigned int svc, group, pin, virq; 270 271 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); 272 group = EXYNOS_SVC_GROUP(svc); 273 pin = svc & EXYNOS_SVC_NUM_MASK; 274 275 if (!group) 276 return IRQ_HANDLED; 277 bank += (group - 1); 278 279 virq = irq_linear_revmap(bank->irq_domain, pin); 280 if (!virq) 281 return IRQ_NONE; 282 generic_handle_irq(virq); 283 return IRQ_HANDLED; 284 } 285 286 struct exynos_eint_gpio_save { 287 u32 eint_con; 288 u32 eint_fltcon0; 289 u32 eint_fltcon1; 290 }; 291 292 /* 293 * exynos_eint_gpio_init() - setup handling of external gpio interrupts. 294 * @d: driver data of samsung pinctrl driver. 295 */ 296 static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) 297 { 298 struct samsung_pin_bank *bank; 299 struct device *dev = d->dev; 300 int ret; 301 int i; 302 303 if (!d->irq) { 304 dev_err(dev, "irq number not available\n"); 305 return -EINVAL; 306 } 307 308 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, 309 0, dev_name(dev), d); 310 if (ret) { 311 dev_err(dev, "irq request failed\n"); 312 return -ENXIO; 313 } 314 315 bank = d->pin_banks; 316 for (i = 0; i < d->nr_banks; ++i, ++bank) { 317 if (bank->eint_type != EINT_TYPE_GPIO) 318 continue; 319 bank->irq_domain = irq_domain_add_linear(bank->of_node, 320 bank->nr_pins, &exynos_eint_irqd_ops, bank); 321 if (!bank->irq_domain) { 322 dev_err(dev, "gpio irq domain add failed\n"); 323 ret = -ENXIO; 324 goto err_domains; 325 } 326 327 bank->soc_priv = devm_kzalloc(d->dev, 328 sizeof(struct exynos_eint_gpio_save), GFP_KERNEL); 329 if (!bank->soc_priv) { 330 irq_domain_remove(bank->irq_domain); 331 ret = -ENOMEM; 332 goto err_domains; 333 } 334 335 bank->irq_chip = &exynos_gpio_irq_chip; 336 } 337 338 return 0; 339 340 err_domains: 341 for (--i, --bank; i >= 0; --i, --bank) { 342 if (bank->eint_type != EINT_TYPE_GPIO) 343 continue; 344 irq_domain_remove(bank->irq_domain); 345 } 346 347 return ret; 348 } 349 350 static u32 exynos_eint_wake_mask = 0xffffffff; 351 352 u32 exynos_get_eint_wake_mask(void) 353 { 354 return exynos_eint_wake_mask; 355 } 356 357 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) 358 { 359 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 360 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); 361 362 pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq); 363 364 if (!on) 365 exynos_eint_wake_mask |= bit; 366 else 367 exynos_eint_wake_mask &= ~bit; 368 369 return 0; 370 } 371 372 /* 373 * irq_chip for wakeup interrupts 374 */ 375 static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = { 376 .chip = { 377 .name = "exynos4210_wkup_irq_chip", 378 .irq_unmask = exynos_irq_unmask, 379 .irq_mask = exynos_irq_mask, 380 .irq_ack = exynos_irq_ack, 381 .irq_set_type = exynos_irq_set_type, 382 .irq_set_wake = exynos_wkup_irq_set_wake, 383 .irq_request_resources = exynos_irq_request_resources, 384 .irq_release_resources = exynos_irq_release_resources, 385 }, 386 .eint_con = EXYNOS_WKUP_ECON_OFFSET, 387 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, 388 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, 389 }; 390 391 static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = { 392 .chip = { 393 .name = "exynos7_wkup_irq_chip", 394 .irq_unmask = exynos_irq_unmask, 395 .irq_mask = exynos_irq_mask, 396 .irq_ack = exynos_irq_ack, 397 .irq_set_type = exynos_irq_set_type, 398 .irq_set_wake = exynos_wkup_irq_set_wake, 399 .irq_request_resources = exynos_irq_request_resources, 400 .irq_release_resources = exynos_irq_release_resources, 401 }, 402 .eint_con = EXYNOS7_WKUP_ECON_OFFSET, 403 .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET, 404 .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET, 405 }; 406 407 /* list of external wakeup controllers supported */ 408 static const struct of_device_id exynos_wkup_irq_ids[] = { 409 { .compatible = "samsung,exynos4210-wakeup-eint", 410 .data = &exynos4210_wkup_irq_chip }, 411 { .compatible = "samsung,exynos7-wakeup-eint", 412 .data = &exynos7_wkup_irq_chip }, 413 { } 414 }; 415 416 /* interrupt handler for wakeup interrupts 0..15 */ 417 static void exynos_irq_eint0_15(struct irq_desc *desc) 418 { 419 struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc); 420 struct samsung_pin_bank *bank = eintd->bank; 421 struct irq_chip *chip = irq_desc_get_chip(desc); 422 int eint_irq; 423 424 chained_irq_enter(chip, desc); 425 426 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq); 427 generic_handle_irq(eint_irq); 428 429 chained_irq_exit(chip, desc); 430 } 431 432 static inline void exynos_irq_demux_eint(unsigned long pend, 433 struct irq_domain *domain) 434 { 435 unsigned int irq; 436 437 while (pend) { 438 irq = fls(pend) - 1; 439 generic_handle_irq(irq_find_mapping(domain, irq)); 440 pend &= ~(1 << irq); 441 } 442 } 443 444 /* interrupt handler for wakeup interrupt 16 */ 445 static void exynos_irq_demux_eint16_31(struct irq_desc *desc) 446 { 447 struct irq_chip *chip = irq_desc_get_chip(desc); 448 struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc); 449 unsigned long pend; 450 unsigned long mask; 451 int i; 452 453 chained_irq_enter(chip, desc); 454 455 for (i = 0; i < eintd->nr_banks; ++i) { 456 struct samsung_pin_bank *b = eintd->banks[i]; 457 pend = readl(b->eint_base + b->irq_chip->eint_pend 458 + b->eint_offset); 459 mask = readl(b->eint_base + b->irq_chip->eint_mask 460 + b->eint_offset); 461 exynos_irq_demux_eint(pend & ~mask, b->irq_domain); 462 } 463 464 chained_irq_exit(chip, desc); 465 } 466 467 /* 468 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. 469 * @d: driver data of samsung pinctrl driver. 470 */ 471 static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) 472 { 473 struct device *dev = d->dev; 474 struct device_node *wkup_np = NULL; 475 struct device_node *np; 476 struct samsung_pin_bank *bank; 477 struct exynos_weint_data *weint_data; 478 struct exynos_muxed_weint_data *muxed_data; 479 struct exynos_irq_chip *irq_chip; 480 unsigned int muxed_banks = 0; 481 unsigned int i; 482 int idx, irq; 483 484 for_each_child_of_node(dev->of_node, np) { 485 const struct of_device_id *match; 486 487 match = of_match_node(exynos_wkup_irq_ids, np); 488 if (match) { 489 irq_chip = kmemdup(match->data, 490 sizeof(*irq_chip), GFP_KERNEL); 491 wkup_np = np; 492 break; 493 } 494 } 495 if (!wkup_np) 496 return -ENODEV; 497 498 bank = d->pin_banks; 499 for (i = 0; i < d->nr_banks; ++i, ++bank) { 500 if (bank->eint_type != EINT_TYPE_WKUP) 501 continue; 502 503 bank->irq_domain = irq_domain_add_linear(bank->of_node, 504 bank->nr_pins, &exynos_eint_irqd_ops, bank); 505 if (!bank->irq_domain) { 506 dev_err(dev, "wkup irq domain add failed\n"); 507 return -ENXIO; 508 } 509 510 bank->irq_chip = irq_chip; 511 512 if (!of_find_property(bank->of_node, "interrupts", NULL)) { 513 bank->eint_type = EINT_TYPE_WKUP_MUX; 514 ++muxed_banks; 515 continue; 516 } 517 518 weint_data = devm_kzalloc(dev, bank->nr_pins 519 * sizeof(*weint_data), GFP_KERNEL); 520 if (!weint_data) { 521 dev_err(dev, "could not allocate memory for weint_data\n"); 522 return -ENOMEM; 523 } 524 525 for (idx = 0; idx < bank->nr_pins; ++idx) { 526 irq = irq_of_parse_and_map(bank->of_node, idx); 527 if (!irq) { 528 dev_err(dev, "irq number for eint-%s-%d not found\n", 529 bank->name, idx); 530 continue; 531 } 532 weint_data[idx].irq = idx; 533 weint_data[idx].bank = bank; 534 irq_set_chained_handler_and_data(irq, 535 exynos_irq_eint0_15, 536 &weint_data[idx]); 537 } 538 } 539 540 if (!muxed_banks) 541 return 0; 542 543 irq = irq_of_parse_and_map(wkup_np, 0); 544 if (!irq) { 545 dev_err(dev, "irq number for muxed EINTs not found\n"); 546 return 0; 547 } 548 549 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data) 550 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL); 551 if (!muxed_data) { 552 dev_err(dev, "could not allocate memory for muxed_data\n"); 553 return -ENOMEM; 554 } 555 556 irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31, 557 muxed_data); 558 559 bank = d->pin_banks; 560 idx = 0; 561 for (i = 0; i < d->nr_banks; ++i, ++bank) { 562 if (bank->eint_type != EINT_TYPE_WKUP_MUX) 563 continue; 564 565 muxed_data->banks[idx++] = bank; 566 } 567 muxed_data->nr_banks = muxed_banks; 568 569 return 0; 570 } 571 572 static void exynos_pinctrl_suspend_bank( 573 struct samsung_pinctrl_drv_data *drvdata, 574 struct samsung_pin_bank *bank) 575 { 576 struct exynos_eint_gpio_save *save = bank->soc_priv; 577 void __iomem *regs = bank->eint_base; 578 579 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET 580 + bank->eint_offset); 581 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 582 + 2 * bank->eint_offset); 583 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 584 + 2 * bank->eint_offset + 4); 585 586 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); 587 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); 588 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); 589 } 590 591 static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) 592 { 593 struct samsung_pin_bank *bank = drvdata->pin_banks; 594 int i; 595 596 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) 597 if (bank->eint_type == EINT_TYPE_GPIO) 598 exynos_pinctrl_suspend_bank(drvdata, bank); 599 } 600 601 static void exynos_pinctrl_resume_bank( 602 struct samsung_pinctrl_drv_data *drvdata, 603 struct samsung_pin_bank *bank) 604 { 605 struct exynos_eint_gpio_save *save = bank->soc_priv; 606 void __iomem *regs = bank->eint_base; 607 608 pr_debug("%s: con %#010x => %#010x\n", bank->name, 609 readl(regs + EXYNOS_GPIO_ECON_OFFSET 610 + bank->eint_offset), save->eint_con); 611 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, 612 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 613 + 2 * bank->eint_offset), save->eint_fltcon0); 614 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, 615 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET 616 + 2 * bank->eint_offset + 4), save->eint_fltcon1); 617 618 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET 619 + bank->eint_offset); 620 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET 621 + 2 * bank->eint_offset); 622 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET 623 + 2 * bank->eint_offset + 4); 624 } 625 626 static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) 627 { 628 struct samsung_pin_bank *bank = drvdata->pin_banks; 629 int i; 630 631 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) 632 if (bank->eint_type == EINT_TYPE_GPIO) 633 exynos_pinctrl_resume_bank(drvdata, bank); 634 } 635 636 /* pin banks of s5pv210 pin-controller */ 637 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = { 638 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 639 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04), 640 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 641 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 642 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 643 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 644 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), 645 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c), 646 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20), 647 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24), 648 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28), 649 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c), 650 EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30), 651 EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34), 652 EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38), 653 EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c), 654 EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40), 655 EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"), 656 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44), 657 EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48), 658 EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c), 659 EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50), 660 EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54), 661 EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"), 662 EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"), 663 EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"), 664 EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"), 665 EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"), 666 EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"), 667 EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"), 668 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00), 669 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04), 670 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08), 671 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c), 672 }; 673 674 const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = { 675 { 676 /* pin-controller instance 0 data */ 677 .pin_banks = s5pv210_pin_bank, 678 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank), 679 .eint_gpio_init = exynos_eint_gpio_init, 680 .eint_wkup_init = exynos_eint_wkup_init, 681 .suspend = exynos_pinctrl_suspend, 682 .resume = exynos_pinctrl_resume, 683 }, 684 }; 685 686 /* pin banks of exynos3250 pin-controller 0 */ 687 static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = { 688 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 689 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 690 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 691 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 692 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 693 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 694 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18), 695 }; 696 697 /* pin banks of exynos3250 pin-controller 1 */ 698 static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = { 699 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"), 700 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"), 701 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"), 702 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08), 703 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 704 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 705 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18), 706 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), 707 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), 708 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c), 709 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30), 710 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34), 711 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), 712 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), 713 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), 714 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), 715 }; 716 717 /* 718 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes 719 * two gpio/pin-mux/pinconfig controllers. 720 */ 721 const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = { 722 { 723 /* pin-controller instance 0 data */ 724 .pin_banks = exynos3250_pin_banks0, 725 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0), 726 .eint_gpio_init = exynos_eint_gpio_init, 727 .suspend = exynos_pinctrl_suspend, 728 .resume = exynos_pinctrl_resume, 729 }, { 730 /* pin-controller instance 1 data */ 731 .pin_banks = exynos3250_pin_banks1, 732 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1), 733 .eint_gpio_init = exynos_eint_gpio_init, 734 .eint_wkup_init = exynos_eint_wkup_init, 735 .suspend = exynos_pinctrl_suspend, 736 .resume = exynos_pinctrl_resume, 737 }, 738 }; 739 740 /* pin banks of exynos4210 pin-controller 0 */ 741 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = { 742 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 743 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 744 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 745 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 746 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 747 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 748 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), 749 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c), 750 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), 751 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24), 752 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28), 753 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c), 754 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), 755 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), 756 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), 757 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), 758 }; 759 760 /* pin banks of exynos4210 pin-controller 1 */ 761 static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = { 762 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), 763 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), 764 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), 765 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 766 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 767 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), 768 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18), 769 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c), 770 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), 771 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), 772 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), 773 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), 774 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), 775 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), 776 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), 777 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), 778 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 779 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 780 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 781 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 782 }; 783 784 /* pin banks of exynos4210 pin-controller 2 */ 785 static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = { 786 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), 787 }; 788 789 /* 790 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes 791 * three gpio/pin-mux/pinconfig controllers. 792 */ 793 const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = { 794 { 795 /* pin-controller instance 0 data */ 796 .pin_banks = exynos4210_pin_banks0, 797 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), 798 .eint_gpio_init = exynos_eint_gpio_init, 799 .suspend = exynos_pinctrl_suspend, 800 .resume = exynos_pinctrl_resume, 801 }, { 802 /* pin-controller instance 1 data */ 803 .pin_banks = exynos4210_pin_banks1, 804 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), 805 .eint_gpio_init = exynos_eint_gpio_init, 806 .eint_wkup_init = exynos_eint_wkup_init, 807 .suspend = exynos_pinctrl_suspend, 808 .resume = exynos_pinctrl_resume, 809 }, { 810 /* pin-controller instance 2 data */ 811 .pin_banks = exynos4210_pin_banks2, 812 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), 813 }, 814 }; 815 816 /* pin banks of exynos4x12 pin-controller 0 */ 817 static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = { 818 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 819 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 820 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 821 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 822 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 823 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 824 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), 825 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), 826 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), 827 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), 828 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), 829 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40), 830 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44), 831 }; 832 833 /* pin banks of exynos4x12 pin-controller 1 */ 834 static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = { 835 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), 836 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 837 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 838 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), 839 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18), 840 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c), 841 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), 842 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), 843 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), 844 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), 845 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), 846 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), 847 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), 848 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), 849 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), 850 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), 851 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), 852 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), 853 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), 854 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 855 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 856 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 857 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 858 }; 859 860 /* pin banks of exynos4x12 pin-controller 2 */ 861 static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = { 862 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 863 }; 864 865 /* pin banks of exynos4x12 pin-controller 3 */ 866 static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = { 867 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 868 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 869 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08), 870 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c), 871 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10), 872 }; 873 874 /* 875 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes 876 * four gpio/pin-mux/pinconfig controllers. 877 */ 878 const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { 879 { 880 /* pin-controller instance 0 data */ 881 .pin_banks = exynos4x12_pin_banks0, 882 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), 883 .eint_gpio_init = exynos_eint_gpio_init, 884 .suspend = exynos_pinctrl_suspend, 885 .resume = exynos_pinctrl_resume, 886 }, { 887 /* pin-controller instance 1 data */ 888 .pin_banks = exynos4x12_pin_banks1, 889 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), 890 .eint_gpio_init = exynos_eint_gpio_init, 891 .eint_wkup_init = exynos_eint_wkup_init, 892 .suspend = exynos_pinctrl_suspend, 893 .resume = exynos_pinctrl_resume, 894 }, { 895 /* pin-controller instance 2 data */ 896 .pin_banks = exynos4x12_pin_banks2, 897 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), 898 .eint_gpio_init = exynos_eint_gpio_init, 899 .suspend = exynos_pinctrl_suspend, 900 .resume = exynos_pinctrl_resume, 901 }, { 902 /* pin-controller instance 3 data */ 903 .pin_banks = exynos4x12_pin_banks3, 904 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), 905 .eint_gpio_init = exynos_eint_gpio_init, 906 .suspend = exynos_pinctrl_suspend, 907 .resume = exynos_pinctrl_resume, 908 }, 909 }; 910 911 /* pin banks of exynos4415 pin-controller 0 */ 912 static const struct samsung_pin_bank_data exynos4415_pin_banks0[] = { 913 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 914 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 915 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 916 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 917 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 918 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 919 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), 920 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), 921 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), 922 EXYNOS_PIN_BANK_EINTG(1, 0x1C0, "gpf2", 0x38), 923 }; 924 925 /* pin banks of exynos4415 pin-controller 1 */ 926 static const struct samsung_pin_bank_data exynos4415_pin_banks1[] = { 927 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08), 928 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 929 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 930 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), 931 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpl0", 0x18), 932 EXYNOS_PIN_BANK_EINTN(6, 0x120, "mp00"), 933 EXYNOS_PIN_BANK_EINTN(4, 0x140, "mp01"), 934 EXYNOS_PIN_BANK_EINTN(6, 0x160, "mp02"), 935 EXYNOS_PIN_BANK_EINTN(8, 0x180, "mp03"), 936 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "mp04"), 937 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "mp05"), 938 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "mp06"), 939 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), 940 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), 941 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), 942 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), 943 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), 944 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 945 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 946 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 947 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 948 }; 949 950 /* pin banks of exynos4415 pin-controller 2 */ 951 static const struct samsung_pin_bank_data exynos4415_pin_banks2[] = { 952 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 953 EXYNOS_PIN_BANK_EINTN(2, 0x000, "etc1"), 954 }; 955 956 /* 957 * Samsung pinctrl driver data for Exynos4415 SoC. Exynos4415 SoC includes 958 * three gpio/pin-mux/pinconfig controllers. 959 */ 960 const struct samsung_pin_ctrl exynos4415_pin_ctrl[] = { 961 { 962 /* pin-controller instance 0 data */ 963 .pin_banks = exynos4415_pin_banks0, 964 .nr_banks = ARRAY_SIZE(exynos4415_pin_banks0), 965 .eint_gpio_init = exynos_eint_gpio_init, 966 .suspend = exynos_pinctrl_suspend, 967 .resume = exynos_pinctrl_resume, 968 }, { 969 /* pin-controller instance 1 data */ 970 .pin_banks = exynos4415_pin_banks1, 971 .nr_banks = ARRAY_SIZE(exynos4415_pin_banks1), 972 .eint_gpio_init = exynos_eint_gpio_init, 973 .eint_wkup_init = exynos_eint_wkup_init, 974 .suspend = exynos_pinctrl_suspend, 975 .resume = exynos_pinctrl_resume, 976 }, { 977 /* pin-controller instance 2 data */ 978 .pin_banks = exynos4415_pin_banks2, 979 .nr_banks = ARRAY_SIZE(exynos4415_pin_banks2), 980 .eint_gpio_init = exynos_eint_gpio_init, 981 .suspend = exynos_pinctrl_suspend, 982 .resume = exynos_pinctrl_resume, 983 }, 984 }; 985 986 /* pin banks of exynos5250 pin-controller 0 */ 987 static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = { 988 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 989 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 990 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 991 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 992 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), 993 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), 994 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), 995 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), 996 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20), 997 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24), 998 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28), 999 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c), 1000 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30), 1001 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34), 1002 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"), 1003 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"), 1004 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"), 1005 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"), 1006 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"), 1007 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"), 1008 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"), 1009 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 1010 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 1011 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 1012 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 1013 }; 1014 1015 /* pin banks of exynos5250 pin-controller 1 */ 1016 static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = { 1017 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), 1018 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), 1019 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08), 1020 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c), 1021 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), 1022 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), 1023 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), 1024 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c), 1025 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20), 1026 }; 1027 1028 /* pin banks of exynos5250 pin-controller 2 */ 1029 static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = { 1030 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 1031 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 1032 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), 1033 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), 1034 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), 1035 }; 1036 1037 /* pin banks of exynos5250 pin-controller 3 */ 1038 static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = { 1039 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 1040 }; 1041 1042 /* 1043 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes 1044 * four gpio/pin-mux/pinconfig controllers. 1045 */ 1046 const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { 1047 { 1048 /* pin-controller instance 0 data */ 1049 .pin_banks = exynos5250_pin_banks0, 1050 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), 1051 .eint_gpio_init = exynos_eint_gpio_init, 1052 .eint_wkup_init = exynos_eint_wkup_init, 1053 .suspend = exynos_pinctrl_suspend, 1054 .resume = exynos_pinctrl_resume, 1055 }, { 1056 /* pin-controller instance 1 data */ 1057 .pin_banks = exynos5250_pin_banks1, 1058 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), 1059 .eint_gpio_init = exynos_eint_gpio_init, 1060 .suspend = exynos_pinctrl_suspend, 1061 .resume = exynos_pinctrl_resume, 1062 }, { 1063 /* pin-controller instance 2 data */ 1064 .pin_banks = exynos5250_pin_banks2, 1065 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), 1066 .eint_gpio_init = exynos_eint_gpio_init, 1067 .suspend = exynos_pinctrl_suspend, 1068 .resume = exynos_pinctrl_resume, 1069 }, { 1070 /* pin-controller instance 3 data */ 1071 .pin_banks = exynos5250_pin_banks3, 1072 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), 1073 .eint_gpio_init = exynos_eint_gpio_init, 1074 .suspend = exynos_pinctrl_suspend, 1075 .resume = exynos_pinctrl_resume, 1076 }, 1077 }; 1078 1079 /* pin banks of exynos5260 pin-controller 0 */ 1080 static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = { 1081 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), 1082 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), 1083 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1084 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 1085 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), 1086 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14), 1087 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18), 1088 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c), 1089 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), 1090 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), 1091 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), 1092 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), 1093 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), 1094 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34), 1095 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), 1096 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c), 1097 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), 1098 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), 1099 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), 1100 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), 1101 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), 1102 }; 1103 1104 /* pin banks of exynos5260 pin-controller 1 */ 1105 static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = { 1106 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), 1107 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), 1108 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), 1109 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), 1110 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), 1111 }; 1112 1113 /* pin banks of exynos5260 pin-controller 2 */ 1114 static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = { 1115 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 1116 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 1117 }; 1118 1119 /* 1120 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes 1121 * three gpio/pin-mux/pinconfig controllers. 1122 */ 1123 const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { 1124 { 1125 /* pin-controller instance 0 data */ 1126 .pin_banks = exynos5260_pin_banks0, 1127 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), 1128 .eint_gpio_init = exynos_eint_gpio_init, 1129 .eint_wkup_init = exynos_eint_wkup_init, 1130 }, { 1131 /* pin-controller instance 1 data */ 1132 .pin_banks = exynos5260_pin_banks1, 1133 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), 1134 .eint_gpio_init = exynos_eint_gpio_init, 1135 }, { 1136 /* pin-controller instance 2 data */ 1137 .pin_banks = exynos5260_pin_banks2, 1138 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), 1139 .eint_gpio_init = exynos_eint_gpio_init, 1140 }, 1141 }; 1142 1143 /* pin banks of exynos5410 pin-controller 0 */ 1144 static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = { 1145 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 1146 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 1147 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1148 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 1149 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), 1150 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), 1151 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), 1152 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), 1153 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20), 1154 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24), 1155 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28), 1156 EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"), 1157 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c), 1158 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30), 1159 EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34), 1160 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38), 1161 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c), 1162 EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40), 1163 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44), 1164 EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48), 1165 EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c), 1166 EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50), 1167 EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"), 1168 EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"), 1169 EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"), 1170 EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"), 1171 EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"), 1172 EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"), 1173 EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"), 1174 EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"), 1175 EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"), 1176 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 1177 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 1178 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 1179 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 1180 }; 1181 1182 /* pin banks of exynos5410 pin-controller 1 */ 1183 static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = { 1184 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00), 1185 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04), 1186 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08), 1187 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c), 1188 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10), 1189 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14), 1190 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18), 1191 EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c), 1192 EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20), 1193 }; 1194 1195 /* pin banks of exynos5410 pin-controller 2 */ 1196 static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = { 1197 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 1198 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 1199 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), 1200 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), 1201 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), 1202 }; 1203 1204 /* pin banks of exynos5410 pin-controller 3 */ 1205 static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = { 1206 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 1207 }; 1208 1209 /* 1210 * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes 1211 * four gpio/pin-mux/pinconfig controllers. 1212 */ 1213 const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = { 1214 { 1215 /* pin-controller instance 0 data */ 1216 .pin_banks = exynos5410_pin_banks0, 1217 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0), 1218 .eint_gpio_init = exynos_eint_gpio_init, 1219 .eint_wkup_init = exynos_eint_wkup_init, 1220 .suspend = exynos_pinctrl_suspend, 1221 .resume = exynos_pinctrl_resume, 1222 }, { 1223 /* pin-controller instance 1 data */ 1224 .pin_banks = exynos5410_pin_banks1, 1225 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1), 1226 .eint_gpio_init = exynos_eint_gpio_init, 1227 .suspend = exynos_pinctrl_suspend, 1228 .resume = exynos_pinctrl_resume, 1229 }, { 1230 /* pin-controller instance 2 data */ 1231 .pin_banks = exynos5410_pin_banks2, 1232 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2), 1233 .eint_gpio_init = exynos_eint_gpio_init, 1234 .suspend = exynos_pinctrl_suspend, 1235 .resume = exynos_pinctrl_resume, 1236 }, { 1237 /* pin-controller instance 3 data */ 1238 .pin_banks = exynos5410_pin_banks3, 1239 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3), 1240 .eint_gpio_init = exynos_eint_gpio_init, 1241 .suspend = exynos_pinctrl_suspend, 1242 .resume = exynos_pinctrl_resume, 1243 }, 1244 }; 1245 1246 /* pin banks of exynos5420 pin-controller 0 */ 1247 static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = { 1248 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), 1249 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 1250 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 1251 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 1252 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 1253 }; 1254 1255 /* pin banks of exynos5420 pin-controller 1 */ 1256 static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = { 1257 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), 1258 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), 1259 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), 1260 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), 1261 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10), 1262 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14), 1263 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"), 1264 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"), 1265 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"), 1266 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"), 1267 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"), 1268 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"), 1269 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"), 1270 }; 1271 1272 /* pin banks of exynos5420 pin-controller 2 */ 1273 static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = { 1274 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), 1275 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), 1276 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08), 1277 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c), 1278 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), 1279 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), 1280 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), 1281 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c), 1282 }; 1283 1284 /* pin banks of exynos5420 pin-controller 3 */ 1285 static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = { 1286 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 1287 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 1288 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1289 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 1290 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), 1291 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), 1292 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), 1293 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c), 1294 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20), 1295 }; 1296 1297 /* pin banks of exynos5420 pin-controller 4 */ 1298 static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = { 1299 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 1300 }; 1301 1302 /* 1303 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes 1304 * four gpio/pin-mux/pinconfig controllers. 1305 */ 1306 const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { 1307 { 1308 /* pin-controller instance 0 data */ 1309 .pin_banks = exynos5420_pin_banks0, 1310 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), 1311 .eint_gpio_init = exynos_eint_gpio_init, 1312 .eint_wkup_init = exynos_eint_wkup_init, 1313 }, { 1314 /* pin-controller instance 1 data */ 1315 .pin_banks = exynos5420_pin_banks1, 1316 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), 1317 .eint_gpio_init = exynos_eint_gpio_init, 1318 }, { 1319 /* pin-controller instance 2 data */ 1320 .pin_banks = exynos5420_pin_banks2, 1321 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), 1322 .eint_gpio_init = exynos_eint_gpio_init, 1323 }, { 1324 /* pin-controller instance 3 data */ 1325 .pin_banks = exynos5420_pin_banks3, 1326 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), 1327 .eint_gpio_init = exynos_eint_gpio_init, 1328 }, { 1329 /* pin-controller instance 4 data */ 1330 .pin_banks = exynos5420_pin_banks4, 1331 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), 1332 .eint_gpio_init = exynos_eint_gpio_init, 1333 }, 1334 }; 1335 1336 /* pin banks of exynos5433 pin-controller - ALIVE */ 1337 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = { 1338 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 1339 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 1340 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 1341 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 1342 EXYNOS_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1), 1343 EXYNOS_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1), 1344 EXYNOS_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1), 1345 EXYNOS_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1), 1346 EXYNOS_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1), 1347 }; 1348 1349 /* pin banks of exynos5433 pin-controller - AUD */ 1350 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = { 1351 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 1352 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 1353 }; 1354 1355 /* pin banks of exynos5433 pin-controller - CPIF */ 1356 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = { 1357 EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), 1358 }; 1359 1360 /* pin banks of exynos5433 pin-controller - eSE */ 1361 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = { 1362 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), 1363 }; 1364 1365 /* pin banks of exynos5433 pin-controller - FINGER */ 1366 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = { 1367 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), 1368 }; 1369 1370 /* pin banks of exynos5433 pin-controller - FSYS */ 1371 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = { 1372 EXYNOS_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), 1373 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), 1374 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08), 1375 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c), 1376 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10), 1377 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14), 1378 }; 1379 1380 /* pin banks of exynos5433 pin-controller - IMEM */ 1381 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = { 1382 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), 1383 }; 1384 1385 /* pin banks of exynos5433 pin-controller - NFC */ 1386 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = { 1387 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 1388 }; 1389 1390 /* pin banks of exynos5433 pin-controller - PERIC */ 1391 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = { 1392 EXYNOS_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), 1393 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), 1394 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08), 1395 EXYNOS_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c), 1396 EXYNOS_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10), 1397 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14), 1398 EXYNOS_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18), 1399 EXYNOS_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c), 1400 EXYNOS_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20), 1401 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24), 1402 EXYNOS_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28), 1403 EXYNOS_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c), 1404 EXYNOS_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30), 1405 EXYNOS_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34), 1406 EXYNOS_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38), 1407 EXYNOS_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c), 1408 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), 1409 }; 1410 1411 /* pin banks of exynos5433 pin-controller - TOUCH */ 1412 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = { 1413 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 1414 }; 1415 1416 /* 1417 * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes 1418 * ten gpio/pin-mux/pinconfig controllers. 1419 */ 1420 const struct samsung_pin_ctrl exynos5433_pin_ctrl[] = { 1421 { 1422 /* pin-controller instance 0 data */ 1423 .pin_banks = exynos5433_pin_banks0, 1424 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0), 1425 .eint_wkup_init = exynos_eint_wkup_init, 1426 .suspend = exynos_pinctrl_suspend, 1427 .resume = exynos_pinctrl_resume, 1428 .nr_ext_resources = 1, 1429 }, { 1430 /* pin-controller instance 1 data */ 1431 .pin_banks = exynos5433_pin_banks1, 1432 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1), 1433 .eint_gpio_init = exynos_eint_gpio_init, 1434 .suspend = exynos_pinctrl_suspend, 1435 .resume = exynos_pinctrl_resume, 1436 }, { 1437 /* pin-controller instance 2 data */ 1438 .pin_banks = exynos5433_pin_banks2, 1439 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2), 1440 .eint_gpio_init = exynos_eint_gpio_init, 1441 .suspend = exynos_pinctrl_suspend, 1442 .resume = exynos_pinctrl_resume, 1443 }, { 1444 /* pin-controller instance 3 data */ 1445 .pin_banks = exynos5433_pin_banks3, 1446 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3), 1447 .eint_gpio_init = exynos_eint_gpio_init, 1448 .suspend = exynos_pinctrl_suspend, 1449 .resume = exynos_pinctrl_resume, 1450 }, { 1451 /* pin-controller instance 4 data */ 1452 .pin_banks = exynos5433_pin_banks4, 1453 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4), 1454 .eint_gpio_init = exynos_eint_gpio_init, 1455 .suspend = exynos_pinctrl_suspend, 1456 .resume = exynos_pinctrl_resume, 1457 }, { 1458 /* pin-controller instance 5 data */ 1459 .pin_banks = exynos5433_pin_banks5, 1460 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5), 1461 .eint_gpio_init = exynos_eint_gpio_init, 1462 .suspend = exynos_pinctrl_suspend, 1463 .resume = exynos_pinctrl_resume, 1464 }, { 1465 /* pin-controller instance 6 data */ 1466 .pin_banks = exynos5433_pin_banks6, 1467 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6), 1468 .eint_gpio_init = exynos_eint_gpio_init, 1469 .suspend = exynos_pinctrl_suspend, 1470 .resume = exynos_pinctrl_resume, 1471 }, { 1472 /* pin-controller instance 7 data */ 1473 .pin_banks = exynos5433_pin_banks7, 1474 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7), 1475 .eint_gpio_init = exynos_eint_gpio_init, 1476 .suspend = exynos_pinctrl_suspend, 1477 .resume = exynos_pinctrl_resume, 1478 }, { 1479 /* pin-controller instance 8 data */ 1480 .pin_banks = exynos5433_pin_banks8, 1481 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8), 1482 .eint_gpio_init = exynos_eint_gpio_init, 1483 .suspend = exynos_pinctrl_suspend, 1484 .resume = exynos_pinctrl_resume, 1485 }, { 1486 /* pin-controller instance 9 data */ 1487 .pin_banks = exynos5433_pin_banks9, 1488 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9), 1489 .eint_gpio_init = exynos_eint_gpio_init, 1490 .suspend = exynos_pinctrl_suspend, 1491 .resume = exynos_pinctrl_resume, 1492 }, 1493 }; 1494 1495 /* pin banks of exynos7 pin-controller - ALIVE */ 1496 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { 1497 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 1498 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 1499 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 1500 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 1501 }; 1502 1503 /* pin banks of exynos7 pin-controller - BUS0 */ 1504 static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = { 1505 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 1506 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04), 1507 EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08), 1508 EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c), 1509 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), 1510 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 1511 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), 1512 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c), 1513 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20), 1514 EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24), 1515 EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28), 1516 EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c), 1517 EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30), 1518 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), 1519 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38), 1520 }; 1521 1522 /* pin banks of exynos7 pin-controller - NFC */ 1523 static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = { 1524 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 1525 }; 1526 1527 /* pin banks of exynos7 pin-controller - TOUCH */ 1528 static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = { 1529 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 1530 }; 1531 1532 /* pin banks of exynos7 pin-controller - FF */ 1533 static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = { 1534 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00), 1535 }; 1536 1537 /* pin banks of exynos7 pin-controller - ESE */ 1538 static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = { 1539 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00), 1540 }; 1541 1542 /* pin banks of exynos7 pin-controller - FSYS0 */ 1543 static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = { 1544 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00), 1545 }; 1546 1547 /* pin banks of exynos7 pin-controller - FSYS1 */ 1548 static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = { 1549 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00), 1550 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), 1551 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08), 1552 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c), 1553 }; 1554 1555 /* pin banks of exynos7 pin-controller - BUS1 */ 1556 static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = { 1557 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00), 1558 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04), 1559 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08), 1560 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c), 1561 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10), 1562 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14), 1563 EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18), 1564 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c), 1565 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20), 1566 EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24), 1567 }; 1568 1569 static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = { 1570 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 1571 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 1572 }; 1573 1574 const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { 1575 { 1576 /* pin-controller instance 0 Alive data */ 1577 .pin_banks = exynos7_pin_banks0, 1578 .nr_banks = ARRAY_SIZE(exynos7_pin_banks0), 1579 .eint_wkup_init = exynos_eint_wkup_init, 1580 }, { 1581 /* pin-controller instance 1 BUS0 data */ 1582 .pin_banks = exynos7_pin_banks1, 1583 .nr_banks = ARRAY_SIZE(exynos7_pin_banks1), 1584 .eint_gpio_init = exynos_eint_gpio_init, 1585 }, { 1586 /* pin-controller instance 2 NFC data */ 1587 .pin_banks = exynos7_pin_banks2, 1588 .nr_banks = ARRAY_SIZE(exynos7_pin_banks2), 1589 .eint_gpio_init = exynos_eint_gpio_init, 1590 }, { 1591 /* pin-controller instance 3 TOUCH data */ 1592 .pin_banks = exynos7_pin_banks3, 1593 .nr_banks = ARRAY_SIZE(exynos7_pin_banks3), 1594 .eint_gpio_init = exynos_eint_gpio_init, 1595 }, { 1596 /* pin-controller instance 4 FF data */ 1597 .pin_banks = exynos7_pin_banks4, 1598 .nr_banks = ARRAY_SIZE(exynos7_pin_banks4), 1599 .eint_gpio_init = exynos_eint_gpio_init, 1600 }, { 1601 /* pin-controller instance 5 ESE data */ 1602 .pin_banks = exynos7_pin_banks5, 1603 .nr_banks = ARRAY_SIZE(exynos7_pin_banks5), 1604 .eint_gpio_init = exynos_eint_gpio_init, 1605 }, { 1606 /* pin-controller instance 6 FSYS0 data */ 1607 .pin_banks = exynos7_pin_banks6, 1608 .nr_banks = ARRAY_SIZE(exynos7_pin_banks6), 1609 .eint_gpio_init = exynos_eint_gpio_init, 1610 }, { 1611 /* pin-controller instance 7 FSYS1 data */ 1612 .pin_banks = exynos7_pin_banks7, 1613 .nr_banks = ARRAY_SIZE(exynos7_pin_banks7), 1614 .eint_gpio_init = exynos_eint_gpio_init, 1615 }, { 1616 /* pin-controller instance 8 BUS1 data */ 1617 .pin_banks = exynos7_pin_banks8, 1618 .nr_banks = ARRAY_SIZE(exynos7_pin_banks8), 1619 .eint_gpio_init = exynos_eint_gpio_init, 1620 }, { 1621 /* pin-controller instance 9 AUD data */ 1622 .pin_banks = exynos7_pin_banks9, 1623 .nr_banks = ARRAY_SIZE(exynos7_pin_banks9), 1624 .eint_gpio_init = exynos_eint_gpio_init, 1625 }, 1626 }; 1627