1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver 4 // with eint support. 5 // 6 // Copyright (c) 2012 Samsung Electronics Co., Ltd. 7 // http://www.samsung.com 8 // Copyright (c) 2012 Linaro Ltd 9 // http://www.linaro.org 10 // Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org> 11 // 12 // This file contains the Samsung Exynos specific information required by the 13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of 14 // external gpio and wakeup interrupt support. 15 16 #include <linux/slab.h> 17 #include <linux/soc/samsung/exynos-regs-pmu.h> 18 19 #include "pinctrl-samsung.h" 20 #include "pinctrl-exynos.h" 21 22 static const struct samsung_pin_bank_type bank_type_off = { 23 .fld_width = { 4, 1, 2, 2, 2, 2, }, 24 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 25 }; 26 27 static const struct samsung_pin_bank_type bank_type_alive = { 28 .fld_width = { 4, 1, 2, 2, }, 29 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 30 }; 31 32 /* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */ 33 static const struct samsung_pin_bank_type exynos5433_bank_type_off = { 34 .fld_width = { 4, 1, 2, 4, 2, 2, }, 35 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 36 }; 37 38 static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { 39 .fld_width = { 4, 1, 2, 4, }, 40 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 41 }; 42 43 /* 44 * Bank type for alive type. Bit fields: 45 * CON: 4, DAT: 1, PUD: 2, DRV: 3 46 */ 47 static const struct samsung_pin_bank_type exynos7870_bank_type_alive = { 48 .fld_width = { 4, 1, 2, 3, }, 49 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 50 }; 51 52 /* 53 * Bank type for non-alive type. Bit fields: 54 * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 55 */ 56 static const struct samsung_pin_bank_type exynos850_bank_type_off = { 57 .fld_width = { 4, 1, 4, 4, 2, 4, }, 58 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 59 }; 60 61 /* 62 * Bank type for alive type. Bit fields: 63 * CON: 4, DAT: 1, PUD: 4, DRV: 4 64 */ 65 static const struct samsung_pin_bank_type exynos850_bank_type_alive = { 66 .fld_width = { 4, 1, 4, 4, }, 67 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 68 }; 69 70 /* 71 * Bank type for non-alive type. Bit fields: 72 * CON: 4, DAT: 1, PUD: 2, DRV: 3, CONPDN: 2, PUDPDN: 2 73 */ 74 static const struct samsung_pin_bank_type exynos8895_bank_type_off = { 75 .fld_width = { 4, 1, 2, 3, 2, 2, }, 76 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 77 }; 78 79 /* 80 * Bank type for non-alive type. Bit fields: 81 * CON: 4, DAT: 1, PUD: 4, DRV: 4 82 */ 83 static const struct samsung_pin_bank_type artpec_bank_type_off = { 84 .fld_width = { 4, 1, 4, 4, }, 85 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 86 }; 87 88 /* Pad retention control code for accessing PMU regmap */ 89 static atomic_t exynos_shared_retention_refcnt; 90 91 /* pin banks of exynos2200 pin-controller - ALIVE */ 92 static const struct samsung_pin_bank_data exynos2200_pin_banks0[] __initconst = { 93 EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00), 94 EXYNOS850_PIN_BANK_EINTW(8, 0x20, "gpa1", 0x04), 95 EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa2", 0x08), 96 EXYNOS850_PIN_BANK_EINTW(8, 0x60, "gpa3", 0x0c), 97 EXYNOS850_PIN_BANK_EINTW(2, 0x80, "gpa4", 0x10), 98 EXYNOS_PIN_BANK_EINTN(4, 0xa0, "gpq0"), 99 EXYNOS_PIN_BANK_EINTN(2, 0xc0, "gpq1"), 100 EXYNOS_PIN_BANK_EINTN(2, 0xe0, "gpq2"), 101 }; 102 103 /* pin banks of exynos2200 pin-controller - CMGP */ 104 static const struct samsung_pin_bank_data exynos2200_pin_banks1[] __initconst = { 105 EXYNOS850_PIN_BANK_EINTW(2, 0x0, "gpm0", 0x00), 106 EXYNOS850_PIN_BANK_EINTW(2, 0x20, "gpm1", 0x04), 107 EXYNOS850_PIN_BANK_EINTW(2, 0x40, "gpm2", 0x08), 108 EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpm3", 0x0c), 109 EXYNOS850_PIN_BANK_EINTW(2, 0x80, "gpm4", 0x10), 110 EXYNOS850_PIN_BANK_EINTW(2, 0xa0, "gpm5", 0x14), 111 EXYNOS850_PIN_BANK_EINTW(2, 0xc0, "gpm6", 0x18), 112 EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpm7", 0x1c), 113 EXYNOS850_PIN_BANK_EINTW(2, 0x100, "gpm8", 0x20), 114 EXYNOS850_PIN_BANK_EINTW(2, 0x120, "gpm9", 0x24), 115 EXYNOS850_PIN_BANK_EINTW(2, 0x140, "gpm10", 0x28), 116 EXYNOS850_PIN_BANK_EINTW(2, 0x160, "gpm11", 0x2c), 117 EXYNOS850_PIN_BANK_EINTW(2, 0x180, "gpm12", 0x30), 118 EXYNOS850_PIN_BANK_EINTW(2, 0x1a0, "gpm13", 0x34), 119 EXYNOS850_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38), 120 EXYNOS850_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c), 121 EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40), 122 EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44), 123 EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm20", 0x48), 124 EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm21", 0x4c), 125 EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm22", 0x50), 126 EXYNOS850_PIN_BANK_EINTW(1, 0x2a0, "gpm23", 0x54), 127 EXYNOS850_PIN_BANK_EINTW(1, 0x2c0, "gpm24", 0x58), 128 }; 129 130 /* pin banks of exynos2200 pin-controller - HSI1 */ 131 static const struct samsung_pin_bank_data exynos2200_pin_banks2[] __initconst = { 132 EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpf0", 0x00), 133 }; 134 135 /* pin banks of exynos2200 pin-controller - UFS */ 136 static const struct samsung_pin_bank_data exynos2200_pin_banks3[] __initconst = { 137 EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpf1", 0x00), 138 }; 139 140 /* pin banks of exynos2200 pin-controller - HSI1UFS */ 141 static const struct samsung_pin_bank_data exynos2200_pin_banks4[] __initconst = { 142 EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gpf2", 0x00), 143 }; 144 145 /* pin banks of exynos2200 pin-controller - PERIC0 */ 146 static const struct samsung_pin_bank_data exynos2200_pin_banks5[] __initconst = { 147 EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpb0", 0x00), 148 EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpb1", 0x04), 149 EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpb2", 0x08), 150 EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpb3", 0x0c), 151 EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10), 152 EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpc0", 0x14), 153 EXYNOS850_PIN_BANK_EINTG(2, 0xc0, "gpc1", 0x18), 154 EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpc2", 0x1c), 155 EXYNOS850_PIN_BANK_EINTG(7, 0x100, "gpg1", 0x20), 156 EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpg2", 0x24), 157 }; 158 159 /* pin banks of exynos2200 pin-controller - PERIC1 */ 160 static const struct samsung_pin_bank_data exynos2200_pin_banks6[] __initconst = { 161 EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpp7", 0x00), 162 EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp8", 0x04), 163 EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp9", 0x08), 164 EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpp10", 0x0c), 165 }; 166 167 /* pin banks of exynos2200 pin-controller - PERIC2 */ 168 static const struct samsung_pin_bank_data exynos2200_pin_banks7[] __initconst = { 169 EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpp0", 0x00), 170 EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04), 171 EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08), 172 EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpp3", 0x0c), 173 EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp5", 0x10), 174 EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp6", 0x14), 175 EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp11", 0x18), 176 EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpc3", 0x1c), 177 EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpc4", 0x20), 178 EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpc5", 0x24), 179 EXYNOS850_PIN_BANK_EINTG(2, 0x140, "gpc6", 0x28), 180 EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpc7", 0x2c), 181 EXYNOS850_PIN_BANK_EINTG(2, 0x180, "gpc8", 0x30), 182 EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpc9", 0x34), 183 EXYNOS850_PIN_BANK_EINTG(5, 0x1c0, "gpg0", 0x38), 184 }; 185 186 /* pin banks of exynos2200 pin-controller - VTS */ 187 static const struct samsung_pin_bank_data exynos2200_pin_banks8[] __initconst = { 188 EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpv0", 0x00), 189 }; 190 191 static const struct samsung_pin_ctrl exynos2200_pin_ctrl[] = { 192 { 193 /* pin-controller instance 0 ALIVE data */ 194 .pin_banks = exynos2200_pin_banks0, 195 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks0), 196 .eint_gpio_init = exynos_eint_gpio_init, 197 .eint_wkup_init = exynos_eint_wkup_init, 198 .suspend = exynos_pinctrl_suspend, 199 .resume = exynos_pinctrl_resume, 200 }, { 201 /* pin-controller instance 1 CMGP data */ 202 .pin_banks = exynos2200_pin_banks1, 203 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks1), 204 .eint_gpio_init = exynos_eint_gpio_init, 205 .eint_wkup_init = exynos_eint_wkup_init, 206 .suspend = exynos_pinctrl_suspend, 207 .resume = exynos_pinctrl_resume, 208 }, { 209 /* pin-controller instance 2 HSI1 data */ 210 .pin_banks = exynos2200_pin_banks2, 211 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks2), 212 }, { 213 /* pin-controller instance 3 UFS data */ 214 .pin_banks = exynos2200_pin_banks3, 215 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks3), 216 .eint_gpio_init = exynos_eint_gpio_init, 217 .suspend = exynos_pinctrl_suspend, 218 .resume = exynos_pinctrl_resume, 219 }, { 220 /* pin-controller instance 4 HSI1UFS data */ 221 .pin_banks = exynos2200_pin_banks4, 222 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks4), 223 .eint_gpio_init = exynos_eint_gpio_init, 224 .suspend = exynos_pinctrl_suspend, 225 .resume = exynos_pinctrl_resume, 226 }, { 227 /* pin-controller instance 5 PERIC0 data */ 228 .pin_banks = exynos2200_pin_banks5, 229 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks5), 230 .eint_gpio_init = exynos_eint_gpio_init, 231 .suspend = exynos_pinctrl_suspend, 232 .resume = exynos_pinctrl_resume, 233 }, { 234 /* pin-controller instance 6 PERIC1 data */ 235 .pin_banks = exynos2200_pin_banks6, 236 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks6), 237 .eint_gpio_init = exynos_eint_gpio_init, 238 .suspend = exynos_pinctrl_suspend, 239 .resume = exynos_pinctrl_resume, 240 }, { 241 /* pin-controller instance 7 PERIC2 data */ 242 .pin_banks = exynos2200_pin_banks7, 243 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks7), 244 .eint_gpio_init = exynos_eint_gpio_init, 245 .suspend = exynos_pinctrl_suspend, 246 .resume = exynos_pinctrl_resume, 247 }, { 248 /* pin-controller instance 8 VTS data */ 249 .pin_banks = exynos2200_pin_banks8, 250 .nr_banks = ARRAY_SIZE(exynos2200_pin_banks8), 251 }, 252 }; 253 254 const struct samsung_pinctrl_of_match_data exynos2200_of_data __initconst = { 255 .ctrl = exynos2200_pin_ctrl, 256 .num_ctrl = ARRAY_SIZE(exynos2200_pin_ctrl), 257 }; 258 259 /* pin banks of exynos5433 pin-controller - ALIVE */ 260 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = { 261 /* Must start with EINTG banks, ordered by EINT group number. */ 262 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 263 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 264 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 265 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 266 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1), 267 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1), 268 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1), 269 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1), 270 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1), 271 }; 272 273 /* pin banks of exynos5433 pin-controller - AUD */ 274 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = { 275 /* Must start with EINTG banks, ordered by EINT group number. */ 276 EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 277 EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 278 }; 279 280 /* pin banks of exynos5433 pin-controller - CPIF */ 281 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = { 282 /* Must start with EINTG banks, ordered by EINT group number. */ 283 EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), 284 }; 285 286 /* pin banks of exynos5433 pin-controller - eSE */ 287 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = { 288 /* Must start with EINTG banks, ordered by EINT group number. */ 289 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), 290 }; 291 292 /* pin banks of exynos5433 pin-controller - FINGER */ 293 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = { 294 /* Must start with EINTG banks, ordered by EINT group number. */ 295 EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), 296 }; 297 298 /* pin banks of exynos5433 pin-controller - FSYS */ 299 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = { 300 /* Must start with EINTG banks, ordered by EINT group number. */ 301 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), 302 EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), 303 EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08), 304 EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c), 305 EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10), 306 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14), 307 }; 308 309 /* pin banks of exynos5433 pin-controller - IMEM */ 310 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = { 311 /* Must start with EINTG banks, ordered by EINT group number. */ 312 EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), 313 }; 314 315 /* pin banks of exynos5433 pin-controller - NFC */ 316 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = { 317 /* Must start with EINTG banks, ordered by EINT group number. */ 318 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 319 }; 320 321 /* pin banks of exynos5433 pin-controller - PERIC */ 322 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = { 323 /* Must start with EINTG banks, ordered by EINT group number. */ 324 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), 325 EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), 326 EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08), 327 EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c), 328 EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10), 329 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14), 330 EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18), 331 EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c), 332 EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20), 333 EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24), 334 EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28), 335 EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c), 336 EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30), 337 EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34), 338 EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38), 339 EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c), 340 EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), 341 }; 342 343 /* pin banks of exynos5433 pin-controller - TOUCH */ 344 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = { 345 /* Must start with EINTG banks, ordered by EINT group number. */ 346 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 347 }; 348 349 /* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */ 350 static const u32 exynos5433_retention_regs[] = { 351 EXYNOS5433_PAD_RETENTION_TOP_OPTION, 352 EXYNOS5433_PAD_RETENTION_UART_OPTION, 353 EXYNOS5433_PAD_RETENTION_EBIA_OPTION, 354 EXYNOS5433_PAD_RETENTION_EBIB_OPTION, 355 EXYNOS5433_PAD_RETENTION_SPI_OPTION, 356 EXYNOS5433_PAD_RETENTION_MIF_OPTION, 357 EXYNOS5433_PAD_RETENTION_USBXTI_OPTION, 358 EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION, 359 EXYNOS5433_PAD_RETENTION_UFS_OPTION, 360 EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION, 361 }; 362 363 static const struct samsung_retention_data exynos5433_retention_data __initconst = { 364 .regs = exynos5433_retention_regs, 365 .nr_regs = ARRAY_SIZE(exynos5433_retention_regs), 366 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 367 .refcnt = &exynos_shared_retention_refcnt, 368 .init = exynos_retention_init, 369 }; 370 371 /* PMU retention control for audio pins can be tied to audio pin bank */ 372 static const u32 exynos5433_audio_retention_regs[] = { 373 EXYNOS5433_PAD_RETENTION_AUD_OPTION, 374 }; 375 376 static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = { 377 .regs = exynos5433_audio_retention_regs, 378 .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs), 379 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 380 .init = exynos_retention_init, 381 }; 382 383 /* PMU retention control for mmc pins can be tied to fsys pin bank */ 384 static const u32 exynos5433_fsys_retention_regs[] = { 385 EXYNOS5433_PAD_RETENTION_MMC0_OPTION, 386 EXYNOS5433_PAD_RETENTION_MMC1_OPTION, 387 EXYNOS5433_PAD_RETENTION_MMC2_OPTION, 388 }; 389 390 static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = { 391 .regs = exynos5433_fsys_retention_regs, 392 .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs), 393 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 394 .init = exynos_retention_init, 395 }; 396 397 /* 398 * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes 399 * ten gpio/pin-mux/pinconfig controllers. 400 */ 401 static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = { 402 { 403 /* pin-controller instance 0 data */ 404 .pin_banks = exynos5433_pin_banks0, 405 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0), 406 .eint_wkup_init = exynos_eint_wkup_init, 407 .suspend = exynos_pinctrl_suspend, 408 .resume = exynos_pinctrl_resume, 409 .nr_ext_resources = 1, 410 .retention_data = &exynos5433_retention_data, 411 }, { 412 /* pin-controller instance 1 data */ 413 .pin_banks = exynos5433_pin_banks1, 414 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1), 415 .eint_gpio_init = exynos_eint_gpio_init, 416 .suspend = exynos_pinctrl_suspend, 417 .resume = exynos_pinctrl_resume, 418 .retention_data = &exynos5433_audio_retention_data, 419 }, { 420 /* pin-controller instance 2 data */ 421 .pin_banks = exynos5433_pin_banks2, 422 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2), 423 .eint_gpio_init = exynos_eint_gpio_init, 424 .suspend = exynos_pinctrl_suspend, 425 .resume = exynos_pinctrl_resume, 426 .retention_data = &exynos5433_retention_data, 427 }, { 428 /* pin-controller instance 3 data */ 429 .pin_banks = exynos5433_pin_banks3, 430 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3), 431 .eint_gpio_init = exynos_eint_gpio_init, 432 .suspend = exynos_pinctrl_suspend, 433 .resume = exynos_pinctrl_resume, 434 .retention_data = &exynos5433_retention_data, 435 }, { 436 /* pin-controller instance 4 data */ 437 .pin_banks = exynos5433_pin_banks4, 438 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4), 439 .eint_gpio_init = exynos_eint_gpio_init, 440 .suspend = exynos_pinctrl_suspend, 441 .resume = exynos_pinctrl_resume, 442 .retention_data = &exynos5433_retention_data, 443 }, { 444 /* pin-controller instance 5 data */ 445 .pin_banks = exynos5433_pin_banks5, 446 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5), 447 .eint_gpio_init = exynos_eint_gpio_init, 448 .suspend = exynos_pinctrl_suspend, 449 .resume = exynos_pinctrl_resume, 450 .retention_data = &exynos5433_fsys_retention_data, 451 }, { 452 /* pin-controller instance 6 data */ 453 .pin_banks = exynos5433_pin_banks6, 454 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6), 455 .eint_gpio_init = exynos_eint_gpio_init, 456 .suspend = exynos_pinctrl_suspend, 457 .resume = exynos_pinctrl_resume, 458 .retention_data = &exynos5433_retention_data, 459 }, { 460 /* pin-controller instance 7 data */ 461 .pin_banks = exynos5433_pin_banks7, 462 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7), 463 .eint_gpio_init = exynos_eint_gpio_init, 464 .suspend = exynos_pinctrl_suspend, 465 .resume = exynos_pinctrl_resume, 466 .retention_data = &exynos5433_retention_data, 467 }, { 468 /* pin-controller instance 8 data */ 469 .pin_banks = exynos5433_pin_banks8, 470 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8), 471 .eint_gpio_init = exynos_eint_gpio_init, 472 .suspend = exynos_pinctrl_suspend, 473 .resume = exynos_pinctrl_resume, 474 .retention_data = &exynos5433_retention_data, 475 }, { 476 /* pin-controller instance 9 data */ 477 .pin_banks = exynos5433_pin_banks9, 478 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9), 479 .eint_gpio_init = exynos_eint_gpio_init, 480 .suspend = exynos_pinctrl_suspend, 481 .resume = exynos_pinctrl_resume, 482 .retention_data = &exynos5433_retention_data, 483 }, 484 }; 485 486 const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = { 487 .ctrl = exynos5433_pin_ctrl, 488 .num_ctrl = ARRAY_SIZE(exynos5433_pin_ctrl), 489 }; 490 491 /* pin banks of exynos7 pin-controller - ALIVE */ 492 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { 493 /* Must start with EINTG banks, ordered by EINT group number. */ 494 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 495 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 496 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 497 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 498 }; 499 500 /* pin banks of exynos7 pin-controller - BUS0 */ 501 static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = { 502 /* Must start with EINTG banks, ordered by EINT group number. */ 503 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 504 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04), 505 EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08), 506 EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c), 507 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), 508 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 509 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), 510 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c), 511 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20), 512 EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24), 513 EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28), 514 EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c), 515 EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30), 516 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), 517 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38), 518 }; 519 520 /* pin banks of exynos7 pin-controller - NFC */ 521 static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = { 522 /* Must start with EINTG banks, ordered by EINT group number. */ 523 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 524 }; 525 526 /* pin banks of exynos7 pin-controller - TOUCH */ 527 static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = { 528 /* Must start with EINTG banks, ordered by EINT group number. */ 529 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 530 }; 531 532 /* pin banks of exynos7 pin-controller - FF */ 533 static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = { 534 /* Must start with EINTG banks, ordered by EINT group number. */ 535 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00), 536 }; 537 538 /* pin banks of exynos7 pin-controller - ESE */ 539 static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = { 540 /* Must start with EINTG banks, ordered by EINT group number. */ 541 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00), 542 }; 543 544 /* pin banks of exynos7 pin-controller - FSYS0 */ 545 static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = { 546 /* Must start with EINTG banks, ordered by EINT group number. */ 547 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00), 548 }; 549 550 /* pin banks of exynos7 pin-controller - FSYS1 */ 551 static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = { 552 /* Must start with EINTG banks, ordered by EINT group number. */ 553 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00), 554 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), 555 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08), 556 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c), 557 }; 558 559 /* pin banks of exynos7 pin-controller - BUS1 */ 560 static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = { 561 /* Must start with EINTG banks, ordered by EINT group number. */ 562 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00), 563 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04), 564 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08), 565 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c), 566 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10), 567 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14), 568 EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18), 569 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c), 570 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20), 571 EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24), 572 }; 573 574 static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = { 575 /* Must start with EINTG banks, ordered by EINT group number. */ 576 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 577 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 578 }; 579 580 static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { 581 { 582 /* pin-controller instance 0 Alive data */ 583 .pin_banks = exynos7_pin_banks0, 584 .nr_banks = ARRAY_SIZE(exynos7_pin_banks0), 585 .eint_wkup_init = exynos_eint_wkup_init, 586 }, { 587 /* pin-controller instance 1 BUS0 data */ 588 .pin_banks = exynos7_pin_banks1, 589 .nr_banks = ARRAY_SIZE(exynos7_pin_banks1), 590 .eint_gpio_init = exynos_eint_gpio_init, 591 }, { 592 /* pin-controller instance 2 NFC data */ 593 .pin_banks = exynos7_pin_banks2, 594 .nr_banks = ARRAY_SIZE(exynos7_pin_banks2), 595 .eint_gpio_init = exynos_eint_gpio_init, 596 }, { 597 /* pin-controller instance 3 TOUCH data */ 598 .pin_banks = exynos7_pin_banks3, 599 .nr_banks = ARRAY_SIZE(exynos7_pin_banks3), 600 .eint_gpio_init = exynos_eint_gpio_init, 601 }, { 602 /* pin-controller instance 4 FF data */ 603 .pin_banks = exynos7_pin_banks4, 604 .nr_banks = ARRAY_SIZE(exynos7_pin_banks4), 605 .eint_gpio_init = exynos_eint_gpio_init, 606 }, { 607 /* pin-controller instance 5 ESE data */ 608 .pin_banks = exynos7_pin_banks5, 609 .nr_banks = ARRAY_SIZE(exynos7_pin_banks5), 610 .eint_gpio_init = exynos_eint_gpio_init, 611 }, { 612 /* pin-controller instance 6 FSYS0 data */ 613 .pin_banks = exynos7_pin_banks6, 614 .nr_banks = ARRAY_SIZE(exynos7_pin_banks6), 615 .eint_gpio_init = exynos_eint_gpio_init, 616 }, { 617 /* pin-controller instance 7 FSYS1 data */ 618 .pin_banks = exynos7_pin_banks7, 619 .nr_banks = ARRAY_SIZE(exynos7_pin_banks7), 620 .eint_gpio_init = exynos_eint_gpio_init, 621 }, { 622 /* pin-controller instance 8 BUS1 data */ 623 .pin_banks = exynos7_pin_banks8, 624 .nr_banks = ARRAY_SIZE(exynos7_pin_banks8), 625 .eint_gpio_init = exynos_eint_gpio_init, 626 }, { 627 /* pin-controller instance 9 AUD data */ 628 .pin_banks = exynos7_pin_banks9, 629 .nr_banks = ARRAY_SIZE(exynos7_pin_banks9), 630 .eint_gpio_init = exynos_eint_gpio_init, 631 }, 632 }; 633 634 const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { 635 .ctrl = exynos7_pin_ctrl, 636 .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), 637 }; 638 639 /* pin banks of exynos7870 pin-controller 0 (ALIVE) */ 640 static const struct samsung_pin_bank_data exynos7870_pin_banks0[] __initconst = { 641 EXYNOS7870_PIN_BANK_EINTN(6, 0x000, "etc0"), 642 EXYNOS7870_PIN_BANK_EINTN(3, 0x020, "etc1"), 643 EXYNOS7870_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00), 644 EXYNOS7870_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04), 645 EXYNOS7870_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08), 646 EXYNOS7870_PIN_BANK_EINTN(2, 0x0c0, "gpq0"), 647 }; 648 649 /* pin banks of exynos7870 pin-controller 1 (DISPAUD) */ 650 static const struct samsung_pin_bank_data exynos7870_pin_banks1[] __initconst = { 651 EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpz0", 0x00), 652 EXYNOS8895_PIN_BANK_EINTG(6, 0x020, "gpz1", 0x04), 653 EXYNOS8895_PIN_BANK_EINTG(4, 0x040, "gpz2", 0x08), 654 }; 655 656 /* pin banks of exynos7870 pin-controller 2 (ESE) */ 657 static const struct samsung_pin_bank_data exynos7870_pin_banks2[] __initconst = { 658 EXYNOS8895_PIN_BANK_EINTG(5, 0x000, "gpc7", 0x00), 659 }; 660 661 /* pin banks of exynos7870 pin-controller 3 (FSYS) */ 662 static const struct samsung_pin_bank_data exynos7870_pin_banks3[] __initconst = { 663 EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpr0", 0x00), 664 EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), 665 EXYNOS8895_PIN_BANK_EINTG(2, 0x040, "gpr2", 0x08), 666 EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpr3", 0x0c), 667 EXYNOS8895_PIN_BANK_EINTG(6, 0x080, "gpr4", 0x10), 668 }; 669 670 /* pin banks of exynos7870 pin-controller 4 (MIF) */ 671 static const struct samsung_pin_bank_data exynos7870_pin_banks4[] __initconst = { 672 EXYNOS8895_PIN_BANK_EINTG(2, 0x000, "gpm0", 0x00), 673 }; 674 675 /* pin banks of exynos7870 pin-controller 5 (NFC) */ 676 static const struct samsung_pin_bank_data exynos7870_pin_banks5[] __initconst = { 677 EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpc2", 0x00), 678 }; 679 680 /* pin banks of exynos7870 pin-controller 6 (TOP) */ 681 static const struct samsung_pin_bank_data exynos7870_pin_banks6[] __initconst = { 682 EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpb0", 0x00), 683 EXYNOS8895_PIN_BANK_EINTG(3, 0x020, "gpc0", 0x04), 684 EXYNOS8895_PIN_BANK_EINTG(4, 0x040, "gpc1", 0x08), 685 EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpc4", 0x0c), 686 EXYNOS8895_PIN_BANK_EINTG(2, 0x080, "gpc5", 0x10), 687 EXYNOS8895_PIN_BANK_EINTG(4, 0x0a0, "gpc6", 0x14), 688 EXYNOS8895_PIN_BANK_EINTG(2, 0x0c0, "gpc8", 0x18), 689 EXYNOS8895_PIN_BANK_EINTG(2, 0x0e0, "gpc9", 0x1c), 690 EXYNOS8895_PIN_BANK_EINTG(7, 0x100, "gpd1", 0x20), 691 EXYNOS8895_PIN_BANK_EINTG(6, 0x120, "gpd2", 0x24), 692 EXYNOS8895_PIN_BANK_EINTG(8, 0x140, "gpd3", 0x28), 693 EXYNOS8895_PIN_BANK_EINTG(7, 0x160, "gpd4", 0x2c), 694 EXYNOS8895_PIN_BANK_EINTG(3, 0x1a0, "gpe0", 0x34), 695 EXYNOS8895_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), 696 EXYNOS8895_PIN_BANK_EINTG(2, 0x1e0, "gpf1", 0x3c), 697 EXYNOS8895_PIN_BANK_EINTG(2, 0x200, "gpf2", 0x40), 698 EXYNOS8895_PIN_BANK_EINTG(4, 0x220, "gpf3", 0x44), 699 EXYNOS8895_PIN_BANK_EINTG(5, 0x240, "gpf4", 0x48), 700 }; 701 702 /* pin banks of exynos7870 pin-controller 7 (TOUCH) */ 703 static const struct samsung_pin_bank_data exynos7870_pin_banks7[] __initconst = { 704 EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpc3", 0x00), 705 }; 706 707 static const struct samsung_pin_ctrl exynos7870_pin_ctrl[] __initconst = { 708 { 709 /* pin-controller instance 0 Alive data */ 710 .pin_banks = exynos7870_pin_banks0, 711 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks0), 712 .eint_wkup_init = exynos_eint_wkup_init, 713 .suspend = exynos_pinctrl_suspend, 714 .resume = exynos_pinctrl_resume, 715 }, { 716 /* pin-controller instance 1 DISPAUD data */ 717 .pin_banks = exynos7870_pin_banks1, 718 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks1), 719 }, { 720 /* pin-controller instance 2 ESE data */ 721 .pin_banks = exynos7870_pin_banks2, 722 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks2), 723 .eint_gpio_init = exynos_eint_gpio_init, 724 .suspend = exynos_pinctrl_suspend, 725 .resume = exynos_pinctrl_resume, 726 }, { 727 /* pin-controller instance 3 FSYS data */ 728 .pin_banks = exynos7870_pin_banks3, 729 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks3), 730 .eint_gpio_init = exynos_eint_gpio_init, 731 .suspend = exynos_pinctrl_suspend, 732 .resume = exynos_pinctrl_resume, 733 }, { 734 /* pin-controller instance 4 MIF data */ 735 .pin_banks = exynos7870_pin_banks4, 736 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks4), 737 .eint_gpio_init = exynos_eint_gpio_init, 738 .suspend = exynos_pinctrl_suspend, 739 .resume = exynos_pinctrl_resume, 740 }, { 741 /* pin-controller instance 5 NFC data */ 742 .pin_banks = exynos7870_pin_banks5, 743 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks5), 744 .eint_gpio_init = exynos_eint_gpio_init, 745 .suspend = exynos_pinctrl_suspend, 746 .resume = exynos_pinctrl_resume, 747 }, { 748 /* pin-controller instance 6 TOP data */ 749 .pin_banks = exynos7870_pin_banks6, 750 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks6), 751 .eint_gpio_init = exynos_eint_gpio_init, 752 .suspend = exynos_pinctrl_suspend, 753 .resume = exynos_pinctrl_resume, 754 }, { 755 /* pin-controller instance 7 TOUCH data */ 756 .pin_banks = exynos7870_pin_banks7, 757 .nr_banks = ARRAY_SIZE(exynos7870_pin_banks7), 758 .eint_gpio_init = exynos_eint_gpio_init, 759 .suspend = exynos_pinctrl_suspend, 760 .resume = exynos_pinctrl_resume, 761 }, 762 }; 763 764 const struct samsung_pinctrl_of_match_data exynos7870_of_data __initconst = { 765 .ctrl = exynos7870_pin_ctrl, 766 .num_ctrl = ARRAY_SIZE(exynos7870_pin_ctrl), 767 }; 768 769 /* pin banks of exynos7885 pin-controller 0 (ALIVE) */ 770 static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = { 771 EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"), 772 EXYNOS_PIN_BANK_EINTN(3, 0x020, "etc1"), 773 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00), 774 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04), 775 EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08), 776 EXYNOS850_PIN_BANK_EINTW(5, 0x0a0, "gpq0", 0x0c), 777 }; 778 779 /* pin banks of exynos7885 pin-controller 1 (DISPAUD) */ 780 static const struct samsung_pin_bank_data exynos7885_pin_banks1[] __initconst = { 781 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 782 EXYNOS850_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04), 783 EXYNOS850_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08), 784 }; 785 786 /* pin banks of exynos7885 pin-controller 2 (FSYS) */ 787 static const struct samsung_pin_bank_data exynos7885_pin_banks2[] __initconst = { 788 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), 789 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf2", 0x04), 790 EXYNOS850_PIN_BANK_EINTG(6, 0x040, "gpf3", 0x08), 791 EXYNOS850_PIN_BANK_EINTG(6, 0x060, "gpf4", 0x0c), 792 }; 793 794 /* pin banks of exynos7885 pin-controller 3 (TOP) */ 795 static const struct samsung_pin_bank_data exynos7885_pin_banks3[] __initconst = { 796 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpp0", 0x00), 797 EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gpg0", 0x04), 798 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), 799 EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c), 800 EXYNOS850_PIN_BANK_EINTG(3, 0x080, "gpp3", 0x10), 801 EXYNOS850_PIN_BANK_EINTG(6, 0x0a0, "gpp4", 0x14), 802 EXYNOS850_PIN_BANK_EINTG(4, 0x0c0, "gpp5", 0x18), 803 EXYNOS850_PIN_BANK_EINTG(5, 0x0e0, "gpp6", 0x1c), 804 EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpp7", 0x20), 805 EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp8", 0x24), 806 EXYNOS850_PIN_BANK_EINTG(8, 0x140, "gpg1", 0x28), 807 EXYNOS850_PIN_BANK_EINTG(8, 0x160, "gpg2", 0x2c), 808 EXYNOS850_PIN_BANK_EINTG(8, 0x180, "gpg3", 0x30), 809 EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpg4", 0x34), 810 EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpc0", 0x38), 811 EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpc1", 0x3c), 812 EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpc2", 0x40), 813 }; 814 815 static const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = { 816 { 817 /* pin-controller instance 0 Alive data */ 818 .pin_banks = exynos7885_pin_banks0, 819 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks0), 820 .eint_gpio_init = exynos_eint_gpio_init, 821 .eint_wkup_init = exynos_eint_wkup_init, 822 .suspend = exynos_pinctrl_suspend, 823 .resume = exynos_pinctrl_resume, 824 }, { 825 /* pin-controller instance 1 DISPAUD data */ 826 .pin_banks = exynos7885_pin_banks1, 827 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks1), 828 }, { 829 /* pin-controller instance 2 FSYS data */ 830 .pin_banks = exynos7885_pin_banks2, 831 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks2), 832 .eint_gpio_init = exynos_eint_gpio_init, 833 .suspend = exynos_pinctrl_suspend, 834 .resume = exynos_pinctrl_resume, 835 }, { 836 /* pin-controller instance 3 TOP data */ 837 .pin_banks = exynos7885_pin_banks3, 838 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks3), 839 .eint_gpio_init = exynos_eint_gpio_init, 840 .suspend = exynos_pinctrl_suspend, 841 .resume = exynos_pinctrl_resume, 842 }, 843 }; 844 845 const struct samsung_pinctrl_of_match_data exynos7885_of_data __initconst = { 846 .ctrl = exynos7885_pin_ctrl, 847 .num_ctrl = ARRAY_SIZE(exynos7885_pin_ctrl), 848 }; 849 850 /* pin banks of exynos850 pin-controller 0 (ALIVE) */ 851 static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = { 852 /* Must start with EINTG banks, ordered by EINT group number. */ 853 EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 854 EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 855 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 856 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 857 EXYNOS850_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10), 858 EXYNOS850_PIN_BANK_EINTN(3, 0x0a0, "gpq0"), 859 }; 860 861 /* pin banks of exynos850 pin-controller 1 (CMGP) */ 862 static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = { 863 /* Must start with EINTG banks, ordered by EINT group number. */ 864 EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), 865 EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), 866 EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), 867 EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0c), 868 EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), 869 EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpm5", 0x14), 870 EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpm6", 0x18), 871 EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpm7", 0x1c), 872 }; 873 874 /* pin banks of exynos850 pin-controller 2 (AUD) */ 875 static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = { 876 /* Must start with EINTG banks, ordered by EINT group number. */ 877 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 878 EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04), 879 }; 880 881 /* pin banks of exynos850 pin-controller 3 (HSI) */ 882 static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = { 883 /* Must start with EINTG banks, ordered by EINT group number. */ 884 EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00), 885 }; 886 887 /* pin banks of exynos850 pin-controller 4 (CORE) */ 888 static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = { 889 /* Must start with EINTG banks, ordered by EINT group number. */ 890 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), 891 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), 892 }; 893 894 /* pin banks of exynos850 pin-controller 5 (PERI) */ 895 static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = { 896 /* Must start with EINTG banks, ordered by EINT group number. */ 897 EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00), 898 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04), 899 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), 900 EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c), 901 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10), 902 EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpg2", 0x14), 903 EXYNOS850_PIN_BANK_EINTG(1, 0x0c0, "gpg3", 0x18), 904 EXYNOS850_PIN_BANK_EINTG(3, 0x0e0, "gpc0", 0x1c), 905 EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20), 906 }; 907 908 static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { 909 { 910 /* pin-controller instance 0 ALIVE data */ 911 .pin_banks = exynos850_pin_banks0, 912 .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), 913 .eint_wkup_init = exynos_eint_wkup_init, 914 }, { 915 /* pin-controller instance 1 CMGP data */ 916 .pin_banks = exynos850_pin_banks1, 917 .nr_banks = ARRAY_SIZE(exynos850_pin_banks1), 918 .eint_wkup_init = exynos_eint_wkup_init, 919 }, { 920 /* pin-controller instance 2 AUD data */ 921 .pin_banks = exynos850_pin_banks2, 922 .nr_banks = ARRAY_SIZE(exynos850_pin_banks2), 923 }, { 924 /* pin-controller instance 3 HSI data */ 925 .pin_banks = exynos850_pin_banks3, 926 .nr_banks = ARRAY_SIZE(exynos850_pin_banks3), 927 .eint_gpio_init = exynos_eint_gpio_init, 928 }, { 929 /* pin-controller instance 4 CORE data */ 930 .pin_banks = exynos850_pin_banks4, 931 .nr_banks = ARRAY_SIZE(exynos850_pin_banks4), 932 .eint_gpio_init = exynos_eint_gpio_init, 933 }, { 934 /* pin-controller instance 5 PERI data */ 935 .pin_banks = exynos850_pin_banks5, 936 .nr_banks = ARRAY_SIZE(exynos850_pin_banks5), 937 .eint_gpio_init = exynos_eint_gpio_init, 938 }, 939 }; 940 941 const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { 942 .ctrl = exynos850_pin_ctrl, 943 .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), 944 }; 945 946 /* pin banks of exynos990 pin-controller 0 (ALIVE) */ 947 static struct samsung_pin_bank_data exynos990_pin_banks0[] = { 948 /* Must start with EINTG banks, ordered by EINT group number. */ 949 EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 950 EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 951 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 952 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 953 EXYNOS850_PIN_BANK_EINTW(2, 0x080, "gpa4", 0x10), 954 EXYNOS850_PIN_BANK_EINTN(7, 0x0A0, "gpq0"), 955 }; 956 957 /* pin banks of exynos990 pin-controller 1 (CMGP) */ 958 static struct samsung_pin_bank_data exynos990_pin_banks1[] = { 959 /* Must start with EINTG banks, ordered by EINT group number. */ 960 EXYNOS850_PIN_BANK_EINTN(1, 0x000, "gpm0"), 961 EXYNOS850_PIN_BANK_EINTN(1, 0x020, "gpm1"), 962 EXYNOS850_PIN_BANK_EINTN(1, 0x040, "gpm2"), 963 EXYNOS850_PIN_BANK_EINTN(1, 0x060, "gpm3"), 964 EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x00), 965 EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x04), 966 EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x08), 967 EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x0c), 968 EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x10), 969 EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x14), 970 EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x18), 971 EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x1c), 972 EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x20), 973 EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x24), 974 EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x28), 975 EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x2c), 976 EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x30), 977 EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x34), 978 EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x38), 979 EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x3c), 980 EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x40), 981 EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x44), 982 EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x48), 983 EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x4c), 984 EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x50), 985 EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x54), 986 EXYNOS850_PIN_BANK_EINTW(1, 0x340, "gpm26", 0x58), 987 EXYNOS850_PIN_BANK_EINTW(1, 0x360, "gpm27", 0x5c), 988 EXYNOS850_PIN_BANK_EINTW(1, 0x380, "gpm28", 0x60), 989 EXYNOS850_PIN_BANK_EINTW(1, 0x3A0, "gpm29", 0x64), 990 EXYNOS850_PIN_BANK_EINTW(1, 0x3C0, "gpm30", 0x68), 991 EXYNOS850_PIN_BANK_EINTW(1, 0x3E0, "gpm31", 0x6c), 992 EXYNOS850_PIN_BANK_EINTW(1, 0x400, "gpm32", 0x70), 993 EXYNOS850_PIN_BANK_EINTW(1, 0x420, "gpm33", 0x74), 994 995 }; 996 997 /* pin banks of exynos990 pin-controller 2 (HSI1) */ 998 static struct samsung_pin_bank_data exynos990_pin_banks2[] = { 999 /* Must start with EINTG banks, ordered by EINT group number. */ 1000 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), 1001 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04), 1002 EXYNOS850_PIN_BANK_EINTG(3, 0x040, "gpf2", 0x08), 1003 }; 1004 1005 /* pin banks of exynos990 pin-controller 3 (HSI2) */ 1006 static struct samsung_pin_bank_data exynos990_pin_banks3[] = { 1007 /* Must start with EINTG banks, ordered by EINT group number. */ 1008 EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf3", 0x00), 1009 }; 1010 1011 /* pin banks of exynos990 pin-controller 4 (PERIC0) */ 1012 static struct samsung_pin_bank_data exynos990_pin_banks4[] = { 1013 /* Must start with EINTG banks, ordered by EINT group number. */ 1014 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), 1015 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), 1016 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), 1017 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp3", 0x0C), 1018 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp4", 0x10), 1019 EXYNOS850_PIN_BANK_EINTG(2, 0x0A0, "gpg0", 0x14), 1020 }; 1021 1022 /* pin banks of exynos990 pin-controller 5 (PERIC1) */ 1023 static struct samsung_pin_bank_data exynos990_pin_banks5[] = { 1024 /* Must start with EINTG banks, ordered by EINT group number. */ 1025 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp5", 0x00), 1026 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp6", 0x04), 1027 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp7", 0x08), 1028 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp8", 0x0C), 1029 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp9", 0x10), 1030 EXYNOS850_PIN_BANK_EINTG(6, 0x0A0, "gpc0", 0x14), 1031 EXYNOS850_PIN_BANK_EINTG(4, 0x0C0, "gpg1", 0x18), 1032 EXYNOS850_PIN_BANK_EINTG(8, 0x0E0, "gpb0", 0x1C), 1033 EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb1", 0x20), 1034 EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb2", 0x24), 1035 }; 1036 1037 /* pin banks of exynos990 pin-controller 6 (VTS) */ 1038 static struct samsung_pin_bank_data exynos990_pin_banks6[] = { 1039 /* Must start with EINTG banks, ordered by EINT group number. */ 1040 EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpv0", 0x00), 1041 }; 1042 1043 static const struct samsung_pin_ctrl exynos990_pin_ctrl[] __initconst = { 1044 { 1045 /* pin-controller instance 0 ALIVE data */ 1046 .pin_banks = exynos990_pin_banks0, 1047 .nr_banks = ARRAY_SIZE(exynos990_pin_banks0), 1048 .eint_wkup_init = exynos_eint_wkup_init, 1049 }, { 1050 /* pin-controller instance 1 CMGP data */ 1051 .pin_banks = exynos990_pin_banks1, 1052 .nr_banks = ARRAY_SIZE(exynos990_pin_banks1), 1053 .eint_wkup_init = exynos_eint_wkup_init, 1054 }, { 1055 /* pin-controller instance 2 HSI1 data */ 1056 .pin_banks = exynos990_pin_banks2, 1057 .nr_banks = ARRAY_SIZE(exynos990_pin_banks2), 1058 .eint_gpio_init = exynos_eint_gpio_init, 1059 }, { 1060 /* pin-controller instance 3 HSI2 data */ 1061 .pin_banks = exynos990_pin_banks3, 1062 .nr_banks = ARRAY_SIZE(exynos990_pin_banks3), 1063 .eint_gpio_init = exynos_eint_gpio_init, 1064 }, { 1065 /* pin-controller instance 4 PERIC0 data */ 1066 .pin_banks = exynos990_pin_banks4, 1067 .nr_banks = ARRAY_SIZE(exynos990_pin_banks4), 1068 .eint_gpio_init = exynos_eint_gpio_init, 1069 }, { 1070 /* pin-controller instance 5 PERIC1 data */ 1071 .pin_banks = exynos990_pin_banks5, 1072 .nr_banks = ARRAY_SIZE(exynos990_pin_banks5), 1073 .eint_gpio_init = exynos_eint_gpio_init, 1074 }, { 1075 /* pin-controller instance 6 VTS data */ 1076 .pin_banks = exynos990_pin_banks6, 1077 .nr_banks = ARRAY_SIZE(exynos990_pin_banks6), 1078 }, 1079 }; 1080 1081 const struct samsung_pinctrl_of_match_data exynos990_of_data __initconst = { 1082 .ctrl = exynos990_pin_ctrl, 1083 .num_ctrl = ARRAY_SIZE(exynos990_pin_ctrl), 1084 }; 1085 1086 /* pin banks of exynos9810 pin-controller 0 (ALIVE) */ 1087 static const struct samsung_pin_bank_data exynos9810_pin_banks0[] __initconst = { 1088 EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc1"), 1089 EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), 1090 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), 1091 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), 1092 EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c), 1093 EXYNOS850_PIN_BANK_EINTN(6, 0x0A0, "gpq0"), 1094 EXYNOS850_PIN_BANK_EINTW(2, 0x0C0, "gpa4", 0x10), 1095 }; 1096 1097 /* pin banks of exynos9810 pin-controller 1 (AUD) */ 1098 static const struct samsung_pin_bank_data exynos9810_pin_banks1[] __initconst = { 1099 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 1100 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04), 1101 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpb2", 0x08), 1102 }; 1103 1104 /* pin banks of exynos9810 pin-controller 2 (CHUB) */ 1105 static const struct samsung_pin_bank_data exynos9810_pin_banks2[] __initconst = { 1106 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00), 1107 EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gph1", 0x04), 1108 }; 1109 1110 /* pin banks of exynos9810 pin-controller 3 (CMGP) */ 1111 static const struct samsung_pin_bank_data exynos9810_pin_banks3[] __initconst = { 1112 EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), 1113 EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), 1114 EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), 1115 EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), 1116 EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), 1117 EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), 1118 EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), 1119 EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), 1120 EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm10", 0x20), 1121 EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm11", 0x24), 1122 EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm12", 0x28), 1123 EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm13", 0x2C), 1124 EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm14", 0x30), 1125 EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm15", 0x34), 1126 EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm16", 0x38), 1127 EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm17", 0x3C), 1128 EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm40", 0x40), 1129 EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm41", 0x44), 1130 EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm42", 0x48), 1131 EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm43", 0x4C), 1132 }; 1133 1134 /* pin banks of exynos9810 pin-controller 4 (FSYS0) */ 1135 static const struct samsung_pin_bank_data exynos9810_pin_banks4[] __initconst = { 1136 EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf0", 0x00), 1137 }; 1138 1139 /* pin banks of exynos9810 pin-controller 5 (FSYS1) */ 1140 static const struct samsung_pin_bank_data exynos9810_pin_banks5[] __initconst = { 1141 EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpf1", 0x00), 1142 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf2", 0x04), 1143 }; 1144 1145 /* pin banks of exynos9810 pin-controller 6 (PERIC0) */ 1146 static const struct samsung_pin_bank_data exynos9810_pin_banks6[] __initconst = { 1147 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), 1148 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), 1149 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), 1150 EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp3", 0x0C), 1151 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), 1152 EXYNOS850_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), 1153 EXYNOS850_PIN_BANK_EINTG(8, 0x0C0, "gpg2", 0x18), 1154 }; 1155 1156 /* pin banks of exynos9810 pin-controller 7 (PERIC1) */ 1157 static const struct samsung_pin_bank_data exynos9810_pin_banks7[] __initconst = { 1158 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp4", 0x00), 1159 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp5", 0x04), 1160 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp6", 0x08), 1161 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C), 1162 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10), 1163 EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 1164 EXYNOS850_PIN_BANK_EINTG(7, 0x0C0, "gpg3", 0x18), 1165 }; 1166 1167 /* pin banks of exynos9810 pin-controller 8 (VTS) */ 1168 static const struct samsung_pin_bank_data exynos9810_pin_banks8[] __initconst = { 1169 EXYNOS850_PIN_BANK_EINTG(3, 0x000, "gpt0", 0x00), 1170 }; 1171 1172 static const struct samsung_pin_ctrl exynos9810_pin_ctrl[] __initconst = { 1173 { 1174 /* pin-controller instance 0 ALIVE data */ 1175 .pin_banks = exynos9810_pin_banks0, 1176 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks0), 1177 .eint_wkup_init = exynos_eint_wkup_init, 1178 .eint_gpio_init = exynos_eint_gpio_init, 1179 .suspend = exynos_pinctrl_suspend, 1180 .resume = exynos_pinctrl_resume, 1181 }, { 1182 /* pin-controller instance 1 AUD data */ 1183 .pin_banks = exynos9810_pin_banks1, 1184 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks1), 1185 }, { 1186 /* pin-controller instance 2 CHUB data */ 1187 .pin_banks = exynos9810_pin_banks2, 1188 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks2), 1189 .eint_gpio_init = exynos_eint_gpio_init, 1190 .suspend = exynos_pinctrl_suspend, 1191 .resume = exynos_pinctrl_resume, 1192 }, { 1193 /* pin-controller instance 3 CMGP data */ 1194 .pin_banks = exynos9810_pin_banks3, 1195 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks3), 1196 .eint_wkup_init = exynos_eint_wkup_init, 1197 .eint_gpio_init = exynos_eint_gpio_init, 1198 .suspend = exynos_pinctrl_suspend, 1199 .resume = exynos_pinctrl_resume, 1200 }, { 1201 /* pin-controller instance 4 FSYS0 data */ 1202 .pin_banks = exynos9810_pin_banks4, 1203 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks4), 1204 .eint_gpio_init = exynos_eint_gpio_init, 1205 .suspend = exynos_pinctrl_suspend, 1206 .resume = exynos_pinctrl_resume, 1207 }, { 1208 /* pin-controller instance 5 FSYS1 data */ 1209 .pin_banks = exynos9810_pin_banks5, 1210 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks5), 1211 .eint_gpio_init = exynos_eint_gpio_init, 1212 .suspend = exynos_pinctrl_suspend, 1213 .resume = exynos_pinctrl_resume, 1214 }, { 1215 /* pin-controller instance 6 PERIC0 data */ 1216 .pin_banks = exynos9810_pin_banks6, 1217 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks6), 1218 .eint_gpio_init = exynos_eint_gpio_init, 1219 .suspend = exynos_pinctrl_suspend, 1220 .resume = exynos_pinctrl_resume, 1221 }, { 1222 /* pin-controller instance 7 PERIC1 data */ 1223 .pin_banks = exynos9810_pin_banks7, 1224 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks7), 1225 .eint_gpio_init = exynos_eint_gpio_init, 1226 .suspend = exynos_pinctrl_suspend, 1227 .resume = exynos_pinctrl_resume, 1228 }, { 1229 /* pin-controller instance 8 VTS data */ 1230 .pin_banks = exynos9810_pin_banks8, 1231 .nr_banks = ARRAY_SIZE(exynos9810_pin_banks8), 1232 }, 1233 }; 1234 1235 const struct samsung_pinctrl_of_match_data exynos9810_of_data __initconst = { 1236 .ctrl = exynos9810_pin_ctrl, 1237 .num_ctrl = ARRAY_SIZE(exynos9810_pin_ctrl), 1238 }; 1239 1240 /* pin banks of exynosautov9 pin-controller 0 (ALIVE) */ 1241 static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = { 1242 EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 1243 EXYNOS850_PIN_BANK_EINTW(2, 0x020, "gpa1", 0x04), 1244 EXYNOS850_PIN_BANK_EINTN(2, 0x040, "gpq0"), 1245 }; 1246 1247 /* pin banks of exynosautov9 pin-controller 1 (AUD) */ 1248 static const struct samsung_pin_bank_data exynosautov9_pin_banks1[] __initconst = { 1249 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), 1250 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04), 1251 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpb2", 0x08), 1252 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpb3", 0x0C), 1253 }; 1254 1255 /* pin banks of exynosautov9 pin-controller 2 (FSYS0) */ 1256 static const struct samsung_pin_bank_data exynosautov9_pin_banks2[] __initconst = { 1257 EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf0", 0x00), 1258 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04), 1259 }; 1260 1261 /* pin banks of exynosautov9 pin-controller 3 (FSYS1) */ 1262 static const struct samsung_pin_bank_data exynosautov9_pin_banks3[] __initconst = { 1263 EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf8", 0x00), 1264 }; 1265 1266 /* pin banks of exynosautov9 pin-controller 4 (FSYS2) */ 1267 static const struct samsung_pin_bank_data exynosautov9_pin_banks4[] __initconst = { 1268 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf2", 0x00), 1269 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf3", 0x04), 1270 EXYNOS850_PIN_BANK_EINTG(7, 0x040, "gpf4", 0x08), 1271 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpf5", 0x0C), 1272 EXYNOS850_PIN_BANK_EINTG(7, 0x080, "gpf6", 0x10), 1273 }; 1274 1275 /* pin banks of exynosautov9 pin-controller 5 (PERIC0) */ 1276 static const struct samsung_pin_bank_data exynosautov9_pin_banks5[] __initconst = { 1277 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), 1278 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), 1279 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), 1280 EXYNOS850_PIN_BANK_EINTG(5, 0x060, "gpg0", 0x0C), 1281 }; 1282 1283 /* pin banks of exynosautov9 pin-controller 6 (PERIC1) */ 1284 static const struct samsung_pin_bank_data exynosautov9_pin_banks6[] __initconst = { 1285 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp3", 0x00), 1286 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp4", 0x04), 1287 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp5", 0x08), 1288 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpg1", 0x0C), 1289 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg2", 0x10), 1290 EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpg3", 0x14), 1291 }; 1292 1293 static const struct samsung_pin_ctrl exynosautov9_pin_ctrl[] __initconst = { 1294 { 1295 /* pin-controller instance 0 ALIVE data */ 1296 .pin_banks = exynosautov9_pin_banks0, 1297 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks0), 1298 .eint_wkup_init = exynos_eint_wkup_init, 1299 .suspend = exynos_pinctrl_suspend, 1300 .resume = exynos_pinctrl_resume, 1301 }, { 1302 /* pin-controller instance 1 AUD data */ 1303 .pin_banks = exynosautov9_pin_banks1, 1304 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks1), 1305 }, { 1306 /* pin-controller instance 2 FSYS0 data */ 1307 .pin_banks = exynosautov9_pin_banks2, 1308 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks2), 1309 .eint_gpio_init = exynos_eint_gpio_init, 1310 .suspend = exynos_pinctrl_suspend, 1311 .resume = exynos_pinctrl_resume, 1312 }, { 1313 /* pin-controller instance 3 FSYS1 data */ 1314 .pin_banks = exynosautov9_pin_banks3, 1315 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks3), 1316 .eint_gpio_init = exynos_eint_gpio_init, 1317 .suspend = exynos_pinctrl_suspend, 1318 .resume = exynos_pinctrl_resume, 1319 }, { 1320 /* pin-controller instance 4 FSYS2 data */ 1321 .pin_banks = exynosautov9_pin_banks4, 1322 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks4), 1323 .eint_gpio_init = exynos_eint_gpio_init, 1324 .suspend = exynos_pinctrl_suspend, 1325 .resume = exynos_pinctrl_resume, 1326 }, { 1327 /* pin-controller instance 5 PERIC0 data */ 1328 .pin_banks = exynosautov9_pin_banks5, 1329 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks5), 1330 .eint_gpio_init = exynos_eint_gpio_init, 1331 .suspend = exynos_pinctrl_suspend, 1332 .resume = exynos_pinctrl_resume, 1333 }, { 1334 /* pin-controller instance 6 PERIC1 data */ 1335 .pin_banks = exynosautov9_pin_banks6, 1336 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks6), 1337 .eint_gpio_init = exynos_eint_gpio_init, 1338 .suspend = exynos_pinctrl_suspend, 1339 .resume = exynos_pinctrl_resume, 1340 }, 1341 }; 1342 1343 const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = { 1344 .ctrl = exynosautov9_pin_ctrl, 1345 .num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl), 1346 }; 1347 1348 /* pin banks of exynosautov920 pin-controller 0 (ALIVE) */ 1349 static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = { 1350 EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28), 1351 EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24), 1352 EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"), 1353 }; 1354 1355 /* pin banks of exynosautov920 pin-controller 1 (AUD) */ 1356 static const struct samsung_pin_bank_data exynosautov920_pin_banks1[] = { 1357 EXYNOSV920_PIN_BANK_EINTG(7, 0x0000, "gpb0", 0x18, 0x24, 0x28), 1358 EXYNOSV920_PIN_BANK_EINTG(6, 0x1000, "gpb1", 0x18, 0x24, 0x28), 1359 EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpb2", 0x18, 0x24, 0x28), 1360 EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpb3", 0x18, 0x24, 0x28), 1361 EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpb4", 0x18, 0x24, 0x28), 1362 EXYNOSV920_PIN_BANK_EINTG(5, 0x5000, "gpb5", 0x18, 0x24, 0x28), 1363 EXYNOSV920_PIN_BANK_EINTG(5, 0x6000, "gpb6", 0x18, 0x24, 0x28), 1364 }; 1365 1366 /* pin banks of exynosautov920 pin-controller 2 (HSI0) */ 1367 static const struct samsung_pin_bank_data exynosautov920_pin_banks2[] = { 1368 EXYNOSV920_PIN_BANK_EINTG(6, 0x0000, "gph0", 0x18, 0x24, 0x28), 1369 EXYNOSV920_PIN_BANK_EINTG(2, 0x1000, "gph1", 0x18, 0x20, 0x24), 1370 }; 1371 1372 /* pin banks of exynosautov920 pin-controller 3 (HSI1) */ 1373 static const struct samsung_pin_bank_data exynosautov920_pin_banks3[] = { 1374 EXYNOSV920_PIN_BANK_EINTG(7, 0x000, "gph8", 0x18, 0x24, 0x28), 1375 }; 1376 1377 /* pin banks of exynosautov920 pin-controller 4 (HSI2) */ 1378 static const struct samsung_pin_bank_data exynosautov920_pin_banks4[] = { 1379 EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gph3", 0x18, 0x24, 0x28), 1380 EXYNOSV920_PIN_BANK_EINTG(7, 0x1000, "gph4", 0x18, 0x24, 0x28), 1381 EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gph5", 0x18, 0x24, 0x28), 1382 EXYNOSV920_PIN_BANK_EINTG(7, 0x3000, "gph6", 0x18, 0x24, 0x28), 1383 }; 1384 1385 /* pin banks of exynosautov920 pin-controller 5 (HSI2UFS) */ 1386 static const struct samsung_pin_bank_data exynosautov920_pin_banks5[] = { 1387 EXYNOSV920_PIN_BANK_EINTG(4, 0x000, "gph2", 0x18, 0x20, 0x24), 1388 }; 1389 1390 /* pin banks of exynosautov920 pin-controller 6 (PERIC0) */ 1391 static const struct samsung_pin_bank_data exynosautov920_pin_banks6[] = { 1392 EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp0", 0x18, 0x24, 0x28), 1393 EXYNOSV920_PIN_BANK_EINTG(8, 0x1000, "gpp1", 0x18, 0x24, 0x28), 1394 EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpp2", 0x18, 0x24, 0x28), 1395 EXYNOSV920_PIN_BANK_EINTG(5, 0x3000, "gpg0", 0x18, 0x24, 0x28), 1396 EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpp3", 0x18, 0x24, 0x28), 1397 EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp4", 0x18, 0x20, 0x24), 1398 EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpg2", 0x18, 0x20, 0x24), 1399 EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpg5", 0x18, 0x20, 0x24), 1400 EXYNOSV920_PIN_BANK_EINTG(3, 0x8000, "gpg3", 0x18, 0x20, 0x24), 1401 EXYNOSV920_PIN_BANK_EINTG(5, 0x9000, "gpg4", 0x18, 0x24, 0x28), 1402 }; 1403 1404 /* pin banks of exynosautov920 pin-controller 7 (PERIC1) */ 1405 static const struct samsung_pin_bank_data exynosautov920_pin_banks7[] = { 1406 EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp5", 0x18, 0x24, 0x28), 1407 EXYNOSV920_PIN_BANK_EINTG(5, 0x1000, "gpp6", 0x18, 0x24, 0x28), 1408 EXYNOSV920_PIN_BANK_EINTG(4, 0x2000, "gpp10", 0x18, 0x20, 0x24), 1409 EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpp7", 0x18, 0x24, 0x28), 1410 EXYNOSV920_PIN_BANK_EINTG(4, 0x4000, "gpp8", 0x18, 0x20, 0x24), 1411 EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp11", 0x18, 0x20, 0x24), 1412 EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpp9", 0x18, 0x20, 0x24), 1413 EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpp12", 0x18, 0x20, 0x24), 1414 EXYNOSV920_PIN_BANK_EINTG(8, 0x8000, "gpg1", 0x18, 0x24, 0x28), 1415 }; 1416 1417 static const struct samsung_retention_data no_retention_data __initconst = { 1418 .regs = NULL, 1419 .nr_regs = 0, 1420 .value = 0, 1421 .refcnt = &exynos_shared_retention_refcnt, 1422 .init = exynos_retention_init, 1423 }; 1424 1425 static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = { 1426 { 1427 /* pin-controller instance 0 ALIVE data */ 1428 .pin_banks = exynosautov920_pin_banks0, 1429 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0), 1430 .eint_wkup_init = exynos_eint_wkup_init, 1431 .suspend = exynosautov920_pinctrl_suspend, 1432 .resume = exynosautov920_pinctrl_resume, 1433 .retention_data = &no_retention_data, 1434 }, { 1435 /* pin-controller instance 1 AUD data */ 1436 .pin_banks = exynosautov920_pin_banks1, 1437 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks1), 1438 }, { 1439 /* pin-controller instance 2 HSI0 data */ 1440 .pin_banks = exynosautov920_pin_banks2, 1441 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2), 1442 .eint_gpio_init = exynos_eint_gpio_init, 1443 .suspend = exynosautov920_pinctrl_suspend, 1444 .resume = exynosautov920_pinctrl_resume, 1445 }, { 1446 /* pin-controller instance 3 HSI1 data */ 1447 .pin_banks = exynosautov920_pin_banks3, 1448 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3), 1449 .eint_gpio_init = exynos_eint_gpio_init, 1450 .suspend = exynosautov920_pinctrl_suspend, 1451 .resume = exynosautov920_pinctrl_resume, 1452 }, { 1453 /* pin-controller instance 4 HSI2 data */ 1454 .pin_banks = exynosautov920_pin_banks4, 1455 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4), 1456 .eint_gpio_init = exynos_eint_gpio_init, 1457 .suspend = exynosautov920_pinctrl_suspend, 1458 .resume = exynosautov920_pinctrl_resume, 1459 }, { 1460 /* pin-controller instance 5 HSI2UFS data */ 1461 .pin_banks = exynosautov920_pin_banks5, 1462 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5), 1463 .eint_gpio_init = exynos_eint_gpio_init, 1464 .suspend = exynosautov920_pinctrl_suspend, 1465 .resume = exynosautov920_pinctrl_resume, 1466 }, { 1467 /* pin-controller instance 6 PERIC0 data */ 1468 .pin_banks = exynosautov920_pin_banks6, 1469 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6), 1470 .eint_gpio_init = exynos_eint_gpio_init, 1471 .suspend = exynosautov920_pinctrl_suspend, 1472 .resume = exynosautov920_pinctrl_resume, 1473 }, { 1474 /* pin-controller instance 7 PERIC1 data */ 1475 .pin_banks = exynosautov920_pin_banks7, 1476 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7), 1477 .eint_gpio_init = exynos_eint_gpio_init, 1478 .suspend = exynosautov920_pinctrl_suspend, 1479 .resume = exynosautov920_pinctrl_resume, 1480 }, 1481 }; 1482 1483 const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = { 1484 .ctrl = exynosautov920_pin_ctrl, 1485 .num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl), 1486 }; 1487 1488 /* pin banks of exynos8895 pin-controller 0 (ALIVE) */ 1489 static const struct samsung_pin_bank_data exynos8895_pin_banks0[] __initconst = { 1490 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), 1491 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), 1492 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), 1493 EXYNOS_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c), 1494 EXYNOS_PIN_BANK_EINTW(7, 0x0a0, "gpa4", 0x24), 1495 }; 1496 1497 /* pin banks of exynos8895 pin-controller 1 (ABOX) */ 1498 static const struct samsung_pin_bank_data exynos8895_pin_banks1[] __initconst = { 1499 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00), 1500 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gph1", 0x04), 1501 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gph3", 0x08), 1502 }; 1503 1504 /* pin banks of exynos8895 pin-controller 2 (VTS) */ 1505 static const struct samsung_pin_bank_data exynos8895_pin_banks2[] __initconst = { 1506 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gph2", 0x00), 1507 }; 1508 1509 /* pin banks of exynos8895 pin-controller 3 (FSYS0) */ 1510 static const struct samsung_pin_bank_data exynos8895_pin_banks3[] __initconst = { 1511 EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpi0", 0x00), 1512 EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpi1", 0x04), 1513 }; 1514 1515 /* pin banks of exynos8895 pin-controller 4 (FSYS1) */ 1516 static const struct samsung_pin_bank_data exynos8895_pin_banks4[] __initconst = { 1517 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj1", 0x00), 1518 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpj0", 0x04), 1519 }; 1520 1521 /* pin banks of exynos8895 pin-controller 5 (BUSC) */ 1522 static const struct samsung_pin_bank_data exynos8895_pin_banks5[] __initconst = { 1523 EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpb2", 0x00), 1524 }; 1525 1526 /* pin banks of exynos8895 pin-controller 6 (PERIC0) */ 1527 static const struct samsung_pin_bank_data exynos8895_pin_banks6[] __initconst = { 1528 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpd0", 0x00), 1529 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpd1", 0x04), 1530 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpd2", 0x08), 1531 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpd3", 0x0C), 1532 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), 1533 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpe7", 0x14), 1534 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf1", 0x18), 1535 }; 1536 1537 /* pin banks of exynos8895 pin-controller 7 (PERIC1) */ 1538 static const struct samsung_pin_bank_data exynos8895_pin_banks7[] __initconst = { 1539 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpb0", 0x00), 1540 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpc0", 0x04), 1541 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpc1", 0x08), 1542 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpc2", 0x0C), 1543 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), 1544 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpk0", 0x14), 1545 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpe5", 0x18), 1546 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe6", 0x1C), 1547 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe2", 0x20), 1548 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpe3", 0x24), 1549 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe4", 0x28), 1550 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpf0", 0x2C), 1551 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe1", 0x30), 1552 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), 1553 }; 1554 1555 static const struct samsung_pin_ctrl exynos8895_pin_ctrl[] __initconst = { 1556 { 1557 /* pin-controller instance 0 ALIVE data */ 1558 .pin_banks = exynos8895_pin_banks0, 1559 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks0), 1560 .eint_gpio_init = exynos_eint_gpio_init, 1561 .eint_wkup_init = exynos_eint_wkup_init, 1562 .suspend = exynos_pinctrl_suspend, 1563 .resume = exynos_pinctrl_resume, 1564 }, { 1565 /* pin-controller instance 1 ABOX data */ 1566 .pin_banks = exynos8895_pin_banks1, 1567 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks1), 1568 }, { 1569 /* pin-controller instance 2 VTS data */ 1570 .pin_banks = exynos8895_pin_banks2, 1571 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks2), 1572 .eint_gpio_init = exynos_eint_gpio_init, 1573 }, { 1574 /* pin-controller instance 3 FSYS0 data */ 1575 .pin_banks = exynos8895_pin_banks3, 1576 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks3), 1577 .eint_gpio_init = exynos_eint_gpio_init, 1578 .suspend = exynos_pinctrl_suspend, 1579 .resume = exynos_pinctrl_resume, 1580 }, { 1581 /* pin-controller instance 4 FSYS1 data */ 1582 .pin_banks = exynos8895_pin_banks4, 1583 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks4), 1584 .eint_gpio_init = exynos_eint_gpio_init, 1585 .suspend = exynos_pinctrl_suspend, 1586 .resume = exynos_pinctrl_resume, 1587 }, { 1588 /* pin-controller instance 5 BUSC data */ 1589 .pin_banks = exynos8895_pin_banks5, 1590 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks5), 1591 .eint_gpio_init = exynos_eint_gpio_init, 1592 .suspend = exynos_pinctrl_suspend, 1593 .resume = exynos_pinctrl_resume, 1594 }, { 1595 /* pin-controller instance 6 PERIC0 data */ 1596 .pin_banks = exynos8895_pin_banks6, 1597 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks6), 1598 .eint_gpio_init = exynos_eint_gpio_init, 1599 .suspend = exynos_pinctrl_suspend, 1600 .resume = exynos_pinctrl_resume, 1601 }, { 1602 /* pin-controller instance 7 PERIC1 data */ 1603 .pin_banks = exynos8895_pin_banks7, 1604 .nr_banks = ARRAY_SIZE(exynos8895_pin_banks7), 1605 .eint_gpio_init = exynos_eint_gpio_init, 1606 .suspend = exynos_pinctrl_suspend, 1607 .resume = exynos_pinctrl_resume, 1608 }, 1609 }; 1610 1611 const struct samsung_pinctrl_of_match_data exynos8895_of_data __initconst = { 1612 .ctrl = exynos8895_pin_ctrl, 1613 .num_ctrl = ARRAY_SIZE(exynos8895_pin_ctrl), 1614 }; 1615 1616 /* 1617 * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three 1618 * gpio/pin-mux/pinconfig controllers. 1619 */ 1620 1621 /* pin banks of FSD pin-controller 0 (FSYS) */ 1622 static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = { 1623 EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00), 1624 EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04), 1625 EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08), 1626 EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c), 1627 EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10), 1628 }; 1629 1630 /* pin banks of FSD pin-controller 1 (PERIC) */ 1631 static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = { 1632 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00), 1633 EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04), 1634 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08), 1635 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c), 1636 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10), 1637 EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14), 1638 EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18), 1639 EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c), 1640 EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20), 1641 EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24), 1642 EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28), 1643 EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), 1644 EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30), 1645 EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34), 1646 EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38), 1647 EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c), 1648 EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), 1649 EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44), 1650 EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48), 1651 EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c), 1652 EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50), 1653 }; 1654 1655 /* pin banks of FSD pin-controller 2 (PMU) */ 1656 static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = { 1657 EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"), 1658 }; 1659 1660 static const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = { 1661 { 1662 /* pin-controller instance 0 FSYS0 data */ 1663 .pin_banks = fsd_pin_banks0, 1664 .nr_banks = ARRAY_SIZE(fsd_pin_banks0), 1665 .eint_gpio_init = exynos_eint_gpio_init, 1666 .suspend = exynos_pinctrl_suspend, 1667 .resume = exynos_pinctrl_resume, 1668 }, { 1669 /* pin-controller instance 1 PERIC data */ 1670 .pin_banks = fsd_pin_banks1, 1671 .nr_banks = ARRAY_SIZE(fsd_pin_banks1), 1672 .eint_gpio_init = exynos_eint_gpio_init, 1673 .suspend = exynos_pinctrl_suspend, 1674 .resume = exynos_pinctrl_resume, 1675 }, { 1676 /* pin-controller instance 2 PMU data */ 1677 .pin_banks = fsd_pin_banks2, 1678 .nr_banks = ARRAY_SIZE(fsd_pin_banks2), 1679 }, 1680 }; 1681 1682 const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { 1683 .ctrl = fsd_pin_ctrl, 1684 .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), 1685 }; 1686 1687 /* pin banks of gs101 pin-controller (ALIVE) */ 1688 static const struct samsung_pin_bank_data gs101_pin_alive[] = { 1689 GS101_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00, 0x00), 1690 GS101_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04, 0x08), 1691 GS101_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08, 0x10), 1692 GS101_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c, 0x18), 1693 GS101_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10, 0x1c), 1694 GS101_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14, 0x20), 1695 GS101_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18, 0x28), 1696 GS101_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c, 0x30), 1697 }; 1698 1699 /* pin banks of gs101 pin-controller (FAR_ALIVE) */ 1700 static const struct samsung_pin_bank_data gs101_pin_far_alive[] = { 1701 GS101_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00, 0x00), 1702 GS101_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04, 0x08), 1703 GS101_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08, 0x0c), 1704 GS101_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c, 0x14), 1705 }; 1706 1707 /* pin banks of gs101 pin-controller (GSACORE) */ 1708 static const struct samsung_pin_bank_data gs101_pin_gsacore[] = { 1709 GS101_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00, 0x00), 1710 GS101_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04, 0x04), 1711 GS101_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08, 0x0c), 1712 }; 1713 1714 /* pin banks of gs101 pin-controller (GSACTRL) */ 1715 static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = { 1716 GS101_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00, 0x00), 1717 }; 1718 1719 /* pin banks of gs101 pin-controller (PERIC0) */ 1720 static const struct samsung_pin_bank_data gs101_pin_peric0[] = { 1721 GS101_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00, 0x00), 1722 GS101_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04, 0x08), 1723 GS101_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08, 0x0c), 1724 GS101_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c, 0x10), 1725 GS101_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10, 0x14), 1726 GS101_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14, 0x18), 1727 GS101_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18, 0x1c), 1728 GS101_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c, 0x20), 1729 GS101_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20, 0x24), 1730 GS101_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24, 0x28), 1731 GS101_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28, 0x2c), 1732 GS101_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c, 0x30), 1733 GS101_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30, 0x34), 1734 GS101_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34, 0x38), 1735 GS101_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38, 0x3c), 1736 GS101_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c, 0x40), 1737 GS101_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40, 0x44), 1738 GS101_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44, 0x48), 1739 GS101_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48, 0x4c), 1740 GS101_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c, 0x50), 1741 }; 1742 1743 /* pin banks of gs101 pin-controller (PERIC1) */ 1744 static const struct samsung_pin_bank_data gs101_pin_peric1[] = { 1745 GS101_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00, 0x00), 1746 GS101_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04, 0x08), 1747 GS101_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08, 0x0c), 1748 GS101_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c, 0x10), 1749 GS101_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10, 0x18), 1750 GS101_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14, 0x1c), 1751 GS101_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18, 0x20), 1752 GS101_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c, 0x28), 1753 }; 1754 1755 /* pin banks of gs101 pin-controller (HSI1) */ 1756 static const struct samsung_pin_bank_data gs101_pin_hsi1[] = { 1757 GS101_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00, 0x00), 1758 GS101_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04, 0x08), 1759 }; 1760 1761 /* pin banks of gs101 pin-controller (HSI2) */ 1762 static const struct samsung_pin_bank_data gs101_pin_hsi2[] = { 1763 GS101_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00, 0x00), 1764 GS101_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04, 0x08), 1765 GS101_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08, 0x0c), 1766 }; 1767 1768 static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { 1769 { 1770 /* pin banks of gs101 pin-controller (ALIVE) */ 1771 .pin_banks = gs101_pin_alive, 1772 .nr_banks = ARRAY_SIZE(gs101_pin_alive), 1773 .eint_wkup_init = exynos_eint_wkup_init, 1774 .suspend = gs101_pinctrl_suspend, 1775 .resume = gs101_pinctrl_resume, 1776 .retention_data = &no_retention_data, 1777 }, { 1778 /* pin banks of gs101 pin-controller (FAR_ALIVE) */ 1779 .pin_banks = gs101_pin_far_alive, 1780 .nr_banks = ARRAY_SIZE(gs101_pin_far_alive), 1781 .eint_wkup_init = exynos_eint_wkup_init, 1782 .suspend = gs101_pinctrl_suspend, 1783 .resume = gs101_pinctrl_resume, 1784 .retention_data = &no_retention_data, 1785 }, { 1786 /* pin banks of gs101 pin-controller (GSACORE) */ 1787 .pin_banks = gs101_pin_gsacore, 1788 .nr_banks = ARRAY_SIZE(gs101_pin_gsacore), 1789 }, { 1790 /* pin banks of gs101 pin-controller (GSACTRL) */ 1791 .pin_banks = gs101_pin_gsactrl, 1792 .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl), 1793 }, { 1794 /* pin banks of gs101 pin-controller (PERIC0) */ 1795 .pin_banks = gs101_pin_peric0, 1796 .nr_banks = ARRAY_SIZE(gs101_pin_peric0), 1797 .eint_gpio_init = exynos_eint_gpio_init, 1798 .suspend = gs101_pinctrl_suspend, 1799 .resume = gs101_pinctrl_resume, 1800 }, { 1801 /* pin banks of gs101 pin-controller (PERIC1) */ 1802 .pin_banks = gs101_pin_peric1, 1803 .nr_banks = ARRAY_SIZE(gs101_pin_peric1), 1804 .eint_gpio_init = exynos_eint_gpio_init, 1805 .suspend = gs101_pinctrl_suspend, 1806 .resume = gs101_pinctrl_resume, 1807 }, { 1808 /* pin banks of gs101 pin-controller (HSI1) */ 1809 .pin_banks = gs101_pin_hsi1, 1810 .nr_banks = ARRAY_SIZE(gs101_pin_hsi1), 1811 .eint_gpio_init = exynos_eint_gpio_init, 1812 .suspend = gs101_pinctrl_suspend, 1813 .resume = gs101_pinctrl_resume, 1814 }, { 1815 /* pin banks of gs101 pin-controller (HSI2) */ 1816 .pin_banks = gs101_pin_hsi2, 1817 .nr_banks = ARRAY_SIZE(gs101_pin_hsi2), 1818 .eint_gpio_init = exynos_eint_gpio_init, 1819 .suspend = gs101_pinctrl_suspend, 1820 .resume = gs101_pinctrl_resume, 1821 }, 1822 }; 1823 1824 const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = { 1825 .ctrl = gs101_pin_ctrl, 1826 .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl), 1827 }; 1828 1829 /* pin banks of artpec8 pin-controller (FSYS0) */ 1830 static const struct samsung_pin_bank_data artpec8_pin_banks0[] __initconst = { 1831 ARTPEC_PIN_BANK_EINTG(5, 0x000, "gpf0", 0x00), 1832 ARTPEC_PIN_BANK_EINTG(4, 0x020, "gpf1", 0x04), 1833 ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpf2", 0x08), 1834 ARTPEC_PIN_BANK_EINTG(4, 0x060, "gpf3", 0x0c), 1835 ARTPEC_PIN_BANK_EINTG(7, 0x080, "gpf4", 0x10), 1836 ARTPEC_PIN_BANK_EINTG(8, 0x0a0, "gpe0", 0x14), 1837 ARTPEC_PIN_BANK_EINTG(8, 0x0c0, "gpe1", 0x18), 1838 ARTPEC_PIN_BANK_EINTG(6, 0x0e0, "gpe2", 0x1c), 1839 ARTPEC_PIN_BANK_EINTG(8, 0x100, "gps0", 0x20), 1840 ARTPEC_PIN_BANK_EINTG(8, 0x120, "gps1", 0x24), 1841 }; 1842 1843 /* pin banks of artpec8 pin-controller (PERIC) */ 1844 static const struct samsung_pin_bank_data artpec8_pin_banks1[] __initconst = { 1845 ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 1846 ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpa1", 0x04), 1847 ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1848 ARTPEC_PIN_BANK_EINTG(2, 0x060, "gpk0", 0x0c), 1849 }; 1850 1851 static const struct samsung_pin_ctrl artpec8_pin_ctrl[] __initconst = { 1852 { 1853 /* pin-controller instance 0 FSYS data */ 1854 .pin_banks = artpec8_pin_banks0, 1855 .nr_banks = ARRAY_SIZE(artpec8_pin_banks0), 1856 .eint_gpio_init = exynos_eint_gpio_init, 1857 }, { 1858 /* pin-controller instance 1 PERIC data */ 1859 .pin_banks = artpec8_pin_banks1, 1860 .nr_banks = ARRAY_SIZE(artpec8_pin_banks1), 1861 .eint_gpio_init = exynos_eint_gpio_init, 1862 }, 1863 }; 1864 1865 const struct samsung_pinctrl_of_match_data artpec8_of_data __initconst = { 1866 .ctrl = artpec8_pin_ctrl, 1867 .num_ctrl = ARRAY_SIZE(artpec8_pin_ctrl), 1868 }; 1869