1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. 4 // 5 // Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 // http://www.samsung.com 7 // Copyright (c) 2012 Linaro Ltd 8 // http://www.linaro.org 9 // 10 // Author: Thomas Abraham <thomas.ab@samsung.com> 11 // 12 // This file contains the Samsung Exynos specific information required by the 13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of 14 // external gpio and wakeup interrupt support. 15 16 #include <linux/device.h> 17 #include <linux/of_address.h> 18 #include <linux/slab.h> 19 #include <linux/err.h> 20 #include <linux/soc/samsung/exynos-regs-pmu.h> 21 22 #include "pinctrl-samsung.h" 23 #include "pinctrl-exynos.h" 24 25 static const struct samsung_pin_bank_type bank_type_off = { 26 .fld_width = { 4, 1, 2, 2, 2, 2, }, 27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 28 }; 29 30 static const struct samsung_pin_bank_type bank_type_alive = { 31 .fld_width = { 4, 1, 2, 2, }, 32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 33 }; 34 35 /* Retention control for S5PV210 are located at the end of clock controller */ 36 #define S5P_OTHERS 0xE000 37 38 #define S5P_OTHERS_RET_IO (1 << 31) 39 #define S5P_OTHERS_RET_CF (1 << 30) 40 #define S5P_OTHERS_RET_MMC (1 << 29) 41 #define S5P_OTHERS_RET_UART (1 << 28) 42 43 static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata) 44 { 45 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; 46 u32 tmp; 47 48 tmp = __raw_readl(clk_base + S5P_OTHERS); 49 tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC | 50 S5P_OTHERS_RET_UART); 51 __raw_writel(tmp, clk_base + S5P_OTHERS); 52 } 53 54 static struct samsung_retention_ctrl * 55 s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata, 56 const struct samsung_retention_data *data) 57 { 58 struct samsung_retention_ctrl *ctrl; 59 struct device_node *np; 60 void __iomem *clk_base; 61 62 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); 63 if (!ctrl) 64 return ERR_PTR(-ENOMEM); 65 66 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); 67 if (!np) { 68 pr_err("%s: failed to find clock controller DT node\n", 69 __func__); 70 return ERR_PTR(-ENODEV); 71 } 72 73 clk_base = of_iomap(np, 0); 74 of_node_put(np); 75 if (!clk_base) { 76 pr_err("%s: failed to map clock registers\n", __func__); 77 return ERR_PTR(-EINVAL); 78 } 79 80 ctrl->priv = (void __force *)clk_base; 81 ctrl->disable = s5pv210_retention_disable; 82 83 return ctrl; 84 } 85 86 static const struct samsung_retention_data s5pv210_retention_data __initconst = { 87 .init = s5pv210_retention_init, 88 }; 89 90 /* pin banks of s5pv210 pin-controller */ 91 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = { 92 /* Must start with EINTG banks, ordered by EINT group number. */ 93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04), 95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 99 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), 100 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c), 101 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20), 102 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24), 103 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28), 104 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c), 105 EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30), 106 EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34), 107 EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38), 108 EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c), 109 EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40), 110 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44), 111 EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48), 112 EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c), 113 EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50), 114 EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54), 115 EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"), 116 EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"), 117 EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"), 118 EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"), 119 EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"), 120 EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"), 121 EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"), 122 EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"), 123 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00), 124 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04), 125 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08), 126 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c), 127 }; 128 129 static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = { 130 { 131 /* pin-controller instance 0 data */ 132 .pin_banks = s5pv210_pin_bank, 133 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank), 134 .eint_gpio_init = exynos_eint_gpio_init, 135 .eint_wkup_init = exynos_eint_wkup_init, 136 .suspend = exynos_pinctrl_suspend, 137 .resume = exynos_pinctrl_resume, 138 .retention_data = &s5pv210_retention_data, 139 }, 140 }; 141 142 const struct samsung_pinctrl_of_match_data s5pv210_of_data __initconst = { 143 .ctrl = s5pv210_pin_ctrl, 144 .num_ctrl = ARRAY_SIZE(s5pv210_pin_ctrl), 145 }; 146 147 /* Pad retention control code for accessing PMU regmap */ 148 static atomic_t exynos_shared_retention_refcnt; 149 150 /* pin banks of exynos3250 pin-controller 0 */ 151 static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = { 152 /* Must start with EINTG banks, ordered by EINT group number. */ 153 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 154 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 155 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 156 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 157 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 158 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), 159 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18), 160 }; 161 162 /* pin banks of exynos3250 pin-controller 1 */ 163 static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = { 164 /* Must start with EINTG banks, ordered by EINT group number. */ 165 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"), 166 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"), 167 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"), 168 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08), 169 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 170 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 171 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18), 172 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), 173 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), 174 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c), 175 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30), 176 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34), 177 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), 178 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), 179 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), 180 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), 181 }; 182 183 /* 184 * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle 185 * them all together 186 */ 187 static const u32 exynos3250_retention_regs[] = { 188 S5P_PAD_RET_MAUDIO_OPTION, 189 S5P_PAD_RET_GPIO_OPTION, 190 S5P_PAD_RET_UART_OPTION, 191 S5P_PAD_RET_MMCA_OPTION, 192 S5P_PAD_RET_MMCB_OPTION, 193 S5P_PAD_RET_EBIA_OPTION, 194 S5P_PAD_RET_EBIB_OPTION, 195 S5P_PAD_RET_MMC2_OPTION, 196 S5P_PAD_RET_SPI_OPTION, 197 }; 198 199 static const struct samsung_retention_data exynos3250_retention_data __initconst = { 200 .regs = exynos3250_retention_regs, 201 .nr_regs = ARRAY_SIZE(exynos3250_retention_regs), 202 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 203 .refcnt = &exynos_shared_retention_refcnt, 204 .init = exynos_retention_init, 205 }; 206 207 /* 208 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes 209 * two gpio/pin-mux/pinconfig controllers. 210 */ 211 static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = { 212 { 213 /* pin-controller instance 0 data */ 214 .pin_banks = exynos3250_pin_banks0, 215 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0), 216 .eint_gpio_init = exynos_eint_gpio_init, 217 .suspend = exynos_pinctrl_suspend, 218 .resume = exynos_pinctrl_resume, 219 .retention_data = &exynos3250_retention_data, 220 }, { 221 /* pin-controller instance 1 data */ 222 .pin_banks = exynos3250_pin_banks1, 223 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1), 224 .eint_gpio_init = exynos_eint_gpio_init, 225 .eint_wkup_init = exynos_eint_wkup_init, 226 .suspend = exynos_pinctrl_suspend, 227 .resume = exynos_pinctrl_resume, 228 .retention_data = &exynos3250_retention_data, 229 }, 230 }; 231 232 const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = { 233 .ctrl = exynos3250_pin_ctrl, 234 .num_ctrl = ARRAY_SIZE(exynos3250_pin_ctrl), 235 }; 236 237 /* pin banks of exynos4210 pin-controller 0 */ 238 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = { 239 /* Must start with EINTG banks, ordered by EINT group number. */ 240 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 241 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 242 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 243 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 244 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 245 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 246 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), 247 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c), 248 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), 249 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24), 250 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28), 251 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c), 252 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), 253 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), 254 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), 255 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), 256 }; 257 258 /* pin banks of exynos4210 pin-controller 1 */ 259 static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = { 260 /* Must start with EINTG banks, ordered by EINT group number. */ 261 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), 262 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), 263 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), 264 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 265 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 266 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), 267 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18), 268 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c), 269 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), 270 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), 271 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), 272 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), 273 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), 274 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), 275 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), 276 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), 277 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 278 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 279 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 280 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 281 }; 282 283 /* pin banks of exynos4210 pin-controller 2 */ 284 static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = { 285 /* Must start with EINTG banks, ordered by EINT group number. */ 286 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), 287 }; 288 289 /* PMU pad retention groups registers for Exynos4 (without audio) */ 290 static const u32 exynos4_retention_regs[] = { 291 S5P_PAD_RET_GPIO_OPTION, 292 S5P_PAD_RET_UART_OPTION, 293 S5P_PAD_RET_MMCA_OPTION, 294 S5P_PAD_RET_MMCB_OPTION, 295 S5P_PAD_RET_EBIA_OPTION, 296 S5P_PAD_RET_EBIB_OPTION, 297 }; 298 299 static const struct samsung_retention_data exynos4_retention_data __initconst = { 300 .regs = exynos4_retention_regs, 301 .nr_regs = ARRAY_SIZE(exynos4_retention_regs), 302 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 303 .refcnt = &exynos_shared_retention_refcnt, 304 .init = exynos_retention_init, 305 }; 306 307 /* PMU retention control for audio pins can be tied to audio pin bank */ 308 static const u32 exynos4_audio_retention_regs[] = { 309 S5P_PAD_RET_MAUDIO_OPTION, 310 }; 311 312 static const struct samsung_retention_data exynos4_audio_retention_data __initconst = { 313 .regs = exynos4_audio_retention_regs, 314 .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs), 315 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 316 .init = exynos_retention_init, 317 }; 318 319 /* 320 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes 321 * three gpio/pin-mux/pinconfig controllers. 322 */ 323 static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = { 324 { 325 /* pin-controller instance 0 data */ 326 .pin_banks = exynos4210_pin_banks0, 327 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), 328 .eint_gpio_init = exynos_eint_gpio_init, 329 .suspend = exynos_pinctrl_suspend, 330 .resume = exynos_pinctrl_resume, 331 .retention_data = &exynos4_retention_data, 332 }, { 333 /* pin-controller instance 1 data */ 334 .pin_banks = exynos4210_pin_banks1, 335 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), 336 .eint_gpio_init = exynos_eint_gpio_init, 337 .eint_wkup_init = exynos_eint_wkup_init, 338 .suspend = exynos_pinctrl_suspend, 339 .resume = exynos_pinctrl_resume, 340 .retention_data = &exynos4_retention_data, 341 }, { 342 /* pin-controller instance 2 data */ 343 .pin_banks = exynos4210_pin_banks2, 344 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), 345 .retention_data = &exynos4_audio_retention_data, 346 }, 347 }; 348 349 const struct samsung_pinctrl_of_match_data exynos4210_of_data __initconst = { 350 .ctrl = exynos4210_pin_ctrl, 351 .num_ctrl = ARRAY_SIZE(exynos4210_pin_ctrl), 352 }; 353 354 /* pin banks of exynos4x12 pin-controller 0 */ 355 static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = { 356 /* Must start with EINTG banks, ordered by EINT group number. */ 357 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 358 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 359 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 360 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 361 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 362 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), 363 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), 364 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), 365 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), 366 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), 367 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), 368 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40), 369 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44), 370 }; 371 372 /* pin banks of exynos4x12 pin-controller 1 */ 373 static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = { 374 /* Must start with EINTG banks, ordered by EINT group number. */ 375 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), 376 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 377 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 378 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), 379 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18), 380 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c), 381 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), 382 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), 383 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), 384 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), 385 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), 386 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), 387 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), 388 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), 389 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), 390 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), 391 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), 392 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), 393 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), 394 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 395 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 396 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 397 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 398 }; 399 400 /* pin banks of exynos4x12 pin-controller 2 */ 401 static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = { 402 /* Must start with EINTG banks, ordered by EINT group number. */ 403 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 404 }; 405 406 /* pin banks of exynos4x12 pin-controller 3 */ 407 static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = { 408 /* Must start with EINTG banks, ordered by EINT group number. */ 409 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 410 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 411 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08), 412 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c), 413 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10), 414 }; 415 416 /* 417 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes 418 * four gpio/pin-mux/pinconfig controllers. 419 */ 420 static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { 421 { 422 /* pin-controller instance 0 data */ 423 .pin_banks = exynos4x12_pin_banks0, 424 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), 425 .eint_gpio_init = exynos_eint_gpio_init, 426 .suspend = exynos_pinctrl_suspend, 427 .resume = exynos_pinctrl_resume, 428 .retention_data = &exynos4_retention_data, 429 }, { 430 /* pin-controller instance 1 data */ 431 .pin_banks = exynos4x12_pin_banks1, 432 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), 433 .eint_gpio_init = exynos_eint_gpio_init, 434 .eint_wkup_init = exynos_eint_wkup_init, 435 .suspend = exynos_pinctrl_suspend, 436 .resume = exynos_pinctrl_resume, 437 .retention_data = &exynos4_retention_data, 438 }, { 439 /* pin-controller instance 2 data */ 440 .pin_banks = exynos4x12_pin_banks2, 441 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), 442 .eint_gpio_init = exynos_eint_gpio_init, 443 .suspend = exynos_pinctrl_suspend, 444 .resume = exynos_pinctrl_resume, 445 .retention_data = &exynos4_audio_retention_data, 446 }, { 447 /* pin-controller instance 3 data */ 448 .pin_banks = exynos4x12_pin_banks3, 449 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), 450 .eint_gpio_init = exynos_eint_gpio_init, 451 .suspend = exynos_pinctrl_suspend, 452 .resume = exynos_pinctrl_resume, 453 }, 454 }; 455 456 const struct samsung_pinctrl_of_match_data exynos4x12_of_data __initconst = { 457 .ctrl = exynos4x12_pin_ctrl, 458 .num_ctrl = ARRAY_SIZE(exynos4x12_pin_ctrl), 459 }; 460 461 /* pin banks of exynos5250 pin-controller 0 */ 462 static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = { 463 /* Must start with EINTG banks, ordered by EINT group number. */ 464 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 465 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 466 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 467 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 468 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), 469 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), 470 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), 471 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), 472 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20), 473 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24), 474 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28), 475 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c), 476 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30), 477 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34), 478 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"), 479 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"), 480 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"), 481 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"), 482 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"), 483 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"), 484 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"), 485 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 486 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 487 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 488 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 489 }; 490 491 /* pin banks of exynos5250 pin-controller 1 */ 492 static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = { 493 /* Must start with EINTG banks, ordered by EINT group number. */ 494 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), 495 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), 496 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08), 497 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c), 498 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), 499 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), 500 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), 501 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c), 502 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20), 503 }; 504 505 /* pin banks of exynos5250 pin-controller 2 */ 506 static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = { 507 /* Must start with EINTG banks, ordered by EINT group number. */ 508 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 509 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 510 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), 511 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), 512 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), 513 }; 514 515 /* pin banks of exynos5250 pin-controller 3 */ 516 static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = { 517 /* Must start with EINTG banks, ordered by EINT group number. */ 518 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 519 }; 520 521 /* 522 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes 523 * four gpio/pin-mux/pinconfig controllers. 524 */ 525 static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { 526 { 527 /* pin-controller instance 0 data */ 528 .pin_banks = exynos5250_pin_banks0, 529 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), 530 .eint_gpio_init = exynos_eint_gpio_init, 531 .eint_wkup_init = exynos_eint_wkup_init, 532 .suspend = exynos_pinctrl_suspend, 533 .resume = exynos_pinctrl_resume, 534 .retention_data = &exynos4_retention_data, 535 }, { 536 /* pin-controller instance 1 data */ 537 .pin_banks = exynos5250_pin_banks1, 538 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), 539 .eint_gpio_init = exynos_eint_gpio_init, 540 .suspend = exynos_pinctrl_suspend, 541 .resume = exynos_pinctrl_resume, 542 .retention_data = &exynos4_retention_data, 543 }, { 544 /* pin-controller instance 2 data */ 545 .pin_banks = exynos5250_pin_banks2, 546 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), 547 .eint_gpio_init = exynos_eint_gpio_init, 548 .suspend = exynos_pinctrl_suspend, 549 .resume = exynos_pinctrl_resume, 550 }, { 551 /* pin-controller instance 3 data */ 552 .pin_banks = exynos5250_pin_banks3, 553 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), 554 .eint_gpio_init = exynos_eint_gpio_init, 555 .suspend = exynos_pinctrl_suspend, 556 .resume = exynos_pinctrl_resume, 557 .retention_data = &exynos4_audio_retention_data, 558 }, 559 }; 560 561 const struct samsung_pinctrl_of_match_data exynos5250_of_data __initconst = { 562 .ctrl = exynos5250_pin_ctrl, 563 .num_ctrl = ARRAY_SIZE(exynos5250_pin_ctrl), 564 }; 565 566 /* pin banks of exynos5260 pin-controller 0 */ 567 static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = { 568 /* Must start with EINTG banks, ordered by EINT group number. */ 569 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), 570 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), 571 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 572 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 573 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), 574 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14), 575 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18), 576 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c), 577 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), 578 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), 579 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), 580 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), 581 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), 582 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34), 583 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), 584 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c), 585 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), 586 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), 587 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), 588 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), 589 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), 590 }; 591 592 /* pin banks of exynos5260 pin-controller 1 */ 593 static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = { 594 /* Must start with EINTG banks, ordered by EINT group number. */ 595 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), 596 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), 597 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), 598 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), 599 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), 600 }; 601 602 /* pin banks of exynos5260 pin-controller 2 */ 603 static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = { 604 /* Must start with EINTG banks, ordered by EINT group number. */ 605 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 606 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 607 }; 608 609 /* 610 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes 611 * three gpio/pin-mux/pinconfig controllers. 612 */ 613 static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { 614 { 615 /* pin-controller instance 0 data */ 616 .pin_banks = exynos5260_pin_banks0, 617 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), 618 .eint_gpio_init = exynos_eint_gpio_init, 619 .eint_wkup_init = exynos_eint_wkup_init, 620 .suspend = exynos_pinctrl_suspend, 621 .resume = exynos_pinctrl_resume, 622 }, { 623 /* pin-controller instance 1 data */ 624 .pin_banks = exynos5260_pin_banks1, 625 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), 626 .eint_gpio_init = exynos_eint_gpio_init, 627 .suspend = exynos_pinctrl_suspend, 628 .resume = exynos_pinctrl_resume, 629 }, { 630 /* pin-controller instance 2 data */ 631 .pin_banks = exynos5260_pin_banks2, 632 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), 633 .eint_gpio_init = exynos_eint_gpio_init, 634 .suspend = exynos_pinctrl_suspend, 635 .resume = exynos_pinctrl_resume, 636 }, 637 }; 638 639 const struct samsung_pinctrl_of_match_data exynos5260_of_data __initconst = { 640 .ctrl = exynos5260_pin_ctrl, 641 .num_ctrl = ARRAY_SIZE(exynos5260_pin_ctrl), 642 }; 643 644 /* pin banks of exynos5410 pin-controller 0 */ 645 static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = { 646 /* Must start with EINTG banks, ordered by EINT group number. */ 647 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 648 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 649 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 650 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 651 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), 652 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), 653 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), 654 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), 655 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20), 656 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24), 657 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28), 658 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c), 659 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30), 660 EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34), 661 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38), 662 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c), 663 EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40), 664 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44), 665 EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48), 666 EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c), 667 EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50), 668 EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"), 669 EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"), 670 EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"), 671 EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"), 672 EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"), 673 EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"), 674 EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"), 675 EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"), 676 EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"), 677 EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"), 678 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 679 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 680 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 681 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 682 }; 683 684 /* pin banks of exynos5410 pin-controller 1 */ 685 static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = { 686 /* Must start with EINTG banks, ordered by EINT group number. */ 687 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00), 688 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04), 689 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08), 690 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c), 691 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10), 692 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14), 693 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18), 694 EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c), 695 EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20), 696 }; 697 698 /* pin banks of exynos5410 pin-controller 2 */ 699 static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = { 700 /* Must start with EINTG banks, ordered by EINT group number. */ 701 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 702 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 703 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), 704 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), 705 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), 706 }; 707 708 /* pin banks of exynos5410 pin-controller 3 */ 709 static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = { 710 /* Must start with EINTG banks, ordered by EINT group number. */ 711 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 712 }; 713 714 /* 715 * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes 716 * four gpio/pin-mux/pinconfig controllers. 717 */ 718 static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = { 719 { 720 /* pin-controller instance 0 data */ 721 .pin_banks = exynos5410_pin_banks0, 722 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0), 723 .eint_gpio_init = exynos_eint_gpio_init, 724 .eint_wkup_init = exynos_eint_wkup_init, 725 .suspend = exynos_pinctrl_suspend, 726 .resume = exynos_pinctrl_resume, 727 }, { 728 /* pin-controller instance 1 data */ 729 .pin_banks = exynos5410_pin_banks1, 730 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1), 731 .eint_gpio_init = exynos_eint_gpio_init, 732 .suspend = exynos_pinctrl_suspend, 733 .resume = exynos_pinctrl_resume, 734 }, { 735 /* pin-controller instance 2 data */ 736 .pin_banks = exynos5410_pin_banks2, 737 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2), 738 .eint_gpio_init = exynos_eint_gpio_init, 739 .suspend = exynos_pinctrl_suspend, 740 .resume = exynos_pinctrl_resume, 741 }, { 742 /* pin-controller instance 3 data */ 743 .pin_banks = exynos5410_pin_banks3, 744 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3), 745 .eint_gpio_init = exynos_eint_gpio_init, 746 .suspend = exynos_pinctrl_suspend, 747 .resume = exynos_pinctrl_resume, 748 }, 749 }; 750 751 const struct samsung_pinctrl_of_match_data exynos5410_of_data __initconst = { 752 .ctrl = exynos5410_pin_ctrl, 753 .num_ctrl = ARRAY_SIZE(exynos5410_pin_ctrl), 754 }; 755 756 /* pin banks of exynos5420 pin-controller 0 */ 757 static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = { 758 /* Must start with EINTG banks, ordered by EINT group number. */ 759 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), 760 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 761 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 762 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), 763 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), 764 }; 765 766 /* pin banks of exynos5420 pin-controller 1 */ 767 static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = { 768 /* Must start with EINTG banks, ordered by EINT group number. */ 769 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), 770 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), 771 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), 772 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), 773 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10), 774 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14), 775 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"), 776 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"), 777 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"), 778 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"), 779 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"), 780 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"), 781 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"), 782 }; 783 784 /* pin banks of exynos5420 pin-controller 2 */ 785 static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = { 786 /* Must start with EINTG banks, ordered by EINT group number. */ 787 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), 788 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), 789 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08), 790 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c), 791 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), 792 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), 793 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), 794 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c), 795 }; 796 797 /* pin banks of exynos5420 pin-controller 3 */ 798 static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = { 799 /* Must start with EINTG banks, ordered by EINT group number. */ 800 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 801 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 802 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 803 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), 804 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), 805 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), 806 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), 807 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c), 808 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20), 809 }; 810 811 /* pin banks of exynos5420 pin-controller 4 */ 812 static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = { 813 /* Must start with EINTG banks, ordered by EINT group number. */ 814 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 815 }; 816 817 /* PMU pad retention groups registers for Exynos5420 (without audio) */ 818 static const u32 exynos5420_retention_regs[] = { 819 EXYNOS_PAD_RET_DRAM_OPTION, 820 EXYNOS_PAD_RET_JTAG_OPTION, 821 EXYNOS5420_PAD_RET_GPIO_OPTION, 822 EXYNOS5420_PAD_RET_UART_OPTION, 823 EXYNOS5420_PAD_RET_MMCA_OPTION, 824 EXYNOS5420_PAD_RET_MMCB_OPTION, 825 EXYNOS5420_PAD_RET_MMCC_OPTION, 826 EXYNOS5420_PAD_RET_HSI_OPTION, 827 EXYNOS_PAD_RET_EBIA_OPTION, 828 EXYNOS_PAD_RET_EBIB_OPTION, 829 EXYNOS5420_PAD_RET_SPI_OPTION, 830 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, 831 }; 832 833 static const struct samsung_retention_data exynos5420_retention_data __initconst = { 834 .regs = exynos5420_retention_regs, 835 .nr_regs = ARRAY_SIZE(exynos5420_retention_regs), 836 .value = EXYNOS_WAKEUP_FROM_LOWPWR, 837 .refcnt = &exynos_shared_retention_refcnt, 838 .init = exynos_retention_init, 839 }; 840 841 /* 842 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes 843 * four gpio/pin-mux/pinconfig controllers. 844 */ 845 static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { 846 { 847 /* pin-controller instance 0 data */ 848 .pin_banks = exynos5420_pin_banks0, 849 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), 850 .eint_gpio_init = exynos_eint_gpio_init, 851 .eint_wkup_init = exynos_eint_wkup_init, 852 .suspend = exynos_pinctrl_suspend, 853 .resume = exynos_pinctrl_resume, 854 .retention_data = &exynos5420_retention_data, 855 }, { 856 /* pin-controller instance 1 data */ 857 .pin_banks = exynos5420_pin_banks1, 858 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), 859 .eint_gpio_init = exynos_eint_gpio_init, 860 .suspend = exynos_pinctrl_suspend, 861 .resume = exynos_pinctrl_resume, 862 .retention_data = &exynos5420_retention_data, 863 }, { 864 /* pin-controller instance 2 data */ 865 .pin_banks = exynos5420_pin_banks2, 866 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), 867 .eint_gpio_init = exynos_eint_gpio_init, 868 .suspend = exynos_pinctrl_suspend, 869 .resume = exynos_pinctrl_resume, 870 .retention_data = &exynos5420_retention_data, 871 }, { 872 /* pin-controller instance 3 data */ 873 .pin_banks = exynos5420_pin_banks3, 874 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), 875 .eint_gpio_init = exynos_eint_gpio_init, 876 .suspend = exynos_pinctrl_suspend, 877 .resume = exynos_pinctrl_resume, 878 .retention_data = &exynos5420_retention_data, 879 }, { 880 /* pin-controller instance 4 data */ 881 .pin_banks = exynos5420_pin_banks4, 882 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), 883 .eint_gpio_init = exynos_eint_gpio_init, 884 .suspend = exynos_pinctrl_suspend, 885 .resume = exynos_pinctrl_resume, 886 .retention_data = &exynos4_audio_retention_data, 887 }, 888 }; 889 890 const struct samsung_pinctrl_of_match_data exynos5420_of_data __initconst = { 891 .ctrl = exynos5420_pin_ctrl, 892 .num_ctrl = ARRAY_SIZE(exynos5420_pin_ctrl), 893 }; 894