1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH Pin Function Controller pinmux support. 4 * 5 * Copyright (C) 2012 Paul Mundt 6 */ 7 8 #define DRV_NAME "sh-pfc" 9 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/seq_file.h> 16 #include <linux/slab.h> 17 #include <linux/spinlock.h> 18 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/pinctrl/machine.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 #include <linux/pinctrl/pinconf.h> 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 26 #include "core.h" 27 #include "../core.h" 28 #include "../pinconf.h" 29 30 struct sh_pfc_pin_config { 31 u16 gpio_enabled:1; 32 u16 mux_mark:15; 33 }; 34 35 struct sh_pfc_pinctrl { 36 struct pinctrl_dev *pctl; 37 struct pinctrl_desc pctl_desc; 38 39 struct sh_pfc *pfc; 40 41 struct pinctrl_pin_desc *pins; 42 struct sh_pfc_pin_config *configs; 43 }; 44 45 static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) 46 { 47 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 48 49 return pmx->pfc->info->nr_groups; 50 } 51 52 static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, 53 unsigned selector) 54 { 55 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 56 57 return pmx->pfc->info->groups[selector].name; 58 } 59 60 static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 61 const unsigned **pins, unsigned *num_pins) 62 { 63 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 64 65 *pins = pmx->pfc->info->groups[selector].pins; 66 *num_pins = pmx->pfc->info->groups[selector].nr_pins; 67 68 return 0; 69 } 70 71 static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 72 unsigned offset) 73 { 74 seq_puts(s, DRV_NAME); 75 } 76 77 #ifdef CONFIG_OF 78 static int sh_pfc_map_add_config(struct pinctrl_map *map, 79 const char *group_or_pin, 80 enum pinctrl_map_type type, 81 unsigned long *configs, 82 unsigned int num_configs) 83 { 84 unsigned long *cfgs; 85 86 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), 87 GFP_KERNEL); 88 if (cfgs == NULL) 89 return -ENOMEM; 90 91 map->type = type; 92 map->data.configs.group_or_pin = group_or_pin; 93 map->data.configs.configs = cfgs; 94 map->data.configs.num_configs = num_configs; 95 96 return 0; 97 } 98 99 static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev, 100 struct device_node *np, 101 struct pinctrl_map **map, 102 unsigned int *num_maps, unsigned int *index) 103 { 104 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 105 struct device *dev = pmx->pfc->dev; 106 struct pinctrl_map *maps = *map; 107 unsigned int nmaps = *num_maps; 108 unsigned int idx = *index; 109 unsigned int num_configs; 110 const char *function = NULL; 111 unsigned long *configs; 112 struct property *prop; 113 unsigned int num_groups; 114 unsigned int num_pins; 115 const char *group; 116 const char *pin; 117 int ret; 118 119 /* Parse the function and configuration properties. At least a function 120 * or one configuration must be specified. 121 */ 122 ret = of_property_read_string(np, "function", &function); 123 if (ret < 0 && ret != -EINVAL) { 124 dev_err(dev, "Invalid function in DT\n"); 125 return ret; 126 } 127 128 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); 129 if (ret < 0) 130 return ret; 131 132 if (!function && num_configs == 0) { 133 dev_err(dev, 134 "DT node must contain at least a function or config\n"); 135 ret = -ENODEV; 136 goto done; 137 } 138 139 /* Count the number of pins and groups and reallocate mappings. */ 140 ret = of_property_count_strings(np, "pins"); 141 if (ret == -EINVAL) { 142 num_pins = 0; 143 } else if (ret < 0) { 144 dev_err(dev, "Invalid pins list in DT\n"); 145 goto done; 146 } else { 147 num_pins = ret; 148 } 149 150 ret = of_property_count_strings(np, "groups"); 151 if (ret == -EINVAL) { 152 num_groups = 0; 153 } else if (ret < 0) { 154 dev_err(dev, "Invalid pin groups list in DT\n"); 155 goto done; 156 } else { 157 num_groups = ret; 158 } 159 160 if (!num_pins && !num_groups) { 161 dev_err(dev, "No pin or group provided in DT node\n"); 162 ret = -ENODEV; 163 goto done; 164 } 165 166 if (function) 167 nmaps += num_groups; 168 if (configs) 169 nmaps += num_pins + num_groups; 170 171 maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL); 172 if (maps == NULL) { 173 ret = -ENOMEM; 174 goto done; 175 } 176 177 *map = maps; 178 *num_maps = nmaps; 179 180 /* Iterate over pins and groups and create the mappings. */ 181 of_property_for_each_string(np, "groups", prop, group) { 182 if (function) { 183 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 184 maps[idx].data.mux.group = group; 185 maps[idx].data.mux.function = function; 186 idx++; 187 } 188 189 if (configs) { 190 ret = sh_pfc_map_add_config(&maps[idx], group, 191 PIN_MAP_TYPE_CONFIGS_GROUP, 192 configs, num_configs); 193 if (ret < 0) 194 goto done; 195 196 idx++; 197 } 198 } 199 200 if (!configs) { 201 ret = 0; 202 goto done; 203 } 204 205 of_property_for_each_string(np, "pins", prop, pin) { 206 ret = sh_pfc_map_add_config(&maps[idx], pin, 207 PIN_MAP_TYPE_CONFIGS_PIN, 208 configs, num_configs); 209 if (ret < 0) 210 goto done; 211 212 idx++; 213 } 214 215 done: 216 *index = idx; 217 kfree(configs); 218 return ret; 219 } 220 221 static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev, 222 struct pinctrl_map *map, unsigned num_maps) 223 { 224 unsigned int i; 225 226 if (map == NULL) 227 return; 228 229 for (i = 0; i < num_maps; ++i) { 230 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 231 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 232 kfree(map[i].data.configs.configs); 233 } 234 235 kfree(map); 236 } 237 238 static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev, 239 struct device_node *np, 240 struct pinctrl_map **map, unsigned *num_maps) 241 { 242 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 243 struct device *dev = pmx->pfc->dev; 244 unsigned int index; 245 int ret; 246 247 *map = NULL; 248 *num_maps = 0; 249 index = 0; 250 251 for_each_child_of_node_scoped(np, child) { 252 ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps, 253 &index); 254 if (ret < 0) 255 goto done; 256 } 257 258 /* If no mapping has been found in child nodes try the config node. */ 259 if (*num_maps == 0) { 260 ret = sh_pfc_dt_subnode_to_map(pctldev, np, map, num_maps, 261 &index); 262 if (ret < 0) 263 goto done; 264 } 265 266 if (*num_maps) 267 return 0; 268 269 dev_err(dev, "no mapping found in node %pOF\n", np); 270 ret = -EINVAL; 271 272 done: 273 if (ret < 0) 274 sh_pfc_dt_free_map(pctldev, *map, *num_maps); 275 276 return ret; 277 } 278 #endif /* CONFIG_OF */ 279 280 static const struct pinctrl_ops sh_pfc_pinctrl_ops = { 281 .get_groups_count = sh_pfc_get_groups_count, 282 .get_group_name = sh_pfc_get_group_name, 283 .get_group_pins = sh_pfc_get_group_pins, 284 .pin_dbg_show = sh_pfc_pin_dbg_show, 285 #ifdef CONFIG_OF 286 .dt_node_to_map = sh_pfc_dt_node_to_map, 287 .dt_free_map = sh_pfc_dt_free_map, 288 #endif 289 }; 290 291 static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) 292 { 293 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 294 295 return pmx->pfc->info->nr_functions; 296 } 297 298 static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, 299 unsigned selector) 300 { 301 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 302 303 return pmx->pfc->info->functions[selector].name; 304 } 305 306 static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, 307 unsigned selector, 308 const char * const **groups, 309 unsigned * const num_groups) 310 { 311 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 312 313 *groups = pmx->pfc->info->functions[selector].groups; 314 *num_groups = pmx->pfc->info->functions[selector].nr_groups; 315 316 return 0; 317 } 318 319 static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector, 320 unsigned group) 321 { 322 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 323 struct sh_pfc *pfc = pmx->pfc; 324 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; 325 unsigned long flags; 326 unsigned int i; 327 int ret = 0; 328 329 dev_dbg(pctldev->dev, "Configuring pin group %s\n", grp->name); 330 331 spin_lock_irqsave(&pfc->lock, flags); 332 333 for (i = 0; i < grp->nr_pins; ++i) { 334 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); 335 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 336 337 /* 338 * This driver cannot manage both gpio and mux when the gpio 339 * pin is already enabled. So, this function fails. 340 */ 341 if (cfg->gpio_enabled) { 342 ret = -EBUSY; 343 goto done; 344 } 345 346 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); 347 if (ret < 0) 348 goto done; 349 } 350 351 /* All group pins are configured, mark the pins as muxed */ 352 for (i = 0; i < grp->nr_pins; ++i) { 353 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); 354 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 355 356 cfg->mux_mark = grp->mux[i]; 357 } 358 359 done: 360 spin_unlock_irqrestore(&pfc->lock, flags); 361 return ret; 362 } 363 364 static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, 365 struct pinctrl_gpio_range *range, 366 unsigned offset) 367 { 368 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 369 struct sh_pfc *pfc = pmx->pfc; 370 int idx = sh_pfc_get_pin_index(pfc, offset); 371 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 372 unsigned long flags; 373 int ret; 374 375 spin_lock_irqsave(&pfc->lock, flags); 376 377 if (!pfc->gpio && !cfg->mux_mark) { 378 /* If GPIOs are handled externally the pin mux type needs to be 379 * set to GPIO here. 380 */ 381 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 382 383 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); 384 if (ret < 0) 385 goto done; 386 } 387 388 cfg->gpio_enabled = true; 389 390 ret = 0; 391 392 done: 393 spin_unlock_irqrestore(&pfc->lock, flags); 394 395 return ret; 396 } 397 398 static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, 399 struct pinctrl_gpio_range *range, 400 unsigned offset) 401 { 402 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 403 struct sh_pfc *pfc = pmx->pfc; 404 int idx = sh_pfc_get_pin_index(pfc, offset); 405 struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; 406 unsigned long flags; 407 408 spin_lock_irqsave(&pfc->lock, flags); 409 cfg->gpio_enabled = false; 410 /* If mux is already set, this configures it here */ 411 if (cfg->mux_mark) 412 sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION); 413 spin_unlock_irqrestore(&pfc->lock, flags); 414 } 415 416 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO 417 static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, 418 struct pinctrl_gpio_range *range, 419 unsigned offset, bool input) 420 { 421 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 422 struct sh_pfc *pfc = pmx->pfc; 423 int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; 424 int idx = sh_pfc_get_pin_index(pfc, offset); 425 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 426 unsigned long flags; 427 unsigned int dir; 428 int ret; 429 430 /* Check if the requested direction is supported by the pin. Not all 431 * SoCs provide pin config data, so perform the check conditionally. 432 */ 433 if (pin->configs) { 434 dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT; 435 if (!(pin->configs & dir)) 436 return -EINVAL; 437 } 438 439 spin_lock_irqsave(&pfc->lock, flags); 440 ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type); 441 spin_unlock_irqrestore(&pfc->lock, flags); 442 return ret; 443 } 444 #else 445 #define sh_pfc_gpio_set_direction NULL 446 #endif 447 448 static const struct pinmux_ops sh_pfc_pinmux_ops = { 449 .get_functions_count = sh_pfc_get_functions_count, 450 .get_function_name = sh_pfc_get_function_name, 451 .get_function_groups = sh_pfc_get_function_groups, 452 .set_mux = sh_pfc_func_set_mux, 453 .gpio_request_enable = sh_pfc_gpio_request_enable, 454 .gpio_disable_free = sh_pfc_gpio_disable_free, 455 .gpio_set_direction = sh_pfc_gpio_set_direction, 456 }; 457 458 static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, 459 unsigned int pin, unsigned int *offset, unsigned int *size) 460 { 461 const struct pinmux_drive_reg_field *field; 462 const struct pinmux_drive_reg *reg; 463 unsigned int i; 464 465 for (reg = pfc->info->drive_regs; reg->reg; ++reg) { 466 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) { 467 field = ®->fields[i]; 468 469 if (field->size && field->pin == pin) { 470 *offset = field->offset; 471 *size = field->size; 472 473 return reg->reg; 474 } 475 } 476 } 477 478 return 0; 479 } 480 481 static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc, 482 unsigned int pin) 483 { 484 unsigned int offset; 485 unsigned int size; 486 u32 reg; 487 u32 val; 488 489 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); 490 if (!reg) 491 return -EINVAL; 492 493 val = (sh_pfc_read(pfc, reg) >> offset) & GENMASK(size - 1, 0); 494 495 /* Convert the value to mA based on a full drive strength value of 24mA. 496 * We can make the full value configurable later if needed. 497 */ 498 return (val + 1) * (size == 2 ? 6 : 3); 499 } 500 501 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, 502 unsigned int pin, u16 strength) 503 { 504 unsigned long flags; 505 unsigned int offset; 506 unsigned int size; 507 unsigned int step; 508 u32 reg; 509 u32 val; 510 511 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); 512 if (!reg) 513 return -EINVAL; 514 515 step = size == 2 ? 6 : 3; 516 517 if (strength < step || strength > 24) 518 return -EINVAL; 519 520 /* Convert the value from mA based on a full drive strength value of 521 * 24mA. We can make the full value configurable later if needed. 522 */ 523 strength = strength / step - 1; 524 525 spin_lock_irqsave(&pfc->lock, flags); 526 527 val = sh_pfc_read(pfc, reg); 528 val &= ~GENMASK(offset + size - 1, offset); 529 val |= strength << offset; 530 531 sh_pfc_write(pfc, reg, val); 532 533 spin_unlock_irqrestore(&pfc->lock, flags); 534 535 return 0; 536 } 537 538 /* Check whether the requested parameter is supported for a pin. */ 539 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, 540 enum pin_config_param param) 541 { 542 int idx = sh_pfc_get_pin_index(pfc, _pin); 543 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 544 545 switch (param) { 546 case PIN_CONFIG_BIAS_DISABLE: 547 return pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN; 548 549 case PIN_CONFIG_BIAS_PULL_UP: 550 return pin->configs & SH_PFC_PIN_CFG_PULL_UP; 551 552 case PIN_CONFIG_BIAS_PULL_DOWN: 553 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; 554 555 case PIN_CONFIG_DRIVE_STRENGTH: 556 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH; 557 558 case PIN_CONFIG_POWER_SOURCE: 559 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK; 560 561 default: 562 return false; 563 } 564 } 565 566 static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, 567 unsigned long *config) 568 { 569 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 570 struct sh_pfc *pfc = pmx->pfc; 571 enum pin_config_param param = pinconf_to_config_param(*config); 572 unsigned long flags; 573 unsigned int arg; 574 575 if (!sh_pfc_pinconf_validate(pfc, _pin, param)) 576 return -ENOTSUPP; 577 578 switch (param) { 579 case PIN_CONFIG_BIAS_DISABLE: 580 case PIN_CONFIG_BIAS_PULL_UP: 581 case PIN_CONFIG_BIAS_PULL_DOWN: { 582 unsigned int bias; 583 584 if (!pfc->info->ops || !pfc->info->ops->get_bias) 585 return -ENOTSUPP; 586 587 spin_lock_irqsave(&pfc->lock, flags); 588 bias = pfc->info->ops->get_bias(pfc, _pin); 589 spin_unlock_irqrestore(&pfc->lock, flags); 590 591 if (bias != param) 592 return -EINVAL; 593 594 arg = 0; 595 break; 596 } 597 598 case PIN_CONFIG_DRIVE_STRENGTH: { 599 int ret; 600 601 ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin); 602 if (ret < 0) 603 return ret; 604 605 arg = ret; 606 break; 607 } 608 609 case PIN_CONFIG_POWER_SOURCE: { 610 int idx = sh_pfc_get_pin_index(pfc, _pin); 611 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 612 unsigned int mode, lo, hi; 613 u32 pocctrl, val; 614 int bit; 615 616 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) 617 return -ENOTSUPP; 618 619 bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl); 620 if (WARN(bit < 0, "invalid pin %#x", _pin)) 621 return bit; 622 623 val = sh_pfc_read(pfc, pocctrl); 624 625 mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK; 626 lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500; 627 hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500; 628 629 arg = (val & BIT(bit)) ? hi : lo; 630 break; 631 } 632 633 default: 634 return -ENOTSUPP; 635 } 636 637 *config = pinconf_to_config_packed(param, arg); 638 return 0; 639 } 640 641 static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, 642 unsigned long *configs, unsigned num_configs) 643 { 644 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 645 struct sh_pfc *pfc = pmx->pfc; 646 enum pin_config_param param; 647 unsigned long flags; 648 unsigned int i; 649 650 for (i = 0; i < num_configs; i++) { 651 param = pinconf_to_config_param(configs[i]); 652 653 if (!sh_pfc_pinconf_validate(pfc, _pin, param)) 654 return -ENOTSUPP; 655 656 switch (param) { 657 case PIN_CONFIG_BIAS_PULL_UP: 658 case PIN_CONFIG_BIAS_PULL_DOWN: 659 case PIN_CONFIG_BIAS_DISABLE: 660 if (!pfc->info->ops || !pfc->info->ops->set_bias) 661 return -ENOTSUPP; 662 663 spin_lock_irqsave(&pfc->lock, flags); 664 pfc->info->ops->set_bias(pfc, _pin, param); 665 spin_unlock_irqrestore(&pfc->lock, flags); 666 667 break; 668 669 case PIN_CONFIG_DRIVE_STRENGTH: { 670 unsigned int arg = 671 pinconf_to_config_argument(configs[i]); 672 int ret; 673 674 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg); 675 if (ret < 0) 676 return ret; 677 678 break; 679 } 680 681 case PIN_CONFIG_POWER_SOURCE: { 682 unsigned int mV = pinconf_to_config_argument(configs[i]); 683 int idx = sh_pfc_get_pin_index(pfc, _pin); 684 const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; 685 unsigned int mode, lo, hi; 686 u32 pocctrl, val; 687 int bit; 688 689 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) 690 return -ENOTSUPP; 691 692 bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl); 693 if (WARN(bit < 0, "invalid pin %#x", _pin)) 694 return bit; 695 696 mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK; 697 lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500; 698 hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500; 699 700 if (mV != lo && mV != hi) 701 return -EINVAL; 702 703 spin_lock_irqsave(&pfc->lock, flags); 704 val = sh_pfc_read(pfc, pocctrl); 705 if (mV == hi) 706 val |= BIT(bit); 707 else 708 val &= ~BIT(bit); 709 sh_pfc_write(pfc, pocctrl, val); 710 spin_unlock_irqrestore(&pfc->lock, flags); 711 712 break; 713 } 714 715 default: 716 return -ENOTSUPP; 717 } 718 } /* for each config */ 719 720 return 0; 721 } 722 723 static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 724 unsigned long *configs, 725 unsigned num_configs) 726 { 727 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 728 const unsigned int *pins; 729 unsigned int num_pins; 730 unsigned int i, ret; 731 732 pins = pmx->pfc->info->groups[group].pins; 733 num_pins = pmx->pfc->info->groups[group].nr_pins; 734 735 for (i = 0; i < num_pins; ++i) { 736 ret = sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs); 737 if (ret) 738 return ret; 739 } 740 741 return 0; 742 } 743 744 static const struct pinconf_ops sh_pfc_pinconf_ops = { 745 .is_generic = true, 746 .pin_config_get = sh_pfc_pinconf_get, 747 .pin_config_set = sh_pfc_pinconf_set, 748 .pin_config_group_set = sh_pfc_pinconf_group_set, 749 .pin_config_config_dbg_show = pinconf_generic_dump_config, 750 }; 751 752 /* PFC ranges -> pinctrl pin descs */ 753 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) 754 { 755 unsigned int i; 756 757 /* Allocate and initialize the pins and configs arrays. */ 758 pmx->pins = devm_kcalloc(pfc->dev, 759 pfc->info->nr_pins, sizeof(*pmx->pins), 760 GFP_KERNEL); 761 if (unlikely(!pmx->pins)) 762 return -ENOMEM; 763 764 pmx->configs = devm_kcalloc(pfc->dev, 765 pfc->info->nr_pins, sizeof(*pmx->configs), 766 GFP_KERNEL); 767 if (unlikely(!pmx->configs)) 768 return -ENOMEM; 769 770 for (i = 0; i < pfc->info->nr_pins; ++i) { 771 const struct sh_pfc_pin *info = &pfc->info->pins[i]; 772 struct pinctrl_pin_desc *pin = &pmx->pins[i]; 773 774 /* If the pin number is equal to -1 all pins are considered */ 775 pin->number = info->pin != (u16)-1 ? info->pin : i; 776 pin->name = info->name; 777 } 778 779 return 0; 780 } 781 782 int sh_pfc_register_pinctrl(struct sh_pfc *pfc) 783 { 784 struct sh_pfc_pinctrl *pmx; 785 int ret; 786 787 pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL); 788 if (unlikely(!pmx)) 789 return -ENOMEM; 790 791 pmx->pfc = pfc; 792 793 ret = sh_pfc_map_pins(pfc, pmx); 794 if (ret < 0) 795 return ret; 796 797 pmx->pctl_desc.name = DRV_NAME; 798 pmx->pctl_desc.owner = THIS_MODULE; 799 pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops; 800 pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops; 801 pmx->pctl_desc.confops = &sh_pfc_pinconf_ops; 802 pmx->pctl_desc.pins = pmx->pins; 803 pmx->pctl_desc.npins = pfc->info->nr_pins; 804 805 ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx, 806 &pmx->pctl); 807 if (ret) { 808 dev_err(pfc->dev, "could not register: %i\n", ret); 809 810 return ret; 811 } 812 813 return pinctrl_enable(pmx->pctl); 814 } 815 816 const struct pinmux_bias_reg * 817 rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin, 818 unsigned int *bit) 819 { 820 unsigned int i, j; 821 822 for (i = 0; info->bias_regs[i].puen || info->bias_regs[i].pud; i++) { 823 for (j = 0; j < ARRAY_SIZE(info->bias_regs[i].pins); j++) { 824 if (info->bias_regs[i].pins[j] == pin) { 825 *bit = j; 826 return &info->bias_regs[i]; 827 } 828 } 829 } 830 831 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin); 832 833 return NULL; 834 } 835 836 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) 837 { 838 const struct pinmux_bias_reg *reg; 839 unsigned int bit; 840 841 reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); 842 if (!reg) 843 return PIN_CONFIG_BIAS_DISABLE; 844 845 if (reg->puen) { 846 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) 847 return PIN_CONFIG_BIAS_DISABLE; 848 else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit))) 849 return PIN_CONFIG_BIAS_PULL_UP; 850 else 851 return PIN_CONFIG_BIAS_PULL_DOWN; 852 } else { 853 if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) 854 return PIN_CONFIG_BIAS_PULL_DOWN; 855 else 856 return PIN_CONFIG_BIAS_DISABLE; 857 } 858 } 859 860 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 861 unsigned int bias) 862 { 863 const struct pinmux_bias_reg *reg; 864 u32 enable, updown; 865 unsigned int bit; 866 867 reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); 868 if (!reg) 869 return; 870 871 if (reg->puen) { 872 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); 873 if (bias != PIN_CONFIG_BIAS_DISABLE) { 874 enable |= BIT(bit); 875 876 if (reg->pud) { 877 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); 878 if (bias == PIN_CONFIG_BIAS_PULL_UP) 879 updown |= BIT(bit); 880 881 sh_pfc_write(pfc, reg->pud, updown); 882 } 883 } 884 sh_pfc_write(pfc, reg->puen, enable); 885 } else { 886 enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); 887 if (bias == PIN_CONFIG_BIAS_PULL_DOWN) 888 enable |= BIT(bit); 889 890 sh_pfc_write(pfc, reg->pud, enable); 891 } 892 } 893 894 #define PORTnCR_PULMD_OFF (0 << 6) 895 #define PORTnCR_PULMD_DOWN (2 << 6) 896 #define PORTnCR_PULMD_UP (3 << 6) 897 #define PORTnCR_PULMD_MASK (3 << 6) 898 899 unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) 900 { 901 void __iomem *reg = pfc->windows->virt + 902 pfc->info->ops->pin_to_portcr(pin); 903 u32 value = ioread8(reg) & PORTnCR_PULMD_MASK; 904 905 switch (value) { 906 case PORTnCR_PULMD_UP: 907 return PIN_CONFIG_BIAS_PULL_UP; 908 case PORTnCR_PULMD_DOWN: 909 return PIN_CONFIG_BIAS_PULL_DOWN; 910 case PORTnCR_PULMD_OFF: 911 default: 912 return PIN_CONFIG_BIAS_DISABLE; 913 } 914 } 915 916 void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 917 unsigned int bias) 918 { 919 void __iomem *reg = pfc->windows->virt + 920 pfc->info->ops->pin_to_portcr(pin); 921 u32 value = ioread8(reg) & ~PORTnCR_PULMD_MASK; 922 923 switch (bias) { 924 case PIN_CONFIG_BIAS_PULL_UP: 925 value |= PORTnCR_PULMD_UP; 926 break; 927 case PIN_CONFIG_BIAS_PULL_DOWN: 928 value |= PORTnCR_PULMD_DOWN; 929 break; 930 } 931 932 iowrite8(value, reg); 933 } 934