1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/V2M Pin Control and GPIO driver core 4 * 5 * Based on: 6 * Renesas RZ/G2L Pin Control and GPIO driver core 7 * 8 * Copyright (C) 2022 Renesas Electronics Corporation. 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/mutex.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/spinlock.h> 21 22 #include <linux/pinctrl/consumer.h> 23 #include <linux/pinctrl/pinconf-generic.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinmux.h> 27 28 #include <dt-bindings/pinctrl/rzv2m-pinctrl.h> 29 30 #include "../core.h" 31 #include "../pinconf.h" 32 #include "../pinmux.h" 33 34 #define DRV_NAME "pinctrl-rzv2m" 35 36 /* 37 * Use 16 lower bits [15:0] for pin identifier 38 * Use 16 higher bits [31:16] for pin mux function 39 */ 40 #define MUX_PIN_ID_MASK GENMASK(15, 0) 41 #define MUX_FUNC_MASK GENMASK(31, 16) 42 #define MUX_FUNC(pinconf) FIELD_GET(MUX_FUNC_MASK, (pinconf)) 43 44 /* PIN capabilities */ 45 #define PIN_CFG_GRP_1_8V_2 1 46 #define PIN_CFG_GRP_1_8V_3 2 47 #define PIN_CFG_GRP_SWIO_1 3 48 #define PIN_CFG_GRP_SWIO_2 4 49 #define PIN_CFG_GRP_3_3V 5 50 #define PIN_CFG_GRP_MASK GENMASK(2, 0) 51 #define PIN_CFG_BIAS BIT(3) 52 #define PIN_CFG_DRV BIT(4) 53 #define PIN_CFG_SLEW BIT(5) 54 55 #define RZV2M_MPXED_PIN_FUNCS (PIN_CFG_BIAS | \ 56 PIN_CFG_DRV | \ 57 PIN_CFG_SLEW) 58 59 /* 60 * n indicates number of pins in the port, a is the register index 61 * and f is pin configuration capabilities supported. 62 */ 63 #define RZV2M_GPIO_PORT_PACK(n, a, f) (((n) << 24) | ((a) << 16) | (f)) 64 #define RZV2M_GPIO_PORT_GET_PINCNT(x) FIELD_GET(GENMASK(31, 24), (x)) 65 #define RZV2M_GPIO_PORT_GET_INDEX(x) FIELD_GET(GENMASK(23, 16), (x)) 66 #define RZV2M_GPIO_PORT_GET_CFGS(x) FIELD_GET(GENMASK(15, 0), (x)) 67 68 #define RZV2M_DEDICATED_PORT_IDX 22 69 70 /* 71 * BIT(31) indicates dedicated pin, b is the register bits (b * 16) 72 * and f is the pin configuration capabilities supported. 73 */ 74 #define RZV2M_SINGLE_PIN BIT(31) 75 #define RZV2M_SINGLE_PIN_PACK(b, f) (RZV2M_SINGLE_PIN | \ 76 ((RZV2M_DEDICATED_PORT_IDX) << 24) | \ 77 ((b) << 16) | (f)) 78 #define RZV2M_SINGLE_PIN_GET_PORT(x) FIELD_GET(GENMASK(30, 24), (x)) 79 #define RZV2M_SINGLE_PIN_GET_BIT(x) FIELD_GET(GENMASK(23, 16), (x)) 80 #define RZV2M_SINGLE_PIN_GET_CFGS(x) FIELD_GET(GENMASK(15, 0), (x)) 81 82 #define RZV2M_PIN_ID_TO_PORT(id) ((id) / RZV2M_PINS_PER_PORT) 83 #define RZV2M_PIN_ID_TO_PIN(id) ((id) % RZV2M_PINS_PER_PORT) 84 85 #define DO(n) (0x00 + (n) * 0x40) 86 #define OE(n) (0x04 + (n) * 0x40) 87 #define IE(n) (0x08 + (n) * 0x40) 88 #define PFSEL(n) (0x10 + (n) * 0x40) 89 #define DI(n) (0x20 + (n) * 0x40) 90 #define PUPD(n) (0x24 + (n) * 0x40) 91 #define DRV(n) ((n) < RZV2M_DEDICATED_PORT_IDX ? (0x28 + (n) * 0x40) \ 92 : 0x590) 93 #define SR(n) ((n) < RZV2M_DEDICATED_PORT_IDX ? (0x2c + (n) * 0x40) \ 94 : 0x594) 95 #define DI_MSK(n) (0x30 + (n) * 0x40) 96 #define EN_MSK(n) (0x34 + (n) * 0x40) 97 98 #define PFC_MASK 0x07 99 #define PUPD_MASK 0x03 100 #define DRV_MASK 0x03 101 102 struct rzv2m_dedicated_configs { 103 const char *name; 104 u32 config; 105 }; 106 107 struct rzv2m_pinctrl_data { 108 const char * const *port_pins; 109 const u32 *port_pin_configs; 110 const struct rzv2m_dedicated_configs *dedicated_pins; 111 unsigned int n_port_pins; 112 unsigned int n_dedicated_pins; 113 }; 114 115 struct rzv2m_pinctrl { 116 struct pinctrl_dev *pctl; 117 struct pinctrl_desc desc; 118 struct pinctrl_pin_desc *pins; 119 120 const struct rzv2m_pinctrl_data *data; 121 void __iomem *base; 122 struct device *dev; 123 124 struct gpio_chip gpio_chip; 125 struct pinctrl_gpio_range gpio_range; 126 127 spinlock_t lock; /* lock read/write registers */ 128 struct mutex mutex; /* serialize adding groups and functions */ 129 }; 130 131 static const unsigned int drv_1_8V_group2_uA[] = { 1800, 3800, 7800, 11000 }; 132 static const unsigned int drv_1_8V_group3_uA[] = { 1600, 3200, 6400, 9600 }; 133 static const unsigned int drv_SWIO_group2_3_3V_uA[] = { 9000, 11000, 13000, 18000 }; 134 static const unsigned int drv_3_3V_group_uA[] = { 2000, 4000, 8000, 12000 }; 135 136 /* Helper for registers that have a write enable bit in the upper word */ 137 static void rzv2m_writel_we(void __iomem *addr, u8 shift, u8 value) 138 { 139 writel((BIT(16) | value) << shift, addr); 140 } 141 142 static void rzv2m_pinctrl_set_pfc_mode(struct rzv2m_pinctrl *pctrl, 143 u8 port, u8 pin, u8 func) 144 { 145 void __iomem *addr; 146 147 /* Mask input/output */ 148 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1); 149 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1); 150 151 /* Select the function and set the write enable bits */ 152 addr = pctrl->base + PFSEL(port) + (pin / 4) * 4; 153 writel(((PFC_MASK << 16) | func) << ((pin % 4) * 4), addr); 154 155 /* Unmask input/output */ 156 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 0); 157 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 0); 158 }; 159 160 static int rzv2m_pinctrl_set_mux(struct pinctrl_dev *pctldev, 161 unsigned int func_selector, 162 unsigned int group_selector) 163 { 164 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 165 struct function_desc *func; 166 unsigned int i, *psel_val; 167 struct group_desc *group; 168 const unsigned int *pins; 169 170 func = pinmux_generic_get_function(pctldev, func_selector); 171 if (!func) 172 return -EINVAL; 173 group = pinctrl_generic_get_group(pctldev, group_selector); 174 if (!group) 175 return -EINVAL; 176 177 psel_val = func->data; 178 pins = group->grp.pins; 179 180 for (i = 0; i < group->grp.npins; i++) { 181 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", 182 RZV2M_PIN_ID_TO_PORT(pins[i]), RZV2M_PIN_ID_TO_PIN(pins[i]), 183 psel_val[i]); 184 rzv2m_pinctrl_set_pfc_mode(pctrl, RZV2M_PIN_ID_TO_PORT(pins[i]), 185 RZV2M_PIN_ID_TO_PIN(pins[i]), psel_val[i]); 186 } 187 188 return 0; 189 }; 190 191 static int rzv2m_map_add_config(struct pinctrl_map *map, 192 const char *group_or_pin, 193 enum pinctrl_map_type type, 194 unsigned long *configs, 195 unsigned int num_configs) 196 { 197 unsigned long *cfgs; 198 199 cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL); 200 if (!cfgs) 201 return -ENOMEM; 202 203 map->type = type; 204 map->data.configs.group_or_pin = group_or_pin; 205 map->data.configs.configs = cfgs; 206 map->data.configs.num_configs = num_configs; 207 208 return 0; 209 } 210 211 static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev, 212 struct device_node *np, 213 struct device_node *parent, 214 struct pinctrl_map **map, 215 unsigned int *num_maps, 216 unsigned int *index) 217 { 218 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 219 struct pinctrl_map *maps = *map; 220 unsigned int nmaps = *num_maps; 221 unsigned long *configs = NULL; 222 unsigned int *pins, *psel_val; 223 unsigned int num_pinmux = 0; 224 unsigned int idx = *index; 225 unsigned int num_pins, i; 226 unsigned int num_configs; 227 struct property *pinmux; 228 struct property *prop; 229 int ret, gsel, fsel; 230 const char **pin_fn; 231 const char *name; 232 const char *pin; 233 234 pinmux = of_find_property(np, "pinmux", NULL); 235 if (pinmux) 236 num_pinmux = pinmux->length / sizeof(u32); 237 238 ret = of_property_count_strings(np, "pins"); 239 if (ret == -EINVAL) { 240 num_pins = 0; 241 } else if (ret < 0) { 242 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 243 return ret; 244 } else { 245 num_pins = ret; 246 } 247 248 if (!num_pinmux && !num_pins) 249 return 0; 250 251 if (num_pinmux && num_pins) { 252 dev_err(pctrl->dev, 253 "DT node must contain either a pinmux or pins and not both\n"); 254 return -EINVAL; 255 } 256 257 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); 258 if (ret < 0) 259 return ret; 260 261 if (num_pins && !num_configs) { 262 dev_err(pctrl->dev, "DT node must contain a config\n"); 263 ret = -ENODEV; 264 goto done; 265 } 266 267 if (num_pinmux) 268 nmaps += 1; 269 270 if (num_pins) 271 nmaps += num_pins; 272 273 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 274 if (!maps) { 275 ret = -ENOMEM; 276 goto done; 277 } 278 279 *map = maps; 280 *num_maps = nmaps; 281 if (num_pins) { 282 of_property_for_each_string(np, "pins", prop, pin) { 283 ret = rzv2m_map_add_config(&maps[idx], pin, 284 PIN_MAP_TYPE_CONFIGS_PIN, 285 configs, num_configs); 286 if (ret < 0) 287 goto done; 288 289 idx++; 290 } 291 ret = 0; 292 goto done; 293 } 294 295 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 296 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 297 GFP_KERNEL); 298 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 299 if (!pins || !psel_val || !pin_fn) { 300 ret = -ENOMEM; 301 goto done; 302 } 303 304 /* Collect pin locations and mux settings from DT properties */ 305 for (i = 0; i < num_pinmux; ++i) { 306 u32 value; 307 308 ret = of_property_read_u32_index(np, "pinmux", i, &value); 309 if (ret) 310 goto done; 311 pins[i] = value & MUX_PIN_ID_MASK; 312 psel_val[i] = MUX_FUNC(value); 313 } 314 315 if (parent) { 316 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", 317 parent, np); 318 if (!name) { 319 ret = -ENOMEM; 320 goto done; 321 } 322 } else { 323 name = np->name; 324 } 325 326 mutex_lock(&pctrl->mutex); 327 328 /* Register a single pin group listing all the pins we read from DT */ 329 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL); 330 if (gsel < 0) { 331 ret = gsel; 332 goto unlock; 333 } 334 335 /* 336 * Register a single group function where the 'data' is an array PSEL 337 * register values read from DT. 338 */ 339 pin_fn[0] = name; 340 fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val); 341 if (fsel < 0) { 342 ret = fsel; 343 goto remove_group; 344 } 345 346 mutex_unlock(&pctrl->mutex); 347 348 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 349 maps[idx].data.mux.group = name; 350 maps[idx].data.mux.function = name; 351 idx++; 352 353 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 354 ret = 0; 355 goto done; 356 357 remove_group: 358 pinctrl_generic_remove_group(pctldev, gsel); 359 unlock: 360 mutex_unlock(&pctrl->mutex); 361 done: 362 *index = idx; 363 kfree(configs); 364 return ret; 365 } 366 367 static void rzv2m_dt_free_map(struct pinctrl_dev *pctldev, 368 struct pinctrl_map *map, 369 unsigned int num_maps) 370 { 371 unsigned int i; 372 373 if (!map) 374 return; 375 376 for (i = 0; i < num_maps; ++i) { 377 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 378 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 379 kfree(map[i].data.configs.configs); 380 } 381 kfree(map); 382 } 383 384 static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev, 385 struct device_node *np, 386 struct pinctrl_map **map, 387 unsigned int *num_maps) 388 { 389 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 390 unsigned int index; 391 int ret; 392 393 *map = NULL; 394 *num_maps = 0; 395 index = 0; 396 397 for_each_child_of_node_scoped(np, child) { 398 ret = rzv2m_dt_subnode_to_map(pctldev, child, np, map, 399 num_maps, &index); 400 if (ret < 0) 401 goto done; 402 } 403 404 if (*num_maps == 0) { 405 ret = rzv2m_dt_subnode_to_map(pctldev, np, NULL, map, 406 num_maps, &index); 407 if (ret < 0) 408 goto done; 409 } 410 411 if (*num_maps) 412 return 0; 413 414 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 415 ret = -EINVAL; 416 417 done: 418 rzv2m_dt_free_map(pctldev, *map, *num_maps); 419 420 return ret; 421 } 422 423 static int rzv2m_validate_gpio_pin(struct rzv2m_pinctrl *pctrl, 424 u32 cfg, u32 port, u8 bit) 425 { 426 u8 pincount = RZV2M_GPIO_PORT_GET_PINCNT(cfg); 427 u32 port_index = RZV2M_GPIO_PORT_GET_INDEX(cfg); 428 u32 data; 429 430 if (bit >= pincount || port >= pctrl->data->n_port_pins) 431 return -EINVAL; 432 433 data = pctrl->data->port_pin_configs[port]; 434 if (port_index != RZV2M_GPIO_PORT_GET_INDEX(data)) 435 return -EINVAL; 436 437 return 0; 438 } 439 440 static void rzv2m_rmw_pin_config(struct rzv2m_pinctrl *pctrl, u32 offset, 441 u8 shift, u32 mask, u32 val) 442 { 443 void __iomem *addr = pctrl->base + offset; 444 unsigned long flags; 445 u32 reg; 446 447 spin_lock_irqsave(&pctrl->lock, flags); 448 reg = readl(addr) & ~(mask << shift); 449 writel(reg | (val << shift), addr); 450 spin_unlock_irqrestore(&pctrl->lock, flags); 451 } 452 453 static int rzv2m_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 454 unsigned int _pin, 455 unsigned long *config) 456 { 457 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 458 enum pin_config_param param = pinconf_to_config_param(*config); 459 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 460 unsigned int *pin_data = pin->drv_data; 461 unsigned int arg = 0; 462 u32 port; 463 u32 cfg; 464 u8 bit; 465 u32 val; 466 467 if (!pin_data) 468 return -EINVAL; 469 470 if (*pin_data & RZV2M_SINGLE_PIN) { 471 port = RZV2M_SINGLE_PIN_GET_PORT(*pin_data); 472 cfg = RZV2M_SINGLE_PIN_GET_CFGS(*pin_data); 473 bit = RZV2M_SINGLE_PIN_GET_BIT(*pin_data); 474 } else { 475 cfg = RZV2M_GPIO_PORT_GET_CFGS(*pin_data); 476 port = RZV2M_PIN_ID_TO_PORT(_pin); 477 bit = RZV2M_PIN_ID_TO_PIN(_pin); 478 479 if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit)) 480 return -EINVAL; 481 } 482 483 switch (param) { 484 case PIN_CONFIG_BIAS_DISABLE: 485 case PIN_CONFIG_BIAS_PULL_UP: 486 case PIN_CONFIG_BIAS_PULL_DOWN: { 487 enum pin_config_param bias; 488 489 if (!(cfg & PIN_CFG_BIAS)) 490 return -EINVAL; 491 492 /* PUPD uses 2-bits per pin */ 493 bit *= 2; 494 495 switch ((readl(pctrl->base + PUPD(port)) >> bit) & PUPD_MASK) { 496 case 0: 497 bias = PIN_CONFIG_BIAS_PULL_DOWN; 498 break; 499 case 2: 500 bias = PIN_CONFIG_BIAS_PULL_UP; 501 break; 502 default: 503 bias = PIN_CONFIG_BIAS_DISABLE; 504 } 505 506 if (bias != param) 507 return -EINVAL; 508 break; 509 } 510 511 case PIN_CONFIG_DRIVE_STRENGTH_UA: 512 if (!(cfg & PIN_CFG_DRV)) 513 return -EINVAL; 514 515 /* DRV uses 2-bits per pin */ 516 bit *= 2; 517 518 val = (readl(pctrl->base + DRV(port)) >> bit) & DRV_MASK; 519 520 switch (cfg & PIN_CFG_GRP_MASK) { 521 case PIN_CFG_GRP_1_8V_2: 522 arg = drv_1_8V_group2_uA[val]; 523 break; 524 case PIN_CFG_GRP_1_8V_3: 525 arg = drv_1_8V_group3_uA[val]; 526 break; 527 case PIN_CFG_GRP_SWIO_2: 528 arg = drv_SWIO_group2_3_3V_uA[val]; 529 break; 530 case PIN_CFG_GRP_SWIO_1: 531 case PIN_CFG_GRP_3_3V: 532 arg = drv_3_3V_group_uA[val]; 533 break; 534 default: 535 return -EINVAL; 536 } 537 538 break; 539 540 case PIN_CONFIG_SLEW_RATE: 541 if (!(cfg & PIN_CFG_SLEW)) 542 return -EINVAL; 543 544 arg = readl(pctrl->base + SR(port)) & BIT(bit); 545 break; 546 547 default: 548 return -ENOTSUPP; 549 } 550 551 *config = pinconf_to_config_packed(param, arg); 552 553 return 0; 554 }; 555 556 static int rzv2m_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 557 unsigned int _pin, 558 unsigned long *_configs, 559 unsigned int num_configs) 560 { 561 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 562 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 563 unsigned int *pin_data = pin->drv_data; 564 enum pin_config_param param; 565 u32 port; 566 unsigned int i; 567 u32 cfg; 568 u8 bit; 569 u32 val; 570 571 if (!pin_data) 572 return -EINVAL; 573 574 if (*pin_data & RZV2M_SINGLE_PIN) { 575 port = RZV2M_SINGLE_PIN_GET_PORT(*pin_data); 576 cfg = RZV2M_SINGLE_PIN_GET_CFGS(*pin_data); 577 bit = RZV2M_SINGLE_PIN_GET_BIT(*pin_data); 578 } else { 579 cfg = RZV2M_GPIO_PORT_GET_CFGS(*pin_data); 580 port = RZV2M_PIN_ID_TO_PORT(_pin); 581 bit = RZV2M_PIN_ID_TO_PIN(_pin); 582 583 if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit)) 584 return -EINVAL; 585 } 586 587 for (i = 0; i < num_configs; i++) { 588 param = pinconf_to_config_param(_configs[i]); 589 switch (param) { 590 case PIN_CONFIG_BIAS_DISABLE: 591 case PIN_CONFIG_BIAS_PULL_UP: 592 case PIN_CONFIG_BIAS_PULL_DOWN: 593 if (!(cfg & PIN_CFG_BIAS)) 594 return -EINVAL; 595 596 /* PUPD uses 2-bits per pin */ 597 bit *= 2; 598 599 switch (param) { 600 case PIN_CONFIG_BIAS_PULL_DOWN: 601 val = 0; 602 break; 603 case PIN_CONFIG_BIAS_PULL_UP: 604 val = 2; 605 break; 606 default: 607 val = 1; 608 } 609 610 rzv2m_rmw_pin_config(pctrl, PUPD(port), bit, PUPD_MASK, val); 611 break; 612 613 case PIN_CONFIG_DRIVE_STRENGTH_UA: { 614 unsigned int arg = pinconf_to_config_argument(_configs[i]); 615 const unsigned int *drv_strengths; 616 unsigned int index; 617 618 if (!(cfg & PIN_CFG_DRV)) 619 return -EINVAL; 620 621 switch (cfg & PIN_CFG_GRP_MASK) { 622 case PIN_CFG_GRP_1_8V_2: 623 drv_strengths = drv_1_8V_group2_uA; 624 break; 625 case PIN_CFG_GRP_1_8V_3: 626 drv_strengths = drv_1_8V_group3_uA; 627 break; 628 case PIN_CFG_GRP_SWIO_2: 629 drv_strengths = drv_SWIO_group2_3_3V_uA; 630 break; 631 case PIN_CFG_GRP_SWIO_1: 632 case PIN_CFG_GRP_3_3V: 633 drv_strengths = drv_3_3V_group_uA; 634 break; 635 default: 636 return -EINVAL; 637 } 638 639 for (index = 0; index < 4; index++) { 640 if (arg == drv_strengths[index]) 641 break; 642 } 643 if (index >= 4) 644 return -EINVAL; 645 646 /* DRV uses 2-bits per pin */ 647 bit *= 2; 648 649 rzv2m_rmw_pin_config(pctrl, DRV(port), bit, DRV_MASK, index); 650 break; 651 } 652 653 case PIN_CONFIG_SLEW_RATE: { 654 unsigned int arg = pinconf_to_config_argument(_configs[i]); 655 656 if (!(cfg & PIN_CFG_SLEW)) 657 return -EINVAL; 658 659 rzv2m_writel_we(pctrl->base + SR(port), bit, !arg); 660 break; 661 } 662 663 default: 664 return -EOPNOTSUPP; 665 } 666 } 667 668 return 0; 669 } 670 671 static int rzv2m_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, 672 unsigned int group, 673 unsigned long *configs, 674 unsigned int num_configs) 675 { 676 const unsigned int *pins; 677 unsigned int i, npins; 678 int ret; 679 680 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 681 if (ret) 682 return ret; 683 684 for (i = 0; i < npins; i++) { 685 ret = rzv2m_pinctrl_pinconf_set(pctldev, pins[i], configs, 686 num_configs); 687 if (ret) 688 return ret; 689 } 690 691 return 0; 692 }; 693 694 static int rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, 695 unsigned int group, 696 unsigned long *config) 697 { 698 const unsigned int *pins; 699 unsigned int i, npins, prev_config = 0; 700 int ret; 701 702 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 703 if (ret) 704 return ret; 705 706 for (i = 0; i < npins; i++) { 707 ret = rzv2m_pinctrl_pinconf_get(pctldev, pins[i], config); 708 if (ret) 709 return ret; 710 711 /* Check config matches previous pins */ 712 if (i && prev_config != *config) 713 return -EOPNOTSUPP; 714 715 prev_config = *config; 716 } 717 718 return 0; 719 }; 720 721 static const struct pinctrl_ops rzv2m_pinctrl_pctlops = { 722 .get_groups_count = pinctrl_generic_get_group_count, 723 .get_group_name = pinctrl_generic_get_group_name, 724 .get_group_pins = pinctrl_generic_get_group_pins, 725 .dt_node_to_map = rzv2m_dt_node_to_map, 726 .dt_free_map = rzv2m_dt_free_map, 727 }; 728 729 static const struct pinmux_ops rzv2m_pinctrl_pmxops = { 730 .get_functions_count = pinmux_generic_get_function_count, 731 .get_function_name = pinmux_generic_get_function_name, 732 .get_function_groups = pinmux_generic_get_function_groups, 733 .set_mux = rzv2m_pinctrl_set_mux, 734 .strict = true, 735 }; 736 737 static const struct pinconf_ops rzv2m_pinctrl_confops = { 738 .is_generic = true, 739 .pin_config_get = rzv2m_pinctrl_pinconf_get, 740 .pin_config_set = rzv2m_pinctrl_pinconf_set, 741 .pin_config_group_set = rzv2m_pinctrl_pinconf_group_set, 742 .pin_config_group_get = rzv2m_pinctrl_pinconf_group_get, 743 .pin_config_config_dbg_show = pinconf_generic_dump_config, 744 }; 745 746 static int rzv2m_gpio_request(struct gpio_chip *chip, unsigned int offset) 747 { 748 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); 749 u32 port = RZV2M_PIN_ID_TO_PORT(offset); 750 u8 bit = RZV2M_PIN_ID_TO_PIN(offset); 751 int ret; 752 753 ret = pinctrl_gpio_request(chip, offset); 754 if (ret) 755 return ret; 756 757 rzv2m_pinctrl_set_pfc_mode(pctrl, port, bit, 0); 758 759 return 0; 760 } 761 762 static void rzv2m_gpio_set_direction(struct rzv2m_pinctrl *pctrl, u32 port, 763 u8 bit, bool output) 764 { 765 rzv2m_writel_we(pctrl->base + OE(port), bit, output); 766 rzv2m_writel_we(pctrl->base + IE(port), bit, !output); 767 } 768 769 static int rzv2m_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 770 { 771 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); 772 u32 port = RZV2M_PIN_ID_TO_PORT(offset); 773 u8 bit = RZV2M_PIN_ID_TO_PIN(offset); 774 775 if (!(readl(pctrl->base + IE(port)) & BIT(bit))) 776 return GPIO_LINE_DIRECTION_OUT; 777 778 return GPIO_LINE_DIRECTION_IN; 779 } 780 781 static int rzv2m_gpio_direction_input(struct gpio_chip *chip, 782 unsigned int offset) 783 { 784 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); 785 u32 port = RZV2M_PIN_ID_TO_PORT(offset); 786 u8 bit = RZV2M_PIN_ID_TO_PIN(offset); 787 788 rzv2m_gpio_set_direction(pctrl, port, bit, false); 789 790 return 0; 791 } 792 793 static void rzv2m_gpio_set(struct gpio_chip *chip, unsigned int offset, 794 int value) 795 { 796 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); 797 u32 port = RZV2M_PIN_ID_TO_PORT(offset); 798 u8 bit = RZV2M_PIN_ID_TO_PIN(offset); 799 800 rzv2m_writel_we(pctrl->base + DO(port), bit, !!value); 801 } 802 803 static int rzv2m_gpio_direction_output(struct gpio_chip *chip, 804 unsigned int offset, int value) 805 { 806 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); 807 u32 port = RZV2M_PIN_ID_TO_PORT(offset); 808 u8 bit = RZV2M_PIN_ID_TO_PIN(offset); 809 810 rzv2m_gpio_set(chip, offset, value); 811 rzv2m_gpio_set_direction(pctrl, port, bit, true); 812 813 return 0; 814 } 815 816 static int rzv2m_gpio_get(struct gpio_chip *chip, unsigned int offset) 817 { 818 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip); 819 u32 port = RZV2M_PIN_ID_TO_PORT(offset); 820 u8 bit = RZV2M_PIN_ID_TO_PIN(offset); 821 int direction = rzv2m_gpio_get_direction(chip, offset); 822 823 if (direction == GPIO_LINE_DIRECTION_IN) 824 return !!(readl(pctrl->base + DI(port)) & BIT(bit)); 825 else 826 return !!(readl(pctrl->base + DO(port)) & BIT(bit)); 827 } 828 829 static void rzv2m_gpio_free(struct gpio_chip *chip, unsigned int offset) 830 { 831 pinctrl_gpio_free(chip, offset); 832 833 /* 834 * Set the GPIO as an input to ensure that the next GPIO request won't 835 * drive the GPIO pin as an output. 836 */ 837 rzv2m_gpio_direction_input(chip, offset); 838 } 839 840 static const char * const rzv2m_gpio_names[] = { 841 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 842 "P0_8", "P0_9", "P0_10", "P0_11", "P0_12", "P0_13", "P0_14", "P0_15", 843 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 844 "P1_8", "P1_9", "P1_10", "P1_11", "P1_12", "P1_13", "P1_14", "P1_15", 845 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 846 "P2_8", "P2_9", "P2_10", "P2_11", "P2_12", "P2_13", "P2_14", "P2_15", 847 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 848 "P3_8", "P3_9", "P3_10", "P3_11", "P3_12", "P3_13", "P3_14", "P3_15", 849 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 850 "P4_8", "P4_9", "P4_10", "P4_11", "P4_12", "P4_13", "P4_14", "P4_15", 851 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 852 "P5_8", "P5_9", "P5_10", "P5_11", "P5_12", "P5_13", "P5_14", "P5_15", 853 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 854 "P6_8", "P6_9", "P6_10", "P6_11", "P6_12", "P6_13", "P6_14", "P6_15", 855 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 856 "P7_8", "P7_9", "P7_10", "P7_11", "P7_12", "P7_13", "P7_14", "P7_15", 857 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 858 "P8_8", "P8_9", "P8_10", "P8_11", "P8_12", "P8_13", "P8_14", "P8_15", 859 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 860 "P9_8", "P9_9", "P9_10", "P9_11", "P9_12", "P9_13", "P9_14", "P9_15", 861 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 862 "P10_8", "P10_9", "P10_10", "P10_11", "P10_12", "P10_13", "P10_14", "P10_15", 863 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 864 "P11_8", "P11_9", "P11_10", "P11_11", "P11_12", "P11_13", "P11_14", "P11_15", 865 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 866 "P12_8", "P12_9", "P12_10", "P12_11", "P12_12", "P12_13", "P12_14", "P12_15", 867 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 868 "P13_8", "P13_9", "P13_10", "P13_11", "P13_12", "P13_13", "P13_14", "P13_15", 869 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 870 "P14_8", "P14_9", "P14_10", "P14_11", "P14_12", "P14_13", "P14_14", "P14_15", 871 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 872 "P15_8", "P15_9", "P15_10", "P15_11", "P15_12", "P15_13", "P15_14", "P15_15", 873 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 874 "P16_8", "P16_9", "P16_10", "P16_11", "P16_12", "P16_13", "P16_14", "P16_15", 875 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 876 "P17_8", "P17_9", "P17_10", "P17_11", "P17_12", "P17_13", "P17_14", "P17_15", 877 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 878 "P18_8", "P18_9", "P18_10", "P18_11", "P18_12", "P18_13", "P18_14", "P18_15", 879 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 880 "P19_8", "P19_9", "P19_10", "P19_11", "P19_12", "P19_13", "P19_14", "P19_15", 881 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 882 "P20_8", "P20_9", "P20_10", "P20_11", "P20_12", "P20_13", "P20_14", "P20_15", 883 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 884 "P21_8", "P21_9", "P21_10", "P21_11", "P21_12", "P21_13", "P21_14", "P21_15", 885 }; 886 887 static const u32 rzv2m_gpio_configs[] = { 888 RZV2M_GPIO_PORT_PACK(14, 0, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS), 889 RZV2M_GPIO_PORT_PACK(16, 1, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS), 890 RZV2M_GPIO_PORT_PACK(8, 2, PIN_CFG_GRP_1_8V_3 | RZV2M_MPXED_PIN_FUNCS), 891 RZV2M_GPIO_PORT_PACK(16, 3, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS), 892 RZV2M_GPIO_PORT_PACK(8, 4, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS), 893 RZV2M_GPIO_PORT_PACK(4, 5, PIN_CFG_GRP_1_8V_3 | RZV2M_MPXED_PIN_FUNCS), 894 RZV2M_GPIO_PORT_PACK(12, 6, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS), 895 RZV2M_GPIO_PORT_PACK(6, 7, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS), 896 RZV2M_GPIO_PORT_PACK(8, 8, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS), 897 RZV2M_GPIO_PORT_PACK(8, 9, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS), 898 RZV2M_GPIO_PORT_PACK(9, 10, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS), 899 RZV2M_GPIO_PORT_PACK(9, 11, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS), 900 RZV2M_GPIO_PORT_PACK(4, 12, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS), 901 RZV2M_GPIO_PORT_PACK(12, 13, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS), 902 RZV2M_GPIO_PORT_PACK(8, 14, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS), 903 RZV2M_GPIO_PORT_PACK(16, 15, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS), 904 RZV2M_GPIO_PORT_PACK(14, 16, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS), 905 RZV2M_GPIO_PORT_PACK(1, 17, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS), 906 RZV2M_GPIO_PORT_PACK(0, 18, 0), 907 RZV2M_GPIO_PORT_PACK(0, 19, 0), 908 RZV2M_GPIO_PORT_PACK(3, 20, PIN_CFG_GRP_1_8V_2 | PIN_CFG_DRV), 909 RZV2M_GPIO_PORT_PACK(1, 21, PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW), 910 }; 911 912 static const struct rzv2m_dedicated_configs rzv2m_dedicated_pins[] = { 913 { "NAWPN", RZV2M_SINGLE_PIN_PACK(0, 914 (PIN_CFG_GRP_SWIO_2 | PIN_CFG_DRV | PIN_CFG_SLEW)) }, 915 { "IM0CLK", RZV2M_SINGLE_PIN_PACK(1, 916 (PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW)) }, 917 { "IM1CLK", RZV2M_SINGLE_PIN_PACK(2, 918 (PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW)) }, 919 { "DETDO", RZV2M_SINGLE_PIN_PACK(5, 920 (PIN_CFG_GRP_1_8V_3 | PIN_CFG_DRV | PIN_CFG_SLEW)) }, 921 { "DETMS", RZV2M_SINGLE_PIN_PACK(6, 922 (PIN_CFG_GRP_1_8V_3 | PIN_CFG_DRV | PIN_CFG_SLEW)) }, 923 { "PCRSTOUTB", RZV2M_SINGLE_PIN_PACK(12, 924 (PIN_CFG_GRP_3_3V | PIN_CFG_DRV | PIN_CFG_SLEW)) }, 925 { "USPWEN", RZV2M_SINGLE_PIN_PACK(14, 926 (PIN_CFG_GRP_3_3V | PIN_CFG_DRV | PIN_CFG_SLEW)) }, 927 }; 928 929 static int rzv2m_gpio_register(struct rzv2m_pinctrl *pctrl) 930 { 931 struct device_node *np = pctrl->dev->of_node; 932 struct gpio_chip *chip = &pctrl->gpio_chip; 933 const char *name = dev_name(pctrl->dev); 934 struct of_phandle_args of_args; 935 int ret; 936 937 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); 938 if (ret) { 939 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); 940 return ret; 941 } 942 943 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 944 of_args.args[2] != pctrl->data->n_port_pins) { 945 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); 946 return -EINVAL; 947 } 948 949 chip->names = pctrl->data->port_pins; 950 chip->request = rzv2m_gpio_request; 951 chip->free = rzv2m_gpio_free; 952 chip->get_direction = rzv2m_gpio_get_direction; 953 chip->direction_input = rzv2m_gpio_direction_input; 954 chip->direction_output = rzv2m_gpio_direction_output; 955 chip->get = rzv2m_gpio_get; 956 chip->set = rzv2m_gpio_set; 957 chip->label = name; 958 chip->parent = pctrl->dev; 959 chip->owner = THIS_MODULE; 960 chip->base = -1; 961 chip->ngpio = of_args.args[2]; 962 963 pctrl->gpio_range.id = 0; 964 pctrl->gpio_range.pin_base = 0; 965 pctrl->gpio_range.base = 0; 966 pctrl->gpio_range.npins = chip->ngpio; 967 pctrl->gpio_range.name = chip->label; 968 pctrl->gpio_range.gc = chip; 969 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 970 if (ret) { 971 dev_err(pctrl->dev, "failed to add GPIO controller\n"); 972 return ret; 973 } 974 975 dev_dbg(pctrl->dev, "Registered gpio controller\n"); 976 977 return 0; 978 } 979 980 static int rzv2m_pinctrl_register(struct rzv2m_pinctrl *pctrl) 981 { 982 struct pinctrl_pin_desc *pins; 983 unsigned int i, j; 984 u32 *pin_data; 985 int ret; 986 987 pctrl->desc.name = DRV_NAME; 988 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; 989 pctrl->desc.pctlops = &rzv2m_pinctrl_pctlops; 990 pctrl->desc.pmxops = &rzv2m_pinctrl_pmxops; 991 pctrl->desc.confops = &rzv2m_pinctrl_confops; 992 pctrl->desc.owner = THIS_MODULE; 993 994 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); 995 if (!pins) 996 return -ENOMEM; 997 998 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, 999 sizeof(*pin_data), GFP_KERNEL); 1000 if (!pin_data) 1001 return -ENOMEM; 1002 1003 pctrl->pins = pins; 1004 pctrl->desc.pins = pins; 1005 1006 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 1007 pins[i].number = i; 1008 pins[i].name = pctrl->data->port_pins[i]; 1009 if (i && !(i % RZV2M_PINS_PER_PORT)) 1010 j++; 1011 pin_data[i] = pctrl->data->port_pin_configs[j]; 1012 pins[i].drv_data = &pin_data[i]; 1013 } 1014 1015 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { 1016 unsigned int index = pctrl->data->n_port_pins + i; 1017 1018 pins[index].number = index; 1019 pins[index].name = pctrl->data->dedicated_pins[i].name; 1020 pin_data[index] = pctrl->data->dedicated_pins[i].config; 1021 pins[index].drv_data = &pin_data[index]; 1022 } 1023 1024 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, 1025 &pctrl->pctl); 1026 if (ret) { 1027 dev_err(pctrl->dev, "pinctrl registration failed\n"); 1028 return ret; 1029 } 1030 1031 ret = pinctrl_enable(pctrl->pctl); 1032 if (ret) { 1033 dev_err(pctrl->dev, "pinctrl enable failed\n"); 1034 return ret; 1035 } 1036 1037 ret = rzv2m_gpio_register(pctrl); 1038 if (ret) { 1039 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); 1040 return ret; 1041 } 1042 1043 return 0; 1044 } 1045 1046 static int rzv2m_pinctrl_probe(struct platform_device *pdev) 1047 { 1048 struct rzv2m_pinctrl *pctrl; 1049 struct clk *clk; 1050 int ret; 1051 1052 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1053 if (!pctrl) 1054 return -ENOMEM; 1055 1056 pctrl->dev = &pdev->dev; 1057 1058 pctrl->data = of_device_get_match_data(&pdev->dev); 1059 if (!pctrl->data) 1060 return -EINVAL; 1061 1062 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 1063 if (IS_ERR(pctrl->base)) 1064 return PTR_ERR(pctrl->base); 1065 1066 clk = devm_clk_get_enabled(pctrl->dev, NULL); 1067 if (IS_ERR(clk)) 1068 return dev_err_probe(pctrl->dev, PTR_ERR(clk), 1069 "failed to enable GPIO clk\n"); 1070 1071 spin_lock_init(&pctrl->lock); 1072 mutex_init(&pctrl->mutex); 1073 1074 platform_set_drvdata(pdev, pctrl); 1075 1076 ret = rzv2m_pinctrl_register(pctrl); 1077 if (ret) 1078 return ret; 1079 1080 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); 1081 return 0; 1082 } 1083 1084 static struct rzv2m_pinctrl_data r9a09g011_data = { 1085 .port_pins = rzv2m_gpio_names, 1086 .port_pin_configs = rzv2m_gpio_configs, 1087 .dedicated_pins = rzv2m_dedicated_pins, 1088 .n_port_pins = ARRAY_SIZE(rzv2m_gpio_configs) * RZV2M_PINS_PER_PORT, 1089 .n_dedicated_pins = ARRAY_SIZE(rzv2m_dedicated_pins), 1090 }; 1091 1092 static const struct of_device_id rzv2m_pinctrl_of_table[] = { 1093 { 1094 .compatible = "renesas,r9a09g011-pinctrl", 1095 .data = &r9a09g011_data, 1096 }, 1097 { /* sentinel */ } 1098 }; 1099 1100 static struct platform_driver rzv2m_pinctrl_driver = { 1101 .driver = { 1102 .name = DRV_NAME, 1103 .of_match_table = of_match_ptr(rzv2m_pinctrl_of_table), 1104 }, 1105 .probe = rzv2m_pinctrl_probe, 1106 }; 1107 1108 static int __init rzv2m_pinctrl_init(void) 1109 { 1110 return platform_driver_register(&rzv2m_pinctrl_driver); 1111 } 1112 core_initcall(rzv2m_pinctrl_init); 1113 1114 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>"); 1115 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/V2M"); 1116