1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G2L Pin Control and GPIO driver core 4 * 5 * Copyright (C) 2021 Renesas Electronics Corporation. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of.h> 17 #include <linux/of_irq.h> 18 #include <linux/platform_device.h> 19 #include <linux/seq_file.h> 20 #include <linux/spinlock.h> 21 22 #include <linux/pinctrl/consumer.h> 23 #include <linux/pinctrl/pinconf-generic.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinmux.h> 27 28 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 29 30 #include "../core.h" 31 #include "../pinconf.h" 32 #include "../pinmux.h" 33 34 #define DRV_NAME "pinctrl-rzg2l" 35 36 /* 37 * Use 16 lower bits [15:0] for pin identifier 38 * Use 16 higher bits [31:16] for pin mux function 39 */ 40 #define MUX_PIN_ID_MASK GENMASK(15, 0) 41 #define MUX_FUNC_MASK GENMASK(31, 16) 42 43 /* PIN capabilities */ 44 #define PIN_CFG_IOLH_A BIT(0) 45 #define PIN_CFG_IOLH_B BIT(1) 46 #define PIN_CFG_SR BIT(2) 47 #define PIN_CFG_IEN BIT(3) 48 #define PIN_CFG_PUPD BIT(4) 49 #define PIN_CFG_IO_VMC_SD0 BIT(5) 50 #define PIN_CFG_IO_VMC_SD1 BIT(6) 51 #define PIN_CFG_IO_VMC_QSPI BIT(7) 52 #define PIN_CFG_IO_VMC_ETH0 BIT(8) 53 #define PIN_CFG_IO_VMC_ETH1 BIT(9) 54 #define PIN_CFG_FILONOFF BIT(10) 55 #define PIN_CFG_FILNUM BIT(11) 56 #define PIN_CFG_FILCLKSEL BIT(12) 57 #define PIN_CFG_IOLH_C BIT(13) 58 #define PIN_CFG_SOFT_PS BIT(14) 59 #define PIN_CFG_OEN BIT(15) 60 #define PIN_CFG_NOGPIO_INT BIT(16) 61 #define PIN_CFG_NOD BIT(17) /* N-ch Open Drain */ 62 #define PIN_CFG_SMT BIT(18) /* Schmitt-trigger input control */ 63 #define PIN_CFG_ELC BIT(19) 64 #define PIN_CFG_IOLH_RZV2H BIT(20) 65 66 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ 67 #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ 68 69 #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ 70 (PIN_CFG_IOLH_##group | \ 71 PIN_CFG_PUPD | \ 72 PIN_CFG_FILONOFF | \ 73 PIN_CFG_FILNUM | \ 74 PIN_CFG_FILCLKSEL) 75 76 #define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \ 77 PIN_CFG_SR) 78 79 #define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \ 80 PIN_CFG_SOFT_PS) 81 82 #define RZV2H_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | \ 83 PIN_CFG_NOD | \ 84 PIN_CFG_SR | \ 85 PIN_CFG_SMT) 86 87 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ 88 PIN_CFG_FILONOFF | \ 89 PIN_CFG_FILNUM | \ 90 PIN_CFG_FILCLKSEL) 91 92 #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54) 93 #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46) 94 #define PIN_CFG_MASK GENMASK_ULL(31, 0) 95 96 /* 97 * m indicates the bitmap of supported pins, a is the register index 98 * and f is pin configuration capabilities supported. 99 */ 100 #define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \ 101 FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ 102 FIELD_PREP_CONST(PIN_CFG_MASK, (f))) 103 #define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a) \ 104 (RZG2L_VARIABLE_CFG | \ 105 RZG2L_GPIO_PORT_SPARSE_PACK(m, a, 0)) 106 107 /* 108 * n indicates number of pins in the port, a is the register index 109 * and f is pin configuration capabilities supported. 110 */ 111 #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f)) 112 #define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a) (RZG2L_VARIABLE_CFG | \ 113 RZG2L_GPIO_PORT_PACK(n, a, 0)) 114 115 #define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56) 116 #define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53) 117 /* 118 * p is the register index while referencing to SR/IEN/IOLH/FILxx 119 * registers, b is the register bits (b * 8) and f is the pin 120 * configuration capabilities supported. 121 */ 122 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ 123 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \ 124 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \ 125 FIELD_PREP_CONST(PIN_CFG_MASK, (f))) 126 127 #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ 128 FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \ 129 FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg))) 130 131 #define VARIABLE_PIN_CFG_PIN_MASK GENMASK_ULL(54, 52) 132 #define VARIABLE_PIN_CFG_PORT_MASK GENMASK_ULL(51, 47) 133 #define RZG2L_VARIABLE_PIN_CFG_PACK(port, pin, cfg) \ 134 (FIELD_PREP_CONST(VARIABLE_PIN_CFG_PIN_MASK, (pin)) | \ 135 FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \ 136 FIELD_PREP_CONST(PIN_CFG_MASK, (cfg))) 137 138 #define P(off) (0x0000 + (off)) 139 #define PM(off) (0x0100 + (off) * 2) 140 #define PMC(off) (0x0200 + (off)) 141 #define PFC(off) (0x0400 + (off) * 4) 142 #define PIN(off) (0x0800 + (off)) 143 #define IOLH(off) (0x1000 + (off) * 8) 144 #define SR(off) (0x1400 + (off) * 8) 145 #define IEN(off) (0x1800 + (off) * 8) 146 #define PUPD(off) (0x1C00 + (off) * 8) 147 #define ISEL(off) (0x2C00 + (off) * 8) 148 #define SD_CH(off, ch) ((off) + (ch) * 4) 149 #define ETH_POC(off, ch) ((off) + (ch) * 4) 150 #define QSPI (0x3008) 151 #define ETH_MODE (0x3018) 152 #define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */ 153 154 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ 155 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ 156 #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ 157 158 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ 159 #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ 160 #define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable on RZ/V2H(P) */ 161 #define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */ 162 163 #define PM_MASK 0x03 164 #define PFC_MASK 0x07 165 #define IEN_MASK 0x01 166 #define IOLH_MASK 0x03 167 #define SR_MASK 0x01 168 #define PUPD_MASK 0x03 169 170 #define PM_INPUT 0x1 171 #define PM_OUTPUT 0x2 172 173 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) 174 #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) 175 176 #define RZG2L_TINT_MAX_INTERRUPT 32 177 #define RZG2L_TINT_IRQ_START_INDEX 9 178 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) 179 180 /* Custom pinconf parameters */ 181 #define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE (PIN_CONFIG_END + 1) 182 183 static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = { 184 { "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 }, 185 }; 186 187 #ifdef CONFIG_DEBUG_FS 188 static const struct pin_config_item renesas_rzv2h_conf_items[] = { 189 PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true), 190 }; 191 #endif 192 193 /* Read/write 8 bits register */ 194 #define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \ 195 do { \ 196 if (_read) \ 197 _val = readb(_addr); \ 198 else \ 199 writeb(_val, _addr); \ 200 } while (0) 201 202 /* Read/write 16 bits register */ 203 #define RZG2L_PCTRL_REG_ACCESS16(_read, _addr, _val) \ 204 do { \ 205 if (_read) \ 206 _val = readw(_addr); \ 207 else \ 208 writew(_val, _addr); \ 209 } while (0) 210 211 /* Read/write 32 bits register */ 212 #define RZG2L_PCTRL_REG_ACCESS32(_read, _addr, _val) \ 213 do { \ 214 if (_read) \ 215 _val = readl(_addr); \ 216 else \ 217 writel(_val, _addr); \ 218 } while (0) 219 220 /** 221 * struct rzg2l_register_offsets - specific register offsets 222 * @pwpr: PWPR register offset 223 * @sd_ch: SD_CH register offset 224 * @eth_poc: ETH_POC register offset 225 */ 226 struct rzg2l_register_offsets { 227 u16 pwpr; 228 u16 sd_ch; 229 u16 eth_poc; 230 }; 231 232 /** 233 * enum rzg2l_iolh_index - starting indices in IOLH specific arrays 234 * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source 235 * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source 236 * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source 237 * @RZG2L_IOLH_IDX_MAX: maximum index 238 */ 239 enum rzg2l_iolh_index { 240 RZG2L_IOLH_IDX_1V8 = 0, 241 RZG2L_IOLH_IDX_2V5 = 4, 242 RZG2L_IOLH_IDX_3V3 = 8, 243 RZG2L_IOLH_IDX_MAX = 12, 244 }; 245 246 /* Maximum number of driver strength entries per power source. */ 247 #define RZG2L_IOLH_MAX_DS_ENTRIES (4) 248 249 /** 250 * struct rzg2l_hwcfg - hardware configuration data structure 251 * @regs: hardware specific register offsets 252 * @iolh_groupa_ua: IOLH group A uA specific values 253 * @iolh_groupb_ua: IOLH group B uA specific values 254 * @iolh_groupc_ua: IOLH group C uA specific values 255 * @iolh_groupb_oi: IOLH group B output impedance specific values 256 * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) 257 * @func_base: base number for port function (see register PFC) 258 * @oen_max_pin: the maximum pin number supporting output enable 259 * @oen_max_port: the maximum port number supporting output enable 260 */ 261 struct rzg2l_hwcfg { 262 const struct rzg2l_register_offsets regs; 263 u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; 264 u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; 265 u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; 266 u16 iolh_groupb_oi[4]; 267 bool drive_strength_ua; 268 u8 func_base; 269 u8 oen_max_pin; 270 u8 oen_max_port; 271 }; 272 273 struct rzg2l_dedicated_configs { 274 const char *name; 275 u64 config; 276 }; 277 278 struct rzg2l_pinctrl; 279 280 struct rzg2l_pinctrl_data { 281 const char * const *port_pins; 282 const u64 *port_pin_configs; 283 unsigned int n_ports; 284 const struct rzg2l_dedicated_configs *dedicated_pins; 285 unsigned int n_port_pins; 286 unsigned int n_dedicated_pins; 287 const struct rzg2l_hwcfg *hwcfg; 288 const u64 *variable_pin_cfg; 289 unsigned int n_variable_pin_cfg; 290 unsigned int num_custom_params; 291 const struct pinconf_generic_params *custom_params; 292 #ifdef CONFIG_DEBUG_FS 293 const struct pin_config_item *custom_conf_items; 294 #endif 295 void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock); 296 void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset); 297 u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); 298 int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen); 299 int (*hw_to_bias_param)(unsigned int val); 300 int (*bias_param_to_hw)(enum pin_config_param param); 301 }; 302 303 /** 304 * struct rzg2l_pinctrl_pin_settings - pin data 305 * @power_source: power source 306 * @drive_strength_ua: drive strength (in micro amps) 307 */ 308 struct rzg2l_pinctrl_pin_settings { 309 u16 power_source; 310 u16 drive_strength_ua; 311 }; 312 313 /** 314 * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume) 315 * @p: P registers cache 316 * @pm: PM registers cache 317 * @pmc: PMC registers cache 318 * @pfc: PFC registers cache 319 * @iolh: IOLH registers cache 320 * @ien: IEN registers cache 321 * @sd_ch: SD_CH registers cache 322 * @eth_poc: ET_POC registers cache 323 * @eth_mode: ETH_MODE register cache 324 * @qspi: QSPI registers cache 325 */ 326 struct rzg2l_pinctrl_reg_cache { 327 u8 *p; 328 u16 *pm; 329 u8 *pmc; 330 u32 *pfc; 331 u32 *iolh[2]; 332 u32 *ien[2]; 333 u8 sd_ch[2]; 334 u8 eth_poc[2]; 335 u8 eth_mode; 336 u8 qspi; 337 }; 338 339 struct rzg2l_pinctrl { 340 struct pinctrl_dev *pctl; 341 struct pinctrl_desc desc; 342 struct pinctrl_pin_desc *pins; 343 344 const struct rzg2l_pinctrl_data *data; 345 void __iomem *base; 346 struct device *dev; 347 348 struct clk *clk; 349 350 struct gpio_chip gpio_chip; 351 struct pinctrl_gpio_range gpio_range; 352 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); 353 spinlock_t bitmap_lock; /* protect tint_slot bitmap */ 354 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; 355 356 spinlock_t lock; /* lock read/write registers */ 357 struct mutex mutex; /* serialize adding groups and functions */ 358 359 struct rzg2l_pinctrl_pin_settings *settings; 360 struct rzg2l_pinctrl_reg_cache *cache; 361 struct rzg2l_pinctrl_reg_cache *dedicated_cache; 362 atomic_t wakeup_path; 363 }; 364 365 static const u16 available_ps[] = { 1800, 2500, 3300 }; 366 367 static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, 368 u64 pincfg, 369 unsigned int port, 370 u8 pin) 371 { 372 unsigned int i; 373 374 for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { 375 u64 cfg = pctrl->data->variable_pin_cfg[i]; 376 377 if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port && 378 FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin) 379 return (pincfg & ~RZG2L_VARIABLE_CFG) | FIELD_GET(PIN_CFG_MASK, cfg); 380 } 381 382 return 0; 383 } 384 385 static const u64 r9a09g057_variable_pin_cfg[] = { 386 RZG2L_VARIABLE_PIN_CFG_PACK(11, 0, RZV2H_MPXED_PIN_FUNCS), 387 RZG2L_VARIABLE_PIN_CFG_PACK(11, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 388 RZG2L_VARIABLE_PIN_CFG_PACK(11, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 389 RZG2L_VARIABLE_PIN_CFG_PACK(11, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 390 RZG2L_VARIABLE_PIN_CFG_PACK(11, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 391 RZG2L_VARIABLE_PIN_CFG_PACK(11, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 392 }; 393 394 #ifdef CONFIG_RISCV 395 static const u64 r9a07g043f_variable_pin_cfg[] = { 396 RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 397 PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | 398 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 399 RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 400 PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | 401 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 402 RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 403 PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | 404 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 405 RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 406 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 407 RZG2L_VARIABLE_PIN_CFG_PACK(20, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 408 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 409 RZG2L_VARIABLE_PIN_CFG_PACK(20, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 410 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 411 RZG2L_VARIABLE_PIN_CFG_PACK(20, 6, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 412 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 413 RZG2L_VARIABLE_PIN_CFG_PACK(20, 7, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 414 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 415 RZG2L_VARIABLE_PIN_CFG_PACK(23, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 416 PIN_CFG_NOGPIO_INT), 417 RZG2L_VARIABLE_PIN_CFG_PACK(23, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 418 PIN_CFG_NOGPIO_INT), 419 RZG2L_VARIABLE_PIN_CFG_PACK(23, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 420 PIN_CFG_NOGPIO_INT), 421 RZG2L_VARIABLE_PIN_CFG_PACK(23, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 422 PIN_CFG_NOGPIO_INT), 423 RZG2L_VARIABLE_PIN_CFG_PACK(23, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT), 424 RZG2L_VARIABLE_PIN_CFG_PACK(24, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT), 425 RZG2L_VARIABLE_PIN_CFG_PACK(24, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 426 PIN_CFG_NOGPIO_INT), 427 RZG2L_VARIABLE_PIN_CFG_PACK(24, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 428 PIN_CFG_NOGPIO_INT), 429 RZG2L_VARIABLE_PIN_CFG_PACK(24, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 430 PIN_CFG_NOGPIO_INT), 431 RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 432 PIN_CFG_NOGPIO_INT), 433 RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 434 PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | 435 PIN_CFG_NOGPIO_INT), 436 }; 437 #endif 438 439 static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) 440 { 441 writeb(val, pctrl->base + offset); 442 } 443 444 static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) 445 { 446 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 447 u8 pwpr; 448 449 pwpr = readb(pctrl->base + regs->pwpr); 450 writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr); 451 writeb(val, pctrl->base + offset); 452 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); 453 } 454 455 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, 456 u8 pin, u8 off, u8 func) 457 { 458 unsigned long flags; 459 u32 reg; 460 461 spin_lock_irqsave(&pctrl->lock, flags); 462 463 /* Set pin to 'Non-use (Hi-Z input protection)' */ 464 reg = readw(pctrl->base + PM(off)); 465 reg &= ~(PM_MASK << (pin * 2)); 466 writew(reg, pctrl->base + PM(off)); 467 468 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); 469 470 /* Temporarily switch to GPIO mode with PMC register */ 471 reg = readb(pctrl->base + PMC(off)); 472 writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); 473 474 /* Select Pin function mode with PFC register */ 475 reg = readl(pctrl->base + PFC(off)); 476 reg &= ~(PFC_MASK << (pin * 4)); 477 writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); 478 479 /* Switch to Peripheral pin function with PMC register */ 480 reg = readb(pctrl->base + PMC(off)); 481 writeb(reg | BIT(pin), pctrl->base + PMC(off)); 482 483 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); 484 485 spin_unlock_irqrestore(&pctrl->lock, flags); 486 }; 487 488 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, 489 unsigned int func_selector, 490 unsigned int group_selector) 491 { 492 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 493 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 494 struct function_desc *func; 495 unsigned int i, *psel_val; 496 struct group_desc *group; 497 const unsigned int *pins; 498 499 func = pinmux_generic_get_function(pctldev, func_selector); 500 if (!func) 501 return -EINVAL; 502 group = pinctrl_generic_get_group(pctldev, group_selector); 503 if (!group) 504 return -EINVAL; 505 506 psel_val = func->data; 507 pins = group->grp.pins; 508 509 for (i = 0; i < group->grp.npins; i++) { 510 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; 511 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 512 u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); 513 514 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", 515 RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); 516 517 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); 518 } 519 520 return 0; 521 }; 522 523 static int rzg2l_map_add_config(struct pinctrl_map *map, 524 const char *group_or_pin, 525 enum pinctrl_map_type type, 526 unsigned long *configs, 527 unsigned int num_configs) 528 { 529 unsigned long *cfgs; 530 531 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), 532 GFP_KERNEL); 533 if (!cfgs) 534 return -ENOMEM; 535 536 map->type = type; 537 map->data.configs.group_or_pin = group_or_pin; 538 map->data.configs.configs = cfgs; 539 map->data.configs.num_configs = num_configs; 540 541 return 0; 542 } 543 544 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, 545 struct device_node *np, 546 struct device_node *parent, 547 struct pinctrl_map **map, 548 unsigned int *num_maps, 549 unsigned int *index) 550 { 551 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 552 struct pinctrl_map *maps = *map; 553 unsigned int nmaps = *num_maps; 554 unsigned long *configs = NULL; 555 unsigned int *pins, *psel_val; 556 unsigned int num_pinmux = 0; 557 unsigned int idx = *index; 558 unsigned int num_pins, i; 559 unsigned int num_configs; 560 struct property *pinmux; 561 struct property *prop; 562 int ret, gsel, fsel; 563 const char **pin_fn; 564 const char *name; 565 const char *pin; 566 567 pinmux = of_find_property(np, "pinmux", NULL); 568 if (pinmux) 569 num_pinmux = pinmux->length / sizeof(u32); 570 571 ret = of_property_count_strings(np, "pins"); 572 if (ret == -EINVAL) { 573 num_pins = 0; 574 } else if (ret < 0) { 575 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 576 return ret; 577 } else { 578 num_pins = ret; 579 } 580 581 if (!num_pinmux && !num_pins) 582 return 0; 583 584 if (num_pinmux && num_pins) { 585 dev_err(pctrl->dev, 586 "DT node must contain either a pinmux or pins and not both\n"); 587 return -EINVAL; 588 } 589 590 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); 591 if (ret < 0) 592 return ret; 593 594 if (num_pins && !num_configs) { 595 dev_err(pctrl->dev, "DT node must contain a config\n"); 596 ret = -ENODEV; 597 goto done; 598 } 599 600 if (num_pinmux) { 601 nmaps += 1; 602 if (num_configs) 603 nmaps += 1; 604 } 605 606 if (num_pins) 607 nmaps += num_pins; 608 609 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 610 if (!maps) { 611 ret = -ENOMEM; 612 goto done; 613 } 614 615 *map = maps; 616 *num_maps = nmaps; 617 if (num_pins) { 618 of_property_for_each_string(np, "pins", prop, pin) { 619 ret = rzg2l_map_add_config(&maps[idx], pin, 620 PIN_MAP_TYPE_CONFIGS_PIN, 621 configs, num_configs); 622 if (ret < 0) 623 goto done; 624 625 idx++; 626 } 627 ret = 0; 628 goto done; 629 } 630 631 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 632 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 633 GFP_KERNEL); 634 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 635 if (!pins || !psel_val || !pin_fn) { 636 ret = -ENOMEM; 637 goto done; 638 } 639 640 /* Collect pin locations and mux settings from DT properties */ 641 for (i = 0; i < num_pinmux; ++i) { 642 u32 value; 643 644 ret = of_property_read_u32_index(np, "pinmux", i, &value); 645 if (ret) 646 goto done; 647 pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value); 648 psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value); 649 } 650 651 if (parent) { 652 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", 653 parent, np); 654 if (!name) { 655 ret = -ENOMEM; 656 goto done; 657 } 658 } else { 659 name = np->name; 660 } 661 662 if (num_configs) { 663 ret = rzg2l_map_add_config(&maps[idx], name, 664 PIN_MAP_TYPE_CONFIGS_GROUP, 665 configs, num_configs); 666 if (ret < 0) 667 goto done; 668 669 idx++; 670 } 671 672 mutex_lock(&pctrl->mutex); 673 674 /* Register a single pin group listing all the pins we read from DT */ 675 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL); 676 if (gsel < 0) { 677 ret = gsel; 678 goto unlock; 679 } 680 681 /* 682 * Register a single group function where the 'data' is an array PSEL 683 * register values read from DT. 684 */ 685 pin_fn[0] = name; 686 fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val); 687 if (fsel < 0) { 688 ret = fsel; 689 goto remove_group; 690 } 691 692 mutex_unlock(&pctrl->mutex); 693 694 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 695 maps[idx].data.mux.group = name; 696 maps[idx].data.mux.function = name; 697 idx++; 698 699 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 700 ret = 0; 701 goto done; 702 703 remove_group: 704 pinctrl_generic_remove_group(pctldev, gsel); 705 unlock: 706 mutex_unlock(&pctrl->mutex); 707 done: 708 *index = idx; 709 kfree(configs); 710 return ret; 711 } 712 713 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, 714 struct pinctrl_map *map, 715 unsigned int num_maps) 716 { 717 unsigned int i; 718 719 if (!map) 720 return; 721 722 for (i = 0; i < num_maps; ++i) { 723 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 724 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 725 kfree(map[i].data.configs.configs); 726 } 727 kfree(map); 728 } 729 730 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, 731 struct device_node *np, 732 struct pinctrl_map **map, 733 unsigned int *num_maps) 734 { 735 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 736 unsigned int index; 737 int ret; 738 739 *map = NULL; 740 *num_maps = 0; 741 index = 0; 742 743 for_each_child_of_node_scoped(np, child) { 744 ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map, 745 num_maps, &index); 746 if (ret < 0) 747 goto done; 748 } 749 750 if (*num_maps == 0) { 751 ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map, 752 num_maps, &index); 753 if (ret < 0) 754 goto done; 755 } 756 757 if (*num_maps) 758 return 0; 759 760 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 761 ret = -EINVAL; 762 763 done: 764 rzg2l_dt_free_map(pctldev, *map, *num_maps); 765 766 return ret; 767 } 768 769 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, 770 u64 cfg, u32 port, u8 bit) 771 { 772 u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); 773 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 774 u64 data; 775 776 if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) 777 return -EINVAL; 778 779 data = pctrl->data->port_pin_configs[port]; 780 if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data)) 781 return -EINVAL; 782 783 return 0; 784 } 785 786 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 787 u8 bit, u32 mask) 788 { 789 void __iomem *addr = pctrl->base + offset; 790 791 /* handle _L/_H for 32-bit register read/write */ 792 if (bit >= 4) { 793 bit -= 4; 794 addr += 4; 795 } 796 797 return (readl(addr) >> (bit * 8)) & mask; 798 } 799 800 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 801 u8 bit, u32 mask, u32 val) 802 { 803 void __iomem *addr = pctrl->base + offset; 804 unsigned long flags; 805 u32 reg; 806 807 /* handle _L/_H for 32-bit register read/write */ 808 if (bit >= 4) { 809 bit -= 4; 810 addr += 4; 811 } 812 813 spin_lock_irqsave(&pctrl->lock, flags); 814 reg = readl(addr) & ~(mask << (bit * 8)); 815 writel(reg | (val << (bit * 8)), addr); 816 spin_unlock_irqrestore(&pctrl->lock, flags); 817 } 818 819 static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps) 820 { 821 if (caps & PIN_CFG_IO_VMC_SD0) 822 return SD_CH(regs->sd_ch, 0); 823 if (caps & PIN_CFG_IO_VMC_SD1) 824 return SD_CH(regs->sd_ch, 1); 825 if (caps & PIN_CFG_IO_VMC_ETH0) 826 return ETH_POC(regs->eth_poc, 0); 827 if (caps & PIN_CFG_IO_VMC_ETH1) 828 return ETH_POC(regs->eth_poc, 1); 829 if (caps & PIN_CFG_IO_VMC_QSPI) 830 return QSPI; 831 832 return -EINVAL; 833 } 834 835 static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) 836 { 837 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 838 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 839 int pwr_reg; 840 u8 val; 841 842 if (caps & PIN_CFG_SOFT_PS) 843 return pctrl->settings[pin].power_source; 844 845 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); 846 if (pwr_reg < 0) 847 return pwr_reg; 848 849 val = readb(pctrl->base + pwr_reg); 850 switch (val) { 851 case PVDD_1800: 852 return 1800; 853 case PVDD_2500: 854 return 2500; 855 case PVDD_3300: 856 return 3300; 857 default: 858 /* Should not happen. */ 859 return -EINVAL; 860 } 861 } 862 863 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) 864 { 865 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 866 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 867 int pwr_reg; 868 u8 val; 869 870 if (caps & PIN_CFG_SOFT_PS) { 871 pctrl->settings[pin].power_source = ps; 872 return 0; 873 } 874 875 switch (ps) { 876 case 1800: 877 val = PVDD_1800; 878 break; 879 case 2500: 880 if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) 881 return -EINVAL; 882 val = PVDD_2500; 883 break; 884 case 3300: 885 val = PVDD_3300; 886 break; 887 default: 888 return -EINVAL; 889 } 890 891 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); 892 if (pwr_reg < 0) 893 return pwr_reg; 894 895 writeb(val, pctrl->base + pwr_reg); 896 pctrl->settings[pin].power_source = ps; 897 898 return 0; 899 } 900 901 static bool rzg2l_ps_is_supported(u16 ps) 902 { 903 unsigned int i; 904 905 for (i = 0; i < ARRAY_SIZE(available_ps); i++) { 906 if (available_ps[i] == ps) 907 return true; 908 } 909 910 return false; 911 } 912 913 static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps) 914 { 915 unsigned int i; 916 917 for (i = 0; i < ARRAY_SIZE(available_ps); i++) { 918 if (available_ps[i] == ps) 919 break; 920 } 921 922 /* 923 * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have 924 * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source 925 */ 926 return i * RZG2L_IOLH_MAX_DS_ENTRIES; 927 } 928 929 static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val) 930 { 931 if (caps & PIN_CFG_IOLH_A) 932 return hwcfg->iolh_groupa_ua[val]; 933 934 if (caps & PIN_CFG_IOLH_B) 935 return hwcfg->iolh_groupb_ua[val]; 936 937 if (caps & PIN_CFG_IOLH_C) 938 return hwcfg->iolh_groupc_ua[val]; 939 940 /* Should not happen. */ 941 return 0; 942 } 943 944 static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps, 945 enum rzg2l_iolh_index ps_index, u16 ua) 946 { 947 const u16 *array = NULL; 948 unsigned int i; 949 950 if (caps & PIN_CFG_IOLH_A) 951 array = &hwcfg->iolh_groupa_ua[ps_index]; 952 953 if (caps & PIN_CFG_IOLH_B) 954 array = &hwcfg->iolh_groupb_ua[ps_index]; 955 956 if (caps & PIN_CFG_IOLH_C) 957 array = &hwcfg->iolh_groupc_ua[ps_index]; 958 959 if (!array) 960 return -EINVAL; 961 962 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { 963 if (array[i] == ua) 964 return i; 965 } 966 967 return -EINVAL; 968 } 969 970 static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, 971 enum rzg2l_iolh_index iolh_idx, 972 u16 ds) 973 { 974 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 975 const u16 *array = NULL; 976 unsigned int i; 977 978 if (caps & PIN_CFG_IOLH_A) 979 array = hwcfg->iolh_groupa_ua; 980 981 if (caps & PIN_CFG_IOLH_B) 982 array = hwcfg->iolh_groupb_ua; 983 984 if (caps & PIN_CFG_IOLH_C) 985 array = hwcfg->iolh_groupc_ua; 986 987 /* Should not happen. */ 988 if (!array) 989 return false; 990 991 if (!array[iolh_idx]) 992 return false; 993 994 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { 995 if (array[iolh_idx + i] == ds) 996 return true; 997 } 998 999 return false; 1000 } 1001 1002 static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1003 { 1004 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; 1005 u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data); 1006 u8 pin = RZG2L_PIN_ID_TO_PIN(_pin); 1007 1008 if (pin > pctrl->data->hwcfg->oen_max_pin) 1009 return -EINVAL; 1010 1011 /* 1012 * We can determine which Ethernet interface we're dealing with from 1013 * the caps. 1014 */ 1015 if (caps & PIN_CFG_IO_VMC_ETH0) 1016 return 0; 1017 if (caps & PIN_CFG_IO_VMC_ETH1) 1018 return 1; 1019 1020 return -EINVAL; 1021 } 1022 1023 static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1024 { 1025 int bit; 1026 1027 bit = rzg2l_pin_to_oen_bit(pctrl, _pin); 1028 if (bit < 0) 1029 return 0; 1030 1031 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); 1032 } 1033 1034 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) 1035 { 1036 unsigned long flags; 1037 int bit; 1038 u8 val; 1039 1040 bit = rzg2l_pin_to_oen_bit(pctrl, _pin); 1041 if (bit < 0) 1042 return bit; 1043 1044 spin_lock_irqsave(&pctrl->lock, flags); 1045 val = readb(pctrl->base + ETH_MODE); 1046 if (oen) 1047 val &= ~BIT(bit); 1048 else 1049 val |= BIT(bit); 1050 writeb(val, pctrl->base + ETH_MODE); 1051 spin_unlock_irqrestore(&pctrl->lock, flags); 1052 1053 return 0; 1054 } 1055 1056 static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1057 { 1058 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; 1059 u8 port, pin, bit; 1060 1061 if (*pin_data & RZG2L_SINGLE_PIN) 1062 return -EINVAL; 1063 1064 port = RZG2L_PIN_ID_TO_PORT(_pin); 1065 pin = RZG2L_PIN_ID_TO_PIN(_pin); 1066 if (pin > pctrl->data->hwcfg->oen_max_pin) 1067 return -EINVAL; 1068 1069 bit = pin * 2; 1070 if (port == pctrl->data->hwcfg->oen_max_port) 1071 bit += 1; 1072 1073 return bit; 1074 } 1075 1076 static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1077 { 1078 int bit; 1079 1080 bit = rzg3s_pin_to_oen_bit(pctrl, _pin); 1081 if (bit < 0) 1082 return bit; 1083 1084 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); 1085 } 1086 1087 static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) 1088 { 1089 unsigned long flags; 1090 int bit; 1091 u8 val; 1092 1093 bit = rzg3s_pin_to_oen_bit(pctrl, _pin); 1094 if (bit < 0) 1095 return bit; 1096 1097 spin_lock_irqsave(&pctrl->lock, flags); 1098 val = readb(pctrl->base + ETH_MODE); 1099 if (oen) 1100 val &= ~BIT(bit); 1101 else 1102 val |= BIT(bit); 1103 writeb(val, pctrl->base + ETH_MODE); 1104 spin_unlock_irqrestore(&pctrl->lock, flags); 1105 1106 return 0; 1107 } 1108 1109 static int rzg2l_hw_to_bias_param(unsigned int bias) 1110 { 1111 switch (bias) { 1112 case 0: 1113 return PIN_CONFIG_BIAS_DISABLE; 1114 case 1: 1115 return PIN_CONFIG_BIAS_PULL_UP; 1116 case 2: 1117 return PIN_CONFIG_BIAS_PULL_DOWN; 1118 default: 1119 break; 1120 } 1121 1122 return -EINVAL; 1123 } 1124 1125 static int rzg2l_bias_param_to_hw(enum pin_config_param param) 1126 { 1127 switch (param) { 1128 case PIN_CONFIG_BIAS_DISABLE: 1129 return 0; 1130 case PIN_CONFIG_BIAS_PULL_UP: 1131 return 1; 1132 case PIN_CONFIG_BIAS_PULL_DOWN: 1133 return 2; 1134 default: 1135 break; 1136 } 1137 1138 return -EINVAL; 1139 } 1140 1141 static int rzv2h_hw_to_bias_param(unsigned int bias) 1142 { 1143 switch (bias) { 1144 case 0: 1145 case 1: 1146 return PIN_CONFIG_BIAS_DISABLE; 1147 case 2: 1148 return PIN_CONFIG_BIAS_PULL_DOWN; 1149 case 3: 1150 return PIN_CONFIG_BIAS_PULL_UP; 1151 default: 1152 break; 1153 } 1154 1155 return -EINVAL; 1156 } 1157 1158 static int rzv2h_bias_param_to_hw(enum pin_config_param param) 1159 { 1160 switch (param) { 1161 case PIN_CONFIG_BIAS_DISABLE: 1162 return 0; 1163 case PIN_CONFIG_BIAS_PULL_DOWN: 1164 return 2; 1165 case PIN_CONFIG_BIAS_PULL_UP: 1166 return 3; 1167 default: 1168 break; 1169 } 1170 1171 return -EINVAL; 1172 } 1173 1174 static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1175 { 1176 static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK", 1177 "XSPI0_RESET0N", "XSPI0_CS0N", 1178 "XSPI0_CKN", "XSPI0_CKP" }; 1179 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin]; 1180 unsigned int i; 1181 1182 for (i = 0; i < ARRAY_SIZE(pin_names); i++) { 1183 if (!strcmp(pin_desc->name, pin_names[i])) 1184 return i; 1185 } 1186 1187 /* Should not happen. */ 1188 return 0; 1189 } 1190 1191 static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1192 { 1193 u8 bit; 1194 1195 bit = rzv2h_pin_to_oen_bit(pctrl, _pin); 1196 1197 return !(readb(pctrl->base + PFC_OEN) & BIT(bit)); 1198 } 1199 1200 static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) 1201 { 1202 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1203 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 1204 unsigned long flags; 1205 u8 val, bit; 1206 u8 pwpr; 1207 1208 bit = rzv2h_pin_to_oen_bit(pctrl, _pin); 1209 spin_lock_irqsave(&pctrl->lock, flags); 1210 val = readb(pctrl->base + PFC_OEN); 1211 if (oen) 1212 val &= ~BIT(bit); 1213 else 1214 val |= BIT(bit); 1215 1216 pwpr = readb(pctrl->base + regs->pwpr); 1217 writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); 1218 writeb(val, pctrl->base + PFC_OEN); 1219 writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); 1220 spin_unlock_irqrestore(&pctrl->lock, flags); 1221 1222 return 0; 1223 } 1224 1225 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 1226 unsigned int _pin, 1227 unsigned long *config) 1228 { 1229 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1230 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1231 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 1232 u32 param = pinconf_to_config_param(*config); 1233 u64 *pin_data = pin->drv_data; 1234 unsigned int arg = 0; 1235 u32 off; 1236 u32 cfg; 1237 int ret; 1238 u8 bit; 1239 1240 if (!pin_data) 1241 return -EINVAL; 1242 1243 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1244 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); 1245 if (*pin_data & RZG2L_SINGLE_PIN) { 1246 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); 1247 } else { 1248 bit = RZG2L_PIN_ID_TO_PIN(_pin); 1249 1250 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 1251 return -EINVAL; 1252 } 1253 1254 switch (param) { 1255 case PIN_CONFIG_INPUT_ENABLE: 1256 if (!(cfg & PIN_CFG_IEN)) 1257 return -EINVAL; 1258 arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK); 1259 if (!arg) 1260 return -EINVAL; 1261 break; 1262 1263 case PIN_CONFIG_OUTPUT_ENABLE: 1264 if (!pctrl->data->oen_read || !(cfg & PIN_CFG_OEN)) 1265 return -EOPNOTSUPP; 1266 arg = pctrl->data->oen_read(pctrl, _pin); 1267 if (!arg) 1268 return -EINVAL; 1269 break; 1270 1271 case PIN_CONFIG_POWER_SOURCE: 1272 ret = rzg2l_get_power_source(pctrl, _pin, cfg); 1273 if (ret < 0) 1274 return ret; 1275 arg = ret; 1276 break; 1277 1278 case PIN_CONFIG_SLEW_RATE: 1279 if (!(cfg & PIN_CFG_SR)) 1280 return -EINVAL; 1281 1282 arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK); 1283 break; 1284 1285 case PIN_CONFIG_BIAS_DISABLE: 1286 case PIN_CONFIG_BIAS_PULL_UP: 1287 case PIN_CONFIG_BIAS_PULL_DOWN: 1288 if (!(cfg & PIN_CFG_PUPD)) 1289 return -EINVAL; 1290 1291 arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK); 1292 ret = pctrl->data->hw_to_bias_param(arg); 1293 if (ret < 0) 1294 return ret; 1295 1296 if (ret != param) 1297 return -EINVAL; 1298 /* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */ 1299 arg = 1; 1300 break; 1301 1302 case PIN_CONFIG_DRIVE_STRENGTH: { 1303 unsigned int index; 1304 1305 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) 1306 return -EINVAL; 1307 1308 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1309 /* 1310 * Drive strenght mA is supported only by group A and only 1311 * for 3V3 port source. 1312 */ 1313 arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; 1314 break; 1315 } 1316 1317 case PIN_CONFIG_DRIVE_STRENGTH_UA: { 1318 enum rzg2l_iolh_index iolh_idx; 1319 u8 val; 1320 1321 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || 1322 !hwcfg->drive_strength_ua) 1323 return -EINVAL; 1324 1325 ret = rzg2l_get_power_source(pctrl, _pin, cfg); 1326 if (ret < 0) 1327 return ret; 1328 iolh_idx = rzg2l_ps_to_iolh_idx(ret); 1329 val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1330 arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val); 1331 break; 1332 } 1333 1334 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 1335 unsigned int index; 1336 1337 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) 1338 return -EINVAL; 1339 1340 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1341 arg = hwcfg->iolh_groupb_oi[index]; 1342 break; 1343 } 1344 1345 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: 1346 if (!(cfg & PIN_CFG_IOLH_RZV2H)) 1347 return -EINVAL; 1348 1349 arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1350 break; 1351 1352 default: 1353 return -ENOTSUPP; 1354 } 1355 1356 *config = pinconf_to_config_packed(param, arg); 1357 1358 return 0; 1359 }; 1360 1361 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 1362 unsigned int _pin, 1363 unsigned long *_configs, 1364 unsigned int num_configs) 1365 { 1366 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1367 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 1368 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1369 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; 1370 u64 *pin_data = pin->drv_data; 1371 unsigned int i, arg, index; 1372 u32 off, param; 1373 u32 cfg; 1374 int ret; 1375 u8 bit; 1376 1377 if (!pin_data) 1378 return -EINVAL; 1379 1380 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1381 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); 1382 if (*pin_data & RZG2L_SINGLE_PIN) { 1383 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); 1384 } else { 1385 bit = RZG2L_PIN_ID_TO_PIN(_pin); 1386 1387 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 1388 return -EINVAL; 1389 } 1390 1391 for (i = 0; i < num_configs; i++) { 1392 param = pinconf_to_config_param(_configs[i]); 1393 switch (param) { 1394 case PIN_CONFIG_INPUT_ENABLE: 1395 arg = pinconf_to_config_argument(_configs[i]); 1396 1397 if (!(cfg & PIN_CFG_IEN)) 1398 return -EINVAL; 1399 1400 rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); 1401 break; 1402 1403 case PIN_CONFIG_OUTPUT_ENABLE: 1404 arg = pinconf_to_config_argument(_configs[i]); 1405 if (!pctrl->data->oen_write || !(cfg & PIN_CFG_OEN)) 1406 return -EOPNOTSUPP; 1407 ret = pctrl->data->oen_write(pctrl, _pin, !!arg); 1408 if (ret) 1409 return ret; 1410 break; 1411 1412 case PIN_CONFIG_POWER_SOURCE: 1413 settings.power_source = pinconf_to_config_argument(_configs[i]); 1414 break; 1415 1416 case PIN_CONFIG_SLEW_RATE: 1417 arg = pinconf_to_config_argument(_configs[i]); 1418 1419 if (!(cfg & PIN_CFG_SR) || arg > 1) 1420 return -EINVAL; 1421 1422 rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg); 1423 break; 1424 1425 case PIN_CONFIG_BIAS_DISABLE: 1426 case PIN_CONFIG_BIAS_PULL_UP: 1427 case PIN_CONFIG_BIAS_PULL_DOWN: 1428 if (!(cfg & PIN_CFG_PUPD)) 1429 return -EINVAL; 1430 1431 ret = pctrl->data->bias_param_to_hw(param); 1432 if (ret < 0) 1433 return ret; 1434 1435 rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, ret); 1436 break; 1437 1438 case PIN_CONFIG_DRIVE_STRENGTH: 1439 arg = pinconf_to_config_argument(_configs[i]); 1440 1441 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) 1442 return -EINVAL; 1443 1444 for (index = RZG2L_IOLH_IDX_3V3; 1445 index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) { 1446 if (arg == (hwcfg->iolh_groupa_ua[index] / 1000)) 1447 break; 1448 } 1449 if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES)) 1450 return -EINVAL; 1451 1452 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); 1453 break; 1454 1455 case PIN_CONFIG_DRIVE_STRENGTH_UA: 1456 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || 1457 !hwcfg->drive_strength_ua) 1458 return -EINVAL; 1459 1460 settings.drive_strength_ua = pinconf_to_config_argument(_configs[i]); 1461 break; 1462 1463 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: 1464 arg = pinconf_to_config_argument(_configs[i]); 1465 1466 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) 1467 return -EINVAL; 1468 1469 for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { 1470 if (arg == hwcfg->iolh_groupb_oi[index]) 1471 break; 1472 } 1473 if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi)) 1474 return -EINVAL; 1475 1476 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); 1477 break; 1478 1479 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: 1480 if (!(cfg & PIN_CFG_IOLH_RZV2H)) 1481 return -EINVAL; 1482 1483 arg = pinconf_to_config_argument(_configs[i]); 1484 if (arg > 3) 1485 return -EINVAL; 1486 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg); 1487 break; 1488 1489 default: 1490 return -EOPNOTSUPP; 1491 } 1492 } 1493 1494 /* Apply power source. */ 1495 if (settings.power_source != pctrl->settings[_pin].power_source) { 1496 ret = rzg2l_ps_is_supported(settings.power_source); 1497 if (!ret) 1498 return -EINVAL; 1499 1500 /* Apply power source. */ 1501 ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source); 1502 if (ret) 1503 return ret; 1504 } 1505 1506 /* Apply drive strength. */ 1507 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { 1508 enum rzg2l_iolh_index iolh_idx; 1509 int val; 1510 1511 iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source); 1512 ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx, 1513 settings.drive_strength_ua); 1514 if (!ret) 1515 return -EINVAL; 1516 1517 /* Get register value for this PS/DS tuple. */ 1518 val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua); 1519 if (val < 0) 1520 return val; 1521 1522 /* Apply drive strength. */ 1523 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val); 1524 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; 1525 } 1526 1527 return 0; 1528 } 1529 1530 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, 1531 unsigned int group, 1532 unsigned long *configs, 1533 unsigned int num_configs) 1534 { 1535 const unsigned int *pins; 1536 unsigned int i, npins; 1537 int ret; 1538 1539 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 1540 if (ret) 1541 return ret; 1542 1543 for (i = 0; i < npins; i++) { 1544 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, 1545 num_configs); 1546 if (ret) 1547 return ret; 1548 } 1549 1550 return 0; 1551 }; 1552 1553 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, 1554 unsigned int group, 1555 unsigned long *config) 1556 { 1557 const unsigned int *pins; 1558 unsigned int i, npins, prev_config = 0; 1559 int ret; 1560 1561 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 1562 if (ret) 1563 return ret; 1564 1565 for (i = 0; i < npins; i++) { 1566 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); 1567 if (ret) 1568 return ret; 1569 1570 /* Check config matching between to pin */ 1571 if (i && prev_config != *config) 1572 return -EOPNOTSUPP; 1573 1574 prev_config = *config; 1575 } 1576 1577 return 0; 1578 }; 1579 1580 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { 1581 .get_groups_count = pinctrl_generic_get_group_count, 1582 .get_group_name = pinctrl_generic_get_group_name, 1583 .get_group_pins = pinctrl_generic_get_group_pins, 1584 .dt_node_to_map = rzg2l_dt_node_to_map, 1585 .dt_free_map = rzg2l_dt_free_map, 1586 }; 1587 1588 static const struct pinmux_ops rzg2l_pinctrl_pmxops = { 1589 .get_functions_count = pinmux_generic_get_function_count, 1590 .get_function_name = pinmux_generic_get_function_name, 1591 .get_function_groups = pinmux_generic_get_function_groups, 1592 .set_mux = rzg2l_pinctrl_set_mux, 1593 .strict = true, 1594 }; 1595 1596 static const struct pinconf_ops rzg2l_pinctrl_confops = { 1597 .is_generic = true, 1598 .pin_config_get = rzg2l_pinctrl_pinconf_get, 1599 .pin_config_set = rzg2l_pinctrl_pinconf_set, 1600 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set, 1601 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get, 1602 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1603 }; 1604 1605 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) 1606 { 1607 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1608 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1609 u64 *pin_data = pin_desc->drv_data; 1610 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1611 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 1612 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1613 unsigned long flags; 1614 u8 reg8; 1615 int ret; 1616 1617 ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit); 1618 if (ret) 1619 return ret; 1620 1621 ret = pinctrl_gpio_request(chip, offset); 1622 if (ret) 1623 return ret; 1624 1625 spin_lock_irqsave(&pctrl->lock, flags); 1626 1627 /* Select GPIO mode in PMC Register */ 1628 reg8 = readb(pctrl->base + PMC(off)); 1629 reg8 &= ~BIT(bit); 1630 pctrl->data->pmc_writeb(pctrl, reg8, PMC(off)); 1631 1632 spin_unlock_irqrestore(&pctrl->lock, flags); 1633 1634 return 0; 1635 } 1636 1637 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, 1638 bool output) 1639 { 1640 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1641 u64 *pin_data = pin_desc->drv_data; 1642 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1643 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1644 unsigned long flags; 1645 u16 reg16; 1646 1647 spin_lock_irqsave(&pctrl->lock, flags); 1648 1649 reg16 = readw(pctrl->base + PM(off)); 1650 reg16 &= ~(PM_MASK << (bit * 2)); 1651 1652 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); 1653 writew(reg16, pctrl->base + PM(off)); 1654 1655 spin_unlock_irqrestore(&pctrl->lock, flags); 1656 } 1657 1658 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1659 { 1660 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1661 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1662 u64 *pin_data = pin_desc->drv_data; 1663 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1664 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1665 1666 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { 1667 u16 reg16; 1668 1669 reg16 = readw(pctrl->base + PM(off)); 1670 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 1671 if (reg16 == PM_OUTPUT) 1672 return GPIO_LINE_DIRECTION_OUT; 1673 } 1674 1675 return GPIO_LINE_DIRECTION_IN; 1676 } 1677 1678 static int rzg2l_gpio_direction_input(struct gpio_chip *chip, 1679 unsigned int offset) 1680 { 1681 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1682 1683 rzg2l_gpio_set_direction(pctrl, offset, false); 1684 1685 return 0; 1686 } 1687 1688 static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, 1689 int value) 1690 { 1691 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1692 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1693 u64 *pin_data = pin_desc->drv_data; 1694 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1695 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1696 unsigned long flags; 1697 u8 reg8; 1698 1699 spin_lock_irqsave(&pctrl->lock, flags); 1700 1701 reg8 = readb(pctrl->base + P(off)); 1702 1703 if (value) 1704 writeb(reg8 | BIT(bit), pctrl->base + P(off)); 1705 else 1706 writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); 1707 1708 spin_unlock_irqrestore(&pctrl->lock, flags); 1709 } 1710 1711 static int rzg2l_gpio_direction_output(struct gpio_chip *chip, 1712 unsigned int offset, int value) 1713 { 1714 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1715 1716 rzg2l_gpio_set(chip, offset, value); 1717 rzg2l_gpio_set_direction(pctrl, offset, true); 1718 1719 return 0; 1720 } 1721 1722 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) 1723 { 1724 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1725 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1726 u64 *pin_data = pin_desc->drv_data; 1727 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1728 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1729 u16 reg16; 1730 1731 reg16 = readw(pctrl->base + PM(off)); 1732 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 1733 1734 if (reg16 == PM_INPUT) 1735 return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); 1736 else if (reg16 == PM_OUTPUT) 1737 return !!(readb(pctrl->base + P(off)) & BIT(bit)); 1738 else 1739 return -EINVAL; 1740 } 1741 1742 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) 1743 { 1744 unsigned int virq; 1745 1746 pinctrl_gpio_free(chip, offset); 1747 1748 virq = irq_find_mapping(chip->irq.domain, offset); 1749 if (virq) 1750 irq_dispose_mapping(virq); 1751 1752 /* 1753 * Set the GPIO as an input to ensure that the next GPIO request won't 1754 * drive the GPIO pin as an output. 1755 */ 1756 rzg2l_gpio_direction_input(chip, offset); 1757 } 1758 1759 static const char * const rzg2l_gpio_names[] = { 1760 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 1761 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 1762 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 1763 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 1764 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 1765 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 1766 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 1767 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 1768 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 1769 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 1770 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 1771 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 1772 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 1773 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 1774 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 1775 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 1776 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 1777 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 1778 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 1779 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 1780 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 1781 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 1782 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 1783 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 1784 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 1785 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 1786 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 1787 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 1788 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 1789 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 1790 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 1791 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 1792 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 1793 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 1794 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 1795 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 1796 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", 1797 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", 1798 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", 1799 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", 1800 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", 1801 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", 1802 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", 1803 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", 1804 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", 1805 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", 1806 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", 1807 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", 1808 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", 1809 }; 1810 1811 static const u64 r9a07g044_gpio_configs[] = { 1812 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), 1813 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), 1814 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), 1815 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), 1816 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), 1817 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), 1818 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), 1819 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), 1820 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), 1821 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), 1822 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), 1823 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1824 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1825 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1826 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1827 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1828 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1829 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), 1830 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), 1831 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), 1832 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), 1833 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1834 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1835 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1836 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1837 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1838 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1839 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1840 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1841 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), 1842 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1843 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1844 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1845 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1846 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1847 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1848 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1849 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1850 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), 1851 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), 1852 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), 1853 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), 1854 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), 1855 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), 1856 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), 1857 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), 1858 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), 1859 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), 1860 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), 1861 }; 1862 1863 static const u64 r9a07g043_gpio_configs[] = { 1864 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), 1865 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), 1866 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1867 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1868 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1869 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), 1870 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), 1871 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), 1872 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1873 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1874 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1875 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1876 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1877 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1878 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1879 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1880 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1881 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), 1882 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), 1883 #ifdef CONFIG_RISCV 1884 /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */ 1885 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 1886 PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | 1887 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */ 1888 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07), /* P20 */ 1889 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 1890 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */ 1891 RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 1892 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */ 1893 RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a), /* P23 */ 1894 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b), /* P24 */ 1895 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF | 1896 PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | 1897 PIN_CFG_NOGPIO_INT), /* P25 */ 1898 0x0, /* P26 */ 1899 0x0, /* P27 */ 1900 RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT), /* P28 */ 1901 #endif 1902 }; 1903 1904 static const u64 r9a08g045_gpio_configs[] = { 1905 RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ 1906 RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1907 PIN_CFG_IO_VMC_ETH0)) | 1908 PIN_CFG_OEN | PIN_CFG_IEN, /* P1 */ 1909 RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1910 PIN_CFG_IO_VMC_ETH0)), /* P2 */ 1911 RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1912 PIN_CFG_IO_VMC_ETH0)), /* P3 */ 1913 RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1914 PIN_CFG_IO_VMC_ETH0)), /* P4 */ 1915 RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */ 1916 RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */ 1917 RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1918 PIN_CFG_IO_VMC_ETH1)) | 1919 PIN_CFG_OEN | PIN_CFG_IEN, /* P7 */ 1920 RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1921 PIN_CFG_IO_VMC_ETH1)), /* P8 */ 1922 RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1923 PIN_CFG_IO_VMC_ETH1)), /* P9 */ 1924 RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1925 PIN_CFG_IO_VMC_ETH1)), /* P10 */ 1926 RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */ 1927 RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */ 1928 RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */ 1929 RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */ 1930 RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */ 1931 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */ 1932 RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */ 1933 RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */ 1934 }; 1935 1936 static const char * const rzv2h_gpio_names[] = { 1937 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", 1938 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", 1939 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", 1940 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", 1941 "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47", 1942 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", 1943 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", 1944 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", 1945 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", 1946 "P90", "P91", "P92", "P93", "P94", "P95", "P96", "P97", 1947 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", 1948 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", 1949 }; 1950 1951 static const u64 r9a09g057_gpio_configs[] = { 1952 RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */ 1953 RZG2L_GPIO_PORT_PACK(6, 0x21, RZV2H_MPXED_PIN_FUNCS), /* P1 */ 1954 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | 1955 PIN_CFG_NOD), /* P2 */ 1956 RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */ 1957 RZG2L_GPIO_PORT_PACK(8, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */ 1958 RZG2L_GPIO_PORT_PACK(8, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */ 1959 RZG2L_GPIO_PORT_PACK(8, 0x26, RZV2H_MPXED_PIN_FUNCS | 1960 PIN_CFG_ELC), /* P6 */ 1961 RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS), /* P7 */ 1962 RZG2L_GPIO_PORT_PACK(8, 0x28, RZV2H_MPXED_PIN_FUNCS | 1963 PIN_CFG_ELC), /* P8 */ 1964 RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS), /* P9 */ 1965 RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS), /* PA */ 1966 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x2b), /* PB */ 1967 }; 1968 1969 static const struct { 1970 struct rzg2l_dedicated_configs common[35]; 1971 struct rzg2l_dedicated_configs rzg2l_pins[7]; 1972 } rzg2l_dedicated_pins = { 1973 .common = { 1974 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, 1975 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, 1976 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, 1977 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1978 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, 1979 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1980 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, 1981 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, 1982 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, 1983 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1984 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 1985 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1986 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, 1987 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1988 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, 1989 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1990 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, 1991 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1992 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, 1993 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1994 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, 1995 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1996 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, 1997 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1998 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, 1999 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2000 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, 2001 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2002 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, 2003 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2004 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, 2005 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, 2006 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, 2007 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2008 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, 2009 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2010 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, 2011 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2012 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, 2013 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2014 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, 2015 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2016 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, 2017 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2018 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, 2019 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2020 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, 2021 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2022 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, 2023 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2024 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, 2025 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2026 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, 2027 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2028 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, 2029 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2030 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, 2031 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2032 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, 2033 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, 2034 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, 2035 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, 2036 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, 2037 }, 2038 .rzg2l_pins = { 2039 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2040 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, 2041 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2042 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, 2043 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2044 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, 2045 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2046 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, 2047 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2048 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, 2049 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2050 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, 2051 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2052 } 2053 }; 2054 2055 static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { 2056 { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | 2057 PIN_CFG_FILCLKSEL)) }, 2058 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN | 2059 PIN_CFG_SOFT_PS)) }, 2060 { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) }, 2061 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) }, 2062 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, 2063 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2064 PIN_CFG_IO_VMC_SD0)) }, 2065 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, 2066 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2067 PIN_CFG_IO_VMC_SD0)) }, 2068 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2069 PIN_CFG_IO_VMC_SD0)) }, 2070 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2071 PIN_CFG_IO_VMC_SD0)) }, 2072 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2073 PIN_CFG_IO_VMC_SD0)) }, 2074 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2075 PIN_CFG_IO_VMC_SD0)) }, 2076 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2077 PIN_CFG_IO_VMC_SD0)) }, 2078 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2079 PIN_CFG_IO_VMC_SD0)) }, 2080 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2081 PIN_CFG_IO_VMC_SD0)) }, 2082 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) }, 2083 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2084 PIN_CFG_IO_VMC_SD1)) }, 2085 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2086 PIN_CFG_IO_VMC_SD1)) }, 2087 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2088 PIN_CFG_IO_VMC_SD1)) }, 2089 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2090 PIN_CFG_IO_VMC_SD1)) }, 2091 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2092 PIN_CFG_IO_VMC_SD1)) }, 2093 }; 2094 2095 static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = { 2096 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | 2097 PIN_CFG_FILCLKSEL)) }, 2098 { "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2099 PIN_CFG_IEN)) }, 2100 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2101 { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2102 PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2103 { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2104 PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2105 { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2106 PIN_CFG_PUPD)) }, 2107 { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2108 PIN_CFG_PUPD)) }, 2109 { "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2110 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2111 { "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2112 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2113 { "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2114 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2115 { "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2116 PIN_CFG_PUPD)) }, 2117 { "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2118 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2119 { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) }, 2120 { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) }, 2121 { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) }, 2122 { "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2123 PIN_CFG_PUPD)) }, 2124 { "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2125 PIN_CFG_PUPD)) }, 2126 { "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2127 PIN_CFG_PUPD)) }, 2128 { "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2129 PIN_CFG_PUPD)) }, 2130 { "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2131 PIN_CFG_PUPD)) }, 2132 { "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2133 PIN_CFG_PUPD)) }, 2134 { "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2135 PIN_CFG_PUPD)) }, 2136 { "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2137 PIN_CFG_PUPD)) }, 2138 { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2139 { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2140 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2141 { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2142 { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2143 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2144 { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2145 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2146 { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2147 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2148 { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2149 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2150 { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2151 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2152 { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2153 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2154 { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2155 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2156 { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2157 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2158 { "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2159 { "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2160 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2161 { "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2162 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2163 { "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2164 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2165 { "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2166 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2167 { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2168 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2169 { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2170 { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2171 { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2172 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2173 { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2174 PIN_CFG_PUPD)) }, 2175 { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) }, 2176 { "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2177 PIN_CFG_PUPD)) }, 2178 { "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2179 PIN_CFG_PUPD)) }, 2180 { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) }, 2181 { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) }, 2182 { "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2183 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2184 { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) }, 2185 { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) }, 2186 { "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2187 PIN_CFG_PUPD)) }, 2188 { "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2189 PIN_CFG_PUPD)) }, 2190 { "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2191 PIN_CFG_PUPD)) }, 2192 { "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2193 PIN_CFG_PUPD)) }, 2194 { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) }, 2195 { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) }, 2196 { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) }, 2197 { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) }, 2198 { "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2199 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2200 { "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2201 PIN_CFG_PUPD)) }, 2202 { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) }, 2203 { "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2204 PIN_CFG_PUPD)) }, 2205 { "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2206 PIN_CFG_PUPD)) }, 2207 { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) }, 2208 { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) }, 2209 { "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2210 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2211 { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) }, 2212 { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) }, 2213 { "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2214 PIN_CFG_PUPD)) }, 2215 { "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2216 PIN_CFG_PUPD)) }, 2217 { "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2218 PIN_CFG_PUPD)) }, 2219 { "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2220 PIN_CFG_PUPD)) }, 2221 { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) }, 2222 { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) }, 2223 { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) }, 2224 { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) }, 2225 }; 2226 2227 static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) 2228 { 2229 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; 2230 const struct rzg2l_pinctrl_data *data = pctrl->data; 2231 u64 *pin_data = pin_desc->drv_data; 2232 unsigned int gpioint; 2233 unsigned int i; 2234 u32 port, bit; 2235 2236 if (*pin_data & PIN_CFG_NOGPIO_INT) 2237 return -EINVAL; 2238 2239 port = virq / 8; 2240 bit = virq % 8; 2241 2242 if (port >= data->n_ports || 2243 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port]))) 2244 return -EINVAL; 2245 2246 gpioint = bit; 2247 for (i = 0; i < port; i++) 2248 gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i])); 2249 2250 return gpioint; 2251 } 2252 2253 static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, 2254 unsigned int hwirq, bool enable) 2255 { 2256 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; 2257 u64 *pin_data = pin_desc->drv_data; 2258 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 2259 u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 2260 unsigned long flags; 2261 void __iomem *addr; 2262 2263 addr = pctrl->base + ISEL(off); 2264 if (bit >= 4) { 2265 bit -= 4; 2266 addr += 4; 2267 } 2268 2269 spin_lock_irqsave(&pctrl->lock, flags); 2270 if (enable) 2271 writel(readl(addr) | BIT(bit * 8), addr); 2272 else 2273 writel(readl(addr) & ~BIT(bit * 8), addr); 2274 spin_unlock_irqrestore(&pctrl->lock, flags); 2275 } 2276 2277 static void rzg2l_gpio_irq_disable(struct irq_data *d) 2278 { 2279 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 2280 unsigned int hwirq = irqd_to_hwirq(d); 2281 2282 irq_chip_disable_parent(d); 2283 gpiochip_disable_irq(gc, hwirq); 2284 } 2285 2286 static void rzg2l_gpio_irq_enable(struct irq_data *d) 2287 { 2288 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 2289 unsigned int hwirq = irqd_to_hwirq(d); 2290 2291 gpiochip_enable_irq(gc, hwirq); 2292 irq_chip_enable_parent(d); 2293 } 2294 2295 static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) 2296 { 2297 return irq_chip_set_type_parent(d, type); 2298 } 2299 2300 static void rzg2l_gpio_irqc_eoi(struct irq_data *d) 2301 { 2302 irq_chip_eoi_parent(d); 2303 } 2304 2305 static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) 2306 { 2307 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 2308 2309 seq_printf(p, dev_name(gc->parent)); 2310 } 2311 2312 static int rzg2l_gpio_irq_set_wake(struct irq_data *data, unsigned int on) 2313 { 2314 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 2315 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 2316 int ret; 2317 2318 /* It should not happen. */ 2319 if (!data->parent_data) 2320 return -EOPNOTSUPP; 2321 2322 ret = irq_chip_set_wake_parent(data, on); 2323 if (ret) 2324 return ret; 2325 2326 if (on) 2327 atomic_inc(&pctrl->wakeup_path); 2328 else 2329 atomic_dec(&pctrl->wakeup_path); 2330 2331 return 0; 2332 } 2333 2334 static const struct irq_chip rzg2l_gpio_irqchip = { 2335 .name = "rzg2l-gpio", 2336 .irq_disable = rzg2l_gpio_irq_disable, 2337 .irq_enable = rzg2l_gpio_irq_enable, 2338 .irq_mask = irq_chip_mask_parent, 2339 .irq_unmask = irq_chip_unmask_parent, 2340 .irq_set_type = rzg2l_gpio_irq_set_type, 2341 .irq_eoi = rzg2l_gpio_irqc_eoi, 2342 .irq_print_chip = rzg2l_gpio_irq_print_chip, 2343 .irq_set_affinity = irq_chip_set_affinity_parent, 2344 .irq_set_wake = rzg2l_gpio_irq_set_wake, 2345 .flags = IRQCHIP_IMMUTABLE, 2346 GPIOCHIP_IRQ_RESOURCE_HELPERS, 2347 }; 2348 2349 static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigned int offset) 2350 { 2351 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 2352 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 2353 u64 *pin_data = pin_desc->drv_data; 2354 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 2355 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 2356 u8 reg8; 2357 int ret; 2358 2359 reg8 = readb(pctrl->base + PMC(off)); 2360 if (reg8 & BIT(bit)) { 2361 ret = rzg2l_gpio_request(chip, offset); 2362 if (ret) 2363 return ret; 2364 } 2365 2366 return rzg2l_gpio_direction_input(chip, offset); 2367 } 2368 2369 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 2370 unsigned int child, 2371 unsigned int child_type, 2372 unsigned int *parent, 2373 unsigned int *parent_type) 2374 { 2375 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 2376 unsigned long flags; 2377 int gpioint, irq; 2378 int ret; 2379 2380 gpioint = rzg2l_gpio_get_gpioint(child, pctrl); 2381 if (gpioint < 0) 2382 return gpioint; 2383 2384 ret = rzg2l_gpio_interrupt_input_mode(gc, child); 2385 if (ret) 2386 return ret; 2387 2388 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 2389 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); 2390 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 2391 if (irq < 0) { 2392 ret = -ENOSPC; 2393 goto err; 2394 } 2395 2396 rzg2l_gpio_irq_endisable(pctrl, child, true); 2397 pctrl->hwirq[irq] = child; 2398 irq += RZG2L_TINT_IRQ_START_INDEX; 2399 2400 /* All these interrupts are level high in the CPU */ 2401 *parent_type = IRQ_TYPE_LEVEL_HIGH; 2402 *parent = RZG2L_PACK_HWIRQ(gpioint, irq); 2403 return 0; 2404 2405 err: 2406 rzg2l_gpio_free(gc, child); 2407 return ret; 2408 } 2409 2410 static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, 2411 union gpio_irq_fwspec *gfwspec, 2412 unsigned int parent_hwirq, 2413 unsigned int parent_type) 2414 { 2415 struct irq_fwspec *fwspec = &gfwspec->fwspec; 2416 2417 fwspec->fwnode = chip->irq.parent_domain->fwnode; 2418 fwspec->param_count = 2; 2419 fwspec->param[0] = parent_hwirq; 2420 fwspec->param[1] = parent_type; 2421 2422 return 0; 2423 } 2424 2425 static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) 2426 { 2427 struct irq_domain *domain = pctrl->gpio_chip.irq.domain; 2428 2429 for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 2430 struct irq_data *data; 2431 unsigned long flags; 2432 unsigned int virq; 2433 int ret; 2434 2435 if (!pctrl->hwirq[i]) 2436 continue; 2437 2438 virq = irq_find_mapping(domain, pctrl->hwirq[i]); 2439 if (!virq) { 2440 dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n", 2441 pctrl->hwirq[i]); 2442 continue; 2443 } 2444 2445 data = irq_domain_get_irq_data(domain, virq); 2446 if (!data) { 2447 dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq); 2448 continue; 2449 } 2450 2451 /* 2452 * This has to be atomically executed to protect against a concurrent 2453 * interrupt. 2454 */ 2455 spin_lock_irqsave(&pctrl->lock, flags); 2456 ret = rzg2l_gpio_irq_set_type(data, irqd_get_trigger_type(data)); 2457 if (!ret && !irqd_irq_disabled(data)) 2458 rzg2l_gpio_irq_enable(data); 2459 spin_unlock_irqrestore(&pctrl->lock, flags); 2460 2461 if (ret) 2462 dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq); 2463 } 2464 } 2465 2466 static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, 2467 unsigned int nr_irqs) 2468 { 2469 struct irq_data *d; 2470 2471 d = irq_domain_get_irq_data(domain, virq); 2472 if (d) { 2473 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 2474 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 2475 irq_hw_number_t hwirq = irqd_to_hwirq(d); 2476 unsigned long flags; 2477 unsigned int i; 2478 2479 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 2480 if (pctrl->hwirq[i] == hwirq) { 2481 rzg2l_gpio_irq_endisable(pctrl, hwirq, false); 2482 rzg2l_gpio_free(gc, hwirq); 2483 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 2484 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); 2485 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 2486 pctrl->hwirq[i] = 0; 2487 break; 2488 } 2489 } 2490 } 2491 irq_domain_free_irqs_common(domain, virq, nr_irqs); 2492 } 2493 2494 static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, 2495 unsigned long *valid_mask, 2496 unsigned int ngpios) 2497 { 2498 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 2499 struct gpio_chip *chip = &pctrl->gpio_chip; 2500 unsigned int offset; 2501 2502 /* Forbid unused lines to be mapped as IRQs */ 2503 for (offset = 0; offset < chip->ngpio; offset++) { 2504 u32 port, bit; 2505 2506 port = offset / 8; 2507 bit = offset % 8; 2508 2509 if (port >= pctrl->data->n_ports || 2510 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, 2511 pctrl->data->port_pin_configs[port]))) 2512 clear_bit(offset, valid_mask); 2513 } 2514 } 2515 2516 static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) 2517 { 2518 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 2519 struct rzg2l_pinctrl_reg_cache *cache, *dedicated_cache; 2520 2521 cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL); 2522 if (!cache) 2523 return -ENOMEM; 2524 2525 dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL); 2526 if (!dedicated_cache) 2527 return -ENOMEM; 2528 2529 cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL); 2530 if (!cache->p) 2531 return -ENOMEM; 2532 2533 cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL); 2534 if (!cache->pm) 2535 return -ENOMEM; 2536 2537 cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL); 2538 if (!cache->pmc) 2539 return -ENOMEM; 2540 2541 cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL); 2542 if (!cache->pfc) 2543 return -ENOMEM; 2544 2545 for (u8 i = 0; i < 2; i++) { 2546 u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; 2547 2548 cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]), 2549 GFP_KERNEL); 2550 if (!cache->iolh[i]) 2551 return -ENOMEM; 2552 2553 cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]), 2554 GFP_KERNEL); 2555 if (!cache->ien[i]) 2556 return -ENOMEM; 2557 2558 /* Allocate dedicated cache. */ 2559 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, 2560 sizeof(*dedicated_cache->iolh[i]), 2561 GFP_KERNEL); 2562 if (!dedicated_cache->iolh[i]) 2563 return -ENOMEM; 2564 2565 dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, 2566 sizeof(*dedicated_cache->ien[i]), 2567 GFP_KERNEL); 2568 if (!dedicated_cache->ien[i]) 2569 return -ENOMEM; 2570 } 2571 2572 pctrl->cache = cache; 2573 pctrl->dedicated_cache = dedicated_cache; 2574 2575 return 0; 2576 } 2577 2578 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) 2579 { 2580 struct device_node *np = pctrl->dev->of_node; 2581 struct gpio_chip *chip = &pctrl->gpio_chip; 2582 const char *name = dev_name(pctrl->dev); 2583 struct irq_domain *parent_domain; 2584 struct of_phandle_args of_args; 2585 struct device_node *parent_np; 2586 struct gpio_irq_chip *girq; 2587 int ret; 2588 2589 parent_np = of_irq_find_parent(np); 2590 if (!parent_np) 2591 return -ENXIO; 2592 2593 parent_domain = irq_find_host(parent_np); 2594 of_node_put(parent_np); 2595 if (!parent_domain) 2596 return -EPROBE_DEFER; 2597 2598 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); 2599 if (ret) { 2600 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); 2601 return ret; 2602 } 2603 2604 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 2605 of_args.args[2] != pctrl->data->n_port_pins) { 2606 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); 2607 return -EINVAL; 2608 } 2609 2610 chip->names = pctrl->data->port_pins; 2611 chip->request = rzg2l_gpio_request; 2612 chip->free = rzg2l_gpio_free; 2613 chip->get_direction = rzg2l_gpio_get_direction; 2614 chip->direction_input = rzg2l_gpio_direction_input; 2615 chip->direction_output = rzg2l_gpio_direction_output; 2616 chip->get = rzg2l_gpio_get; 2617 chip->set = rzg2l_gpio_set; 2618 chip->label = name; 2619 chip->parent = pctrl->dev; 2620 chip->owner = THIS_MODULE; 2621 chip->base = -1; 2622 chip->ngpio = of_args.args[2]; 2623 2624 girq = &chip->irq; 2625 gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip); 2626 girq->fwnode = of_node_to_fwnode(np); 2627 girq->parent_domain = parent_domain; 2628 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; 2629 girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec; 2630 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; 2631 girq->init_valid_mask = rzg2l_init_irq_valid_mask; 2632 2633 pctrl->gpio_range.id = 0; 2634 pctrl->gpio_range.pin_base = 0; 2635 pctrl->gpio_range.base = 0; 2636 pctrl->gpio_range.npins = chip->ngpio; 2637 pctrl->gpio_range.name = chip->label; 2638 pctrl->gpio_range.gc = chip; 2639 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 2640 if (ret) { 2641 dev_err(pctrl->dev, "failed to add GPIO controller\n"); 2642 return ret; 2643 } 2644 2645 dev_dbg(pctrl->dev, "Registered gpio controller\n"); 2646 2647 return 0; 2648 } 2649 2650 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) 2651 { 2652 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 2653 struct pinctrl_pin_desc *pins; 2654 unsigned int i, j; 2655 u64 *pin_data; 2656 int ret; 2657 2658 pctrl->desc.name = DRV_NAME; 2659 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; 2660 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; 2661 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; 2662 pctrl->desc.confops = &rzg2l_pinctrl_confops; 2663 pctrl->desc.owner = THIS_MODULE; 2664 if (pctrl->data->num_custom_params) { 2665 pctrl->desc.num_custom_params = pctrl->data->num_custom_params; 2666 pctrl->desc.custom_params = pctrl->data->custom_params; 2667 #ifdef CONFIG_DEBUG_FS 2668 pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items; 2669 #endif 2670 } 2671 2672 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); 2673 if (!pins) 2674 return -ENOMEM; 2675 2676 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, 2677 sizeof(*pin_data), GFP_KERNEL); 2678 if (!pin_data) 2679 return -ENOMEM; 2680 2681 pctrl->pins = pins; 2682 pctrl->desc.pins = pins; 2683 2684 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 2685 pins[i].number = i; 2686 pins[i].name = pctrl->data->port_pins[i]; 2687 if (i && !(i % RZG2L_PINS_PER_PORT)) 2688 j++; 2689 pin_data[i] = pctrl->data->port_pin_configs[j]; 2690 if (pin_data[i] & RZG2L_VARIABLE_CFG) 2691 pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, 2692 pin_data[i], 2693 j, 2694 i % RZG2L_PINS_PER_PORT); 2695 pins[i].drv_data = &pin_data[i]; 2696 } 2697 2698 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { 2699 unsigned int index = pctrl->data->n_port_pins + i; 2700 2701 pins[index].number = index; 2702 pins[index].name = pctrl->data->dedicated_pins[i].name; 2703 pin_data[index] = pctrl->data->dedicated_pins[i].config; 2704 pins[index].drv_data = &pin_data[index]; 2705 } 2706 2707 pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), 2708 GFP_KERNEL); 2709 if (!pctrl->settings) 2710 return -ENOMEM; 2711 2712 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { 2713 if (pin_data[i] & PIN_CFG_SOFT_PS) { 2714 pctrl->settings[i].power_source = 3300; 2715 } else { 2716 ret = rzg2l_get_power_source(pctrl, i, pin_data[i]); 2717 if (ret < 0) 2718 continue; 2719 pctrl->settings[i].power_source = ret; 2720 } 2721 } 2722 2723 ret = rzg2l_pinctrl_reg_cache_alloc(pctrl); 2724 if (ret) 2725 return ret; 2726 2727 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, 2728 &pctrl->pctl); 2729 if (ret) { 2730 dev_err(pctrl->dev, "pinctrl registration failed\n"); 2731 return ret; 2732 } 2733 2734 ret = pinctrl_enable(pctrl->pctl); 2735 if (ret) { 2736 dev_err(pctrl->dev, "pinctrl enable failed\n"); 2737 return ret; 2738 } 2739 2740 ret = rzg2l_gpio_register(pctrl); 2741 if (ret) { 2742 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); 2743 return ret; 2744 } 2745 2746 return 0; 2747 } 2748 2749 static int rzg2l_pinctrl_probe(struct platform_device *pdev) 2750 { 2751 struct rzg2l_pinctrl *pctrl; 2752 int ret; 2753 2754 BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT > 2755 ARRAY_SIZE(rzg2l_gpio_names)); 2756 2757 BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > 2758 ARRAY_SIZE(rzg2l_gpio_names)); 2759 2760 BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > 2761 ARRAY_SIZE(rzg2l_gpio_names)); 2762 2763 BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT > 2764 ARRAY_SIZE(rzv2h_gpio_names)); 2765 2766 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 2767 if (!pctrl) 2768 return -ENOMEM; 2769 2770 pctrl->dev = &pdev->dev; 2771 2772 pctrl->data = of_device_get_match_data(&pdev->dev); 2773 if (!pctrl->data) 2774 return -EINVAL; 2775 2776 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 2777 if (IS_ERR(pctrl->base)) 2778 return PTR_ERR(pctrl->base); 2779 2780 pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL); 2781 if (IS_ERR(pctrl->clk)) { 2782 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk), 2783 "failed to enable GPIO clk\n"); 2784 } 2785 2786 spin_lock_init(&pctrl->lock); 2787 spin_lock_init(&pctrl->bitmap_lock); 2788 mutex_init(&pctrl->mutex); 2789 atomic_set(&pctrl->wakeup_path, 0); 2790 2791 platform_set_drvdata(pdev, pctrl); 2792 2793 ret = rzg2l_pinctrl_register(pctrl); 2794 if (ret) 2795 return ret; 2796 2797 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); 2798 return 0; 2799 } 2800 2801 static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend) 2802 { 2803 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 2804 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 2805 2806 for (u32 port = 0; port < nports; port++) { 2807 bool has_iolh, has_ien; 2808 u32 off, caps; 2809 u8 pincnt; 2810 u64 cfg; 2811 2812 cfg = pctrl->data->port_pin_configs[port]; 2813 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 2814 pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg)); 2815 2816 caps = FIELD_GET(PIN_CFG_MASK, cfg); 2817 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); 2818 has_ien = !!(caps & PIN_CFG_IEN); 2819 2820 if (suspend) 2821 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); 2822 2823 /* 2824 * Now cache the registers or set them in the order suggested by 2825 * HW manual (section "Operation for GPIO Function"). 2826 */ 2827 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); 2828 if (has_iolh) { 2829 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), 2830 cache->iolh[0][port]); 2831 if (pincnt >= 4) { 2832 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4, 2833 cache->iolh[1][port]); 2834 } 2835 } 2836 2837 RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]); 2838 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]); 2839 2840 if (has_ien) { 2841 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), 2842 cache->ien[0][port]); 2843 if (pincnt >= 4) { 2844 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4, 2845 cache->ien[1][port]); 2846 } 2847 } 2848 } 2849 } 2850 2851 static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) 2852 { 2853 struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; 2854 u32 caps; 2855 u32 i; 2856 2857 /* 2858 * Make sure entries in pctrl->data->n_dedicated_pins[] having the same 2859 * port offset are close together. 2860 */ 2861 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { 2862 bool has_iolh, has_ien; 2863 u32 off, next_off = 0; 2864 u64 cfg, next_cfg; 2865 u8 pincnt; 2866 2867 cfg = pctrl->data->dedicated_pins[i].config; 2868 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 2869 if (i + 1 < pctrl->data->n_dedicated_pins) { 2870 next_cfg = pctrl->data->dedicated_pins[i + 1].config; 2871 next_off = RZG2L_PIN_CFG_TO_PORT_OFFSET(next_cfg); 2872 } 2873 2874 if (off == next_off) { 2875 /* Gather caps of all port pins. */ 2876 caps |= FIELD_GET(PIN_CFG_MASK, cfg); 2877 continue; 2878 } 2879 2880 /* And apply them in a single shot. */ 2881 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); 2882 has_ien = !!(caps & PIN_CFG_IEN); 2883 pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg)); 2884 2885 if (has_iolh) { 2886 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), 2887 cache->iolh[0][i]); 2888 } 2889 if (has_ien) { 2890 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), 2891 cache->ien[0][i]); 2892 } 2893 2894 if (pincnt >= 4) { 2895 if (has_iolh) { 2896 RZG2L_PCTRL_REG_ACCESS32(suspend, 2897 pctrl->base + IOLH(off) + 4, 2898 cache->iolh[1][i]); 2899 } 2900 if (has_ien) { 2901 RZG2L_PCTRL_REG_ACCESS32(suspend, 2902 pctrl->base + IEN(off) + 4, 2903 cache->ien[1][i]); 2904 } 2905 } 2906 caps = 0; 2907 } 2908 } 2909 2910 static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) 2911 { 2912 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 2913 unsigned long flags; 2914 2915 spin_lock_irqsave(&pctrl->lock, flags); 2916 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); 2917 2918 /* Restore port registers. */ 2919 for (u32 port = 0; port < nports; port++) { 2920 unsigned long pinmap; 2921 u8 pmc = 0, max_pin; 2922 u32 off, pfc = 0; 2923 u64 cfg; 2924 u16 pm; 2925 u8 pin; 2926 2927 cfg = pctrl->data->port_pin_configs[port]; 2928 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 2929 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); 2930 max_pin = fls(pinmap); 2931 2932 pm = readw(pctrl->base + PM(off)); 2933 for_each_set_bit(pin, &pinmap, max_pin) { 2934 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 2935 2936 /* Nothing to do if PFC was not configured before. */ 2937 if (!(cache->pmc[port] & BIT(pin))) 2938 continue; 2939 2940 /* Set pin to 'Non-use (Hi-Z input protection)' */ 2941 pm &= ~(PM_MASK << (pin * 2)); 2942 writew(pm, pctrl->base + PM(off)); 2943 2944 /* Temporarily switch to GPIO mode with PMC register */ 2945 pmc &= ~BIT(pin); 2946 writeb(pmc, pctrl->base + PMC(off)); 2947 2948 /* Select Pin function mode. */ 2949 pfc &= ~(PFC_MASK << (pin * 4)); 2950 pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4))); 2951 writel(pfc, pctrl->base + PFC(off)); 2952 2953 /* Switch to Peripheral pin function. */ 2954 pmc |= BIT(pin); 2955 writeb(pmc, pctrl->base + PMC(off)); 2956 } 2957 } 2958 2959 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); 2960 spin_unlock_irqrestore(&pctrl->lock, flags); 2961 } 2962 2963 static int rzg2l_pinctrl_suspend_noirq(struct device *dev) 2964 { 2965 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); 2966 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 2967 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 2968 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 2969 2970 rzg2l_pinctrl_pm_setup_regs(pctrl, true); 2971 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true); 2972 2973 for (u8 i = 0; i < 2; i++) { 2974 if (regs->sd_ch) 2975 cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); 2976 if (regs->eth_poc) 2977 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); 2978 } 2979 2980 cache->qspi = readb(pctrl->base + QSPI); 2981 cache->eth_mode = readb(pctrl->base + ETH_MODE); 2982 2983 if (!atomic_read(&pctrl->wakeup_path)) 2984 clk_disable_unprepare(pctrl->clk); 2985 else 2986 device_set_wakeup_path(dev); 2987 2988 return 0; 2989 } 2990 2991 static int rzg2l_pinctrl_resume_noirq(struct device *dev) 2992 { 2993 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); 2994 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 2995 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 2996 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 2997 int ret; 2998 2999 if (!atomic_read(&pctrl->wakeup_path)) { 3000 ret = clk_prepare_enable(pctrl->clk); 3001 if (ret) 3002 return ret; 3003 } 3004 3005 writeb(cache->qspi, pctrl->base + QSPI); 3006 writeb(cache->eth_mode, pctrl->base + ETH_MODE); 3007 for (u8 i = 0; i < 2; i++) { 3008 if (regs->sd_ch) 3009 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); 3010 if (regs->eth_poc) 3011 writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); 3012 } 3013 3014 rzg2l_pinctrl_pm_setup_pfc(pctrl); 3015 rzg2l_pinctrl_pm_setup_regs(pctrl, false); 3016 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false); 3017 rzg2l_gpio_irq_restore(pctrl); 3018 3019 return 0; 3020 } 3021 3022 static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) 3023 { 3024 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 3025 3026 if (lock) { 3027 /* Set the PWPR register to be write-protected */ 3028 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 3029 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ 3030 } else { 3031 /* Set the PWPR register to allow PFC register to write */ 3032 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 3033 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ 3034 } 3035 } 3036 3037 static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) 3038 { 3039 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 3040 u8 pwpr; 3041 3042 if (lock) { 3043 /* Set the PWPR register to be write-protected */ 3044 pwpr = readb(pctrl->base + regs->pwpr); 3045 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); 3046 } else { 3047 /* Set the PWPR register to allow PFC and PMC register to write */ 3048 pwpr = readb(pctrl->base + regs->pwpr); 3049 writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr); 3050 } 3051 } 3052 3053 static const struct rzg2l_hwcfg rzg2l_hwcfg = { 3054 .regs = { 3055 .pwpr = 0x3014, 3056 .sd_ch = 0x3000, 3057 .eth_poc = 0x300c, 3058 }, 3059 .iolh_groupa_ua = { 3060 /* 3v3 power source */ 3061 [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000, 3062 }, 3063 .iolh_groupb_oi = { 100, 66, 50, 33, }, 3064 .oen_max_pin = 0, 3065 }; 3066 3067 static const struct rzg2l_hwcfg rzg3s_hwcfg = { 3068 .regs = { 3069 .pwpr = 0x3000, 3070 .sd_ch = 0x3004, 3071 .eth_poc = 0x3010, 3072 }, 3073 .iolh_groupa_ua = { 3074 /* 1v8 power source */ 3075 [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000, 3076 /* 3v3 power source */ 3077 [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000, 3078 }, 3079 .iolh_groupb_ua = { 3080 /* 1v8 power source */ 3081 [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000, 3082 /* 3v3 power source */ 3083 [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000, 3084 }, 3085 .iolh_groupc_ua = { 3086 /* 1v8 power source */ 3087 [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800, 3088 /* 2v5 source */ 3089 [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100, 3090 /* 3v3 power source */ 3091 [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050, 3092 }, 3093 .drive_strength_ua = true, 3094 .func_base = 1, 3095 .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */ 3096 .oen_max_port = 7, /* P7_1 is the maximum OEN port. */ 3097 }; 3098 3099 static const struct rzg2l_hwcfg rzv2h_hwcfg = { 3100 .regs = { 3101 .pwpr = 0x3c04, 3102 }, 3103 }; 3104 3105 static struct rzg2l_pinctrl_data r9a07g043_data = { 3106 .port_pins = rzg2l_gpio_names, 3107 .port_pin_configs = r9a07g043_gpio_configs, 3108 .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs), 3109 .dedicated_pins = rzg2l_dedicated_pins.common, 3110 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, 3111 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), 3112 .hwcfg = &rzg2l_hwcfg, 3113 #ifdef CONFIG_RISCV 3114 .variable_pin_cfg = r9a07g043f_variable_pin_cfg, 3115 .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg), 3116 #endif 3117 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3118 .pmc_writeb = &rzg2l_pmc_writeb, 3119 .oen_read = &rzg2l_read_oen, 3120 .oen_write = &rzg2l_write_oen, 3121 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3122 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3123 }; 3124 3125 static struct rzg2l_pinctrl_data r9a07g044_data = { 3126 .port_pins = rzg2l_gpio_names, 3127 .port_pin_configs = r9a07g044_gpio_configs, 3128 .n_ports = ARRAY_SIZE(r9a07g044_gpio_configs), 3129 .dedicated_pins = rzg2l_dedicated_pins.common, 3130 .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT, 3131 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + 3132 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), 3133 .hwcfg = &rzg2l_hwcfg, 3134 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3135 .pmc_writeb = &rzg2l_pmc_writeb, 3136 .oen_read = &rzg2l_read_oen, 3137 .oen_write = &rzg2l_write_oen, 3138 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3139 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3140 }; 3141 3142 static struct rzg2l_pinctrl_data r9a08g045_data = { 3143 .port_pins = rzg2l_gpio_names, 3144 .port_pin_configs = r9a08g045_gpio_configs, 3145 .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs), 3146 .dedicated_pins = rzg3s_dedicated_pins, 3147 .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT, 3148 .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins), 3149 .hwcfg = &rzg3s_hwcfg, 3150 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3151 .pmc_writeb = &rzg2l_pmc_writeb, 3152 .oen_read = &rzg3s_oen_read, 3153 .oen_write = &rzg3s_oen_write, 3154 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3155 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3156 }; 3157 3158 static struct rzg2l_pinctrl_data r9a09g057_data = { 3159 .port_pins = rzv2h_gpio_names, 3160 .port_pin_configs = r9a09g057_gpio_configs, 3161 .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs), 3162 .dedicated_pins = rzv2h_dedicated_pins, 3163 .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT, 3164 .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins), 3165 .hwcfg = &rzv2h_hwcfg, 3166 .variable_pin_cfg = r9a09g057_variable_pin_cfg, 3167 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg), 3168 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), 3169 .custom_params = renesas_rzv2h_custom_bindings, 3170 #ifdef CONFIG_DEBUG_FS 3171 .custom_conf_items = renesas_rzv2h_conf_items, 3172 #endif 3173 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, 3174 .pmc_writeb = &rzv2h_pmc_writeb, 3175 .oen_read = &rzv2h_oen_read, 3176 .oen_write = &rzv2h_oen_write, 3177 .hw_to_bias_param = &rzv2h_hw_to_bias_param, 3178 .bias_param_to_hw = &rzv2h_bias_param_to_hw, 3179 }; 3180 3181 static const struct of_device_id rzg2l_pinctrl_of_table[] = { 3182 { 3183 .compatible = "renesas,r9a07g043-pinctrl", 3184 .data = &r9a07g043_data, 3185 }, 3186 { 3187 .compatible = "renesas,r9a07g044-pinctrl", 3188 .data = &r9a07g044_data, 3189 }, 3190 { 3191 .compatible = "renesas,r9a08g045-pinctrl", 3192 .data = &r9a08g045_data, 3193 }, 3194 { 3195 .compatible = "renesas,r9a09g057-pinctrl", 3196 .data = &r9a09g057_data, 3197 }, 3198 { /* sentinel */ } 3199 }; 3200 3201 static const struct dev_pm_ops rzg2l_pinctrl_pm_ops = { 3202 NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg2l_pinctrl_suspend_noirq, rzg2l_pinctrl_resume_noirq) 3203 }; 3204 3205 static struct platform_driver rzg2l_pinctrl_driver = { 3206 .driver = { 3207 .name = DRV_NAME, 3208 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), 3209 .pm = pm_sleep_ptr(&rzg2l_pinctrl_pm_ops), 3210 }, 3211 .probe = rzg2l_pinctrl_probe, 3212 }; 3213 3214 static int __init rzg2l_pinctrl_init(void) 3215 { 3216 return platform_driver_register(&rzg2l_pinctrl_driver); 3217 } 3218 core_initcall(rzg2l_pinctrl_init); 3219 3220 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 3221 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); 3222