1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G2L Pin Control and GPIO driver core 4 * 5 * Copyright (C) 2021 Renesas Electronics Corporation. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of.h> 17 #include <linux/of_irq.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/seq_file.h> 21 #include <linux/spinlock.h> 22 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinctrl.h> 27 #include <linux/pinctrl/pinmux.h> 28 29 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 30 31 #include "../core.h" 32 #include "../pinconf.h" 33 #include "../pinmux.h" 34 35 #define DRV_NAME "pinctrl-rzg2l" 36 37 /* 38 * Use 16 lower bits [15:0] for pin identifier 39 * Use 16 higher bits [31:16] for pin mux function 40 */ 41 #define MUX_PIN_ID_MASK GENMASK(15, 0) 42 #define MUX_FUNC_MASK GENMASK(31, 16) 43 44 /* PIN capabilities */ 45 #define PIN_CFG_IOLH_A BIT(0) 46 #define PIN_CFG_IOLH_B BIT(1) 47 #define PIN_CFG_SR BIT(2) 48 #define PIN_CFG_IEN BIT(3) 49 #define PIN_CFG_PUPD BIT(4) 50 #define PIN_CFG_IO_VMC_SD0 BIT(5) 51 #define PIN_CFG_IO_VMC_SD1 BIT(6) 52 #define PIN_CFG_IO_VMC_QSPI BIT(7) 53 #define PIN_CFG_IO_VMC_ETH0 BIT(8) 54 #define PIN_CFG_IO_VMC_ETH1 BIT(9) 55 #define PIN_CFG_NF BIT(10) /* Digital noise filter */ 56 #define PIN_CFG_IOLH_C BIT(11) 57 #define PIN_CFG_SOFT_PS BIT(12) 58 #define PIN_CFG_OEN BIT(13) 59 #define PIN_CFG_NOGPIO_INT BIT(14) 60 #define PIN_CFG_NOD BIT(15) /* N-ch Open Drain */ 61 #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */ 62 #define PIN_CFG_ELC BIT(17) 63 #define PIN_CFG_IOLH_RZV2H BIT(18) 64 65 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ 66 #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ 67 68 #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ 69 (PIN_CFG_IOLH_##group | \ 70 PIN_CFG_PUPD | \ 71 PIN_CFG_NF) 72 73 #define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \ 74 PIN_CFG_SR) 75 76 #define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \ 77 PIN_CFG_SOFT_PS) 78 79 #define RZV2H_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | \ 80 PIN_CFG_NOD | \ 81 PIN_CFG_SR | \ 82 PIN_CFG_SMT) 83 84 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF) 85 86 #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54) 87 #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46) 88 #define PIN_CFG_MASK GENMASK_ULL(31, 0) 89 90 /* 91 * m indicates the bitmap of supported pins, a is the register index 92 * and f is pin configuration capabilities supported. 93 */ 94 #define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \ 95 FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ 96 FIELD_PREP_CONST(PIN_CFG_MASK, (f))) 97 #define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a) \ 98 (RZG2L_VARIABLE_CFG | \ 99 RZG2L_GPIO_PORT_SPARSE_PACK(m, a, 0)) 100 101 /* 102 * n indicates number of pins in the port, a is the register index 103 * and f is pin configuration capabilities supported. 104 */ 105 #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f)) 106 #define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a) (RZG2L_VARIABLE_CFG | \ 107 RZG2L_GPIO_PORT_PACK(n, a, 0)) 108 109 #define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56) 110 #define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53) 111 /* 112 * p is the register index while referencing to SR/IEN/IOLH/FILxx 113 * registers, b is the register bits (b * 8) and f is the pin 114 * configuration capabilities supported. 115 */ 116 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ 117 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \ 118 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \ 119 FIELD_PREP_CONST(PIN_CFG_MASK, (f))) 120 121 #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ 122 FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \ 123 FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg))) 124 125 #define VARIABLE_PIN_CFG_PIN_MASK GENMASK_ULL(54, 52) 126 #define VARIABLE_PIN_CFG_PORT_MASK GENMASK_ULL(51, 47) 127 #define RZG2L_VARIABLE_PIN_CFG_PACK(port, pin, cfg) \ 128 (FIELD_PREP_CONST(VARIABLE_PIN_CFG_PIN_MASK, (pin)) | \ 129 FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \ 130 FIELD_PREP_CONST(PIN_CFG_MASK, (cfg))) 131 132 #define P(off) (0x0000 + (off)) 133 #define PM(off) (0x0100 + (off) * 2) 134 #define PMC(off) (0x0200 + (off)) 135 #define PFC(off) (0x0400 + (off) * 4) 136 #define PIN(off) (0x0800 + (off)) 137 #define IOLH(off) (0x1000 + (off) * 8) 138 #define SR(off) (0x1400 + (off) * 8) 139 #define IEN(off) (0x1800 + (off) * 8) 140 #define PUPD(off) (0x1C00 + (off) * 8) 141 #define ISEL(off) (0x2C00 + (off) * 8) 142 #define NOD(off) (0x3000 + (off) * 8) 143 #define SMT(off) (0x3400 + (off) * 8) 144 #define SD_CH(off, ch) ((off) + (ch) * 4) 145 #define ETH_POC(off, ch) ((off) + (ch) * 4) 146 #define QSPI (0x3008) 147 #define ETH_MODE (0x3018) 148 #define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */ 149 150 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ 151 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ 152 #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ 153 154 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ 155 #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ 156 #define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable on RZ/V2H(P) */ 157 #define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */ 158 159 #define PM_MASK 0x03 160 #define PFC_MASK 0x07 161 #define IEN_MASK 0x01 162 #define IOLH_MASK 0x03 163 #define SR_MASK 0x01 164 #define PUPD_MASK 0x03 165 #define NOD_MASK 0x01 166 #define SMT_MASK 0x01 167 168 #define PM_INPUT 0x1 169 #define PM_OUTPUT 0x2 170 171 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) 172 #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) 173 174 #define RZG2L_TINT_MAX_INTERRUPT 32 175 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) 176 177 /* Custom pinconf parameters */ 178 #define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE (PIN_CONFIG_END + 1) 179 180 static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = { 181 { "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 }, 182 }; 183 184 #ifdef CONFIG_DEBUG_FS 185 static const struct pin_config_item renesas_rzv2h_conf_items[] = { 186 PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true), 187 }; 188 #endif 189 190 /* Read/write 8 bits register */ 191 #define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \ 192 do { \ 193 if (_read) \ 194 _val = readb(_addr); \ 195 else \ 196 writeb(_val, _addr); \ 197 } while (0) 198 199 /* Read/write 16 bits register */ 200 #define RZG2L_PCTRL_REG_ACCESS16(_read, _addr, _val) \ 201 do { \ 202 if (_read) \ 203 _val = readw(_addr); \ 204 else \ 205 writew(_val, _addr); \ 206 } while (0) 207 208 /* Read/write 32 bits register */ 209 #define RZG2L_PCTRL_REG_ACCESS32(_read, _addr, _val) \ 210 do { \ 211 if (_read) \ 212 _val = readl(_addr); \ 213 else \ 214 writel(_val, _addr); \ 215 } while (0) 216 217 /** 218 * struct rzg2l_register_offsets - specific register offsets 219 * @pwpr: PWPR register offset 220 * @sd_ch: SD_CH register offset 221 * @eth_poc: ETH_POC register offset 222 */ 223 struct rzg2l_register_offsets { 224 u16 pwpr; 225 u16 sd_ch; 226 u16 eth_poc; 227 }; 228 229 /** 230 * enum rzg2l_iolh_index - starting indices in IOLH specific arrays 231 * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source 232 * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source 233 * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source 234 * @RZG2L_IOLH_IDX_MAX: maximum index 235 */ 236 enum rzg2l_iolh_index { 237 RZG2L_IOLH_IDX_1V8 = 0, 238 RZG2L_IOLH_IDX_2V5 = 4, 239 RZG2L_IOLH_IDX_3V3 = 8, 240 RZG2L_IOLH_IDX_MAX = 12, 241 }; 242 243 /* Maximum number of driver strength entries per power source. */ 244 #define RZG2L_IOLH_MAX_DS_ENTRIES (4) 245 246 /** 247 * struct rzg2l_hwcfg - hardware configuration data structure 248 * @regs: hardware specific register offsets 249 * @iolh_groupa_ua: IOLH group A uA specific values 250 * @iolh_groupb_ua: IOLH group B uA specific values 251 * @iolh_groupc_ua: IOLH group C uA specific values 252 * @iolh_groupb_oi: IOLH group B output impedance specific values 253 * @tint_start_index: the start index for the TINT interrupts 254 * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) 255 * @func_base: base number for port function (see register PFC) 256 * @oen_max_pin: the maximum pin number supporting output enable 257 * @oen_max_port: the maximum port number supporting output enable 258 */ 259 struct rzg2l_hwcfg { 260 const struct rzg2l_register_offsets regs; 261 u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; 262 u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; 263 u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; 264 u16 iolh_groupb_oi[4]; 265 u16 tint_start_index; 266 bool drive_strength_ua; 267 u8 func_base; 268 u8 oen_max_pin; 269 u8 oen_max_port; 270 }; 271 272 struct rzg2l_dedicated_configs { 273 const char *name; 274 u64 config; 275 }; 276 277 struct rzg2l_pinctrl; 278 279 struct rzg2l_pinctrl_data { 280 const char * const *port_pins; 281 const u64 *port_pin_configs; 282 unsigned int n_ports; 283 const struct rzg2l_dedicated_configs *dedicated_pins; 284 unsigned int n_port_pins; 285 unsigned int n_dedicated_pins; 286 const struct rzg2l_hwcfg *hwcfg; 287 const u64 *variable_pin_cfg; 288 unsigned int n_variable_pin_cfg; 289 unsigned int num_custom_params; 290 const struct pinconf_generic_params *custom_params; 291 #ifdef CONFIG_DEBUG_FS 292 const struct pin_config_item *custom_conf_items; 293 #endif 294 void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock); 295 void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset); 296 u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); 297 int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen); 298 int (*hw_to_bias_param)(unsigned int val); 299 int (*bias_param_to_hw)(enum pin_config_param param); 300 }; 301 302 /** 303 * struct rzg2l_pinctrl_pin_settings - pin data 304 * @power_source: power source 305 * @drive_strength_ua: drive strength (in micro amps) 306 */ 307 struct rzg2l_pinctrl_pin_settings { 308 u16 power_source; 309 u16 drive_strength_ua; 310 }; 311 312 /** 313 * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume) 314 * @p: P registers cache 315 * @pm: PM registers cache 316 * @pmc: PMC registers cache 317 * @pfc: PFC registers cache 318 * @iolh: IOLH registers cache 319 * @ien: IEN registers cache 320 * @sd_ch: SD_CH registers cache 321 * @eth_poc: ET_POC registers cache 322 * @eth_mode: ETH_MODE register cache 323 * @qspi: QSPI registers cache 324 */ 325 struct rzg2l_pinctrl_reg_cache { 326 u8 *p; 327 u16 *pm; 328 u8 *pmc; 329 u32 *pfc; 330 u32 *iolh[2]; 331 u32 *ien[2]; 332 u8 sd_ch[2]; 333 u8 eth_poc[2]; 334 u8 eth_mode; 335 u8 qspi; 336 }; 337 338 struct rzg2l_pinctrl { 339 struct pinctrl_dev *pctl; 340 struct pinctrl_desc desc; 341 struct pinctrl_pin_desc *pins; 342 343 const struct rzg2l_pinctrl_data *data; 344 void __iomem *base; 345 struct device *dev; 346 347 struct clk *clk; 348 349 struct gpio_chip gpio_chip; 350 struct pinctrl_gpio_range gpio_range; 351 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); 352 spinlock_t bitmap_lock; /* protect tint_slot bitmap */ 353 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; 354 355 spinlock_t lock; /* lock read/write registers */ 356 struct mutex mutex; /* serialize adding groups and functions */ 357 358 struct rzg2l_pinctrl_pin_settings *settings; 359 struct rzg2l_pinctrl_reg_cache *cache; 360 struct rzg2l_pinctrl_reg_cache *dedicated_cache; 361 atomic_t wakeup_path; 362 }; 363 364 static const u16 available_ps[] = { 1800, 2500, 3300 }; 365 366 static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, 367 u64 pincfg, 368 unsigned int port, 369 u8 pin) 370 { 371 unsigned int i; 372 373 for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { 374 u64 cfg = pctrl->data->variable_pin_cfg[i]; 375 376 if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port && 377 FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin) 378 return (pincfg & ~RZG2L_VARIABLE_CFG) | FIELD_GET(PIN_CFG_MASK, cfg); 379 } 380 381 return 0; 382 } 383 384 static const u64 r9a09g057_variable_pin_cfg[] = { 385 RZG2L_VARIABLE_PIN_CFG_PACK(11, 0, RZV2H_MPXED_PIN_FUNCS), 386 RZG2L_VARIABLE_PIN_CFG_PACK(11, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 387 RZG2L_VARIABLE_PIN_CFG_PACK(11, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 388 RZG2L_VARIABLE_PIN_CFG_PACK(11, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 389 RZG2L_VARIABLE_PIN_CFG_PACK(11, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 390 RZG2L_VARIABLE_PIN_CFG_PACK(11, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 391 }; 392 393 #ifdef CONFIG_RISCV 394 static const u64 r9a07g043f_variable_pin_cfg[] = { 395 RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 396 PIN_CFG_NF | 397 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 398 RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 399 PIN_CFG_NF | 400 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 401 RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 402 PIN_CFG_NF | 403 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 404 RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 405 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 406 RZG2L_VARIABLE_PIN_CFG_PACK(20, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 407 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 408 RZG2L_VARIABLE_PIN_CFG_PACK(20, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 409 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 410 RZG2L_VARIABLE_PIN_CFG_PACK(20, 6, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 411 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 412 RZG2L_VARIABLE_PIN_CFG_PACK(20, 7, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 413 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 414 RZG2L_VARIABLE_PIN_CFG_PACK(23, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 415 PIN_CFG_NOGPIO_INT), 416 RZG2L_VARIABLE_PIN_CFG_PACK(23, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 417 PIN_CFG_NOGPIO_INT), 418 RZG2L_VARIABLE_PIN_CFG_PACK(23, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 419 PIN_CFG_NOGPIO_INT), 420 RZG2L_VARIABLE_PIN_CFG_PACK(23, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 421 PIN_CFG_NOGPIO_INT), 422 RZG2L_VARIABLE_PIN_CFG_PACK(23, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT), 423 RZG2L_VARIABLE_PIN_CFG_PACK(24, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT), 424 RZG2L_VARIABLE_PIN_CFG_PACK(24, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 425 PIN_CFG_NOGPIO_INT), 426 RZG2L_VARIABLE_PIN_CFG_PACK(24, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 427 PIN_CFG_NOGPIO_INT), 428 RZG2L_VARIABLE_PIN_CFG_PACK(24, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 429 PIN_CFG_NOGPIO_INT), 430 RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 431 PIN_CFG_NOGPIO_INT), 432 RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 433 PIN_CFG_NF | 434 PIN_CFG_NOGPIO_INT), 435 }; 436 #endif 437 438 static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) 439 { 440 writeb(val, pctrl->base + offset); 441 } 442 443 static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) 444 { 445 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 446 u8 pwpr; 447 448 pwpr = readb(pctrl->base + regs->pwpr); 449 writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr); 450 writeb(val, pctrl->base + offset); 451 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); 452 } 453 454 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, 455 u8 pin, u8 off, u8 func) 456 { 457 unsigned long flags; 458 u32 reg; 459 460 spin_lock_irqsave(&pctrl->lock, flags); 461 462 /* Set pin to 'Non-use (Hi-Z input protection)' */ 463 reg = readw(pctrl->base + PM(off)); 464 reg &= ~(PM_MASK << (pin * 2)); 465 writew(reg, pctrl->base + PM(off)); 466 467 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); 468 469 /* Temporarily switch to GPIO mode with PMC register */ 470 reg = readb(pctrl->base + PMC(off)); 471 writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); 472 473 /* Select Pin function mode with PFC register */ 474 reg = readl(pctrl->base + PFC(off)); 475 reg &= ~(PFC_MASK << (pin * 4)); 476 writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); 477 478 /* Switch to Peripheral pin function with PMC register */ 479 reg = readb(pctrl->base + PMC(off)); 480 writeb(reg | BIT(pin), pctrl->base + PMC(off)); 481 482 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); 483 484 spin_unlock_irqrestore(&pctrl->lock, flags); 485 }; 486 487 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, 488 unsigned int func_selector, 489 unsigned int group_selector) 490 { 491 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 492 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 493 struct function_desc *func; 494 unsigned int i, *psel_val; 495 struct group_desc *group; 496 const unsigned int *pins; 497 498 func = pinmux_generic_get_function(pctldev, func_selector); 499 if (!func) 500 return -EINVAL; 501 group = pinctrl_generic_get_group(pctldev, group_selector); 502 if (!group) 503 return -EINVAL; 504 505 psel_val = func->data; 506 pins = group->grp.pins; 507 508 for (i = 0; i < group->grp.npins; i++) { 509 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; 510 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 511 u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); 512 513 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", 514 RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); 515 516 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); 517 } 518 519 return 0; 520 }; 521 522 static int rzg2l_map_add_config(struct pinctrl_map *map, 523 const char *group_or_pin, 524 enum pinctrl_map_type type, 525 unsigned long *configs, 526 unsigned int num_configs) 527 { 528 unsigned long *cfgs; 529 530 cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL); 531 if (!cfgs) 532 return -ENOMEM; 533 534 map->type = type; 535 map->data.configs.group_or_pin = group_or_pin; 536 map->data.configs.configs = cfgs; 537 map->data.configs.num_configs = num_configs; 538 539 return 0; 540 } 541 542 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, 543 struct device_node *np, 544 struct device_node *parent, 545 struct pinctrl_map **map, 546 unsigned int *num_maps, 547 unsigned int *index) 548 { 549 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 550 struct pinctrl_map *maps = *map; 551 unsigned int nmaps = *num_maps; 552 unsigned long *configs = NULL; 553 unsigned int *pins, *psel_val; 554 unsigned int num_pinmux = 0; 555 unsigned int idx = *index; 556 unsigned int num_pins, i; 557 unsigned int num_configs; 558 struct property *pinmux; 559 struct property *prop; 560 int ret, gsel, fsel; 561 const char **pin_fn; 562 const char *name; 563 const char *pin; 564 565 pinmux = of_find_property(np, "pinmux", NULL); 566 if (pinmux) 567 num_pinmux = pinmux->length / sizeof(u32); 568 569 ret = of_property_count_strings(np, "pins"); 570 if (ret == -EINVAL) { 571 num_pins = 0; 572 } else if (ret < 0) { 573 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 574 return ret; 575 } else { 576 num_pins = ret; 577 } 578 579 if (!num_pinmux && !num_pins) 580 return 0; 581 582 if (num_pinmux && num_pins) { 583 dev_err(pctrl->dev, 584 "DT node must contain either a pinmux or pins and not both\n"); 585 return -EINVAL; 586 } 587 588 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); 589 if (ret < 0) 590 return ret; 591 592 if (num_pins && !num_configs) { 593 dev_err(pctrl->dev, "DT node must contain a config\n"); 594 ret = -ENODEV; 595 goto done; 596 } 597 598 if (num_pinmux) { 599 nmaps += 1; 600 if (num_configs) 601 nmaps += 1; 602 } 603 604 if (num_pins) 605 nmaps += num_pins; 606 607 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 608 if (!maps) { 609 ret = -ENOMEM; 610 goto done; 611 } 612 613 *map = maps; 614 *num_maps = nmaps; 615 if (num_pins) { 616 of_property_for_each_string(np, "pins", prop, pin) { 617 ret = rzg2l_map_add_config(&maps[idx], pin, 618 PIN_MAP_TYPE_CONFIGS_PIN, 619 configs, num_configs); 620 if (ret < 0) 621 goto done; 622 623 idx++; 624 } 625 ret = 0; 626 goto done; 627 } 628 629 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 630 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 631 GFP_KERNEL); 632 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 633 if (!pins || !psel_val || !pin_fn) { 634 ret = -ENOMEM; 635 goto done; 636 } 637 638 /* Collect pin locations and mux settings from DT properties */ 639 for (i = 0; i < num_pinmux; ++i) { 640 u32 value; 641 642 ret = of_property_read_u32_index(np, "pinmux", i, &value); 643 if (ret) 644 goto done; 645 pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value); 646 psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value); 647 } 648 649 if (parent) { 650 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", 651 parent, np); 652 if (!name) { 653 ret = -ENOMEM; 654 goto done; 655 } 656 } else { 657 name = np->name; 658 } 659 660 if (num_configs) { 661 ret = rzg2l_map_add_config(&maps[idx], name, 662 PIN_MAP_TYPE_CONFIGS_GROUP, 663 configs, num_configs); 664 if (ret < 0) 665 goto done; 666 667 idx++; 668 } 669 670 mutex_lock(&pctrl->mutex); 671 672 /* Register a single pin group listing all the pins we read from DT */ 673 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL); 674 if (gsel < 0) { 675 ret = gsel; 676 goto unlock; 677 } 678 679 /* 680 * Register a single group function where the 'data' is an array PSEL 681 * register values read from DT. 682 */ 683 pin_fn[0] = name; 684 fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val); 685 if (fsel < 0) { 686 ret = fsel; 687 goto remove_group; 688 } 689 690 mutex_unlock(&pctrl->mutex); 691 692 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 693 maps[idx].data.mux.group = name; 694 maps[idx].data.mux.function = name; 695 idx++; 696 697 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 698 ret = 0; 699 goto done; 700 701 remove_group: 702 pinctrl_generic_remove_group(pctldev, gsel); 703 unlock: 704 mutex_unlock(&pctrl->mutex); 705 done: 706 *index = idx; 707 kfree(configs); 708 return ret; 709 } 710 711 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, 712 struct pinctrl_map *map, 713 unsigned int num_maps) 714 { 715 unsigned int i; 716 717 if (!map) 718 return; 719 720 for (i = 0; i < num_maps; ++i) { 721 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 722 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 723 kfree(map[i].data.configs.configs); 724 } 725 kfree(map); 726 } 727 728 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, 729 struct device_node *np, 730 struct pinctrl_map **map, 731 unsigned int *num_maps) 732 { 733 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 734 unsigned int index; 735 int ret; 736 737 *map = NULL; 738 *num_maps = 0; 739 index = 0; 740 741 for_each_child_of_node_scoped(np, child) { 742 ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map, 743 num_maps, &index); 744 if (ret < 0) 745 goto done; 746 } 747 748 if (*num_maps == 0) { 749 ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map, 750 num_maps, &index); 751 if (ret < 0) 752 goto done; 753 } 754 755 if (*num_maps) 756 return 0; 757 758 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 759 ret = -EINVAL; 760 761 done: 762 rzg2l_dt_free_map(pctldev, *map, *num_maps); 763 764 return ret; 765 } 766 767 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, 768 u64 cfg, u32 port, u8 bit) 769 { 770 u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); 771 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 772 u64 data; 773 774 if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) 775 return -EINVAL; 776 777 data = pctrl->data->port_pin_configs[port]; 778 if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data)) 779 return -EINVAL; 780 781 return 0; 782 } 783 784 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 785 u8 bit, u32 mask) 786 { 787 void __iomem *addr = pctrl->base + offset; 788 789 /* handle _L/_H for 32-bit register read/write */ 790 if (bit >= 4) { 791 bit -= 4; 792 addr += 4; 793 } 794 795 return (readl(addr) >> (bit * 8)) & mask; 796 } 797 798 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 799 u8 bit, u32 mask, u32 val) 800 { 801 void __iomem *addr = pctrl->base + offset; 802 unsigned long flags; 803 u32 reg; 804 805 /* handle _L/_H for 32-bit register read/write */ 806 if (bit >= 4) { 807 bit -= 4; 808 addr += 4; 809 } 810 811 spin_lock_irqsave(&pctrl->lock, flags); 812 reg = readl(addr) & ~(mask << (bit * 8)); 813 writel(reg | (val << (bit * 8)), addr); 814 spin_unlock_irqrestore(&pctrl->lock, flags); 815 } 816 817 static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps) 818 { 819 if (caps & PIN_CFG_IO_VMC_SD0) 820 return SD_CH(regs->sd_ch, 0); 821 if (caps & PIN_CFG_IO_VMC_SD1) 822 return SD_CH(regs->sd_ch, 1); 823 if (caps & PIN_CFG_IO_VMC_ETH0) 824 return ETH_POC(regs->eth_poc, 0); 825 if (caps & PIN_CFG_IO_VMC_ETH1) 826 return ETH_POC(regs->eth_poc, 1); 827 if (caps & PIN_CFG_IO_VMC_QSPI) 828 return QSPI; 829 830 return -EINVAL; 831 } 832 833 static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) 834 { 835 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 836 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 837 int pwr_reg; 838 u8 val; 839 840 if (caps & PIN_CFG_SOFT_PS) 841 return pctrl->settings[pin].power_source; 842 843 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); 844 if (pwr_reg < 0) 845 return pwr_reg; 846 847 val = readb(pctrl->base + pwr_reg); 848 switch (val) { 849 case PVDD_1800: 850 return 1800; 851 case PVDD_2500: 852 return 2500; 853 case PVDD_3300: 854 return 3300; 855 default: 856 /* Should not happen. */ 857 return -EINVAL; 858 } 859 } 860 861 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) 862 { 863 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 864 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 865 int pwr_reg; 866 u8 val; 867 868 if (caps & PIN_CFG_SOFT_PS) { 869 pctrl->settings[pin].power_source = ps; 870 return 0; 871 } 872 873 switch (ps) { 874 case 1800: 875 val = PVDD_1800; 876 break; 877 case 2500: 878 if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) 879 return -EINVAL; 880 val = PVDD_2500; 881 break; 882 case 3300: 883 val = PVDD_3300; 884 break; 885 default: 886 return -EINVAL; 887 } 888 889 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); 890 if (pwr_reg < 0) 891 return pwr_reg; 892 893 writeb(val, pctrl->base + pwr_reg); 894 pctrl->settings[pin].power_source = ps; 895 896 return 0; 897 } 898 899 static bool rzg2l_ps_is_supported(u16 ps) 900 { 901 unsigned int i; 902 903 for (i = 0; i < ARRAY_SIZE(available_ps); i++) { 904 if (available_ps[i] == ps) 905 return true; 906 } 907 908 return false; 909 } 910 911 static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps) 912 { 913 unsigned int i; 914 915 for (i = 0; i < ARRAY_SIZE(available_ps); i++) { 916 if (available_ps[i] == ps) 917 break; 918 } 919 920 /* 921 * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have 922 * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source 923 */ 924 return i * RZG2L_IOLH_MAX_DS_ENTRIES; 925 } 926 927 static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val) 928 { 929 if (caps & PIN_CFG_IOLH_A) 930 return hwcfg->iolh_groupa_ua[val]; 931 932 if (caps & PIN_CFG_IOLH_B) 933 return hwcfg->iolh_groupb_ua[val]; 934 935 if (caps & PIN_CFG_IOLH_C) 936 return hwcfg->iolh_groupc_ua[val]; 937 938 /* Should not happen. */ 939 return 0; 940 } 941 942 static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps, 943 enum rzg2l_iolh_index ps_index, u16 ua) 944 { 945 const u16 *array = NULL; 946 unsigned int i; 947 948 if (caps & PIN_CFG_IOLH_A) 949 array = &hwcfg->iolh_groupa_ua[ps_index]; 950 951 if (caps & PIN_CFG_IOLH_B) 952 array = &hwcfg->iolh_groupb_ua[ps_index]; 953 954 if (caps & PIN_CFG_IOLH_C) 955 array = &hwcfg->iolh_groupc_ua[ps_index]; 956 957 if (!array) 958 return -EINVAL; 959 960 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { 961 if (array[i] == ua) 962 return i; 963 } 964 965 return -EINVAL; 966 } 967 968 static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, 969 enum rzg2l_iolh_index iolh_idx, 970 u16 ds) 971 { 972 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 973 const u16 *array = NULL; 974 unsigned int i; 975 976 if (caps & PIN_CFG_IOLH_A) 977 array = hwcfg->iolh_groupa_ua; 978 979 if (caps & PIN_CFG_IOLH_B) 980 array = hwcfg->iolh_groupb_ua; 981 982 if (caps & PIN_CFG_IOLH_C) 983 array = hwcfg->iolh_groupc_ua; 984 985 /* Should not happen. */ 986 if (!array) 987 return false; 988 989 if (!array[iolh_idx]) 990 return false; 991 992 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { 993 if (array[iolh_idx + i] == ds) 994 return true; 995 } 996 997 return false; 998 } 999 1000 static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1001 { 1002 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; 1003 u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data); 1004 u8 pin = RZG2L_PIN_ID_TO_PIN(_pin); 1005 1006 if (pin > pctrl->data->hwcfg->oen_max_pin) 1007 return -EINVAL; 1008 1009 /* 1010 * We can determine which Ethernet interface we're dealing with from 1011 * the caps. 1012 */ 1013 if (caps & PIN_CFG_IO_VMC_ETH0) 1014 return 0; 1015 if (caps & PIN_CFG_IO_VMC_ETH1) 1016 return 1; 1017 1018 return -EINVAL; 1019 } 1020 1021 static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1022 { 1023 int bit; 1024 1025 bit = rzg2l_pin_to_oen_bit(pctrl, _pin); 1026 if (bit < 0) 1027 return 0; 1028 1029 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); 1030 } 1031 1032 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) 1033 { 1034 unsigned long flags; 1035 int bit; 1036 u8 val; 1037 1038 bit = rzg2l_pin_to_oen_bit(pctrl, _pin); 1039 if (bit < 0) 1040 return bit; 1041 1042 spin_lock_irqsave(&pctrl->lock, flags); 1043 val = readb(pctrl->base + ETH_MODE); 1044 if (oen) 1045 val &= ~BIT(bit); 1046 else 1047 val |= BIT(bit); 1048 writeb(val, pctrl->base + ETH_MODE); 1049 spin_unlock_irqrestore(&pctrl->lock, flags); 1050 1051 return 0; 1052 } 1053 1054 static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1055 { 1056 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; 1057 u8 port, pin, bit; 1058 1059 if (*pin_data & RZG2L_SINGLE_PIN) 1060 return -EINVAL; 1061 1062 port = RZG2L_PIN_ID_TO_PORT(_pin); 1063 pin = RZG2L_PIN_ID_TO_PIN(_pin); 1064 if (pin > pctrl->data->hwcfg->oen_max_pin) 1065 return -EINVAL; 1066 1067 bit = pin * 2; 1068 if (port == pctrl->data->hwcfg->oen_max_port) 1069 bit += 1; 1070 1071 return bit; 1072 } 1073 1074 static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1075 { 1076 int bit; 1077 1078 bit = rzg3s_pin_to_oen_bit(pctrl, _pin); 1079 if (bit < 0) 1080 return bit; 1081 1082 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); 1083 } 1084 1085 static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) 1086 { 1087 unsigned long flags; 1088 int bit; 1089 u8 val; 1090 1091 bit = rzg3s_pin_to_oen_bit(pctrl, _pin); 1092 if (bit < 0) 1093 return bit; 1094 1095 spin_lock_irqsave(&pctrl->lock, flags); 1096 val = readb(pctrl->base + ETH_MODE); 1097 if (oen) 1098 val &= ~BIT(bit); 1099 else 1100 val |= BIT(bit); 1101 writeb(val, pctrl->base + ETH_MODE); 1102 spin_unlock_irqrestore(&pctrl->lock, flags); 1103 1104 return 0; 1105 } 1106 1107 static int rzg2l_hw_to_bias_param(unsigned int bias) 1108 { 1109 switch (bias) { 1110 case 0: 1111 return PIN_CONFIG_BIAS_DISABLE; 1112 case 1: 1113 return PIN_CONFIG_BIAS_PULL_UP; 1114 case 2: 1115 return PIN_CONFIG_BIAS_PULL_DOWN; 1116 default: 1117 break; 1118 } 1119 1120 return -EINVAL; 1121 } 1122 1123 static int rzg2l_bias_param_to_hw(enum pin_config_param param) 1124 { 1125 switch (param) { 1126 case PIN_CONFIG_BIAS_DISABLE: 1127 return 0; 1128 case PIN_CONFIG_BIAS_PULL_UP: 1129 return 1; 1130 case PIN_CONFIG_BIAS_PULL_DOWN: 1131 return 2; 1132 default: 1133 break; 1134 } 1135 1136 return -EINVAL; 1137 } 1138 1139 static int rzv2h_hw_to_bias_param(unsigned int bias) 1140 { 1141 switch (bias) { 1142 case 0: 1143 case 1: 1144 return PIN_CONFIG_BIAS_DISABLE; 1145 case 2: 1146 return PIN_CONFIG_BIAS_PULL_DOWN; 1147 case 3: 1148 return PIN_CONFIG_BIAS_PULL_UP; 1149 default: 1150 break; 1151 } 1152 1153 return -EINVAL; 1154 } 1155 1156 static int rzv2h_bias_param_to_hw(enum pin_config_param param) 1157 { 1158 switch (param) { 1159 case PIN_CONFIG_BIAS_DISABLE: 1160 return 0; 1161 case PIN_CONFIG_BIAS_PULL_DOWN: 1162 return 2; 1163 case PIN_CONFIG_BIAS_PULL_UP: 1164 return 3; 1165 default: 1166 break; 1167 } 1168 1169 return -EINVAL; 1170 } 1171 1172 static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1173 { 1174 static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK", 1175 "XSPI0_RESET0N", "XSPI0_CS0N", 1176 "XSPI0_CKN", "XSPI0_CKP" }; 1177 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin]; 1178 unsigned int i; 1179 1180 for (i = 0; i < ARRAY_SIZE(pin_names); i++) { 1181 if (!strcmp(pin_desc->name, pin_names[i])) 1182 return i; 1183 } 1184 1185 /* Should not happen. */ 1186 return 0; 1187 } 1188 1189 static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1190 { 1191 u8 bit; 1192 1193 bit = rzv2h_pin_to_oen_bit(pctrl, _pin); 1194 1195 return !(readb(pctrl->base + PFC_OEN) & BIT(bit)); 1196 } 1197 1198 static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) 1199 { 1200 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1201 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 1202 unsigned long flags; 1203 u8 val, bit; 1204 u8 pwpr; 1205 1206 bit = rzv2h_pin_to_oen_bit(pctrl, _pin); 1207 spin_lock_irqsave(&pctrl->lock, flags); 1208 val = readb(pctrl->base + PFC_OEN); 1209 if (oen) 1210 val &= ~BIT(bit); 1211 else 1212 val |= BIT(bit); 1213 1214 pwpr = readb(pctrl->base + regs->pwpr); 1215 writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); 1216 writeb(val, pctrl->base + PFC_OEN); 1217 writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); 1218 spin_unlock_irqrestore(&pctrl->lock, flags); 1219 1220 return 0; 1221 } 1222 1223 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 1224 unsigned int _pin, 1225 unsigned long *config) 1226 { 1227 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1228 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1229 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 1230 u32 param = pinconf_to_config_param(*config); 1231 u64 *pin_data = pin->drv_data; 1232 unsigned int arg = 0; 1233 u32 off; 1234 u32 cfg; 1235 int ret; 1236 u8 bit; 1237 1238 if (!pin_data) 1239 return -EINVAL; 1240 1241 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1242 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); 1243 if (*pin_data & RZG2L_SINGLE_PIN) { 1244 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); 1245 } else { 1246 bit = RZG2L_PIN_ID_TO_PIN(_pin); 1247 1248 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 1249 return -EINVAL; 1250 } 1251 1252 switch (param) { 1253 case PIN_CONFIG_INPUT_ENABLE: 1254 if (!(cfg & PIN_CFG_IEN)) 1255 return -EINVAL; 1256 arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK); 1257 if (!arg) 1258 return -EINVAL; 1259 break; 1260 1261 case PIN_CONFIG_OUTPUT_ENABLE: 1262 if (!(cfg & PIN_CFG_OEN)) 1263 return -EINVAL; 1264 if (!pctrl->data->oen_read) 1265 return -EOPNOTSUPP; 1266 arg = pctrl->data->oen_read(pctrl, _pin); 1267 if (!arg) 1268 return -EINVAL; 1269 break; 1270 1271 case PIN_CONFIG_POWER_SOURCE: 1272 ret = rzg2l_get_power_source(pctrl, _pin, cfg); 1273 if (ret < 0) 1274 return ret; 1275 arg = ret; 1276 break; 1277 1278 case PIN_CONFIG_SLEW_RATE: 1279 if (!(cfg & PIN_CFG_SR)) 1280 return -EINVAL; 1281 1282 arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK); 1283 break; 1284 1285 case PIN_CONFIG_BIAS_DISABLE: 1286 case PIN_CONFIG_BIAS_PULL_UP: 1287 case PIN_CONFIG_BIAS_PULL_DOWN: 1288 if (!(cfg & PIN_CFG_PUPD)) 1289 return -EINVAL; 1290 1291 arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK); 1292 ret = pctrl->data->hw_to_bias_param(arg); 1293 if (ret < 0) 1294 return ret; 1295 1296 if (ret != param) 1297 return -EINVAL; 1298 /* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */ 1299 arg = 1; 1300 break; 1301 1302 case PIN_CONFIG_DRIVE_STRENGTH: { 1303 unsigned int index; 1304 1305 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) 1306 return -EINVAL; 1307 1308 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1309 /* 1310 * Drive strenght mA is supported only by group A and only 1311 * for 3V3 port source. 1312 */ 1313 arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; 1314 break; 1315 } 1316 1317 case PIN_CONFIG_DRIVE_STRENGTH_UA: { 1318 enum rzg2l_iolh_index iolh_idx; 1319 u8 val; 1320 1321 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || 1322 !hwcfg->drive_strength_ua) 1323 return -EINVAL; 1324 1325 ret = rzg2l_get_power_source(pctrl, _pin, cfg); 1326 if (ret < 0) 1327 return ret; 1328 iolh_idx = rzg2l_ps_to_iolh_idx(ret); 1329 val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1330 arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val); 1331 break; 1332 } 1333 1334 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 1335 unsigned int index; 1336 1337 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) 1338 return -EINVAL; 1339 1340 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1341 arg = hwcfg->iolh_groupb_oi[index]; 1342 break; 1343 } 1344 1345 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1346 case PIN_CONFIG_DRIVE_PUSH_PULL: 1347 if (!(cfg & PIN_CFG_NOD)) 1348 return -EINVAL; 1349 1350 arg = rzg2l_read_pin_config(pctrl, NOD(off), bit, NOD_MASK); 1351 if (!arg && param != PIN_CONFIG_DRIVE_PUSH_PULL) 1352 return -EINVAL; 1353 if (arg && param != PIN_CONFIG_DRIVE_OPEN_DRAIN) 1354 return -EINVAL; 1355 break; 1356 1357 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1358 if (!(cfg & PIN_CFG_SMT)) 1359 return -EINVAL; 1360 1361 arg = rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK); 1362 if (!arg) 1363 return -EINVAL; 1364 break; 1365 1366 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: 1367 if (!(cfg & PIN_CFG_IOLH_RZV2H)) 1368 return -EINVAL; 1369 1370 arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1371 break; 1372 1373 default: 1374 return -ENOTSUPP; 1375 } 1376 1377 *config = pinconf_to_config_packed(param, arg); 1378 1379 return 0; 1380 }; 1381 1382 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 1383 unsigned int _pin, 1384 unsigned long *_configs, 1385 unsigned int num_configs) 1386 { 1387 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1388 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 1389 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1390 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; 1391 u64 *pin_data = pin->drv_data; 1392 unsigned int i, arg, index; 1393 u32 off, param; 1394 u32 cfg; 1395 int ret; 1396 u8 bit; 1397 1398 if (!pin_data) 1399 return -EINVAL; 1400 1401 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1402 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); 1403 if (*pin_data & RZG2L_SINGLE_PIN) { 1404 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); 1405 } else { 1406 bit = RZG2L_PIN_ID_TO_PIN(_pin); 1407 1408 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 1409 return -EINVAL; 1410 } 1411 1412 for (i = 0; i < num_configs; i++) { 1413 param = pinconf_to_config_param(_configs[i]); 1414 arg = pinconf_to_config_argument(_configs[i]); 1415 switch (param) { 1416 case PIN_CONFIG_INPUT_ENABLE: 1417 1418 if (!(cfg & PIN_CFG_IEN)) 1419 return -EINVAL; 1420 1421 rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); 1422 break; 1423 1424 case PIN_CONFIG_OUTPUT_ENABLE: 1425 if (!(cfg & PIN_CFG_OEN)) 1426 return -EINVAL; 1427 if (!pctrl->data->oen_write) 1428 return -EOPNOTSUPP; 1429 ret = pctrl->data->oen_write(pctrl, _pin, !!arg); 1430 if (ret) 1431 return ret; 1432 break; 1433 1434 case PIN_CONFIG_POWER_SOURCE: 1435 settings.power_source = arg; 1436 break; 1437 1438 case PIN_CONFIG_SLEW_RATE: 1439 if (!(cfg & PIN_CFG_SR) || arg > 1) 1440 return -EINVAL; 1441 1442 rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg); 1443 break; 1444 1445 case PIN_CONFIG_BIAS_DISABLE: 1446 case PIN_CONFIG_BIAS_PULL_UP: 1447 case PIN_CONFIG_BIAS_PULL_DOWN: 1448 if (!(cfg & PIN_CFG_PUPD)) 1449 return -EINVAL; 1450 1451 ret = pctrl->data->bias_param_to_hw(param); 1452 if (ret < 0) 1453 return ret; 1454 1455 rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, ret); 1456 break; 1457 1458 case PIN_CONFIG_DRIVE_STRENGTH: 1459 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) 1460 return -EINVAL; 1461 1462 for (index = RZG2L_IOLH_IDX_3V3; 1463 index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) { 1464 if (arg == (hwcfg->iolh_groupa_ua[index] / 1000)) 1465 break; 1466 } 1467 if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES)) 1468 return -EINVAL; 1469 1470 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); 1471 break; 1472 1473 case PIN_CONFIG_DRIVE_STRENGTH_UA: 1474 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || 1475 !hwcfg->drive_strength_ua) 1476 return -EINVAL; 1477 1478 settings.drive_strength_ua = arg; 1479 break; 1480 1481 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: 1482 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) 1483 return -EINVAL; 1484 1485 for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { 1486 if (arg == hwcfg->iolh_groupb_oi[index]) 1487 break; 1488 } 1489 if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi)) 1490 return -EINVAL; 1491 1492 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); 1493 break; 1494 1495 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1496 case PIN_CONFIG_DRIVE_PUSH_PULL: 1497 if (!(cfg & PIN_CFG_NOD)) 1498 return -EINVAL; 1499 1500 rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK, 1501 param == PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0); 1502 break; 1503 1504 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1505 if (!(cfg & PIN_CFG_SMT)) 1506 return -EINVAL; 1507 1508 rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, arg); 1509 break; 1510 1511 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: 1512 if (!(cfg & PIN_CFG_IOLH_RZV2H)) 1513 return -EINVAL; 1514 1515 if (arg > 3) 1516 return -EINVAL; 1517 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg); 1518 break; 1519 1520 default: 1521 return -EOPNOTSUPP; 1522 } 1523 } 1524 1525 /* Apply power source. */ 1526 if (settings.power_source != pctrl->settings[_pin].power_source) { 1527 ret = rzg2l_ps_is_supported(settings.power_source); 1528 if (!ret) 1529 return -EINVAL; 1530 1531 /* Apply power source. */ 1532 ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source); 1533 if (ret) 1534 return ret; 1535 } 1536 1537 /* Apply drive strength. */ 1538 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { 1539 enum rzg2l_iolh_index iolh_idx; 1540 int val; 1541 1542 iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source); 1543 ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx, 1544 settings.drive_strength_ua); 1545 if (!ret) 1546 return -EINVAL; 1547 1548 /* Get register value for this PS/DS tuple. */ 1549 val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua); 1550 if (val < 0) 1551 return val; 1552 1553 /* Apply drive strength. */ 1554 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val); 1555 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; 1556 } 1557 1558 return 0; 1559 } 1560 1561 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, 1562 unsigned int group, 1563 unsigned long *configs, 1564 unsigned int num_configs) 1565 { 1566 const unsigned int *pins; 1567 unsigned int i, npins; 1568 int ret; 1569 1570 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 1571 if (ret) 1572 return ret; 1573 1574 for (i = 0; i < npins; i++) { 1575 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, 1576 num_configs); 1577 if (ret) 1578 return ret; 1579 } 1580 1581 return 0; 1582 }; 1583 1584 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, 1585 unsigned int group, 1586 unsigned long *config) 1587 { 1588 const unsigned int *pins; 1589 unsigned int i, npins, prev_config = 0; 1590 int ret; 1591 1592 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 1593 if (ret) 1594 return ret; 1595 1596 for (i = 0; i < npins; i++) { 1597 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); 1598 if (ret) 1599 return ret; 1600 1601 /* Check config matching between to pin */ 1602 if (i && prev_config != *config) 1603 return -EOPNOTSUPP; 1604 1605 prev_config = *config; 1606 } 1607 1608 return 0; 1609 }; 1610 1611 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { 1612 .get_groups_count = pinctrl_generic_get_group_count, 1613 .get_group_name = pinctrl_generic_get_group_name, 1614 .get_group_pins = pinctrl_generic_get_group_pins, 1615 .dt_node_to_map = rzg2l_dt_node_to_map, 1616 .dt_free_map = rzg2l_dt_free_map, 1617 }; 1618 1619 static const struct pinmux_ops rzg2l_pinctrl_pmxops = { 1620 .get_functions_count = pinmux_generic_get_function_count, 1621 .get_function_name = pinmux_generic_get_function_name, 1622 .get_function_groups = pinmux_generic_get_function_groups, 1623 .set_mux = rzg2l_pinctrl_set_mux, 1624 .strict = true, 1625 }; 1626 1627 static const struct pinconf_ops rzg2l_pinctrl_confops = { 1628 .is_generic = true, 1629 .pin_config_get = rzg2l_pinctrl_pinconf_get, 1630 .pin_config_set = rzg2l_pinctrl_pinconf_set, 1631 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set, 1632 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get, 1633 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1634 }; 1635 1636 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) 1637 { 1638 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1639 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1640 u64 *pin_data = pin_desc->drv_data; 1641 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1642 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 1643 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1644 unsigned long flags; 1645 u8 reg8; 1646 int ret; 1647 1648 ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit); 1649 if (ret) 1650 return ret; 1651 1652 ret = pinctrl_gpio_request(chip, offset); 1653 if (ret) 1654 return ret; 1655 1656 spin_lock_irqsave(&pctrl->lock, flags); 1657 1658 /* Select GPIO mode in PMC Register */ 1659 reg8 = readb(pctrl->base + PMC(off)); 1660 reg8 &= ~BIT(bit); 1661 pctrl->data->pmc_writeb(pctrl, reg8, PMC(off)); 1662 1663 spin_unlock_irqrestore(&pctrl->lock, flags); 1664 1665 return 0; 1666 } 1667 1668 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, 1669 bool output) 1670 { 1671 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1672 u64 *pin_data = pin_desc->drv_data; 1673 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1674 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1675 unsigned long flags; 1676 u16 reg16; 1677 1678 spin_lock_irqsave(&pctrl->lock, flags); 1679 1680 reg16 = readw(pctrl->base + PM(off)); 1681 reg16 &= ~(PM_MASK << (bit * 2)); 1682 1683 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); 1684 writew(reg16, pctrl->base + PM(off)); 1685 1686 spin_unlock_irqrestore(&pctrl->lock, flags); 1687 } 1688 1689 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1690 { 1691 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1692 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1693 u64 *pin_data = pin_desc->drv_data; 1694 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1695 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1696 1697 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { 1698 u16 reg16; 1699 1700 reg16 = readw(pctrl->base + PM(off)); 1701 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 1702 if (reg16 == PM_OUTPUT) 1703 return GPIO_LINE_DIRECTION_OUT; 1704 } 1705 1706 return GPIO_LINE_DIRECTION_IN; 1707 } 1708 1709 static int rzg2l_gpio_direction_input(struct gpio_chip *chip, 1710 unsigned int offset) 1711 { 1712 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1713 1714 rzg2l_gpio_set_direction(pctrl, offset, false); 1715 1716 return 0; 1717 } 1718 1719 static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, 1720 int value) 1721 { 1722 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1723 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1724 u64 *pin_data = pin_desc->drv_data; 1725 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1726 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1727 unsigned long flags; 1728 u8 reg8; 1729 1730 spin_lock_irqsave(&pctrl->lock, flags); 1731 1732 reg8 = readb(pctrl->base + P(off)); 1733 1734 if (value) 1735 writeb(reg8 | BIT(bit), pctrl->base + P(off)); 1736 else 1737 writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); 1738 1739 spin_unlock_irqrestore(&pctrl->lock, flags); 1740 } 1741 1742 static int rzg2l_gpio_direction_output(struct gpio_chip *chip, 1743 unsigned int offset, int value) 1744 { 1745 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1746 1747 rzg2l_gpio_set(chip, offset, value); 1748 rzg2l_gpio_set_direction(pctrl, offset, true); 1749 1750 return 0; 1751 } 1752 1753 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) 1754 { 1755 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1756 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1757 u64 *pin_data = pin_desc->drv_data; 1758 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1759 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1760 u16 reg16; 1761 1762 reg16 = readw(pctrl->base + PM(off)); 1763 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 1764 1765 if (reg16 == PM_INPUT) 1766 return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); 1767 else if (reg16 == PM_OUTPUT) 1768 return !!(readb(pctrl->base + P(off)) & BIT(bit)); 1769 else 1770 return -EINVAL; 1771 } 1772 1773 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) 1774 { 1775 unsigned int virq; 1776 1777 pinctrl_gpio_free(chip, offset); 1778 1779 virq = irq_find_mapping(chip->irq.domain, offset); 1780 if (virq) 1781 irq_dispose_mapping(virq); 1782 1783 /* 1784 * Set the GPIO as an input to ensure that the next GPIO request won't 1785 * drive the GPIO pin as an output. 1786 */ 1787 rzg2l_gpio_direction_input(chip, offset); 1788 } 1789 1790 static const char * const rzg2l_gpio_names[] = { 1791 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 1792 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 1793 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 1794 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 1795 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 1796 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 1797 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 1798 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 1799 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 1800 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 1801 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 1802 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 1803 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 1804 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 1805 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 1806 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 1807 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 1808 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 1809 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 1810 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 1811 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 1812 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 1813 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 1814 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 1815 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 1816 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 1817 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 1818 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 1819 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 1820 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 1821 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 1822 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 1823 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 1824 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 1825 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 1826 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 1827 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", 1828 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", 1829 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", 1830 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", 1831 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", 1832 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", 1833 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", 1834 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", 1835 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", 1836 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", 1837 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", 1838 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", 1839 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", 1840 }; 1841 1842 static const u64 r9a07g044_gpio_configs[] = { 1843 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), 1844 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), 1845 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), 1846 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), 1847 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), 1848 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), 1849 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), 1850 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), 1851 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), 1852 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), 1853 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), 1854 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1855 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1856 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1857 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1858 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1859 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1860 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), 1861 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), 1862 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), 1863 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), 1864 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1865 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1866 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1867 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1868 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1869 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1870 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1871 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1872 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), 1873 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1874 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1875 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1876 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1877 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1878 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1879 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1880 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1881 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), 1882 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), 1883 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), 1884 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), 1885 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), 1886 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), 1887 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), 1888 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), 1889 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), 1890 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), 1891 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), 1892 }; 1893 1894 static const u64 r9a07g043_gpio_configs[] = { 1895 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), 1896 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), 1897 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1898 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1899 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1900 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), 1901 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), 1902 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), 1903 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1904 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1905 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1906 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1907 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1908 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1909 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1910 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1911 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1912 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), 1913 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), 1914 #ifdef CONFIG_RISCV 1915 /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */ 1916 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 1917 PIN_CFG_NF | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */ 1918 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07), /* P20 */ 1919 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 1920 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */ 1921 RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 1922 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */ 1923 RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a), /* P23 */ 1924 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b), /* P24 */ 1925 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NF | 1926 PIN_CFG_NOGPIO_INT), /* P25 */ 1927 0x0, /* P26 */ 1928 0x0, /* P27 */ 1929 RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT), /* P28 */ 1930 #endif 1931 }; 1932 1933 static const u64 r9a08g045_gpio_configs[] = { 1934 RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ 1935 RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1936 PIN_CFG_IO_VMC_ETH0)) | 1937 PIN_CFG_OEN | PIN_CFG_IEN, /* P1 */ 1938 RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1939 PIN_CFG_IO_VMC_ETH0)), /* P2 */ 1940 RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1941 PIN_CFG_IO_VMC_ETH0)), /* P3 */ 1942 RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1943 PIN_CFG_IO_VMC_ETH0)), /* P4 */ 1944 RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */ 1945 RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */ 1946 RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1947 PIN_CFG_IO_VMC_ETH1)) | 1948 PIN_CFG_OEN | PIN_CFG_IEN, /* P7 */ 1949 RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1950 PIN_CFG_IO_VMC_ETH1)), /* P8 */ 1951 RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1952 PIN_CFG_IO_VMC_ETH1)), /* P9 */ 1953 RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1954 PIN_CFG_IO_VMC_ETH1)), /* P10 */ 1955 RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */ 1956 RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */ 1957 RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */ 1958 RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */ 1959 RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */ 1960 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */ 1961 RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */ 1962 RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */ 1963 }; 1964 1965 static const char * const rzv2h_gpio_names[] = { 1966 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", 1967 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", 1968 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", 1969 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", 1970 "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47", 1971 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", 1972 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", 1973 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", 1974 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", 1975 "P90", "P91", "P92", "P93", "P94", "P95", "P96", "P97", 1976 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", 1977 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", 1978 }; 1979 1980 static const u64 r9a09g057_gpio_configs[] = { 1981 RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */ 1982 RZG2L_GPIO_PORT_PACK(6, 0x21, RZV2H_MPXED_PIN_FUNCS), /* P1 */ 1983 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | 1984 PIN_CFG_NOD), /* P2 */ 1985 RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */ 1986 RZG2L_GPIO_PORT_PACK(8, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */ 1987 RZG2L_GPIO_PORT_PACK(8, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */ 1988 RZG2L_GPIO_PORT_PACK(8, 0x26, RZV2H_MPXED_PIN_FUNCS | 1989 PIN_CFG_ELC), /* P6 */ 1990 RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS), /* P7 */ 1991 RZG2L_GPIO_PORT_PACK(8, 0x28, RZV2H_MPXED_PIN_FUNCS | 1992 PIN_CFG_ELC), /* P8 */ 1993 RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS), /* P9 */ 1994 RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS), /* PA */ 1995 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x2b), /* PB */ 1996 }; 1997 1998 static const struct { 1999 struct rzg2l_dedicated_configs common[35]; 2000 struct rzg2l_dedicated_configs rzg2l_pins[7]; 2001 } rzg2l_dedicated_pins = { 2002 .common = { 2003 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) }, 2004 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, 2005 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 2006 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, 2007 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 2008 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, 2009 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, 2010 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, 2011 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 2012 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 2013 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2014 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, 2015 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 2016 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, 2017 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2018 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, 2019 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2020 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, 2021 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2022 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, 2023 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2024 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, 2025 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2026 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, 2027 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2028 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, 2029 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2030 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, 2031 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2032 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, 2033 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, 2034 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, 2035 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2036 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, 2037 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2038 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, 2039 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2040 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, 2041 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2042 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, 2043 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2044 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, 2045 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2046 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, 2047 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2048 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, 2049 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2050 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, 2051 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2052 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, 2053 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2054 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, 2055 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2056 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, 2057 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2058 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, 2059 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2060 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, 2061 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, 2062 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, 2063 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, 2064 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, 2065 }, 2066 .rzg2l_pins = { 2067 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2068 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, 2069 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2070 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, 2071 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2072 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, 2073 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2074 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, 2075 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2076 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, 2077 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2078 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, 2079 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2080 } 2081 }; 2082 2083 static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { 2084 { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, PIN_CFG_NF) }, 2085 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN | 2086 PIN_CFG_SOFT_PS)) }, 2087 { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) }, 2088 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) }, 2089 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, 2090 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2091 PIN_CFG_IO_VMC_SD0)) }, 2092 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, 2093 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2094 PIN_CFG_IO_VMC_SD0)) }, 2095 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2096 PIN_CFG_IO_VMC_SD0)) }, 2097 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2098 PIN_CFG_IO_VMC_SD0)) }, 2099 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2100 PIN_CFG_IO_VMC_SD0)) }, 2101 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2102 PIN_CFG_IO_VMC_SD0)) }, 2103 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2104 PIN_CFG_IO_VMC_SD0)) }, 2105 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2106 PIN_CFG_IO_VMC_SD0)) }, 2107 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2108 PIN_CFG_IO_VMC_SD0)) }, 2109 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) }, 2110 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2111 PIN_CFG_IO_VMC_SD1)) }, 2112 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2113 PIN_CFG_IO_VMC_SD1)) }, 2114 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2115 PIN_CFG_IO_VMC_SD1)) }, 2116 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2117 PIN_CFG_IO_VMC_SD1)) }, 2118 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2119 PIN_CFG_IO_VMC_SD1)) }, 2120 }; 2121 2122 static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = { 2123 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) }, 2124 { "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2125 PIN_CFG_IEN)) }, 2126 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2127 { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2128 PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2129 { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2130 PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2131 { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2132 PIN_CFG_PUPD)) }, 2133 { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2134 PIN_CFG_PUPD)) }, 2135 { "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2136 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2137 { "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2138 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2139 { "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2140 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2141 { "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2142 PIN_CFG_PUPD)) }, 2143 { "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2144 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2145 { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) }, 2146 { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) }, 2147 { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) }, 2148 { "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2149 PIN_CFG_PUPD)) }, 2150 { "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2151 PIN_CFG_PUPD)) }, 2152 { "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2153 PIN_CFG_PUPD)) }, 2154 { "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2155 PIN_CFG_PUPD)) }, 2156 { "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2157 PIN_CFG_PUPD)) }, 2158 { "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2159 PIN_CFG_PUPD)) }, 2160 { "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2161 PIN_CFG_PUPD)) }, 2162 { "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2163 PIN_CFG_PUPD)) }, 2164 { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2165 { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2166 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2167 { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2168 { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2169 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2170 { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2171 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2172 { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2173 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2174 { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2175 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2176 { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2177 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2178 { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2179 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2180 { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2181 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2182 { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2183 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2184 { "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2185 { "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2186 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2187 { "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2188 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2189 { "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2190 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2191 { "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2192 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2193 { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2194 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2195 { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2196 { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2197 { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2198 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2199 { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2200 PIN_CFG_PUPD)) }, 2201 { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) }, 2202 { "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2203 PIN_CFG_PUPD)) }, 2204 { "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2205 PIN_CFG_PUPD)) }, 2206 { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) }, 2207 { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) }, 2208 { "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2209 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2210 { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) }, 2211 { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) }, 2212 { "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2213 PIN_CFG_PUPD)) }, 2214 { "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2215 PIN_CFG_PUPD)) }, 2216 { "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2217 PIN_CFG_PUPD)) }, 2218 { "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2219 PIN_CFG_PUPD)) }, 2220 { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) }, 2221 { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) }, 2222 { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) }, 2223 { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) }, 2224 { "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2225 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2226 { "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2227 PIN_CFG_PUPD)) }, 2228 { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) }, 2229 { "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2230 PIN_CFG_PUPD)) }, 2231 { "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2232 PIN_CFG_PUPD)) }, 2233 { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) }, 2234 { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) }, 2235 { "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2236 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2237 { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) }, 2238 { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) }, 2239 { "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2240 PIN_CFG_PUPD)) }, 2241 { "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2242 PIN_CFG_PUPD)) }, 2243 { "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2244 PIN_CFG_PUPD)) }, 2245 { "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2246 PIN_CFG_PUPD)) }, 2247 { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) }, 2248 { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) }, 2249 { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) }, 2250 { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) }, 2251 }; 2252 2253 static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) 2254 { 2255 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; 2256 const struct rzg2l_pinctrl_data *data = pctrl->data; 2257 u64 *pin_data = pin_desc->drv_data; 2258 unsigned int gpioint; 2259 unsigned int i; 2260 u32 port, bit; 2261 2262 if (*pin_data & PIN_CFG_NOGPIO_INT) 2263 return -EINVAL; 2264 2265 port = virq / 8; 2266 bit = virq % 8; 2267 2268 if (port >= data->n_ports || 2269 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port]))) 2270 return -EINVAL; 2271 2272 gpioint = bit; 2273 for (i = 0; i < port; i++) 2274 gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i])); 2275 2276 return gpioint; 2277 } 2278 2279 static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, 2280 unsigned int hwirq, bool enable) 2281 { 2282 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; 2283 u64 *pin_data = pin_desc->drv_data; 2284 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 2285 u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 2286 unsigned long flags; 2287 void __iomem *addr; 2288 2289 addr = pctrl->base + ISEL(off); 2290 if (bit >= 4) { 2291 bit -= 4; 2292 addr += 4; 2293 } 2294 2295 spin_lock_irqsave(&pctrl->lock, flags); 2296 if (enable) 2297 writel(readl(addr) | BIT(bit * 8), addr); 2298 else 2299 writel(readl(addr) & ~BIT(bit * 8), addr); 2300 spin_unlock_irqrestore(&pctrl->lock, flags); 2301 } 2302 2303 static void rzg2l_gpio_irq_disable(struct irq_data *d) 2304 { 2305 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 2306 unsigned int hwirq = irqd_to_hwirq(d); 2307 2308 irq_chip_disable_parent(d); 2309 gpiochip_disable_irq(gc, hwirq); 2310 } 2311 2312 static void rzg2l_gpio_irq_enable(struct irq_data *d) 2313 { 2314 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 2315 unsigned int hwirq = irqd_to_hwirq(d); 2316 2317 gpiochip_enable_irq(gc, hwirq); 2318 irq_chip_enable_parent(d); 2319 } 2320 2321 static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) 2322 { 2323 return irq_chip_set_type_parent(d, type); 2324 } 2325 2326 static void rzg2l_gpio_irqc_eoi(struct irq_data *d) 2327 { 2328 irq_chip_eoi_parent(d); 2329 } 2330 2331 static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) 2332 { 2333 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 2334 2335 seq_puts(p, dev_name(gc->parent)); 2336 } 2337 2338 static int rzg2l_gpio_irq_set_wake(struct irq_data *data, unsigned int on) 2339 { 2340 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 2341 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 2342 int ret; 2343 2344 /* It should not happen. */ 2345 if (!data->parent_data) 2346 return -EOPNOTSUPP; 2347 2348 ret = irq_chip_set_wake_parent(data, on); 2349 if (ret) 2350 return ret; 2351 2352 if (on) 2353 atomic_inc(&pctrl->wakeup_path); 2354 else 2355 atomic_dec(&pctrl->wakeup_path); 2356 2357 return 0; 2358 } 2359 2360 static const struct irq_chip rzg2l_gpio_irqchip = { 2361 .name = "rzg2l-gpio", 2362 .irq_disable = rzg2l_gpio_irq_disable, 2363 .irq_enable = rzg2l_gpio_irq_enable, 2364 .irq_mask = irq_chip_mask_parent, 2365 .irq_unmask = irq_chip_unmask_parent, 2366 .irq_set_type = rzg2l_gpio_irq_set_type, 2367 .irq_eoi = rzg2l_gpio_irqc_eoi, 2368 .irq_print_chip = rzg2l_gpio_irq_print_chip, 2369 .irq_set_affinity = irq_chip_set_affinity_parent, 2370 .irq_set_wake = rzg2l_gpio_irq_set_wake, 2371 .flags = IRQCHIP_IMMUTABLE, 2372 GPIOCHIP_IRQ_RESOURCE_HELPERS, 2373 }; 2374 2375 static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigned int offset) 2376 { 2377 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 2378 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 2379 u64 *pin_data = pin_desc->drv_data; 2380 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 2381 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 2382 u8 reg8; 2383 int ret; 2384 2385 reg8 = readb(pctrl->base + PMC(off)); 2386 if (reg8 & BIT(bit)) { 2387 ret = rzg2l_gpio_request(chip, offset); 2388 if (ret) 2389 return ret; 2390 } 2391 2392 return rzg2l_gpio_direction_input(chip, offset); 2393 } 2394 2395 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 2396 unsigned int child, 2397 unsigned int child_type, 2398 unsigned int *parent, 2399 unsigned int *parent_type) 2400 { 2401 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 2402 unsigned long flags; 2403 int gpioint, irq; 2404 int ret; 2405 2406 gpioint = rzg2l_gpio_get_gpioint(child, pctrl); 2407 if (gpioint < 0) 2408 return gpioint; 2409 2410 ret = rzg2l_gpio_interrupt_input_mode(gc, child); 2411 if (ret) 2412 return ret; 2413 2414 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 2415 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); 2416 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 2417 if (irq < 0) { 2418 ret = -ENOSPC; 2419 goto err; 2420 } 2421 2422 rzg2l_gpio_irq_endisable(pctrl, child, true); 2423 pctrl->hwirq[irq] = child; 2424 irq += pctrl->data->hwcfg->tint_start_index; 2425 2426 /* All these interrupts are level high in the CPU */ 2427 *parent_type = IRQ_TYPE_LEVEL_HIGH; 2428 *parent = RZG2L_PACK_HWIRQ(gpioint, irq); 2429 return 0; 2430 2431 err: 2432 rzg2l_gpio_free(gc, child); 2433 return ret; 2434 } 2435 2436 static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) 2437 { 2438 struct irq_domain *domain = pctrl->gpio_chip.irq.domain; 2439 2440 for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 2441 struct irq_data *data; 2442 unsigned long flags; 2443 unsigned int virq; 2444 int ret; 2445 2446 if (!pctrl->hwirq[i]) 2447 continue; 2448 2449 virq = irq_find_mapping(domain, pctrl->hwirq[i]); 2450 if (!virq) { 2451 dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n", 2452 pctrl->hwirq[i]); 2453 continue; 2454 } 2455 2456 data = irq_domain_get_irq_data(domain, virq); 2457 if (!data) { 2458 dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq); 2459 continue; 2460 } 2461 2462 /* 2463 * This has to be atomically executed to protect against a concurrent 2464 * interrupt. 2465 */ 2466 spin_lock_irqsave(&pctrl->lock, flags); 2467 ret = rzg2l_gpio_irq_set_type(data, irqd_get_trigger_type(data)); 2468 if (!ret && !irqd_irq_disabled(data)) 2469 rzg2l_gpio_irq_enable(data); 2470 spin_unlock_irqrestore(&pctrl->lock, flags); 2471 2472 if (ret) 2473 dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq); 2474 } 2475 } 2476 2477 static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, 2478 unsigned int nr_irqs) 2479 { 2480 struct irq_data *d; 2481 2482 d = irq_domain_get_irq_data(domain, virq); 2483 if (d) { 2484 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 2485 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 2486 irq_hw_number_t hwirq = irqd_to_hwirq(d); 2487 unsigned long flags; 2488 unsigned int i; 2489 2490 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 2491 if (pctrl->hwirq[i] == hwirq) { 2492 rzg2l_gpio_irq_endisable(pctrl, hwirq, false); 2493 rzg2l_gpio_free(gc, hwirq); 2494 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 2495 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); 2496 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 2497 pctrl->hwirq[i] = 0; 2498 break; 2499 } 2500 } 2501 } 2502 irq_domain_free_irqs_common(domain, virq, nr_irqs); 2503 } 2504 2505 static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, 2506 unsigned long *valid_mask, 2507 unsigned int ngpios) 2508 { 2509 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 2510 struct gpio_chip *chip = &pctrl->gpio_chip; 2511 unsigned int offset; 2512 2513 /* Forbid unused lines to be mapped as IRQs */ 2514 for (offset = 0; offset < chip->ngpio; offset++) { 2515 u32 port, bit; 2516 2517 port = offset / 8; 2518 bit = offset % 8; 2519 2520 if (port >= pctrl->data->n_ports || 2521 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, 2522 pctrl->data->port_pin_configs[port]))) 2523 clear_bit(offset, valid_mask); 2524 } 2525 } 2526 2527 static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) 2528 { 2529 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 2530 struct rzg2l_pinctrl_reg_cache *cache, *dedicated_cache; 2531 2532 cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL); 2533 if (!cache) 2534 return -ENOMEM; 2535 2536 dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL); 2537 if (!dedicated_cache) 2538 return -ENOMEM; 2539 2540 cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL); 2541 if (!cache->p) 2542 return -ENOMEM; 2543 2544 cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL); 2545 if (!cache->pm) 2546 return -ENOMEM; 2547 2548 cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL); 2549 if (!cache->pmc) 2550 return -ENOMEM; 2551 2552 cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL); 2553 if (!cache->pfc) 2554 return -ENOMEM; 2555 2556 for (u8 i = 0; i < 2; i++) { 2557 u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; 2558 2559 cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]), 2560 GFP_KERNEL); 2561 if (!cache->iolh[i]) 2562 return -ENOMEM; 2563 2564 cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]), 2565 GFP_KERNEL); 2566 if (!cache->ien[i]) 2567 return -ENOMEM; 2568 2569 /* Allocate dedicated cache. */ 2570 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, 2571 sizeof(*dedicated_cache->iolh[i]), 2572 GFP_KERNEL); 2573 if (!dedicated_cache->iolh[i]) 2574 return -ENOMEM; 2575 2576 dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, 2577 sizeof(*dedicated_cache->ien[i]), 2578 GFP_KERNEL); 2579 if (!dedicated_cache->ien[i]) 2580 return -ENOMEM; 2581 } 2582 2583 pctrl->cache = cache; 2584 pctrl->dedicated_cache = dedicated_cache; 2585 2586 return 0; 2587 } 2588 2589 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) 2590 { 2591 struct device_node *np = pctrl->dev->of_node; 2592 struct gpio_chip *chip = &pctrl->gpio_chip; 2593 const char *name = dev_name(pctrl->dev); 2594 struct irq_domain *parent_domain; 2595 struct of_phandle_args of_args; 2596 struct device_node *parent_np; 2597 struct gpio_irq_chip *girq; 2598 int ret; 2599 2600 parent_np = of_irq_find_parent(np); 2601 if (!parent_np) 2602 return -ENXIO; 2603 2604 parent_domain = irq_find_host(parent_np); 2605 of_node_put(parent_np); 2606 if (!parent_domain) 2607 return -EPROBE_DEFER; 2608 2609 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); 2610 if (ret) 2611 return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n"); 2612 2613 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 2614 of_args.args[2] != pctrl->data->n_port_pins) 2615 return dev_err_probe(pctrl->dev, -EINVAL, 2616 "gpio-ranges does not match selected SOC\n"); 2617 2618 chip->names = pctrl->data->port_pins; 2619 chip->request = rzg2l_gpio_request; 2620 chip->free = rzg2l_gpio_free; 2621 chip->get_direction = rzg2l_gpio_get_direction; 2622 chip->direction_input = rzg2l_gpio_direction_input; 2623 chip->direction_output = rzg2l_gpio_direction_output; 2624 chip->get = rzg2l_gpio_get; 2625 chip->set = rzg2l_gpio_set; 2626 chip->label = name; 2627 chip->parent = pctrl->dev; 2628 chip->owner = THIS_MODULE; 2629 chip->base = -1; 2630 chip->ngpio = of_args.args[2]; 2631 2632 girq = &chip->irq; 2633 gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip); 2634 girq->fwnode = dev_fwnode(pctrl->dev); 2635 girq->parent_domain = parent_domain; 2636 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; 2637 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; 2638 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; 2639 girq->init_valid_mask = rzg2l_init_irq_valid_mask; 2640 2641 pctrl->gpio_range.id = 0; 2642 pctrl->gpio_range.pin_base = 0; 2643 pctrl->gpio_range.base = 0; 2644 pctrl->gpio_range.npins = chip->ngpio; 2645 pctrl->gpio_range.name = chip->label; 2646 pctrl->gpio_range.gc = chip; 2647 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 2648 if (ret) 2649 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n"); 2650 2651 dev_dbg(pctrl->dev, "Registered gpio controller\n"); 2652 2653 return 0; 2654 } 2655 2656 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) 2657 { 2658 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 2659 struct pinctrl_pin_desc *pins; 2660 unsigned int i, j; 2661 u64 *pin_data; 2662 int ret; 2663 2664 pctrl->desc.name = DRV_NAME; 2665 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; 2666 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; 2667 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; 2668 pctrl->desc.confops = &rzg2l_pinctrl_confops; 2669 pctrl->desc.owner = THIS_MODULE; 2670 if (pctrl->data->num_custom_params) { 2671 pctrl->desc.num_custom_params = pctrl->data->num_custom_params; 2672 pctrl->desc.custom_params = pctrl->data->custom_params; 2673 #ifdef CONFIG_DEBUG_FS 2674 pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items; 2675 #endif 2676 } 2677 2678 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); 2679 if (!pins) 2680 return -ENOMEM; 2681 2682 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, 2683 sizeof(*pin_data), GFP_KERNEL); 2684 if (!pin_data) 2685 return -ENOMEM; 2686 2687 pctrl->pins = pins; 2688 pctrl->desc.pins = pins; 2689 2690 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 2691 pins[i].number = i; 2692 pins[i].name = pctrl->data->port_pins[i]; 2693 if (i && !(i % RZG2L_PINS_PER_PORT)) 2694 j++; 2695 pin_data[i] = pctrl->data->port_pin_configs[j]; 2696 if (pin_data[i] & RZG2L_VARIABLE_CFG) 2697 pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, 2698 pin_data[i], 2699 j, 2700 i % RZG2L_PINS_PER_PORT); 2701 pins[i].drv_data = &pin_data[i]; 2702 } 2703 2704 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { 2705 unsigned int index = pctrl->data->n_port_pins + i; 2706 2707 pins[index].number = index; 2708 pins[index].name = pctrl->data->dedicated_pins[i].name; 2709 pin_data[index] = pctrl->data->dedicated_pins[i].config; 2710 pins[index].drv_data = &pin_data[index]; 2711 } 2712 2713 pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), 2714 GFP_KERNEL); 2715 if (!pctrl->settings) 2716 return -ENOMEM; 2717 2718 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { 2719 if (pin_data[i] & PIN_CFG_SOFT_PS) { 2720 pctrl->settings[i].power_source = 3300; 2721 } else { 2722 ret = rzg2l_get_power_source(pctrl, i, pin_data[i]); 2723 if (ret < 0) 2724 continue; 2725 pctrl->settings[i].power_source = ret; 2726 } 2727 } 2728 2729 ret = rzg2l_pinctrl_reg_cache_alloc(pctrl); 2730 if (ret) 2731 return ret; 2732 2733 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, 2734 &pctrl->pctl); 2735 if (ret) 2736 return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n"); 2737 2738 ret = pinctrl_enable(pctrl->pctl); 2739 if (ret) 2740 return dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n"); 2741 2742 ret = rzg2l_gpio_register(pctrl); 2743 if (ret) 2744 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n"); 2745 2746 return 0; 2747 } 2748 2749 static int rzg2l_pinctrl_probe(struct platform_device *pdev) 2750 { 2751 struct rzg2l_pinctrl *pctrl; 2752 int ret; 2753 2754 BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT > 2755 ARRAY_SIZE(rzg2l_gpio_names)); 2756 2757 BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > 2758 ARRAY_SIZE(rzg2l_gpio_names)); 2759 2760 BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > 2761 ARRAY_SIZE(rzg2l_gpio_names)); 2762 2763 BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT > 2764 ARRAY_SIZE(rzv2h_gpio_names)); 2765 2766 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 2767 if (!pctrl) 2768 return -ENOMEM; 2769 2770 pctrl->dev = &pdev->dev; 2771 2772 pctrl->data = of_device_get_match_data(&pdev->dev); 2773 if (!pctrl->data) 2774 return -EINVAL; 2775 2776 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 2777 if (IS_ERR(pctrl->base)) 2778 return PTR_ERR(pctrl->base); 2779 2780 pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL); 2781 if (IS_ERR(pctrl->clk)) { 2782 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk), 2783 "failed to enable GPIO clk\n"); 2784 } 2785 2786 spin_lock_init(&pctrl->lock); 2787 spin_lock_init(&pctrl->bitmap_lock); 2788 mutex_init(&pctrl->mutex); 2789 atomic_set(&pctrl->wakeup_path, 0); 2790 2791 platform_set_drvdata(pdev, pctrl); 2792 2793 ret = rzg2l_pinctrl_register(pctrl); 2794 if (ret) 2795 return ret; 2796 2797 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); 2798 return 0; 2799 } 2800 2801 static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend) 2802 { 2803 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 2804 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 2805 2806 for (u32 port = 0; port < nports; port++) { 2807 bool has_iolh, has_ien; 2808 u32 off, caps; 2809 u8 pincnt; 2810 u64 cfg; 2811 2812 cfg = pctrl->data->port_pin_configs[port]; 2813 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 2814 pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg)); 2815 2816 caps = FIELD_GET(PIN_CFG_MASK, cfg); 2817 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); 2818 has_ien = !!(caps & PIN_CFG_IEN); 2819 2820 if (suspend) 2821 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); 2822 2823 /* 2824 * Now cache the registers or set them in the order suggested by 2825 * HW manual (section "Operation for GPIO Function"). 2826 */ 2827 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); 2828 if (has_iolh) { 2829 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), 2830 cache->iolh[0][port]); 2831 if (pincnt >= 4) { 2832 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4, 2833 cache->iolh[1][port]); 2834 } 2835 } 2836 2837 RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]); 2838 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]); 2839 2840 if (has_ien) { 2841 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), 2842 cache->ien[0][port]); 2843 if (pincnt >= 4) { 2844 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4, 2845 cache->ien[1][port]); 2846 } 2847 } 2848 } 2849 } 2850 2851 static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) 2852 { 2853 struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; 2854 u32 caps; 2855 u32 i; 2856 2857 /* 2858 * Make sure entries in pctrl->data->n_dedicated_pins[] having the same 2859 * port offset are close together. 2860 */ 2861 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { 2862 bool has_iolh, has_ien; 2863 u32 off, next_off = 0; 2864 u64 cfg, next_cfg; 2865 u8 pincnt; 2866 2867 cfg = pctrl->data->dedicated_pins[i].config; 2868 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 2869 if (i + 1 < pctrl->data->n_dedicated_pins) { 2870 next_cfg = pctrl->data->dedicated_pins[i + 1].config; 2871 next_off = RZG2L_PIN_CFG_TO_PORT_OFFSET(next_cfg); 2872 } 2873 2874 if (off == next_off) { 2875 /* Gather caps of all port pins. */ 2876 caps |= FIELD_GET(PIN_CFG_MASK, cfg); 2877 continue; 2878 } 2879 2880 /* And apply them in a single shot. */ 2881 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); 2882 has_ien = !!(caps & PIN_CFG_IEN); 2883 pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg)); 2884 2885 if (has_iolh) { 2886 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), 2887 cache->iolh[0][i]); 2888 } 2889 if (has_ien) { 2890 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), 2891 cache->ien[0][i]); 2892 } 2893 2894 if (pincnt >= 4) { 2895 if (has_iolh) { 2896 RZG2L_PCTRL_REG_ACCESS32(suspend, 2897 pctrl->base + IOLH(off) + 4, 2898 cache->iolh[1][i]); 2899 } 2900 if (has_ien) { 2901 RZG2L_PCTRL_REG_ACCESS32(suspend, 2902 pctrl->base + IEN(off) + 4, 2903 cache->ien[1][i]); 2904 } 2905 } 2906 caps = 0; 2907 } 2908 } 2909 2910 static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) 2911 { 2912 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 2913 unsigned long flags; 2914 2915 spin_lock_irqsave(&pctrl->lock, flags); 2916 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); 2917 2918 /* Restore port registers. */ 2919 for (u32 port = 0; port < nports; port++) { 2920 unsigned long pinmap; 2921 u8 pmc = 0, max_pin; 2922 u32 off, pfc = 0; 2923 u64 cfg; 2924 u16 pm; 2925 u8 pin; 2926 2927 cfg = pctrl->data->port_pin_configs[port]; 2928 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 2929 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); 2930 max_pin = fls(pinmap); 2931 2932 pm = readw(pctrl->base + PM(off)); 2933 for_each_set_bit(pin, &pinmap, max_pin) { 2934 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 2935 2936 /* Nothing to do if PFC was not configured before. */ 2937 if (!(cache->pmc[port] & BIT(pin))) 2938 continue; 2939 2940 /* Set pin to 'Non-use (Hi-Z input protection)' */ 2941 pm &= ~(PM_MASK << (pin * 2)); 2942 writew(pm, pctrl->base + PM(off)); 2943 2944 /* Temporarily switch to GPIO mode with PMC register */ 2945 pmc &= ~BIT(pin); 2946 writeb(pmc, pctrl->base + PMC(off)); 2947 2948 /* Select Pin function mode. */ 2949 pfc &= ~(PFC_MASK << (pin * 4)); 2950 pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4))); 2951 writel(pfc, pctrl->base + PFC(off)); 2952 2953 /* Switch to Peripheral pin function. */ 2954 pmc |= BIT(pin); 2955 writeb(pmc, pctrl->base + PMC(off)); 2956 } 2957 } 2958 2959 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); 2960 spin_unlock_irqrestore(&pctrl->lock, flags); 2961 } 2962 2963 static int rzg2l_pinctrl_suspend_noirq(struct device *dev) 2964 { 2965 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); 2966 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 2967 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 2968 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 2969 2970 rzg2l_pinctrl_pm_setup_regs(pctrl, true); 2971 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true); 2972 2973 for (u8 i = 0; i < 2; i++) { 2974 if (regs->sd_ch) 2975 cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); 2976 if (regs->eth_poc) 2977 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); 2978 } 2979 2980 cache->qspi = readb(pctrl->base + QSPI); 2981 cache->eth_mode = readb(pctrl->base + ETH_MODE); 2982 2983 if (!atomic_read(&pctrl->wakeup_path)) 2984 clk_disable_unprepare(pctrl->clk); 2985 else 2986 device_set_wakeup_path(dev); 2987 2988 return 0; 2989 } 2990 2991 static int rzg2l_pinctrl_resume_noirq(struct device *dev) 2992 { 2993 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); 2994 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 2995 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 2996 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 2997 int ret; 2998 2999 if (!atomic_read(&pctrl->wakeup_path)) { 3000 ret = clk_prepare_enable(pctrl->clk); 3001 if (ret) 3002 return ret; 3003 } 3004 3005 writeb(cache->qspi, pctrl->base + QSPI); 3006 writeb(cache->eth_mode, pctrl->base + ETH_MODE); 3007 for (u8 i = 0; i < 2; i++) { 3008 if (regs->sd_ch) 3009 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); 3010 if (regs->eth_poc) 3011 writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); 3012 } 3013 3014 rzg2l_pinctrl_pm_setup_pfc(pctrl); 3015 rzg2l_pinctrl_pm_setup_regs(pctrl, false); 3016 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false); 3017 rzg2l_gpio_irq_restore(pctrl); 3018 3019 return 0; 3020 } 3021 3022 static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) 3023 { 3024 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 3025 3026 if (lock) { 3027 /* Set the PWPR register to be write-protected */ 3028 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 3029 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ 3030 } else { 3031 /* Set the PWPR register to allow PFC register to write */ 3032 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 3033 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ 3034 } 3035 } 3036 3037 static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) 3038 { 3039 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 3040 u8 pwpr; 3041 3042 if (lock) { 3043 /* Set the PWPR register to be write-protected */ 3044 pwpr = readb(pctrl->base + regs->pwpr); 3045 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); 3046 } else { 3047 /* Set the PWPR register to allow PFC and PMC register to write */ 3048 pwpr = readb(pctrl->base + regs->pwpr); 3049 writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr); 3050 } 3051 } 3052 3053 static const struct rzg2l_hwcfg rzg2l_hwcfg = { 3054 .regs = { 3055 .pwpr = 0x3014, 3056 .sd_ch = 0x3000, 3057 .eth_poc = 0x300c, 3058 }, 3059 .iolh_groupa_ua = { 3060 /* 3v3 power source */ 3061 [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000, 3062 }, 3063 .iolh_groupb_oi = { 100, 66, 50, 33, }, 3064 .tint_start_index = 9, 3065 .oen_max_pin = 0, 3066 }; 3067 3068 static const struct rzg2l_hwcfg rzg3s_hwcfg = { 3069 .regs = { 3070 .pwpr = 0x3000, 3071 .sd_ch = 0x3004, 3072 .eth_poc = 0x3010, 3073 }, 3074 .iolh_groupa_ua = { 3075 /* 1v8 power source */ 3076 [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000, 3077 /* 3v3 power source */ 3078 [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000, 3079 }, 3080 .iolh_groupb_ua = { 3081 /* 1v8 power source */ 3082 [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000, 3083 /* 3v3 power source */ 3084 [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000, 3085 }, 3086 .iolh_groupc_ua = { 3087 /* 1v8 power source */ 3088 [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800, 3089 /* 2v5 source */ 3090 [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100, 3091 /* 3v3 power source */ 3092 [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050, 3093 }, 3094 .tint_start_index = 9, 3095 .drive_strength_ua = true, 3096 .func_base = 1, 3097 .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */ 3098 .oen_max_port = 7, /* P7_1 is the maximum OEN port. */ 3099 }; 3100 3101 static const struct rzg2l_hwcfg rzv2h_hwcfg = { 3102 .regs = { 3103 .pwpr = 0x3c04, 3104 }, 3105 .tint_start_index = 17, 3106 }; 3107 3108 static struct rzg2l_pinctrl_data r9a07g043_data = { 3109 .port_pins = rzg2l_gpio_names, 3110 .port_pin_configs = r9a07g043_gpio_configs, 3111 .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs), 3112 .dedicated_pins = rzg2l_dedicated_pins.common, 3113 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, 3114 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), 3115 .hwcfg = &rzg2l_hwcfg, 3116 #ifdef CONFIG_RISCV 3117 .variable_pin_cfg = r9a07g043f_variable_pin_cfg, 3118 .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg), 3119 #endif 3120 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3121 .pmc_writeb = &rzg2l_pmc_writeb, 3122 .oen_read = &rzg2l_read_oen, 3123 .oen_write = &rzg2l_write_oen, 3124 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3125 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3126 }; 3127 3128 static struct rzg2l_pinctrl_data r9a07g044_data = { 3129 .port_pins = rzg2l_gpio_names, 3130 .port_pin_configs = r9a07g044_gpio_configs, 3131 .n_ports = ARRAY_SIZE(r9a07g044_gpio_configs), 3132 .dedicated_pins = rzg2l_dedicated_pins.common, 3133 .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT, 3134 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + 3135 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), 3136 .hwcfg = &rzg2l_hwcfg, 3137 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3138 .pmc_writeb = &rzg2l_pmc_writeb, 3139 .oen_read = &rzg2l_read_oen, 3140 .oen_write = &rzg2l_write_oen, 3141 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3142 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3143 }; 3144 3145 static struct rzg2l_pinctrl_data r9a08g045_data = { 3146 .port_pins = rzg2l_gpio_names, 3147 .port_pin_configs = r9a08g045_gpio_configs, 3148 .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs), 3149 .dedicated_pins = rzg3s_dedicated_pins, 3150 .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT, 3151 .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins), 3152 .hwcfg = &rzg3s_hwcfg, 3153 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3154 .pmc_writeb = &rzg2l_pmc_writeb, 3155 .oen_read = &rzg3s_oen_read, 3156 .oen_write = &rzg3s_oen_write, 3157 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3158 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3159 }; 3160 3161 static struct rzg2l_pinctrl_data r9a09g057_data = { 3162 .port_pins = rzv2h_gpio_names, 3163 .port_pin_configs = r9a09g057_gpio_configs, 3164 .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs), 3165 .dedicated_pins = rzv2h_dedicated_pins, 3166 .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT, 3167 .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins), 3168 .hwcfg = &rzv2h_hwcfg, 3169 .variable_pin_cfg = r9a09g057_variable_pin_cfg, 3170 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg), 3171 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), 3172 .custom_params = renesas_rzv2h_custom_bindings, 3173 #ifdef CONFIG_DEBUG_FS 3174 .custom_conf_items = renesas_rzv2h_conf_items, 3175 #endif 3176 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, 3177 .pmc_writeb = &rzv2h_pmc_writeb, 3178 .oen_read = &rzv2h_oen_read, 3179 .oen_write = &rzv2h_oen_write, 3180 .hw_to_bias_param = &rzv2h_hw_to_bias_param, 3181 .bias_param_to_hw = &rzv2h_bias_param_to_hw, 3182 }; 3183 3184 static const struct of_device_id rzg2l_pinctrl_of_table[] = { 3185 { 3186 .compatible = "renesas,r9a07g043-pinctrl", 3187 .data = &r9a07g043_data, 3188 }, 3189 { 3190 .compatible = "renesas,r9a07g044-pinctrl", 3191 .data = &r9a07g044_data, 3192 }, 3193 { 3194 .compatible = "renesas,r9a08g045-pinctrl", 3195 .data = &r9a08g045_data, 3196 }, 3197 { 3198 .compatible = "renesas,r9a09g057-pinctrl", 3199 .data = &r9a09g057_data, 3200 }, 3201 { /* sentinel */ } 3202 }; 3203 3204 static const struct dev_pm_ops rzg2l_pinctrl_pm_ops = { 3205 NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg2l_pinctrl_suspend_noirq, rzg2l_pinctrl_resume_noirq) 3206 }; 3207 3208 static struct platform_driver rzg2l_pinctrl_driver = { 3209 .driver = { 3210 .name = DRV_NAME, 3211 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), 3212 .pm = pm_sleep_ptr(&rzg2l_pinctrl_pm_ops), 3213 }, 3214 .probe = rzg2l_pinctrl_probe, 3215 }; 3216 3217 static int __init rzg2l_pinctrl_init(void) 3218 { 3219 return platform_driver_register(&rzg2l_pinctrl_driver); 3220 } 3221 core_initcall(rzg2l_pinctrl_init); 3222 3223 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 3224 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); 3225