1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G2L Pin Control and GPIO driver core 4 * 5 * Copyright (C) 2021 Renesas Electronics Corporation. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of.h> 17 #include <linux/of_irq.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/seq_file.h> 21 #include <linux/spinlock.h> 22 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinctrl.h> 27 #include <linux/pinctrl/pinmux.h> 28 29 #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h> 30 #include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h> 31 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 32 33 #include "../core.h" 34 #include "../pinconf.h" 35 #include "../pinmux.h" 36 37 #define DRV_NAME "pinctrl-rzg2l" 38 39 /* 40 * Use 16 lower bits [15:0] for pin identifier 41 * Use 16 higher bits [31:16] for pin mux function 42 */ 43 #define MUX_PIN_ID_MASK GENMASK(15, 0) 44 #define MUX_FUNC_MASK GENMASK(31, 16) 45 46 /* PIN capabilities */ 47 #define PIN_CFG_IOLH_A BIT(0) 48 #define PIN_CFG_IOLH_B BIT(1) 49 #define PIN_CFG_SR BIT(2) 50 #define PIN_CFG_IEN BIT(3) 51 #define PIN_CFG_PUPD BIT(4) 52 #define PIN_CFG_IO_VMC_SD0 BIT(5) 53 #define PIN_CFG_IO_VMC_SD1 BIT(6) 54 #define PIN_CFG_IO_VMC_QSPI BIT(7) 55 #define PIN_CFG_IO_VMC_ETH0 BIT(8) 56 #define PIN_CFG_IO_VMC_ETH1 BIT(9) 57 #define PIN_CFG_NF BIT(10) /* Digital noise filter */ 58 #define PIN_CFG_IOLH_C BIT(11) 59 #define PIN_CFG_SOFT_PS BIT(12) 60 #define PIN_CFG_OEN BIT(13) 61 #define PIN_CFG_NOGPIO_INT BIT(14) 62 #define PIN_CFG_NOD BIT(15) /* N-ch Open Drain */ 63 #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */ 64 #define PIN_CFG_ELC BIT(17) 65 #define PIN_CFG_IOLH_RZV2H BIT(18) 66 67 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ 68 #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ 69 70 #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ 71 (PIN_CFG_IOLH_##group | \ 72 PIN_CFG_PUPD | \ 73 PIN_CFG_NF) 74 75 #define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \ 76 PIN_CFG_SR) 77 78 #define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \ 79 PIN_CFG_SOFT_PS) 80 81 #define RZV2H_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | \ 82 PIN_CFG_NOD | \ 83 PIN_CFG_SR | \ 84 PIN_CFG_SMT) 85 86 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF) 87 88 #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54) 89 #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46) 90 #define PIN_CFG_MASK GENMASK_ULL(31, 0) 91 92 /* 93 * m indicates the bitmap of supported pins, a is the register index 94 * and f is pin configuration capabilities supported. 95 */ 96 #define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \ 97 FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ 98 FIELD_PREP_CONST(PIN_CFG_MASK, (f))) 99 #define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a) \ 100 (RZG2L_VARIABLE_CFG | \ 101 RZG2L_GPIO_PORT_SPARSE_PACK(m, a, 0)) 102 103 /* 104 * n indicates number of pins in the port, a is the register index 105 * and f is pin configuration capabilities supported. 106 */ 107 #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f)) 108 #define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a) (RZG2L_VARIABLE_CFG | \ 109 RZG2L_GPIO_PORT_PACK(n, a, 0)) 110 111 #define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56) 112 #define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53) 113 /* 114 * p is the register index while referencing to SR/IEN/IOLH/FILxx 115 * registers, b is the register bits (b * 8) and f is the pin 116 * configuration capabilities supported. 117 */ 118 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ 119 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \ 120 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \ 121 FIELD_PREP_CONST(PIN_CFG_MASK, (f))) 122 123 #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ 124 FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \ 125 FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg))) 126 127 #define VARIABLE_PIN_CFG_PIN_MASK GENMASK_ULL(54, 52) 128 #define VARIABLE_PIN_CFG_PORT_MASK GENMASK_ULL(51, 47) 129 #define RZG2L_VARIABLE_PIN_CFG_PACK(port, pin, cfg) \ 130 (FIELD_PREP_CONST(VARIABLE_PIN_CFG_PIN_MASK, (pin)) | \ 131 FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \ 132 FIELD_PREP_CONST(PIN_CFG_MASK, (cfg))) 133 134 #define P(off) (0x0000 + (off)) 135 #define PM(off) (0x0100 + (off) * 2) 136 #define PMC(off) (0x0200 + (off)) 137 #define PFC(off) (0x0400 + (off) * 4) 138 #define PIN(off) (0x0800 + (off)) 139 #define IOLH(off) (0x1000 + (off) * 8) 140 #define SR(off) (0x1400 + (off) * 8) 141 #define IEN(off) (0x1800 + (off) * 8) 142 #define PUPD(off) (0x1C00 + (off) * 8) 143 #define ISEL(off) (0x2C00 + (off) * 8) 144 #define NOD(off) (0x3000 + (off) * 8) 145 #define SMT(off) (0x3400 + (off) * 8) 146 #define SD_CH(off, ch) ((off) + (ch) * 4) 147 #define ETH_POC(off, ch) ((off) + (ch) * 4) 148 #define QSPI (0x3008) 149 150 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ 151 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ 152 #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ 153 154 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ 155 #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ 156 #define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable on RZ/V2H(P) */ 157 #define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */ 158 159 #define PM_MASK 0x03 160 #define PFC_MASK 0x0f 161 #define IEN_MASK 0x01 162 #define IOLH_MASK 0x03 163 #define SR_MASK 0x01 164 #define PUPD_MASK 0x03 165 #define NOD_MASK 0x01 166 #define SMT_MASK 0x01 167 168 #define PM_INPUT 0x1 169 #define PM_OUTPUT 0x2 170 171 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) 172 #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) 173 174 #define RZG2L_TINT_MAX_INTERRUPT 32 175 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) 176 177 /* Custom pinconf parameters */ 178 #define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE (PIN_CONFIG_END + 1) 179 180 static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = { 181 { "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 }, 182 }; 183 184 #ifdef CONFIG_DEBUG_FS 185 static const struct pin_config_item renesas_rzv2h_conf_items[] = { 186 PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true), 187 }; 188 #endif 189 190 /* Read/write 8 bits register */ 191 #define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \ 192 do { \ 193 if (_read) \ 194 _val = readb(_addr); \ 195 else \ 196 writeb(_val, _addr); \ 197 } while (0) 198 199 /* Read/write 16 bits register */ 200 #define RZG2L_PCTRL_REG_ACCESS16(_read, _addr, _val) \ 201 do { \ 202 if (_read) \ 203 _val = readw(_addr); \ 204 else \ 205 writew(_val, _addr); \ 206 } while (0) 207 208 /* Read/write 32 bits register */ 209 #define RZG2L_PCTRL_REG_ACCESS32(_read, _addr, _val) \ 210 do { \ 211 if (_read) \ 212 _val = readl(_addr); \ 213 else \ 214 writel(_val, _addr); \ 215 } while (0) 216 217 /** 218 * struct rzg2l_register_offsets - specific register offsets 219 * @pwpr: PWPR register offset 220 * @sd_ch: SD_CH register offset 221 * @eth_poc: ETH_POC register offset 222 * @oen: OEN register offset 223 */ 224 struct rzg2l_register_offsets { 225 u16 pwpr; 226 u16 sd_ch; 227 u16 eth_poc; 228 u16 oen; 229 }; 230 231 /** 232 * enum rzg2l_iolh_index - starting indices in IOLH specific arrays 233 * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source 234 * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source 235 * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source 236 * @RZG2L_IOLH_IDX_MAX: maximum index 237 */ 238 enum rzg2l_iolh_index { 239 RZG2L_IOLH_IDX_1V8 = 0, 240 RZG2L_IOLH_IDX_2V5 = 4, 241 RZG2L_IOLH_IDX_3V3 = 8, 242 RZG2L_IOLH_IDX_MAX = 12, 243 }; 244 245 /* Maximum number of driver strength entries per power source. */ 246 #define RZG2L_IOLH_MAX_DS_ENTRIES (4) 247 248 /** 249 * struct rzg2l_hwcfg - hardware configuration data structure 250 * @regs: hardware specific register offsets 251 * @iolh_groupa_ua: IOLH group A uA specific values 252 * @iolh_groupb_ua: IOLH group B uA specific values 253 * @iolh_groupc_ua: IOLH group C uA specific values 254 * @iolh_groupb_oi: IOLH group B output impedance specific values 255 * @tint_start_index: the start index for the TINT interrupts 256 * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) 257 * @oen_pwpr_lock: flag indicating if the OEN register is locked by PWPR 258 * @func_base: base number for port function (see register PFC) 259 * @oen_max_pin: the maximum pin number supporting output enable 260 * @oen_max_port: the maximum port number supporting output enable 261 */ 262 struct rzg2l_hwcfg { 263 const struct rzg2l_register_offsets regs; 264 u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; 265 u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; 266 u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; 267 u16 iolh_groupb_oi[4]; 268 u16 tint_start_index; 269 bool drive_strength_ua; 270 bool oen_pwpr_lock; 271 u8 func_base; 272 u8 oen_max_pin; 273 u8 oen_max_port; 274 }; 275 276 struct rzg2l_dedicated_configs { 277 const char *name; 278 u64 config; 279 }; 280 281 struct rzg2l_pinctrl; 282 283 struct rzg2l_pinctrl_data { 284 const char * const *port_pins; 285 const u64 *port_pin_configs; 286 unsigned int n_ports; 287 const struct rzg2l_dedicated_configs *dedicated_pins; 288 unsigned int n_port_pins; 289 unsigned int n_dedicated_pins; 290 const struct rzg2l_hwcfg *hwcfg; 291 const u64 *variable_pin_cfg; 292 unsigned int n_variable_pin_cfg; 293 unsigned int num_custom_params; 294 const struct pinconf_generic_params *custom_params; 295 #ifdef CONFIG_DEBUG_FS 296 const struct pin_config_item *custom_conf_items; 297 #endif 298 void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock); 299 void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset); 300 int (*pin_to_oen_bit)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); 301 int (*hw_to_bias_param)(unsigned int val); 302 int (*bias_param_to_hw)(enum pin_config_param param); 303 }; 304 305 /** 306 * struct rzg2l_pinctrl_pin_settings - pin data 307 * @power_source: power source 308 * @drive_strength_ua: drive strength (in micro amps) 309 */ 310 struct rzg2l_pinctrl_pin_settings { 311 u16 power_source; 312 u16 drive_strength_ua; 313 }; 314 315 /** 316 * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume) 317 * @p: P registers cache 318 * @pm: PM registers cache 319 * @pmc: PMC registers cache 320 * @pfc: PFC registers cache 321 * @iolh: IOLH registers cache 322 * @pupd: PUPD registers cache 323 * @ien: IEN registers cache 324 * @smt: SMT registers cache 325 * @sd_ch: SD_CH registers cache 326 * @eth_poc: ET_POC registers cache 327 * @oen: Output Enable register cache 328 * @qspi: QSPI registers cache 329 */ 330 struct rzg2l_pinctrl_reg_cache { 331 u8 *p; 332 u16 *pm; 333 u8 *pmc; 334 u32 *pfc; 335 u32 *iolh[2]; 336 u32 *ien[2]; 337 u32 *pupd[2]; 338 u32 *smt; 339 u8 sd_ch[2]; 340 u8 eth_poc[2]; 341 u8 oen; 342 u8 qspi; 343 }; 344 345 struct rzg2l_pinctrl { 346 struct pinctrl_dev *pctl; 347 struct pinctrl_desc desc; 348 struct pinctrl_pin_desc *pins; 349 350 const struct rzg2l_pinctrl_data *data; 351 void __iomem *base; 352 struct device *dev; 353 354 struct clk *clk; 355 356 struct gpio_chip gpio_chip; 357 struct pinctrl_gpio_range gpio_range; 358 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); 359 spinlock_t bitmap_lock; /* protect tint_slot bitmap */ 360 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; 361 362 spinlock_t lock; /* lock read/write registers */ 363 struct mutex mutex; /* serialize adding groups and functions */ 364 365 struct rzg2l_pinctrl_pin_settings *settings; 366 struct rzg2l_pinctrl_reg_cache *cache; 367 struct rzg2l_pinctrl_reg_cache *dedicated_cache; 368 atomic_t wakeup_path; 369 }; 370 371 static const u16 available_ps[] = { 1800, 2500, 3300 }; 372 373 static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, 374 u64 pincfg, 375 unsigned int port, 376 u8 pin) 377 { 378 unsigned int i; 379 380 for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { 381 u64 cfg = pctrl->data->variable_pin_cfg[i]; 382 383 if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port && 384 FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin) 385 return (pincfg & ~RZG2L_VARIABLE_CFG) | FIELD_GET(PIN_CFG_MASK, cfg); 386 } 387 388 return 0; 389 } 390 391 static const u64 r9a09g047_variable_pin_cfg[] = { 392 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 393 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS), 394 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 2, RZV2H_MPXED_PIN_FUNCS), 395 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 3, RZV2H_MPXED_PIN_FUNCS), 396 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 4, RZV2H_MPXED_PIN_FUNCS), 397 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS), 398 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS), 399 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS), 400 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 0, RZV2H_MPXED_PIN_FUNCS), 401 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 402 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 2, RZV2H_MPXED_PIN_FUNCS), 403 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 3, RZV2H_MPXED_PIN_FUNCS), 404 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 4, RZV2H_MPXED_PIN_FUNCS), 405 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 5, RZV2H_MPXED_PIN_FUNCS), 406 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 6, RZV2H_MPXED_PIN_FUNCS), 407 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 7, RZV2H_MPXED_PIN_FUNCS), 408 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 409 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS), 410 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS), 411 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 3, RZV2H_MPXED_PIN_FUNCS), 412 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 4, RZV2H_MPXED_PIN_FUNCS), 413 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS), 414 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS), 415 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS), 416 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 0, RZV2H_MPXED_PIN_FUNCS), 417 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 418 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 2, RZV2H_MPXED_PIN_FUNCS), 419 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 3, RZV2H_MPXED_PIN_FUNCS), 420 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 4, RZV2H_MPXED_PIN_FUNCS), 421 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 5, RZV2H_MPXED_PIN_FUNCS), 422 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 6, RZV2H_MPXED_PIN_FUNCS), 423 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 7, RZV2H_MPXED_PIN_FUNCS), 424 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS), 425 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 426 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 427 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 428 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 429 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 430 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 6, RZV2H_MPXED_PIN_FUNCS), 431 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 7, RZV2H_MPXED_PIN_FUNCS), 432 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 0, RZV2H_MPXED_PIN_FUNCS), 433 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 434 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 435 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 436 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 437 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 438 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 439 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 1, RZV2H_MPXED_PIN_FUNCS), 440 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS), 441 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS), 442 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS), 443 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 444 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 445 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 446 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 3, RZV2H_MPXED_PIN_FUNCS), 447 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 448 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 5, RZV2H_MPXED_PIN_FUNCS), 449 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 6, RZV2H_MPXED_PIN_FUNCS), 450 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 7, RZV2H_MPXED_PIN_FUNCS), 451 }; 452 453 static const u64 r9a09g057_variable_pin_cfg[] = { 454 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 0, RZV2H_MPXED_PIN_FUNCS), 455 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 456 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 457 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 458 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 459 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 460 }; 461 462 #ifdef CONFIG_RISCV 463 static const u64 r9a07g043f_variable_pin_cfg[] = { 464 RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 465 PIN_CFG_NF | 466 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 467 RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 468 PIN_CFG_NF | 469 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 470 RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 471 PIN_CFG_NF | 472 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 473 RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 474 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 475 RZG2L_VARIABLE_PIN_CFG_PACK(20, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 476 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 477 RZG2L_VARIABLE_PIN_CFG_PACK(20, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 478 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 479 RZG2L_VARIABLE_PIN_CFG_PACK(20, 6, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 480 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 481 RZG2L_VARIABLE_PIN_CFG_PACK(20, 7, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 482 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 483 RZG2L_VARIABLE_PIN_CFG_PACK(23, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 484 PIN_CFG_NOGPIO_INT), 485 RZG2L_VARIABLE_PIN_CFG_PACK(23, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 486 PIN_CFG_NOGPIO_INT), 487 RZG2L_VARIABLE_PIN_CFG_PACK(23, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 488 PIN_CFG_NOGPIO_INT), 489 RZG2L_VARIABLE_PIN_CFG_PACK(23, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 490 PIN_CFG_NOGPIO_INT), 491 RZG2L_VARIABLE_PIN_CFG_PACK(23, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT), 492 RZG2L_VARIABLE_PIN_CFG_PACK(24, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT), 493 RZG2L_VARIABLE_PIN_CFG_PACK(24, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 494 PIN_CFG_NOGPIO_INT), 495 RZG2L_VARIABLE_PIN_CFG_PACK(24, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 496 PIN_CFG_NOGPIO_INT), 497 RZG2L_VARIABLE_PIN_CFG_PACK(24, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 498 PIN_CFG_NOGPIO_INT), 499 RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 500 PIN_CFG_NOGPIO_INT), 501 RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 502 PIN_CFG_NF | 503 PIN_CFG_NOGPIO_INT), 504 }; 505 #endif 506 507 static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) 508 { 509 writeb(val, pctrl->base + offset); 510 } 511 512 static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) 513 { 514 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 515 u8 pwpr; 516 517 pwpr = readb(pctrl->base + regs->pwpr); 518 writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr); 519 writeb(val, pctrl->base + offset); 520 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); 521 } 522 523 static int rzg2l_validate_pin(struct rzg2l_pinctrl *pctrl, 524 u64 cfg, u32 port, u8 bit) 525 { 526 u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); 527 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 528 u64 data; 529 530 if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) 531 return -EINVAL; 532 533 data = pctrl->data->port_pin_configs[port]; 534 if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data)) 535 return -EINVAL; 536 537 return 0; 538 } 539 540 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, 541 u8 pin, u8 off, u8 func) 542 { 543 unsigned long flags; 544 u32 reg; 545 546 spin_lock_irqsave(&pctrl->lock, flags); 547 548 /* Set pin to 'Non-use (Hi-Z input protection)' */ 549 reg = readw(pctrl->base + PM(off)); 550 reg &= ~(PM_MASK << (pin * 2)); 551 writew(reg, pctrl->base + PM(off)); 552 553 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); 554 555 /* Temporarily switch to GPIO mode with PMC register */ 556 reg = readb(pctrl->base + PMC(off)); 557 writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); 558 559 /* Select Pin function mode with PFC register */ 560 reg = readl(pctrl->base + PFC(off)); 561 reg &= ~(PFC_MASK << (pin * 4)); 562 writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); 563 564 /* Switch to Peripheral pin function with PMC register */ 565 reg = readb(pctrl->base + PMC(off)); 566 writeb(reg | BIT(pin), pctrl->base + PMC(off)); 567 568 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); 569 570 spin_unlock_irqrestore(&pctrl->lock, flags); 571 }; 572 573 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, 574 unsigned int func_selector, 575 unsigned int group_selector) 576 { 577 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 578 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 579 const struct function_desc *func; 580 unsigned int i, *psel_val; 581 struct group_desc *group; 582 const unsigned int *pins; 583 int ret; 584 585 func = pinmux_generic_get_function(pctldev, func_selector); 586 if (!func) 587 return -EINVAL; 588 group = pinctrl_generic_get_group(pctldev, group_selector); 589 if (!group) 590 return -EINVAL; 591 592 psel_val = func->data; 593 pins = group->grp.pins; 594 595 for (i = 0; i < group->grp.npins; i++) { 596 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; 597 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 598 u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); 599 600 ret = rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(pins[i]), pin); 601 if (ret) 602 return ret; 603 604 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", 605 RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); 606 607 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); 608 } 609 610 return 0; 611 }; 612 613 static int rzg2l_map_add_config(struct pinctrl_map *map, 614 const char *group_or_pin, 615 enum pinctrl_map_type type, 616 unsigned long *configs, 617 unsigned int num_configs) 618 { 619 unsigned long *cfgs; 620 621 cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL); 622 if (!cfgs) 623 return -ENOMEM; 624 625 map->type = type; 626 map->data.configs.group_or_pin = group_or_pin; 627 map->data.configs.configs = cfgs; 628 map->data.configs.num_configs = num_configs; 629 630 return 0; 631 } 632 633 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, 634 struct device_node *np, 635 struct device_node *parent, 636 struct pinctrl_map **map, 637 unsigned int *num_maps, 638 unsigned int *index) 639 { 640 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 641 struct pinctrl_map *maps = *map; 642 unsigned int nmaps = *num_maps; 643 unsigned long *configs = NULL; 644 unsigned int *pins, *psel_val; 645 unsigned int num_pinmux = 0; 646 unsigned int idx = *index; 647 unsigned int num_pins, i; 648 unsigned int num_configs; 649 struct property *pinmux; 650 struct property *prop; 651 int ret, gsel, fsel; 652 const char **pin_fn; 653 const char *name; 654 const char *pin; 655 656 pinmux = of_find_property(np, "pinmux", NULL); 657 if (pinmux) 658 num_pinmux = pinmux->length / sizeof(u32); 659 660 ret = of_property_count_strings(np, "pins"); 661 if (ret == -EINVAL) { 662 num_pins = 0; 663 } else if (ret < 0) { 664 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 665 return ret; 666 } else { 667 num_pins = ret; 668 } 669 670 if (!num_pinmux && !num_pins) 671 return 0; 672 673 if (num_pinmux && num_pins) { 674 dev_err(pctrl->dev, 675 "DT node must contain either a pinmux or pins and not both\n"); 676 return -EINVAL; 677 } 678 679 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); 680 if (ret < 0) 681 return ret; 682 683 if (num_pins && !num_configs) { 684 dev_err(pctrl->dev, "DT node must contain a config\n"); 685 ret = -ENODEV; 686 goto done; 687 } 688 689 if (num_pinmux) { 690 nmaps += 1; 691 if (num_configs) 692 nmaps += 1; 693 } 694 695 if (num_pins) 696 nmaps += num_pins; 697 698 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 699 if (!maps) { 700 ret = -ENOMEM; 701 goto done; 702 } 703 704 *map = maps; 705 *num_maps = nmaps; 706 if (num_pins) { 707 of_property_for_each_string(np, "pins", prop, pin) { 708 ret = rzg2l_map_add_config(&maps[idx], pin, 709 PIN_MAP_TYPE_CONFIGS_PIN, 710 configs, num_configs); 711 if (ret < 0) 712 goto done; 713 714 idx++; 715 } 716 ret = 0; 717 goto done; 718 } 719 720 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 721 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 722 GFP_KERNEL); 723 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 724 if (!pins || !psel_val || !pin_fn) { 725 ret = -ENOMEM; 726 goto done; 727 } 728 729 /* Collect pin locations and mux settings from DT properties */ 730 for (i = 0; i < num_pinmux; ++i) { 731 u32 value; 732 733 ret = of_property_read_u32_index(np, "pinmux", i, &value); 734 if (ret) 735 goto done; 736 pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value); 737 psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value); 738 } 739 740 if (parent) { 741 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", 742 parent, np); 743 if (!name) { 744 ret = -ENOMEM; 745 goto done; 746 } 747 } else { 748 name = np->name; 749 } 750 751 if (num_configs) { 752 ret = rzg2l_map_add_config(&maps[idx], name, 753 PIN_MAP_TYPE_CONFIGS_GROUP, 754 configs, num_configs); 755 if (ret < 0) 756 goto done; 757 758 idx++; 759 } 760 761 mutex_lock(&pctrl->mutex); 762 763 /* Register a single pin group listing all the pins we read from DT */ 764 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL); 765 if (gsel < 0) { 766 ret = gsel; 767 goto unlock; 768 } 769 770 /* 771 * Register a single group function where the 'data' is an array PSEL 772 * register values read from DT. 773 */ 774 pin_fn[0] = name; 775 fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val); 776 if (fsel < 0) { 777 ret = fsel; 778 goto remove_group; 779 } 780 781 mutex_unlock(&pctrl->mutex); 782 783 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 784 maps[idx].data.mux.group = name; 785 maps[idx].data.mux.function = name; 786 idx++; 787 788 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 789 ret = 0; 790 goto done; 791 792 remove_group: 793 pinctrl_generic_remove_group(pctldev, gsel); 794 unlock: 795 mutex_unlock(&pctrl->mutex); 796 done: 797 *index = idx; 798 kfree(configs); 799 return ret; 800 } 801 802 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, 803 struct pinctrl_map *map, 804 unsigned int num_maps) 805 { 806 unsigned int i; 807 808 if (!map) 809 return; 810 811 for (i = 0; i < num_maps; ++i) { 812 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 813 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 814 kfree(map[i].data.configs.configs); 815 } 816 kfree(map); 817 } 818 819 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, 820 struct device_node *np, 821 struct pinctrl_map **map, 822 unsigned int *num_maps) 823 { 824 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 825 unsigned int index; 826 int ret; 827 828 *map = NULL; 829 *num_maps = 0; 830 index = 0; 831 832 for_each_child_of_node_scoped(np, child) { 833 ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map, 834 num_maps, &index); 835 if (ret < 0) 836 goto done; 837 } 838 839 if (*num_maps == 0) { 840 ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map, 841 num_maps, &index); 842 if (ret < 0) 843 goto done; 844 } 845 846 if (*num_maps) 847 return 0; 848 849 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 850 ret = -EINVAL; 851 852 done: 853 rzg2l_dt_free_map(pctldev, *map, *num_maps); 854 855 return ret; 856 } 857 858 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 859 u8 bit, u32 mask) 860 { 861 void __iomem *addr = pctrl->base + offset; 862 863 /* handle _L/_H for 32-bit register read/write */ 864 if (bit >= 4) { 865 bit -= 4; 866 addr += 4; 867 } 868 869 return (readl(addr) >> (bit * 8)) & mask; 870 } 871 872 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 873 u8 bit, u32 mask, u32 val) 874 { 875 void __iomem *addr = pctrl->base + offset; 876 unsigned long flags; 877 u32 reg; 878 879 /* handle _L/_H for 32-bit register read/write */ 880 if (bit >= 4) { 881 bit -= 4; 882 addr += 4; 883 } 884 885 spin_lock_irqsave(&pctrl->lock, flags); 886 reg = readl(addr) & ~(mask << (bit * 8)); 887 writel(reg | (val << (bit * 8)), addr); 888 spin_unlock_irqrestore(&pctrl->lock, flags); 889 } 890 891 static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps) 892 { 893 if (caps & PIN_CFG_IO_VMC_SD0) 894 return SD_CH(regs->sd_ch, 0); 895 if (caps & PIN_CFG_IO_VMC_SD1) 896 return SD_CH(regs->sd_ch, 1); 897 if (caps & PIN_CFG_IO_VMC_ETH0) 898 return ETH_POC(regs->eth_poc, 0); 899 if (caps & PIN_CFG_IO_VMC_ETH1) 900 return ETH_POC(regs->eth_poc, 1); 901 if (caps & PIN_CFG_IO_VMC_QSPI) 902 return QSPI; 903 904 return -EINVAL; 905 } 906 907 static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) 908 { 909 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 910 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 911 int pwr_reg; 912 u8 val; 913 914 if (caps & PIN_CFG_SOFT_PS) 915 return pctrl->settings[pin].power_source; 916 917 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); 918 if (pwr_reg < 0) 919 return pwr_reg; 920 921 val = readb(pctrl->base + pwr_reg); 922 switch (val) { 923 case PVDD_1800: 924 return 1800; 925 case PVDD_2500: 926 return 2500; 927 case PVDD_3300: 928 return 3300; 929 default: 930 /* Should not happen. */ 931 return -EINVAL; 932 } 933 } 934 935 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) 936 { 937 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 938 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 939 int pwr_reg; 940 u8 val; 941 942 if (caps & PIN_CFG_SOFT_PS) { 943 pctrl->settings[pin].power_source = ps; 944 return 0; 945 } 946 947 switch (ps) { 948 case 1800: 949 val = PVDD_1800; 950 break; 951 case 2500: 952 if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) 953 return -EINVAL; 954 val = PVDD_2500; 955 break; 956 case 3300: 957 val = PVDD_3300; 958 break; 959 default: 960 return -EINVAL; 961 } 962 963 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); 964 if (pwr_reg < 0) 965 return pwr_reg; 966 967 writeb(val, pctrl->base + pwr_reg); 968 pctrl->settings[pin].power_source = ps; 969 970 return 0; 971 } 972 973 static bool rzg2l_ps_is_supported(u16 ps) 974 { 975 unsigned int i; 976 977 for (i = 0; i < ARRAY_SIZE(available_ps); i++) { 978 if (available_ps[i] == ps) 979 return true; 980 } 981 982 return false; 983 } 984 985 static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps) 986 { 987 unsigned int i; 988 989 for (i = 0; i < ARRAY_SIZE(available_ps); i++) { 990 if (available_ps[i] == ps) 991 break; 992 } 993 994 /* 995 * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have 996 * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source 997 */ 998 return i * RZG2L_IOLH_MAX_DS_ENTRIES; 999 } 1000 1001 static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val) 1002 { 1003 if (caps & PIN_CFG_IOLH_A) 1004 return hwcfg->iolh_groupa_ua[val]; 1005 1006 if (caps & PIN_CFG_IOLH_B) 1007 return hwcfg->iolh_groupb_ua[val]; 1008 1009 if (caps & PIN_CFG_IOLH_C) 1010 return hwcfg->iolh_groupc_ua[val]; 1011 1012 /* Should not happen. */ 1013 return 0; 1014 } 1015 1016 static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps, 1017 enum rzg2l_iolh_index ps_index, u16 ua) 1018 { 1019 const u16 *array = NULL; 1020 unsigned int i; 1021 1022 if (caps & PIN_CFG_IOLH_A) 1023 array = &hwcfg->iolh_groupa_ua[ps_index]; 1024 1025 if (caps & PIN_CFG_IOLH_B) 1026 array = &hwcfg->iolh_groupb_ua[ps_index]; 1027 1028 if (caps & PIN_CFG_IOLH_C) 1029 array = &hwcfg->iolh_groupc_ua[ps_index]; 1030 1031 if (!array) 1032 return -EINVAL; 1033 1034 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { 1035 if (array[i] == ua) 1036 return i; 1037 } 1038 1039 return -EINVAL; 1040 } 1041 1042 static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, 1043 enum rzg2l_iolh_index iolh_idx, 1044 u16 ds) 1045 { 1046 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1047 const u16 *array = NULL; 1048 unsigned int i; 1049 1050 if (caps & PIN_CFG_IOLH_A) 1051 array = hwcfg->iolh_groupa_ua; 1052 1053 if (caps & PIN_CFG_IOLH_B) 1054 array = hwcfg->iolh_groupb_ua; 1055 1056 if (caps & PIN_CFG_IOLH_C) 1057 array = hwcfg->iolh_groupc_ua; 1058 1059 /* Should not happen. */ 1060 if (!array) 1061 return false; 1062 1063 if (!array[iolh_idx]) 1064 return false; 1065 1066 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { 1067 if (array[iolh_idx + i] == ds) 1068 return true; 1069 } 1070 1071 return false; 1072 } 1073 1074 static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1075 { 1076 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; 1077 u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data); 1078 u8 pin = RZG2L_PIN_ID_TO_PIN(_pin); 1079 1080 if (pin > pctrl->data->hwcfg->oen_max_pin) 1081 return -EINVAL; 1082 1083 /* 1084 * We can determine which Ethernet interface we're dealing with from 1085 * the caps. 1086 */ 1087 if (caps & PIN_CFG_IO_VMC_ETH0) 1088 return 0; 1089 if (caps & PIN_CFG_IO_VMC_ETH1) 1090 return 1; 1091 1092 return -EINVAL; 1093 } 1094 1095 static int rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1096 { 1097 int bit; 1098 1099 if (!pctrl->data->pin_to_oen_bit) 1100 return -EOPNOTSUPP; 1101 1102 bit = pctrl->data->pin_to_oen_bit(pctrl, _pin); 1103 if (bit < 0) 1104 return -EINVAL; 1105 1106 return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); 1107 } 1108 1109 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) 1110 { 1111 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 1112 u16 oen_offset = pctrl->data->hwcfg->regs.oen; 1113 unsigned long flags; 1114 u8 val, pwpr; 1115 int bit; 1116 1117 if (!pctrl->data->pin_to_oen_bit) 1118 return -EOPNOTSUPP; 1119 1120 bit = pctrl->data->pin_to_oen_bit(pctrl, _pin); 1121 if (bit < 0) 1122 return -EINVAL; 1123 1124 spin_lock_irqsave(&pctrl->lock, flags); 1125 val = readb(pctrl->base + oen_offset); 1126 if (oen) 1127 val &= ~BIT(bit); 1128 else 1129 val |= BIT(bit); 1130 if (pctrl->data->hwcfg->oen_pwpr_lock) { 1131 pwpr = readb(pctrl->base + regs->pwpr); 1132 writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); 1133 } 1134 writeb(val, pctrl->base + oen_offset); 1135 if (pctrl->data->hwcfg->oen_pwpr_lock) 1136 writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); 1137 spin_unlock_irqrestore(&pctrl->lock, flags); 1138 1139 return 0; 1140 } 1141 1142 static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1143 { 1144 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; 1145 u8 port, pin, bit; 1146 1147 if (*pin_data & RZG2L_SINGLE_PIN) 1148 return -EINVAL; 1149 1150 port = RZG2L_PIN_ID_TO_PORT(_pin); 1151 pin = RZG2L_PIN_ID_TO_PIN(_pin); 1152 if (pin > pctrl->data->hwcfg->oen_max_pin) 1153 return -EINVAL; 1154 1155 bit = pin * 2; 1156 if (port == pctrl->data->hwcfg->oen_max_port) 1157 bit += 1; 1158 1159 return bit; 1160 } 1161 1162 static int rzg2l_hw_to_bias_param(unsigned int bias) 1163 { 1164 switch (bias) { 1165 case 0: 1166 return PIN_CONFIG_BIAS_DISABLE; 1167 case 1: 1168 return PIN_CONFIG_BIAS_PULL_UP; 1169 case 2: 1170 return PIN_CONFIG_BIAS_PULL_DOWN; 1171 default: 1172 break; 1173 } 1174 1175 return -EINVAL; 1176 } 1177 1178 static int rzg2l_bias_param_to_hw(enum pin_config_param param) 1179 { 1180 switch (param) { 1181 case PIN_CONFIG_BIAS_DISABLE: 1182 return 0; 1183 case PIN_CONFIG_BIAS_PULL_UP: 1184 return 1; 1185 case PIN_CONFIG_BIAS_PULL_DOWN: 1186 return 2; 1187 default: 1188 break; 1189 } 1190 1191 return -EINVAL; 1192 } 1193 1194 static int rzv2h_hw_to_bias_param(unsigned int bias) 1195 { 1196 switch (bias) { 1197 case 0: 1198 case 1: 1199 return PIN_CONFIG_BIAS_DISABLE; 1200 case 2: 1201 return PIN_CONFIG_BIAS_PULL_DOWN; 1202 case 3: 1203 return PIN_CONFIG_BIAS_PULL_UP; 1204 default: 1205 break; 1206 } 1207 1208 return -EINVAL; 1209 } 1210 1211 static int rzv2h_bias_param_to_hw(enum pin_config_param param) 1212 { 1213 switch (param) { 1214 case PIN_CONFIG_BIAS_DISABLE: 1215 return 0; 1216 case PIN_CONFIG_BIAS_PULL_DOWN: 1217 return 2; 1218 case PIN_CONFIG_BIAS_PULL_UP: 1219 return 3; 1220 default: 1221 break; 1222 } 1223 1224 return -EINVAL; 1225 } 1226 1227 static int rzg2l_pin_names_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin, 1228 const char * const pin_names[], unsigned int count) 1229 { 1230 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin]; 1231 unsigned int i; 1232 1233 for (i = 0; i < count; i++) { 1234 if (!strcmp(pin_desc->name, pin_names[i])) 1235 return i; 1236 } 1237 1238 return -EINVAL; 1239 } 1240 1241 static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1242 { 1243 static const char * const pin_names[] = { 1244 "ET0_TXC_TXCLK", "ET1_TXC_TXCLK", "XSPI0_RESET0N", 1245 "XSPI0_CS0N", "XSPI0_CKN", "XSPI0_CKP" 1246 }; 1247 1248 return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_names)); 1249 } 1250 1251 static int rzg3e_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1252 { 1253 static const char * const pin_names[] = { 1254 "PB1", "PE1", "PL4", "PL1", "PL2", "PL0" 1255 }; 1256 1257 return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_names)); 1258 } 1259 1260 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 1261 unsigned int _pin, 1262 unsigned long *config) 1263 { 1264 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1265 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1266 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 1267 u32 param = pinconf_to_config_param(*config); 1268 u64 *pin_data = pin->drv_data; 1269 unsigned int arg = 0; 1270 u32 off; 1271 u32 cfg; 1272 int ret; 1273 u8 bit; 1274 1275 if (!pin_data) 1276 return -EINVAL; 1277 1278 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1279 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); 1280 if (*pin_data & RZG2L_SINGLE_PIN) { 1281 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); 1282 } else { 1283 bit = RZG2L_PIN_ID_TO_PIN(_pin); 1284 1285 if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 1286 return -EINVAL; 1287 } 1288 1289 switch (param) { 1290 case PIN_CONFIG_INPUT_ENABLE: 1291 if (!(cfg & PIN_CFG_IEN)) 1292 return -EINVAL; 1293 arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK); 1294 if (!arg) 1295 return -EINVAL; 1296 break; 1297 1298 case PIN_CONFIG_OUTPUT_ENABLE: 1299 if (!(cfg & PIN_CFG_OEN)) 1300 return -EINVAL; 1301 ret = rzg2l_read_oen(pctrl, _pin); 1302 if (ret < 0) 1303 return ret; 1304 arg = ret; 1305 break; 1306 1307 case PIN_CONFIG_POWER_SOURCE: 1308 ret = rzg2l_get_power_source(pctrl, _pin, cfg); 1309 if (ret < 0) 1310 return ret; 1311 arg = ret; 1312 break; 1313 1314 case PIN_CONFIG_SLEW_RATE: 1315 if (!(cfg & PIN_CFG_SR)) 1316 return -EINVAL; 1317 1318 arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK); 1319 break; 1320 1321 case PIN_CONFIG_BIAS_DISABLE: 1322 case PIN_CONFIG_BIAS_PULL_UP: 1323 case PIN_CONFIG_BIAS_PULL_DOWN: 1324 if (!(cfg & PIN_CFG_PUPD)) 1325 return -EINVAL; 1326 1327 arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK); 1328 ret = pctrl->data->hw_to_bias_param(arg); 1329 if (ret < 0) 1330 return ret; 1331 1332 if (ret != param) 1333 return -EINVAL; 1334 /* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */ 1335 arg = 1; 1336 break; 1337 1338 case PIN_CONFIG_DRIVE_STRENGTH: { 1339 unsigned int index; 1340 1341 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) 1342 return -EINVAL; 1343 1344 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1345 /* 1346 * Drive strenght mA is supported only by group A and only 1347 * for 3V3 port source. 1348 */ 1349 arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; 1350 break; 1351 } 1352 1353 case PIN_CONFIG_DRIVE_STRENGTH_UA: { 1354 enum rzg2l_iolh_index iolh_idx; 1355 u8 val; 1356 1357 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || 1358 !hwcfg->drive_strength_ua) 1359 return -EINVAL; 1360 1361 ret = rzg2l_get_power_source(pctrl, _pin, cfg); 1362 if (ret < 0) 1363 return ret; 1364 iolh_idx = rzg2l_ps_to_iolh_idx(ret); 1365 val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1366 arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val); 1367 break; 1368 } 1369 1370 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 1371 unsigned int index; 1372 1373 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) 1374 return -EINVAL; 1375 1376 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1377 arg = hwcfg->iolh_groupb_oi[index]; 1378 break; 1379 } 1380 1381 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1382 case PIN_CONFIG_DRIVE_PUSH_PULL: 1383 if (!(cfg & PIN_CFG_NOD)) 1384 return -EINVAL; 1385 1386 arg = rzg2l_read_pin_config(pctrl, NOD(off), bit, NOD_MASK); 1387 if (!arg && param != PIN_CONFIG_DRIVE_PUSH_PULL) 1388 return -EINVAL; 1389 if (arg && param != PIN_CONFIG_DRIVE_OPEN_DRAIN) 1390 return -EINVAL; 1391 break; 1392 1393 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1394 if (!(cfg & PIN_CFG_SMT)) 1395 return -EINVAL; 1396 1397 arg = rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK); 1398 if (!arg) 1399 return -EINVAL; 1400 break; 1401 1402 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: 1403 if (!(cfg & PIN_CFG_IOLH_RZV2H)) 1404 return -EINVAL; 1405 1406 arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1407 break; 1408 1409 default: 1410 return -ENOTSUPP; 1411 } 1412 1413 *config = pinconf_to_config_packed(param, arg); 1414 1415 return 0; 1416 }; 1417 1418 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 1419 unsigned int _pin, 1420 unsigned long *_configs, 1421 unsigned int num_configs) 1422 { 1423 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1424 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 1425 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1426 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; 1427 u64 *pin_data = pin->drv_data; 1428 unsigned int i, arg, index; 1429 u32 off, param; 1430 u32 cfg; 1431 int ret; 1432 u8 bit; 1433 1434 if (!pin_data) 1435 return -EINVAL; 1436 1437 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1438 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); 1439 if (*pin_data & RZG2L_SINGLE_PIN) { 1440 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); 1441 } else { 1442 bit = RZG2L_PIN_ID_TO_PIN(_pin); 1443 1444 if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 1445 return -EINVAL; 1446 } 1447 1448 for (i = 0; i < num_configs; i++) { 1449 param = pinconf_to_config_param(_configs[i]); 1450 arg = pinconf_to_config_argument(_configs[i]); 1451 switch (param) { 1452 case PIN_CONFIG_INPUT_ENABLE: 1453 1454 if (!(cfg & PIN_CFG_IEN)) 1455 return -EINVAL; 1456 1457 rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); 1458 break; 1459 1460 case PIN_CONFIG_OUTPUT_ENABLE: 1461 if (!(cfg & PIN_CFG_OEN)) 1462 return -EINVAL; 1463 ret = rzg2l_write_oen(pctrl, _pin, !!arg); 1464 if (ret) 1465 return ret; 1466 break; 1467 1468 case PIN_CONFIG_POWER_SOURCE: 1469 settings.power_source = arg; 1470 break; 1471 1472 case PIN_CONFIG_SLEW_RATE: 1473 if (!(cfg & PIN_CFG_SR) || arg > 1) 1474 return -EINVAL; 1475 1476 rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg); 1477 break; 1478 1479 case PIN_CONFIG_BIAS_DISABLE: 1480 case PIN_CONFIG_BIAS_PULL_UP: 1481 case PIN_CONFIG_BIAS_PULL_DOWN: 1482 if (!(cfg & PIN_CFG_PUPD)) 1483 return -EINVAL; 1484 1485 ret = pctrl->data->bias_param_to_hw(param); 1486 if (ret < 0) 1487 return ret; 1488 1489 rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, ret); 1490 break; 1491 1492 case PIN_CONFIG_DRIVE_STRENGTH: 1493 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) 1494 return -EINVAL; 1495 1496 for (index = RZG2L_IOLH_IDX_3V3; 1497 index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) { 1498 if (arg == (hwcfg->iolh_groupa_ua[index] / 1000)) 1499 break; 1500 } 1501 if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES)) 1502 return -EINVAL; 1503 1504 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); 1505 break; 1506 1507 case PIN_CONFIG_DRIVE_STRENGTH_UA: 1508 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || 1509 !hwcfg->drive_strength_ua) 1510 return -EINVAL; 1511 1512 settings.drive_strength_ua = arg; 1513 break; 1514 1515 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: 1516 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) 1517 return -EINVAL; 1518 1519 for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { 1520 if (arg == hwcfg->iolh_groupb_oi[index]) 1521 break; 1522 } 1523 if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi)) 1524 return -EINVAL; 1525 1526 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); 1527 break; 1528 1529 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1530 case PIN_CONFIG_DRIVE_PUSH_PULL: 1531 if (!(cfg & PIN_CFG_NOD)) 1532 return -EINVAL; 1533 1534 rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK, 1535 param == PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0); 1536 break; 1537 1538 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1539 if (!(cfg & PIN_CFG_SMT)) 1540 return -EINVAL; 1541 1542 rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, arg); 1543 break; 1544 1545 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: 1546 if (!(cfg & PIN_CFG_IOLH_RZV2H)) 1547 return -EINVAL; 1548 1549 if (arg > 3) 1550 return -EINVAL; 1551 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg); 1552 break; 1553 1554 default: 1555 return -EOPNOTSUPP; 1556 } 1557 } 1558 1559 /* Apply power source. */ 1560 if (settings.power_source != pctrl->settings[_pin].power_source) { 1561 ret = rzg2l_ps_is_supported(settings.power_source); 1562 if (!ret) 1563 return -EINVAL; 1564 1565 /* Apply power source. */ 1566 ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source); 1567 if (ret) 1568 return ret; 1569 } 1570 1571 /* Apply drive strength. */ 1572 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { 1573 enum rzg2l_iolh_index iolh_idx; 1574 int val; 1575 1576 iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source); 1577 ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx, 1578 settings.drive_strength_ua); 1579 if (!ret) 1580 return -EINVAL; 1581 1582 /* Get register value for this PS/DS tuple. */ 1583 val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua); 1584 if (val < 0) 1585 return val; 1586 1587 /* Apply drive strength. */ 1588 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val); 1589 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; 1590 } 1591 1592 return 0; 1593 } 1594 1595 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, 1596 unsigned int group, 1597 unsigned long *configs, 1598 unsigned int num_configs) 1599 { 1600 const unsigned int *pins; 1601 unsigned int i, npins; 1602 int ret; 1603 1604 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 1605 if (ret) 1606 return ret; 1607 1608 for (i = 0; i < npins; i++) { 1609 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, 1610 num_configs); 1611 if (ret) 1612 return ret; 1613 } 1614 1615 return 0; 1616 }; 1617 1618 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, 1619 unsigned int group, 1620 unsigned long *config) 1621 { 1622 const unsigned int *pins; 1623 unsigned int i, npins, prev_config = 0; 1624 int ret; 1625 1626 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 1627 if (ret) 1628 return ret; 1629 1630 for (i = 0; i < npins; i++) { 1631 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); 1632 if (ret) 1633 return ret; 1634 1635 /* Check config matching between to pin */ 1636 if (i && prev_config != *config) 1637 return -EOPNOTSUPP; 1638 1639 prev_config = *config; 1640 } 1641 1642 return 0; 1643 }; 1644 1645 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { 1646 .get_groups_count = pinctrl_generic_get_group_count, 1647 .get_group_name = pinctrl_generic_get_group_name, 1648 .get_group_pins = pinctrl_generic_get_group_pins, 1649 .dt_node_to_map = rzg2l_dt_node_to_map, 1650 .dt_free_map = rzg2l_dt_free_map, 1651 }; 1652 1653 static const struct pinmux_ops rzg2l_pinctrl_pmxops = { 1654 .get_functions_count = pinmux_generic_get_function_count, 1655 .get_function_name = pinmux_generic_get_function_name, 1656 .get_function_groups = pinmux_generic_get_function_groups, 1657 .set_mux = rzg2l_pinctrl_set_mux, 1658 .strict = true, 1659 }; 1660 1661 static const struct pinconf_ops rzg2l_pinctrl_confops = { 1662 .is_generic = true, 1663 .pin_config_get = rzg2l_pinctrl_pinconf_get, 1664 .pin_config_set = rzg2l_pinctrl_pinconf_set, 1665 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set, 1666 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get, 1667 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1668 }; 1669 1670 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) 1671 { 1672 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1673 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1674 u64 *pin_data = pin_desc->drv_data; 1675 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1676 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 1677 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1678 unsigned long flags; 1679 u8 reg8; 1680 int ret; 1681 1682 ret = rzg2l_validate_pin(pctrl, *pin_data, port, bit); 1683 if (ret) 1684 return ret; 1685 1686 ret = pinctrl_gpio_request(chip, offset); 1687 if (ret) 1688 return ret; 1689 1690 spin_lock_irqsave(&pctrl->lock, flags); 1691 1692 /* Select GPIO mode in PMC Register */ 1693 reg8 = readb(pctrl->base + PMC(off)); 1694 reg8 &= ~BIT(bit); 1695 pctrl->data->pmc_writeb(pctrl, reg8, PMC(off)); 1696 1697 spin_unlock_irqrestore(&pctrl->lock, flags); 1698 1699 return 0; 1700 } 1701 1702 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, 1703 bool output) 1704 { 1705 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1706 u64 *pin_data = pin_desc->drv_data; 1707 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1708 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1709 unsigned long flags; 1710 u16 reg16; 1711 1712 spin_lock_irqsave(&pctrl->lock, flags); 1713 1714 reg16 = readw(pctrl->base + PM(off)); 1715 reg16 &= ~(PM_MASK << (bit * 2)); 1716 1717 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); 1718 writew(reg16, pctrl->base + PM(off)); 1719 1720 spin_unlock_irqrestore(&pctrl->lock, flags); 1721 } 1722 1723 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1724 { 1725 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1726 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1727 u64 *pin_data = pin_desc->drv_data; 1728 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1729 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1730 1731 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { 1732 u16 reg16; 1733 1734 reg16 = readw(pctrl->base + PM(off)); 1735 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 1736 if (reg16 == PM_OUTPUT) 1737 return GPIO_LINE_DIRECTION_OUT; 1738 } 1739 1740 return GPIO_LINE_DIRECTION_IN; 1741 } 1742 1743 static int rzg2l_gpio_direction_input(struct gpio_chip *chip, 1744 unsigned int offset) 1745 { 1746 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1747 1748 rzg2l_gpio_set_direction(pctrl, offset, false); 1749 1750 return 0; 1751 } 1752 1753 static int rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, 1754 int value) 1755 { 1756 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1757 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1758 u64 *pin_data = pin_desc->drv_data; 1759 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1760 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1761 unsigned long flags; 1762 u8 reg8; 1763 1764 spin_lock_irqsave(&pctrl->lock, flags); 1765 1766 reg8 = readb(pctrl->base + P(off)); 1767 1768 if (value) 1769 writeb(reg8 | BIT(bit), pctrl->base + P(off)); 1770 else 1771 writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); 1772 1773 spin_unlock_irqrestore(&pctrl->lock, flags); 1774 1775 return 0; 1776 } 1777 1778 static int rzg2l_gpio_direction_output(struct gpio_chip *chip, 1779 unsigned int offset, int value) 1780 { 1781 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1782 1783 rzg2l_gpio_set(chip, offset, value); 1784 rzg2l_gpio_set_direction(pctrl, offset, true); 1785 1786 return 0; 1787 } 1788 1789 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) 1790 { 1791 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1792 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1793 u64 *pin_data = pin_desc->drv_data; 1794 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1795 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1796 u16 reg16; 1797 1798 reg16 = readw(pctrl->base + PM(off)); 1799 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 1800 1801 if (reg16 == PM_INPUT) 1802 return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); 1803 else if (reg16 == PM_OUTPUT) 1804 return !!(readb(pctrl->base + P(off)) & BIT(bit)); 1805 else 1806 return -EINVAL; 1807 } 1808 1809 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) 1810 { 1811 unsigned int virq; 1812 1813 pinctrl_gpio_free(chip, offset); 1814 1815 virq = irq_find_mapping(chip->irq.domain, offset); 1816 if (virq) 1817 irq_dispose_mapping(virq); 1818 1819 /* 1820 * Set the GPIO as an input to ensure that the next GPIO request won't 1821 * drive the GPIO pin as an output. 1822 */ 1823 rzg2l_gpio_direction_input(chip, offset); 1824 } 1825 1826 static const char * const rzg2l_gpio_names[] = { 1827 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 1828 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 1829 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 1830 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 1831 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 1832 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 1833 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 1834 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 1835 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 1836 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 1837 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 1838 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 1839 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 1840 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 1841 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 1842 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 1843 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 1844 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 1845 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 1846 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 1847 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 1848 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 1849 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 1850 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 1851 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 1852 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 1853 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 1854 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 1855 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 1856 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 1857 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 1858 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 1859 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 1860 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 1861 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 1862 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 1863 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", 1864 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", 1865 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", 1866 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", 1867 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", 1868 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", 1869 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", 1870 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", 1871 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", 1872 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", 1873 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", 1874 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", 1875 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", 1876 }; 1877 1878 static const u64 r9a07g044_gpio_configs[] = { 1879 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), 1880 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), 1881 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), 1882 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), 1883 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), 1884 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), 1885 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), 1886 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), 1887 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), 1888 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), 1889 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), 1890 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1891 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1892 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1893 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1894 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1895 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1896 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), 1897 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), 1898 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), 1899 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), 1900 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1901 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1902 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1903 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1904 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1905 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1906 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1907 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1908 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), 1909 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1910 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1911 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1912 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1913 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1914 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1915 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1916 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1917 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), 1918 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), 1919 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), 1920 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), 1921 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), 1922 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), 1923 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), 1924 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), 1925 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), 1926 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), 1927 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), 1928 }; 1929 1930 static const u64 r9a07g043_gpio_configs[] = { 1931 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), 1932 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), 1933 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1934 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1935 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1936 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), 1937 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), 1938 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), 1939 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1940 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1941 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1942 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1943 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1944 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1945 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1946 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1947 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1948 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), 1949 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), 1950 #ifdef CONFIG_RISCV 1951 /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */ 1952 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 1953 PIN_CFG_NF | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */ 1954 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07), /* P20 */ 1955 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 1956 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */ 1957 RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 1958 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */ 1959 RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a), /* P23 */ 1960 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b), /* P24 */ 1961 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NF | 1962 PIN_CFG_NOGPIO_INT), /* P25 */ 1963 0x0, /* P26 */ 1964 0x0, /* P27 */ 1965 RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT), /* P28 */ 1966 #endif 1967 }; 1968 1969 static const u64 r9a08g045_gpio_configs[] = { 1970 RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ 1971 RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1972 PIN_CFG_IO_VMC_ETH0)) | 1973 PIN_CFG_OEN | PIN_CFG_IEN, /* P1 */ 1974 RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1975 PIN_CFG_IO_VMC_ETH0)), /* P2 */ 1976 RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1977 PIN_CFG_IO_VMC_ETH0)), /* P3 */ 1978 RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1979 PIN_CFG_IO_VMC_ETH0)), /* P4 */ 1980 RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */ 1981 RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */ 1982 RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1983 PIN_CFG_IO_VMC_ETH1)) | 1984 PIN_CFG_OEN | PIN_CFG_IEN, /* P7 */ 1985 RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1986 PIN_CFG_IO_VMC_ETH1)), /* P8 */ 1987 RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1988 PIN_CFG_IO_VMC_ETH1)), /* P9 */ 1989 RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1990 PIN_CFG_IO_VMC_ETH1)), /* P10 */ 1991 RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */ 1992 RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */ 1993 RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */ 1994 RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */ 1995 RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */ 1996 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */ 1997 RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */ 1998 RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */ 1999 }; 2000 2001 static const char * const rzg3e_gpio_names[] = { 2002 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", 2003 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", 2004 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", 2005 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", 2006 "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47", 2007 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", 2008 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", 2009 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", 2010 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", 2011 "", "", "", "", "", "", "", "", 2012 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", 2013 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", 2014 "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", 2015 "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 2016 "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", 2017 "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7", 2018 "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7", 2019 "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7", 2020 "", "", "", "", "", "", "", "", 2021 "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", 2022 "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7", 2023 "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7", 2024 "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7", 2025 "", "", "", "", "", "", "", "", 2026 "", "", "", "", "", "", "", "", 2027 "", "", "", "", "", "", "", "", 2028 "", "", "", "", "", "", "", "", 2029 "", "", "", "", "", "", "", "", 2030 "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7", 2031 }; 2032 2033 static const u64 r9a09g047_gpio_configs[] = { 2034 RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */ 2035 RZG2L_GPIO_PORT_PACK(8, 0x21, RZV2H_MPXED_PIN_FUNCS | 2036 PIN_CFG_ELC), /* P1 */ 2037 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | 2038 PIN_CFG_NOD), /* P2 */ 2039 RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */ 2040 RZG2L_GPIO_PORT_PACK(6, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */ 2041 RZG2L_GPIO_PORT_PACK(7, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */ 2042 RZG2L_GPIO_PORT_PACK(7, 0x26, RZV2H_MPXED_PIN_FUNCS), /* P6 */ 2043 RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS | 2044 PIN_CFG_ELC), /* P7 */ 2045 RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */ 2046 0x0, 2047 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */ 2048 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */ 2049 RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */ 2050 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */ 2051 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */ 2052 RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */ 2053 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */ 2054 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */ 2055 0x0, 2056 RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */ 2057 RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */ 2058 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x35), /* PL */ 2059 RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */ 2060 0x0, 2061 0x0, 2062 0x0, 2063 0x0, 2064 0x0, 2065 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */ 2066 }; 2067 2068 static const char * const rzv2h_gpio_names[] = { 2069 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", 2070 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", 2071 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", 2072 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", 2073 "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47", 2074 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", 2075 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", 2076 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", 2077 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", 2078 "P90", "P91", "P92", "P93", "P94", "P95", "P96", "P97", 2079 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", 2080 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", 2081 }; 2082 2083 static const u64 r9a09g057_gpio_configs[] = { 2084 RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */ 2085 RZG2L_GPIO_PORT_PACK(6, 0x21, RZV2H_MPXED_PIN_FUNCS), /* P1 */ 2086 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | 2087 PIN_CFG_NOD), /* P2 */ 2088 RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */ 2089 RZG2L_GPIO_PORT_PACK(8, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */ 2090 RZG2L_GPIO_PORT_PACK(8, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */ 2091 RZG2L_GPIO_PORT_PACK(8, 0x26, RZV2H_MPXED_PIN_FUNCS | 2092 PIN_CFG_ELC), /* P6 */ 2093 RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS), /* P7 */ 2094 RZG2L_GPIO_PORT_PACK(8, 0x28, RZV2H_MPXED_PIN_FUNCS | 2095 PIN_CFG_ELC), /* P8 */ 2096 RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS), /* P9 */ 2097 RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS), /* PA */ 2098 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x2b), /* PB */ 2099 }; 2100 2101 static const struct { 2102 struct rzg2l_dedicated_configs common[35]; 2103 struct rzg2l_dedicated_configs rzg2l_pins[7]; 2104 } rzg2l_dedicated_pins = { 2105 .common = { 2106 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) }, 2107 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, 2108 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 2109 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, 2110 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 2111 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, 2112 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, 2113 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, 2114 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 2115 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 2116 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2117 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, 2118 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 2119 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, 2120 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2121 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, 2122 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2123 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, 2124 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2125 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, 2126 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2127 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, 2128 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2129 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, 2130 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2131 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, 2132 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2133 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, 2134 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2135 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, 2136 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, 2137 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, 2138 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2139 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, 2140 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2141 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, 2142 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2143 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, 2144 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2145 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, 2146 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2147 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, 2148 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2149 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, 2150 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2151 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, 2152 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2153 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, 2154 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2155 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, 2156 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2157 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, 2158 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2159 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, 2160 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2161 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, 2162 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2163 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, 2164 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, 2165 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, 2166 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, 2167 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, 2168 }, 2169 .rzg2l_pins = { 2170 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2171 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, 2172 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2173 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, 2174 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2175 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, 2176 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2177 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, 2178 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2179 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, 2180 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2181 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, 2182 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2183 } 2184 }; 2185 2186 static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { 2187 { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, PIN_CFG_NF) }, 2188 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN | 2189 PIN_CFG_SOFT_PS)) }, 2190 { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) }, 2191 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) }, 2192 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) }, 2193 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) }, 2194 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, 2195 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2196 PIN_CFG_IO_VMC_SD0)) }, 2197 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, 2198 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2199 PIN_CFG_IO_VMC_SD0)) }, 2200 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2201 PIN_CFG_IO_VMC_SD0)) }, 2202 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2203 PIN_CFG_IO_VMC_SD0)) }, 2204 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2205 PIN_CFG_IO_VMC_SD0)) }, 2206 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2207 PIN_CFG_IO_VMC_SD0)) }, 2208 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2209 PIN_CFG_IO_VMC_SD0)) }, 2210 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2211 PIN_CFG_IO_VMC_SD0)) }, 2212 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2213 PIN_CFG_IO_VMC_SD0)) }, 2214 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) }, 2215 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2216 PIN_CFG_IO_VMC_SD1)) }, 2217 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2218 PIN_CFG_IO_VMC_SD1)) }, 2219 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2220 PIN_CFG_IO_VMC_SD1)) }, 2221 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2222 PIN_CFG_IO_VMC_SD1)) }, 2223 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2224 PIN_CFG_IO_VMC_SD1)) }, 2225 }; 2226 2227 static const struct { 2228 struct rzg2l_dedicated_configs common[77]; 2229 struct rzg2l_dedicated_configs pcie1[1]; 2230 } rzv2h_dedicated_pins = { 2231 .common = { 2232 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) }, 2233 { "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2234 PIN_CFG_IEN)) }, 2235 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2236 { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2237 PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2238 { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2239 PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2240 { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2241 PIN_CFG_PUPD)) }, 2242 { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2243 PIN_CFG_PUPD)) }, 2244 { "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2245 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2246 { "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2247 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2248 { "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2249 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2250 { "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2251 PIN_CFG_PUPD)) }, 2252 { "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2253 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2254 { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) }, 2255 { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) }, 2256 { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) }, 2257 { "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2258 PIN_CFG_PUPD)) }, 2259 { "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2260 PIN_CFG_PUPD)) }, 2261 { "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2262 PIN_CFG_PUPD)) }, 2263 { "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2264 PIN_CFG_PUPD)) }, 2265 { "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2266 PIN_CFG_PUPD)) }, 2267 { "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2268 PIN_CFG_PUPD)) }, 2269 { "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2270 PIN_CFG_PUPD)) }, 2271 { "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2272 PIN_CFG_PUPD)) }, 2273 { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2274 { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2275 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2276 { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2277 { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2278 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2279 { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2280 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2281 { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2282 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2283 { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2284 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2285 { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2286 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2287 { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2288 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2289 { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2290 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2291 { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2292 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2293 { "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2294 { "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2295 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2296 { "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2297 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2298 { "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2299 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2300 { "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2301 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2302 { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2303 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2304 { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | 2305 PIN_CFG_SR)) }, 2306 { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2307 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2308 { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2309 PIN_CFG_PUPD)) }, 2310 { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) }, 2311 { "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H | 2312 PIN_CFG_SR | 2313 PIN_CFG_PUPD)) }, 2314 { "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2315 PIN_CFG_PUPD)) }, 2316 { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) }, 2317 { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) }, 2318 { "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2319 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2320 { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) }, 2321 { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) }, 2322 { "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2323 PIN_CFG_PUPD)) }, 2324 { "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2325 PIN_CFG_PUPD)) }, 2326 { "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2327 PIN_CFG_PUPD)) }, 2328 { "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2329 PIN_CFG_PUPD)) }, 2330 { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) }, 2331 { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) }, 2332 { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) }, 2333 { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) }, 2334 { "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2335 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2336 { "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2337 PIN_CFG_PUPD)) }, 2338 { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) }, 2339 { "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H | 2340 PIN_CFG_SR | 2341 PIN_CFG_PUPD)) }, 2342 { "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2343 PIN_CFG_PUPD)) }, 2344 { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) }, 2345 { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) }, 2346 { "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2347 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2348 { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) }, 2349 { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) }, 2350 { "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2351 PIN_CFG_PUPD)) }, 2352 { "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2353 PIN_CFG_PUPD)) }, 2354 { "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2355 PIN_CFG_PUPD)) }, 2356 { "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2357 PIN_CFG_PUPD)) }, 2358 { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) }, 2359 { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) }, 2360 { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) }, 2361 { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) }, 2362 }, 2363 .pcie1 = { 2364 { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | 2365 PIN_CFG_SR)) }, 2366 }, 2367 }; 2368 2369 static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = { 2370 { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, 2371 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2372 { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, 2373 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2374 { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, 2375 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) }, 2376 { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 2377 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) }, 2378 { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, 2379 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2380 { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, 2381 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2382 { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, 2383 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2384 { "SD0PWEN", RZG2L_SINGLE_PIN_PACK(0x9, 3, 2385 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2386 { "SD0IOVS", RZG2L_SINGLE_PIN_PACK(0x9, 4, 2387 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2388 { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, 2389 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2390 { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, 2391 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2392 { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, 2393 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2394 { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, 2395 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2396 { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, 2397 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2398 { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, 2399 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2400 { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, 2401 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2402 { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, 2403 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2404 }; 2405 2406 static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) 2407 { 2408 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; 2409 const struct rzg2l_pinctrl_data *data = pctrl->data; 2410 u64 *pin_data = pin_desc->drv_data; 2411 unsigned int gpioint; 2412 unsigned int i; 2413 u32 port, bit; 2414 2415 if (*pin_data & PIN_CFG_NOGPIO_INT) 2416 return -EINVAL; 2417 2418 port = virq / 8; 2419 bit = virq % 8; 2420 2421 if (port >= data->n_ports || 2422 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port]))) 2423 return -EINVAL; 2424 2425 gpioint = bit; 2426 for (i = 0; i < port; i++) 2427 gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i])); 2428 2429 return gpioint; 2430 } 2431 2432 static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, 2433 unsigned int hwirq, bool enable) 2434 { 2435 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; 2436 u64 *pin_data = pin_desc->drv_data; 2437 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 2438 u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 2439 unsigned long flags; 2440 void __iomem *addr; 2441 2442 addr = pctrl->base + ISEL(off); 2443 if (bit >= 4) { 2444 bit -= 4; 2445 addr += 4; 2446 } 2447 2448 spin_lock_irqsave(&pctrl->lock, flags); 2449 if (enable) 2450 writel(readl(addr) | BIT(bit * 8), addr); 2451 else 2452 writel(readl(addr) & ~BIT(bit * 8), addr); 2453 spin_unlock_irqrestore(&pctrl->lock, flags); 2454 } 2455 2456 static void rzg2l_gpio_irq_disable(struct irq_data *d) 2457 { 2458 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 2459 unsigned int hwirq = irqd_to_hwirq(d); 2460 2461 irq_chip_disable_parent(d); 2462 gpiochip_disable_irq(gc, hwirq); 2463 } 2464 2465 static void rzg2l_gpio_irq_enable(struct irq_data *d) 2466 { 2467 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 2468 unsigned int hwirq = irqd_to_hwirq(d); 2469 2470 gpiochip_enable_irq(gc, hwirq); 2471 irq_chip_enable_parent(d); 2472 } 2473 2474 static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) 2475 { 2476 return irq_chip_set_type_parent(d, type); 2477 } 2478 2479 static void rzg2l_gpio_irqc_eoi(struct irq_data *d) 2480 { 2481 irq_chip_eoi_parent(d); 2482 } 2483 2484 static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) 2485 { 2486 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 2487 2488 seq_puts(p, dev_name(gc->parent)); 2489 } 2490 2491 static int rzg2l_gpio_irq_set_wake(struct irq_data *data, unsigned int on) 2492 { 2493 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 2494 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 2495 int ret; 2496 2497 /* It should not happen. */ 2498 if (!data->parent_data) 2499 return -EOPNOTSUPP; 2500 2501 ret = irq_chip_set_wake_parent(data, on); 2502 if (ret) 2503 return ret; 2504 2505 if (on) 2506 atomic_inc(&pctrl->wakeup_path); 2507 else 2508 atomic_dec(&pctrl->wakeup_path); 2509 2510 return 0; 2511 } 2512 2513 static const struct irq_chip rzg2l_gpio_irqchip = { 2514 .name = "rzg2l-gpio", 2515 .irq_disable = rzg2l_gpio_irq_disable, 2516 .irq_enable = rzg2l_gpio_irq_enable, 2517 .irq_mask = irq_chip_mask_parent, 2518 .irq_unmask = irq_chip_unmask_parent, 2519 .irq_set_type = rzg2l_gpio_irq_set_type, 2520 .irq_eoi = rzg2l_gpio_irqc_eoi, 2521 .irq_print_chip = rzg2l_gpio_irq_print_chip, 2522 .irq_set_affinity = irq_chip_set_affinity_parent, 2523 .irq_set_wake = rzg2l_gpio_irq_set_wake, 2524 .flags = IRQCHIP_IMMUTABLE, 2525 GPIOCHIP_IRQ_RESOURCE_HELPERS, 2526 }; 2527 2528 static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigned int offset) 2529 { 2530 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 2531 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 2532 u64 *pin_data = pin_desc->drv_data; 2533 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 2534 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 2535 u8 reg8; 2536 int ret; 2537 2538 reg8 = readb(pctrl->base + PMC(off)); 2539 if (reg8 & BIT(bit)) { 2540 ret = rzg2l_gpio_request(chip, offset); 2541 if (ret) 2542 return ret; 2543 } 2544 2545 return rzg2l_gpio_direction_input(chip, offset); 2546 } 2547 2548 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 2549 unsigned int child, 2550 unsigned int child_type, 2551 unsigned int *parent, 2552 unsigned int *parent_type) 2553 { 2554 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 2555 unsigned long flags; 2556 int gpioint, irq; 2557 int ret; 2558 2559 gpioint = rzg2l_gpio_get_gpioint(child, pctrl); 2560 if (gpioint < 0) 2561 return gpioint; 2562 2563 ret = rzg2l_gpio_interrupt_input_mode(gc, child); 2564 if (ret) 2565 return ret; 2566 2567 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 2568 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); 2569 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 2570 if (irq < 0) { 2571 ret = -ENOSPC; 2572 goto err; 2573 } 2574 2575 rzg2l_gpio_irq_endisable(pctrl, child, true); 2576 pctrl->hwirq[irq] = child; 2577 irq += pctrl->data->hwcfg->tint_start_index; 2578 2579 /* All these interrupts are level high in the CPU */ 2580 *parent_type = IRQ_TYPE_LEVEL_HIGH; 2581 *parent = RZG2L_PACK_HWIRQ(gpioint, irq); 2582 return 0; 2583 2584 err: 2585 rzg2l_gpio_free(gc, child); 2586 return ret; 2587 } 2588 2589 static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) 2590 { 2591 struct irq_domain *domain = pctrl->gpio_chip.irq.domain; 2592 2593 for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 2594 struct irq_data *data; 2595 unsigned long flags; 2596 unsigned int virq; 2597 int ret; 2598 2599 if (!pctrl->hwirq[i]) 2600 continue; 2601 2602 virq = irq_find_mapping(domain, pctrl->hwirq[i]); 2603 if (!virq) { 2604 dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n", 2605 pctrl->hwirq[i]); 2606 continue; 2607 } 2608 2609 data = irq_domain_get_irq_data(domain, virq); 2610 if (!data) { 2611 dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq); 2612 continue; 2613 } 2614 2615 /* 2616 * This has to be atomically executed to protect against a concurrent 2617 * interrupt. 2618 */ 2619 spin_lock_irqsave(&pctrl->lock, flags); 2620 ret = rzg2l_gpio_irq_set_type(data, irqd_get_trigger_type(data)); 2621 if (!ret && !irqd_irq_disabled(data)) 2622 rzg2l_gpio_irq_enable(data); 2623 spin_unlock_irqrestore(&pctrl->lock, flags); 2624 2625 if (ret) 2626 dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq); 2627 } 2628 } 2629 2630 static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, 2631 unsigned int nr_irqs) 2632 { 2633 struct irq_data *d; 2634 2635 d = irq_domain_get_irq_data(domain, virq); 2636 if (d) { 2637 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 2638 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 2639 irq_hw_number_t hwirq = irqd_to_hwirq(d); 2640 unsigned long flags; 2641 unsigned int i; 2642 2643 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 2644 if (pctrl->hwirq[i] == hwirq) { 2645 rzg2l_gpio_irq_endisable(pctrl, hwirq, false); 2646 rzg2l_gpio_free(gc, hwirq); 2647 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 2648 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); 2649 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 2650 pctrl->hwirq[i] = 0; 2651 break; 2652 } 2653 } 2654 } 2655 irq_domain_free_irqs_common(domain, virq, nr_irqs); 2656 } 2657 2658 static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, 2659 unsigned long *valid_mask, 2660 unsigned int ngpios) 2661 { 2662 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 2663 struct gpio_chip *chip = &pctrl->gpio_chip; 2664 unsigned int offset; 2665 2666 /* Forbid unused lines to be mapped as IRQs */ 2667 for (offset = 0; offset < chip->ngpio; offset++) { 2668 u32 port, bit; 2669 2670 port = offset / 8; 2671 bit = offset % 8; 2672 2673 if (port >= pctrl->data->n_ports || 2674 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, 2675 pctrl->data->port_pin_configs[port]))) 2676 clear_bit(offset, valid_mask); 2677 } 2678 } 2679 2680 static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) 2681 { 2682 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 2683 struct rzg2l_pinctrl_reg_cache *cache, *dedicated_cache; 2684 2685 cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL); 2686 if (!cache) 2687 return -ENOMEM; 2688 2689 dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL); 2690 if (!dedicated_cache) 2691 return -ENOMEM; 2692 2693 cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL); 2694 if (!cache->p) 2695 return -ENOMEM; 2696 2697 cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL); 2698 if (!cache->pm) 2699 return -ENOMEM; 2700 2701 cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL); 2702 if (!cache->pmc) 2703 return -ENOMEM; 2704 2705 cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL); 2706 if (!cache->pfc) 2707 return -ENOMEM; 2708 2709 cache->smt = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt), GFP_KERNEL); 2710 if (!cache->smt) 2711 return -ENOMEM; 2712 2713 for (u8 i = 0; i < 2; i++) { 2714 u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; 2715 2716 cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]), 2717 GFP_KERNEL); 2718 if (!cache->iolh[i]) 2719 return -ENOMEM; 2720 2721 cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]), 2722 GFP_KERNEL); 2723 if (!cache->ien[i]) 2724 return -ENOMEM; 2725 2726 cache->pupd[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pupd[i]), 2727 GFP_KERNEL); 2728 if (!cache->pupd[i]) 2729 return -ENOMEM; 2730 2731 /* Allocate dedicated cache. */ 2732 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, 2733 sizeof(*dedicated_cache->iolh[i]), 2734 GFP_KERNEL); 2735 if (!dedicated_cache->iolh[i]) 2736 return -ENOMEM; 2737 2738 dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, 2739 sizeof(*dedicated_cache->ien[i]), 2740 GFP_KERNEL); 2741 if (!dedicated_cache->ien[i]) 2742 return -ENOMEM; 2743 } 2744 2745 pctrl->cache = cache; 2746 pctrl->dedicated_cache = dedicated_cache; 2747 2748 return 0; 2749 } 2750 2751 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) 2752 { 2753 struct device_node *np = pctrl->dev->of_node; 2754 struct gpio_chip *chip = &pctrl->gpio_chip; 2755 const char *name = dev_name(pctrl->dev); 2756 struct irq_domain *parent_domain; 2757 struct of_phandle_args of_args; 2758 struct device_node *parent_np; 2759 struct gpio_irq_chip *girq; 2760 int ret; 2761 2762 parent_np = of_irq_find_parent(np); 2763 if (!parent_np) 2764 return -ENXIO; 2765 2766 parent_domain = irq_find_host(parent_np); 2767 of_node_put(parent_np); 2768 if (!parent_domain) 2769 return -EPROBE_DEFER; 2770 2771 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); 2772 if (ret) 2773 return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n"); 2774 2775 of_node_put(of_args.np); 2776 2777 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 2778 of_args.args[2] != pctrl->data->n_port_pins) 2779 return dev_err_probe(pctrl->dev, -EINVAL, 2780 "gpio-ranges does not match selected SOC\n"); 2781 2782 chip->names = pctrl->data->port_pins; 2783 chip->request = rzg2l_gpio_request; 2784 chip->free = rzg2l_gpio_free; 2785 chip->get_direction = rzg2l_gpio_get_direction; 2786 chip->direction_input = rzg2l_gpio_direction_input; 2787 chip->direction_output = rzg2l_gpio_direction_output; 2788 chip->get = rzg2l_gpio_get; 2789 chip->set = rzg2l_gpio_set; 2790 chip->label = name; 2791 chip->parent = pctrl->dev; 2792 chip->owner = THIS_MODULE; 2793 chip->base = -1; 2794 chip->ngpio = of_args.args[2]; 2795 2796 girq = &chip->irq; 2797 gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip); 2798 girq->fwnode = dev_fwnode(pctrl->dev); 2799 girq->parent_domain = parent_domain; 2800 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; 2801 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; 2802 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; 2803 girq->init_valid_mask = rzg2l_init_irq_valid_mask; 2804 2805 pctrl->gpio_range.id = 0; 2806 pctrl->gpio_range.pin_base = 0; 2807 pctrl->gpio_range.base = 0; 2808 pctrl->gpio_range.npins = chip->ngpio; 2809 pctrl->gpio_range.name = chip->label; 2810 pctrl->gpio_range.gc = chip; 2811 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 2812 if (ret) 2813 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n"); 2814 2815 dev_dbg(pctrl->dev, "Registered gpio controller\n"); 2816 2817 return 0; 2818 } 2819 2820 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) 2821 { 2822 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 2823 struct pinctrl_pin_desc *pins; 2824 unsigned int i, j; 2825 u64 *pin_data; 2826 int ret; 2827 2828 pctrl->desc.name = DRV_NAME; 2829 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; 2830 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; 2831 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; 2832 pctrl->desc.confops = &rzg2l_pinctrl_confops; 2833 pctrl->desc.owner = THIS_MODULE; 2834 if (pctrl->data->num_custom_params) { 2835 pctrl->desc.num_custom_params = pctrl->data->num_custom_params; 2836 pctrl->desc.custom_params = pctrl->data->custom_params; 2837 #ifdef CONFIG_DEBUG_FS 2838 pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items; 2839 #endif 2840 } 2841 2842 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); 2843 if (!pins) 2844 return -ENOMEM; 2845 2846 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, 2847 sizeof(*pin_data), GFP_KERNEL); 2848 if (!pin_data) 2849 return -ENOMEM; 2850 2851 pctrl->pins = pins; 2852 pctrl->desc.pins = pins; 2853 2854 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 2855 pins[i].number = i; 2856 pins[i].name = pctrl->data->port_pins[i]; 2857 if (i && !(i % RZG2L_PINS_PER_PORT)) 2858 j++; 2859 pin_data[i] = pctrl->data->port_pin_configs[j]; 2860 if (pin_data[i] & RZG2L_VARIABLE_CFG) 2861 pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, 2862 pin_data[i], 2863 j, 2864 i % RZG2L_PINS_PER_PORT); 2865 pins[i].drv_data = &pin_data[i]; 2866 } 2867 2868 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { 2869 unsigned int index = pctrl->data->n_port_pins + i; 2870 2871 pins[index].number = index; 2872 pins[index].name = pctrl->data->dedicated_pins[i].name; 2873 pin_data[index] = pctrl->data->dedicated_pins[i].config; 2874 pins[index].drv_data = &pin_data[index]; 2875 } 2876 2877 pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), 2878 GFP_KERNEL); 2879 if (!pctrl->settings) 2880 return -ENOMEM; 2881 2882 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { 2883 if (pin_data[i] & PIN_CFG_SOFT_PS) { 2884 pctrl->settings[i].power_source = 3300; 2885 } else { 2886 ret = rzg2l_get_power_source(pctrl, i, pin_data[i]); 2887 if (ret < 0) 2888 continue; 2889 pctrl->settings[i].power_source = ret; 2890 } 2891 } 2892 2893 ret = rzg2l_pinctrl_reg_cache_alloc(pctrl); 2894 if (ret) 2895 return ret; 2896 2897 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, 2898 &pctrl->pctl); 2899 if (ret) 2900 return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n"); 2901 2902 ret = pinctrl_enable(pctrl->pctl); 2903 if (ret) 2904 return dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n"); 2905 2906 ret = rzg2l_gpio_register(pctrl); 2907 if (ret) 2908 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n"); 2909 2910 return 0; 2911 } 2912 2913 static int rzg2l_pinctrl_probe(struct platform_device *pdev) 2914 { 2915 struct rzg2l_pinctrl *pctrl; 2916 int ret; 2917 2918 BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT > 2919 ARRAY_SIZE(rzg2l_gpio_names)); 2920 2921 BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > 2922 ARRAY_SIZE(rzg2l_gpio_names)); 2923 2924 BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > 2925 ARRAY_SIZE(rzg2l_gpio_names)); 2926 2927 BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT > 2928 ARRAY_SIZE(rzg3e_gpio_names)); 2929 2930 BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT > 2931 ARRAY_SIZE(rzv2h_gpio_names)); 2932 2933 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 2934 if (!pctrl) 2935 return -ENOMEM; 2936 2937 pctrl->dev = &pdev->dev; 2938 2939 pctrl->data = of_device_get_match_data(&pdev->dev); 2940 if (!pctrl->data) 2941 return -EINVAL; 2942 2943 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 2944 if (IS_ERR(pctrl->base)) 2945 return PTR_ERR(pctrl->base); 2946 2947 pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL); 2948 if (IS_ERR(pctrl->clk)) { 2949 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk), 2950 "failed to enable GPIO clk\n"); 2951 } 2952 2953 spin_lock_init(&pctrl->lock); 2954 spin_lock_init(&pctrl->bitmap_lock); 2955 mutex_init(&pctrl->mutex); 2956 atomic_set(&pctrl->wakeup_path, 0); 2957 2958 platform_set_drvdata(pdev, pctrl); 2959 2960 ret = rzg2l_pinctrl_register(pctrl); 2961 if (ret) 2962 return ret; 2963 2964 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); 2965 return 0; 2966 } 2967 2968 static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend) 2969 { 2970 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 2971 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 2972 2973 for (u32 port = 0; port < nports; port++) { 2974 bool has_iolh, has_ien, has_pupd, has_smt; 2975 u32 off, caps; 2976 u8 pincnt; 2977 u64 cfg; 2978 2979 cfg = pctrl->data->port_pin_configs[port]; 2980 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 2981 pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg)); 2982 2983 caps = FIELD_GET(PIN_CFG_MASK, cfg); 2984 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); 2985 has_ien = !!(caps & PIN_CFG_IEN); 2986 has_pupd = !!(caps & PIN_CFG_PUPD); 2987 has_smt = !!(caps & PIN_CFG_SMT); 2988 2989 if (suspend) 2990 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); 2991 2992 /* 2993 * Now cache the registers or set them in the order suggested by 2994 * HW manual (section "Operation for GPIO Function"). 2995 */ 2996 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); 2997 if (has_iolh) { 2998 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), 2999 cache->iolh[0][port]); 3000 if (pincnt >= 4) { 3001 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4, 3002 cache->iolh[1][port]); 3003 } 3004 } 3005 3006 if (has_pupd) { 3007 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), 3008 cache->pupd[0][port]); 3009 if (pincnt >= 4) { 3010 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), 3011 cache->pupd[1][port]); 3012 } 3013 } 3014 3015 RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]); 3016 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]); 3017 3018 if (has_ien) { 3019 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), 3020 cache->ien[0][port]); 3021 if (pincnt >= 4) { 3022 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4, 3023 cache->ien[1][port]); 3024 } 3025 } 3026 3027 if (has_smt) 3028 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), cache->smt[port]); 3029 } 3030 } 3031 3032 static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) 3033 { 3034 struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; 3035 u32 caps; 3036 u32 i; 3037 3038 /* 3039 * Make sure entries in pctrl->data->n_dedicated_pins[] having the same 3040 * port offset are close together. 3041 */ 3042 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { 3043 bool has_iolh, has_ien; 3044 u32 off, next_off = 0; 3045 u64 cfg, next_cfg; 3046 u8 pincnt; 3047 3048 cfg = pctrl->data->dedicated_pins[i].config; 3049 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 3050 if (i + 1 < pctrl->data->n_dedicated_pins) { 3051 next_cfg = pctrl->data->dedicated_pins[i + 1].config; 3052 next_off = RZG2L_PIN_CFG_TO_PORT_OFFSET(next_cfg); 3053 } 3054 3055 if (off == next_off) { 3056 /* Gather caps of all port pins. */ 3057 caps |= FIELD_GET(PIN_CFG_MASK, cfg); 3058 continue; 3059 } 3060 3061 /* And apply them in a single shot. */ 3062 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); 3063 has_ien = !!(caps & PIN_CFG_IEN); 3064 pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg)); 3065 3066 if (has_iolh) { 3067 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), 3068 cache->iolh[0][i]); 3069 } 3070 if (has_ien) { 3071 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), 3072 cache->ien[0][i]); 3073 } 3074 3075 if (pincnt >= 4) { 3076 if (has_iolh) { 3077 RZG2L_PCTRL_REG_ACCESS32(suspend, 3078 pctrl->base + IOLH(off) + 4, 3079 cache->iolh[1][i]); 3080 } 3081 if (has_ien) { 3082 RZG2L_PCTRL_REG_ACCESS32(suspend, 3083 pctrl->base + IEN(off) + 4, 3084 cache->ien[1][i]); 3085 } 3086 } 3087 caps = 0; 3088 } 3089 } 3090 3091 static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) 3092 { 3093 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 3094 unsigned long flags; 3095 3096 spin_lock_irqsave(&pctrl->lock, flags); 3097 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); 3098 3099 /* Restore port registers. */ 3100 for (u32 port = 0; port < nports; port++) { 3101 unsigned long pinmap; 3102 u8 pmc = 0, max_pin; 3103 u32 off, pfc = 0; 3104 u64 cfg; 3105 u16 pm; 3106 u8 pin; 3107 3108 cfg = pctrl->data->port_pin_configs[port]; 3109 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 3110 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); 3111 max_pin = fls(pinmap); 3112 3113 pm = readw(pctrl->base + PM(off)); 3114 for_each_set_bit(pin, &pinmap, max_pin) { 3115 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 3116 3117 /* Nothing to do if PFC was not configured before. */ 3118 if (!(cache->pmc[port] & BIT(pin))) 3119 continue; 3120 3121 /* Set pin to 'Non-use (Hi-Z input protection)' */ 3122 pm &= ~(PM_MASK << (pin * 2)); 3123 writew(pm, pctrl->base + PM(off)); 3124 3125 /* Temporarily switch to GPIO mode with PMC register */ 3126 pmc &= ~BIT(pin); 3127 writeb(pmc, pctrl->base + PMC(off)); 3128 3129 /* Select Pin function mode. */ 3130 pfc &= ~(PFC_MASK << (pin * 4)); 3131 pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4))); 3132 writel(pfc, pctrl->base + PFC(off)); 3133 3134 /* Switch to Peripheral pin function. */ 3135 pmc |= BIT(pin); 3136 writeb(pmc, pctrl->base + PMC(off)); 3137 } 3138 } 3139 3140 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); 3141 spin_unlock_irqrestore(&pctrl->lock, flags); 3142 } 3143 3144 static int rzg2l_pinctrl_suspend_noirq(struct device *dev) 3145 { 3146 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); 3147 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 3148 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 3149 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 3150 3151 rzg2l_pinctrl_pm_setup_regs(pctrl, true); 3152 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true); 3153 3154 for (u8 i = 0; i < 2; i++) { 3155 if (regs->sd_ch) 3156 cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); 3157 if (regs->eth_poc) 3158 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); 3159 } 3160 3161 cache->qspi = readb(pctrl->base + QSPI); 3162 cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen); 3163 3164 if (!atomic_read(&pctrl->wakeup_path)) 3165 clk_disable_unprepare(pctrl->clk); 3166 else 3167 device_set_wakeup_path(dev); 3168 3169 return 0; 3170 } 3171 3172 static int rzg2l_pinctrl_resume_noirq(struct device *dev) 3173 { 3174 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); 3175 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 3176 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 3177 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 3178 unsigned long flags; 3179 u8 pwpr; 3180 int ret; 3181 3182 if (!atomic_read(&pctrl->wakeup_path)) { 3183 ret = clk_prepare_enable(pctrl->clk); 3184 if (ret) 3185 return ret; 3186 } 3187 3188 writeb(cache->qspi, pctrl->base + QSPI); 3189 if (pctrl->data->hwcfg->oen_pwpr_lock) { 3190 spin_lock_irqsave(&pctrl->lock, flags); 3191 pwpr = readb(pctrl->base + regs->pwpr); 3192 writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); 3193 } 3194 writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen); 3195 if (pctrl->data->hwcfg->oen_pwpr_lock) { 3196 writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); 3197 spin_unlock_irqrestore(&pctrl->lock, flags); 3198 } 3199 for (u8 i = 0; i < 2; i++) { 3200 if (regs->sd_ch) 3201 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); 3202 if (regs->eth_poc) 3203 writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); 3204 } 3205 3206 rzg2l_pinctrl_pm_setup_pfc(pctrl); 3207 rzg2l_pinctrl_pm_setup_regs(pctrl, false); 3208 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false); 3209 rzg2l_gpio_irq_restore(pctrl); 3210 3211 return 0; 3212 } 3213 3214 static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) 3215 { 3216 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 3217 3218 if (lock) { 3219 /* Set the PWPR register to be write-protected */ 3220 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 3221 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ 3222 } else { 3223 /* Set the PWPR register to allow PFC register to write */ 3224 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 3225 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ 3226 } 3227 } 3228 3229 static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) 3230 { 3231 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 3232 u8 pwpr; 3233 3234 if (lock) { 3235 /* Set the PWPR register to be write-protected */ 3236 pwpr = readb(pctrl->base + regs->pwpr); 3237 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); 3238 } else { 3239 /* Set the PWPR register to allow PFC and PMC register to write */ 3240 pwpr = readb(pctrl->base + regs->pwpr); 3241 writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr); 3242 } 3243 } 3244 3245 static const struct rzg2l_hwcfg rzg2l_hwcfg = { 3246 .regs = { 3247 .pwpr = 0x3014, 3248 .sd_ch = 0x3000, 3249 .eth_poc = 0x300c, 3250 .oen = 0x3018, 3251 }, 3252 .iolh_groupa_ua = { 3253 /* 3v3 power source */ 3254 [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000, 3255 }, 3256 .iolh_groupb_oi = { 100, 66, 50, 33, }, 3257 .tint_start_index = 9, 3258 .oen_max_pin = 0, 3259 }; 3260 3261 static const struct rzg2l_hwcfg rzg3s_hwcfg = { 3262 .regs = { 3263 .pwpr = 0x3000, 3264 .sd_ch = 0x3004, 3265 .eth_poc = 0x3010, 3266 .oen = 0x3018, 3267 }, 3268 .iolh_groupa_ua = { 3269 /* 1v8 power source */ 3270 [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000, 3271 /* 3v3 power source */ 3272 [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000, 3273 }, 3274 .iolh_groupb_ua = { 3275 /* 1v8 power source */ 3276 [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000, 3277 /* 3v3 power source */ 3278 [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000, 3279 }, 3280 .iolh_groupc_ua = { 3281 /* 1v8 power source */ 3282 [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800, 3283 /* 2v5 source */ 3284 [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100, 3285 /* 3v3 power source */ 3286 [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050, 3287 }, 3288 .tint_start_index = 9, 3289 .drive_strength_ua = true, 3290 .func_base = 1, 3291 .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */ 3292 .oen_max_port = 7, /* P7_1 is the maximum OEN port. */ 3293 }; 3294 3295 static const struct rzg2l_hwcfg rzv2h_hwcfg = { 3296 .regs = { 3297 .pwpr = 0x3c04, 3298 .oen = 0x3c40, 3299 }, 3300 .tint_start_index = 17, 3301 .oen_pwpr_lock = true, 3302 }; 3303 3304 static struct rzg2l_pinctrl_data r9a07g043_data = { 3305 .port_pins = rzg2l_gpio_names, 3306 .port_pin_configs = r9a07g043_gpio_configs, 3307 .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs), 3308 .dedicated_pins = rzg2l_dedicated_pins.common, 3309 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, 3310 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), 3311 .hwcfg = &rzg2l_hwcfg, 3312 #ifdef CONFIG_RISCV 3313 .variable_pin_cfg = r9a07g043f_variable_pin_cfg, 3314 .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg), 3315 #endif 3316 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3317 .pmc_writeb = &rzg2l_pmc_writeb, 3318 .pin_to_oen_bit = &rzg2l_pin_to_oen_bit, 3319 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3320 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3321 }; 3322 3323 static struct rzg2l_pinctrl_data r9a07g044_data = { 3324 .port_pins = rzg2l_gpio_names, 3325 .port_pin_configs = r9a07g044_gpio_configs, 3326 .n_ports = ARRAY_SIZE(r9a07g044_gpio_configs), 3327 .dedicated_pins = rzg2l_dedicated_pins.common, 3328 .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT, 3329 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + 3330 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), 3331 .hwcfg = &rzg2l_hwcfg, 3332 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3333 .pmc_writeb = &rzg2l_pmc_writeb, 3334 .pin_to_oen_bit = &rzg2l_pin_to_oen_bit, 3335 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3336 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3337 }; 3338 3339 static struct rzg2l_pinctrl_data r9a08g045_data = { 3340 .port_pins = rzg2l_gpio_names, 3341 .port_pin_configs = r9a08g045_gpio_configs, 3342 .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs), 3343 .dedicated_pins = rzg3s_dedicated_pins, 3344 .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT, 3345 .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins), 3346 .hwcfg = &rzg3s_hwcfg, 3347 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3348 .pmc_writeb = &rzg2l_pmc_writeb, 3349 .pin_to_oen_bit = &rzg3s_pin_to_oen_bit, 3350 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3351 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3352 }; 3353 3354 static struct rzg2l_pinctrl_data r9a09g047_data = { 3355 .port_pins = rzg3e_gpio_names, 3356 .port_pin_configs = r9a09g047_gpio_configs, 3357 .n_ports = ARRAY_SIZE(r9a09g047_gpio_configs), 3358 .dedicated_pins = rzg3e_dedicated_pins, 3359 .n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT, 3360 .n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins), 3361 .hwcfg = &rzv2h_hwcfg, 3362 .variable_pin_cfg = r9a09g047_variable_pin_cfg, 3363 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg), 3364 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), 3365 .custom_params = renesas_rzv2h_custom_bindings, 3366 #ifdef CONFIG_DEBUG_FS 3367 .custom_conf_items = renesas_rzv2h_conf_items, 3368 #endif 3369 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, 3370 .pmc_writeb = &rzv2h_pmc_writeb, 3371 .pin_to_oen_bit = &rzg3e_pin_to_oen_bit, 3372 .hw_to_bias_param = &rzv2h_hw_to_bias_param, 3373 .bias_param_to_hw = &rzv2h_bias_param_to_hw, 3374 }; 3375 3376 static struct rzg2l_pinctrl_data r9a09g056_data = { 3377 .port_pins = rzv2h_gpio_names, 3378 .port_pin_configs = r9a09g057_gpio_configs, 3379 .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs), 3380 .dedicated_pins = rzv2h_dedicated_pins.common, 3381 .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT, 3382 .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common), 3383 .hwcfg = &rzv2h_hwcfg, 3384 .variable_pin_cfg = r9a09g057_variable_pin_cfg, 3385 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg), 3386 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), 3387 .custom_params = renesas_rzv2h_custom_bindings, 3388 #ifdef CONFIG_DEBUG_FS 3389 .custom_conf_items = renesas_rzv2h_conf_items, 3390 #endif 3391 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, 3392 .pmc_writeb = &rzv2h_pmc_writeb, 3393 .pin_to_oen_bit = &rzv2h_pin_to_oen_bit, 3394 .hw_to_bias_param = &rzv2h_hw_to_bias_param, 3395 .bias_param_to_hw = &rzv2h_bias_param_to_hw, 3396 }; 3397 3398 static struct rzg2l_pinctrl_data r9a09g057_data = { 3399 .port_pins = rzv2h_gpio_names, 3400 .port_pin_configs = r9a09g057_gpio_configs, 3401 .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs), 3402 .dedicated_pins = rzv2h_dedicated_pins.common, 3403 .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT, 3404 .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common) + 3405 ARRAY_SIZE(rzv2h_dedicated_pins.pcie1), 3406 .hwcfg = &rzv2h_hwcfg, 3407 .variable_pin_cfg = r9a09g057_variable_pin_cfg, 3408 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg), 3409 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), 3410 .custom_params = renesas_rzv2h_custom_bindings, 3411 #ifdef CONFIG_DEBUG_FS 3412 .custom_conf_items = renesas_rzv2h_conf_items, 3413 #endif 3414 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, 3415 .pmc_writeb = &rzv2h_pmc_writeb, 3416 .pin_to_oen_bit = &rzv2h_pin_to_oen_bit, 3417 .hw_to_bias_param = &rzv2h_hw_to_bias_param, 3418 .bias_param_to_hw = &rzv2h_bias_param_to_hw, 3419 }; 3420 3421 static const struct of_device_id rzg2l_pinctrl_of_table[] = { 3422 { 3423 .compatible = "renesas,r9a07g043-pinctrl", 3424 .data = &r9a07g043_data, 3425 }, 3426 { 3427 .compatible = "renesas,r9a07g044-pinctrl", 3428 .data = &r9a07g044_data, 3429 }, 3430 { 3431 .compatible = "renesas,r9a08g045-pinctrl", 3432 .data = &r9a08g045_data, 3433 }, 3434 { 3435 .compatible = "renesas,r9a09g047-pinctrl", 3436 .data = &r9a09g047_data, 3437 }, 3438 { 3439 .compatible = "renesas,r9a09g056-pinctrl", 3440 .data = &r9a09g056_data, 3441 }, 3442 { 3443 .compatible = "renesas,r9a09g057-pinctrl", 3444 .data = &r9a09g057_data, 3445 }, 3446 { /* sentinel */ } 3447 }; 3448 3449 static const struct dev_pm_ops rzg2l_pinctrl_pm_ops = { 3450 NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg2l_pinctrl_suspend_noirq, rzg2l_pinctrl_resume_noirq) 3451 }; 3452 3453 static struct platform_driver rzg2l_pinctrl_driver = { 3454 .driver = { 3455 .name = DRV_NAME, 3456 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), 3457 .pm = pm_sleep_ptr(&rzg2l_pinctrl_pm_ops), 3458 .suppress_bind_attrs = true, 3459 }, 3460 .probe = rzg2l_pinctrl_probe, 3461 }; 3462 3463 static int __init rzg2l_pinctrl_init(void) 3464 { 3465 return platform_driver_register(&rzg2l_pinctrl_driver); 3466 } 3467 core_initcall(rzg2l_pinctrl_init); 3468 3469 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 3470 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); 3471