1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G2L Pin Control and GPIO driver core 4 * 5 * Copyright (C) 2021 Renesas Electronics Corporation. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/seq_file.h> 17 #include <linux/spinlock.h> 18 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/pinctrl/pinconf-generic.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 25 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 26 27 #include "../core.h" 28 #include "../pinconf.h" 29 #include "../pinmux.h" 30 31 #define DRV_NAME "pinctrl-rzg2l" 32 33 /* 34 * Use 16 lower bits [15:0] for pin identifier 35 * Use 16 higher bits [31:16] for pin mux function 36 */ 37 #define MUX_PIN_ID_MASK GENMASK(15, 0) 38 #define MUX_FUNC_MASK GENMASK(31, 16) 39 #define MUX_FUNC_OFFS 16 40 #define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) 41 42 /* PIN capabilities */ 43 #define PIN_CFG_IOLH_A BIT(0) 44 #define PIN_CFG_IOLH_B BIT(1) 45 #define PIN_CFG_SR BIT(2) 46 #define PIN_CFG_IEN BIT(3) 47 #define PIN_CFG_PUPD BIT(4) 48 #define PIN_CFG_IO_VMC_SD0 BIT(5) 49 #define PIN_CFG_IO_VMC_SD1 BIT(6) 50 #define PIN_CFG_IO_VMC_QSPI BIT(7) 51 #define PIN_CFG_IO_VMC_ETH0 BIT(8) 52 #define PIN_CFG_IO_VMC_ETH1 BIT(9) 53 #define PIN_CFG_FILONOFF BIT(10) 54 #define PIN_CFG_FILNUM BIT(11) 55 #define PIN_CFG_FILCLKSEL BIT(12) 56 57 #define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ 58 PIN_CFG_SR | \ 59 PIN_CFG_PUPD | \ 60 PIN_CFG_FILONOFF | \ 61 PIN_CFG_FILNUM | \ 62 PIN_CFG_FILCLKSEL) 63 64 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ 65 PIN_CFG_FILONOFF | \ 66 PIN_CFG_FILNUM | \ 67 PIN_CFG_FILCLKSEL) 68 69 /* 70 * n indicates number of pins in the port, a is the register index 71 * and f is pin configuration capabilities supported. 72 */ 73 #define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) 74 #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) 75 #define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20) 76 #define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) 77 78 /* 79 * BIT(31) indicates dedicated pin, p is the register index while 80 * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits 81 * (b * 8) and f is the pin configuration capabilities supported. 82 */ 83 #define RZG2L_SINGLE_PIN BIT(31) 84 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ 85 ((p) << 24) | ((b) << 20) | (f)) 86 #define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x) (((x) & GENMASK(30, 24)) >> 24) 87 #define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) 88 #define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0)) 89 90 #define P(n) (0x0000 + 0x10 + (n)) 91 #define PM(n) (0x0100 + 0x20 + (n) * 2) 92 #define PMC(n) (0x0200 + 0x10 + (n)) 93 #define PFC(n) (0x0400 + 0x40 + (n) * 4) 94 #define PIN(n) (0x0800 + 0x10 + (n)) 95 #define IOLH(n) (0x1000 + (n) * 8) 96 #define IEN(n) (0x1800 + (n) * 8) 97 #define ISEL(n) (0x2c80 + (n) * 8) 98 #define PWPR (0x3014) 99 #define SD_CH(n) (0x3000 + (n) * 4) 100 #define QSPI (0x3008) 101 102 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ 103 #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ 104 105 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ 106 #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ 107 108 #define PM_MASK 0x03 109 #define PVDD_MASK 0x01 110 #define PFC_MASK 0x07 111 #define IEN_MASK 0x01 112 #define IOLH_MASK 0x03 113 114 #define PM_INPUT 0x1 115 #define PM_OUTPUT 0x2 116 117 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) 118 #define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10) 119 #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) 120 121 #define RZG2L_TINT_MAX_INTERRUPT 32 122 #define RZG2L_TINT_IRQ_START_INDEX 9 123 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) 124 125 struct rzg2l_dedicated_configs { 126 const char *name; 127 u32 config; 128 }; 129 130 struct rzg2l_pinctrl_data { 131 const char * const *port_pins; 132 const u32 *port_pin_configs; 133 struct rzg2l_dedicated_configs *dedicated_pins; 134 unsigned int n_port_pins; 135 unsigned int n_dedicated_pins; 136 }; 137 138 struct rzg2l_pinctrl { 139 struct pinctrl_dev *pctl; 140 struct pinctrl_desc desc; 141 struct pinctrl_pin_desc *pins; 142 143 const struct rzg2l_pinctrl_data *data; 144 void __iomem *base; 145 struct device *dev; 146 struct clk *clk; 147 148 struct gpio_chip gpio_chip; 149 struct pinctrl_gpio_range gpio_range; 150 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); 151 spinlock_t bitmap_lock; 152 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; 153 154 spinlock_t lock; 155 }; 156 157 static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 }; 158 static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 }; 159 160 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, 161 u8 port, u8 pin, u8 func) 162 { 163 unsigned long flags; 164 u32 reg; 165 166 spin_lock_irqsave(&pctrl->lock, flags); 167 168 /* Set pin to 'Non-use (Hi-Z input protection)' */ 169 reg = readw(pctrl->base + PM(port)); 170 reg &= ~(PM_MASK << (pin * 2)); 171 writew(reg, pctrl->base + PM(port)); 172 173 /* Temporarily switch to GPIO mode with PMC register */ 174 reg = readb(pctrl->base + PMC(port)); 175 writeb(reg & ~BIT(pin), pctrl->base + PMC(port)); 176 177 /* Set the PWPR register to allow PFC register to write */ 178 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ 179 writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */ 180 181 /* Select Pin function mode with PFC register */ 182 reg = readl(pctrl->base + PFC(port)); 183 reg &= ~(PFC_MASK << (pin * 4)); 184 writel(reg | (func << (pin * 4)), pctrl->base + PFC(port)); 185 186 /* Set the PWPR register to be write-protected */ 187 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ 188 writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */ 189 190 /* Switch to Peripheral pin function with PMC register */ 191 reg = readb(pctrl->base + PMC(port)); 192 writeb(reg | BIT(pin), pctrl->base + PMC(port)); 193 194 spin_unlock_irqrestore(&pctrl->lock, flags); 195 }; 196 197 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, 198 unsigned int func_selector, 199 unsigned int group_selector) 200 { 201 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 202 struct function_desc *func; 203 unsigned int i, *psel_val; 204 struct group_desc *group; 205 int *pins; 206 207 func = pinmux_generic_get_function(pctldev, func_selector); 208 if (!func) 209 return -EINVAL; 210 group = pinctrl_generic_get_group(pctldev, group_selector); 211 if (!group) 212 return -EINVAL; 213 214 psel_val = func->data; 215 pins = group->pins; 216 217 for (i = 0; i < group->num_pins; i++) { 218 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", 219 RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]), 220 psel_val[i]); 221 rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]), 222 RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]); 223 } 224 225 return 0; 226 }; 227 228 static int rzg2l_map_add_config(struct pinctrl_map *map, 229 const char *group_or_pin, 230 enum pinctrl_map_type type, 231 unsigned long *configs, 232 unsigned int num_configs) 233 { 234 unsigned long *cfgs; 235 236 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), 237 GFP_KERNEL); 238 if (!cfgs) 239 return -ENOMEM; 240 241 map->type = type; 242 map->data.configs.group_or_pin = group_or_pin; 243 map->data.configs.configs = cfgs; 244 map->data.configs.num_configs = num_configs; 245 246 return 0; 247 } 248 249 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, 250 struct device_node *np, 251 struct pinctrl_map **map, 252 unsigned int *num_maps, 253 unsigned int *index) 254 { 255 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 256 struct pinctrl_map *maps = *map; 257 unsigned int nmaps = *num_maps; 258 unsigned long *configs = NULL; 259 unsigned int *pins, *psel_val; 260 unsigned int num_pinmux = 0; 261 unsigned int idx = *index; 262 unsigned int num_pins, i; 263 unsigned int num_configs; 264 struct property *pinmux; 265 struct property *prop; 266 int ret, gsel, fsel; 267 const char **pin_fn; 268 const char *pin; 269 270 pinmux = of_find_property(np, "pinmux", NULL); 271 if (pinmux) 272 num_pinmux = pinmux->length / sizeof(u32); 273 274 ret = of_property_count_strings(np, "pins"); 275 if (ret == -EINVAL) { 276 num_pins = 0; 277 } else if (ret < 0) { 278 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 279 return ret; 280 } else { 281 num_pins = ret; 282 } 283 284 if (!num_pinmux && !num_pins) 285 return 0; 286 287 if (num_pinmux && num_pins) { 288 dev_err(pctrl->dev, 289 "DT node must contain either a pinmux or pins and not both\n"); 290 return -EINVAL; 291 } 292 293 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); 294 if (ret < 0) 295 return ret; 296 297 if (num_pins && !num_configs) { 298 dev_err(pctrl->dev, "DT node must contain a config\n"); 299 ret = -ENODEV; 300 goto done; 301 } 302 303 if (num_pinmux) 304 nmaps += 1; 305 306 if (num_pins) 307 nmaps += num_pins; 308 309 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 310 if (!maps) { 311 ret = -ENOMEM; 312 goto done; 313 } 314 315 *map = maps; 316 *num_maps = nmaps; 317 if (num_pins) { 318 of_property_for_each_string(np, "pins", prop, pin) { 319 ret = rzg2l_map_add_config(&maps[idx], pin, 320 PIN_MAP_TYPE_CONFIGS_PIN, 321 configs, num_configs); 322 if (ret < 0) 323 goto done; 324 325 idx++; 326 } 327 ret = 0; 328 goto done; 329 } 330 331 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 332 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 333 GFP_KERNEL); 334 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 335 if (!pins || !psel_val || !pin_fn) { 336 ret = -ENOMEM; 337 goto done; 338 } 339 340 /* Collect pin locations and mux settings from DT properties */ 341 for (i = 0; i < num_pinmux; ++i) { 342 u32 value; 343 344 ret = of_property_read_u32_index(np, "pinmux", i, &value); 345 if (ret) 346 goto done; 347 pins[i] = value & MUX_PIN_ID_MASK; 348 psel_val[i] = MUX_FUNC(value); 349 } 350 351 /* Register a single pin group listing all the pins we read from DT */ 352 gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL); 353 if (gsel < 0) { 354 ret = gsel; 355 goto done; 356 } 357 358 /* 359 * Register a single group function where the 'data' is an array PSEL 360 * register values read from DT. 361 */ 362 pin_fn[0] = np->name; 363 fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1, 364 psel_val); 365 if (fsel < 0) { 366 ret = fsel; 367 goto remove_group; 368 } 369 370 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 371 maps[idx].data.mux.group = np->name; 372 maps[idx].data.mux.function = np->name; 373 idx++; 374 375 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 376 ret = 0; 377 goto done; 378 379 remove_group: 380 pinctrl_generic_remove_group(pctldev, gsel); 381 done: 382 *index = idx; 383 kfree(configs); 384 return ret; 385 } 386 387 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, 388 struct pinctrl_map *map, 389 unsigned int num_maps) 390 { 391 unsigned int i; 392 393 if (!map) 394 return; 395 396 for (i = 0; i < num_maps; ++i) { 397 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 398 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 399 kfree(map[i].data.configs.configs); 400 } 401 kfree(map); 402 } 403 404 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, 405 struct device_node *np, 406 struct pinctrl_map **map, 407 unsigned int *num_maps) 408 { 409 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 410 struct device_node *child; 411 unsigned int index; 412 int ret; 413 414 *map = NULL; 415 *num_maps = 0; 416 index = 0; 417 418 for_each_child_of_node(np, child) { 419 ret = rzg2l_dt_subnode_to_map(pctldev, child, map, 420 num_maps, &index); 421 if (ret < 0) { 422 of_node_put(child); 423 goto done; 424 } 425 } 426 427 if (*num_maps == 0) { 428 ret = rzg2l_dt_subnode_to_map(pctldev, np, map, 429 num_maps, &index); 430 if (ret < 0) 431 goto done; 432 } 433 434 if (*num_maps) 435 return 0; 436 437 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 438 ret = -EINVAL; 439 440 done: 441 rzg2l_dt_free_map(pctldev, *map, *num_maps); 442 443 return ret; 444 } 445 446 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, 447 u32 cfg, u32 port, u8 bit) 448 { 449 u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg); 450 u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg); 451 u32 data; 452 453 if (bit >= pincount || port >= pctrl->data->n_port_pins) 454 return -EINVAL; 455 456 data = pctrl->data->port_pin_configs[port]; 457 if (port_index != RZG2L_GPIO_PORT_GET_INDEX(data)) 458 return -EINVAL; 459 460 return 0; 461 } 462 463 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 464 u8 bit, u32 mask) 465 { 466 void __iomem *addr = pctrl->base + offset; 467 468 /* handle _L/_H for 32-bit register read/write */ 469 if (bit >= 4) { 470 bit -= 4; 471 addr += 4; 472 } 473 474 return (readl(addr) >> (bit * 8)) & mask; 475 } 476 477 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 478 u8 bit, u32 mask, u32 val) 479 { 480 void __iomem *addr = pctrl->base + offset; 481 unsigned long flags; 482 u32 reg; 483 484 /* handle _L/_H for 32-bit register read/write */ 485 if (bit >= 4) { 486 bit -= 4; 487 addr += 4; 488 } 489 490 spin_lock_irqsave(&pctrl->lock, flags); 491 reg = readl(addr) & ~(mask << (bit * 8)); 492 writel(reg | (val << (bit * 8)), addr); 493 spin_unlock_irqrestore(&pctrl->lock, flags); 494 } 495 496 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 497 unsigned int _pin, 498 unsigned long *config) 499 { 500 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 501 enum pin_config_param param = pinconf_to_config_param(*config); 502 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 503 unsigned int *pin_data = pin->drv_data; 504 unsigned int arg = 0; 505 unsigned long flags; 506 void __iomem *addr; 507 u32 port_offset; 508 u32 cfg = 0; 509 u8 bit = 0; 510 511 if (!pin_data) 512 return -EINVAL; 513 514 if (*pin_data & RZG2L_SINGLE_PIN) { 515 port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); 516 cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); 517 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); 518 } else { 519 cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); 520 port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); 521 bit = RZG2L_PIN_ID_TO_PIN(_pin); 522 523 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 524 return -EINVAL; 525 } 526 527 switch (param) { 528 case PIN_CONFIG_INPUT_ENABLE: 529 if (!(cfg & PIN_CFG_IEN)) 530 return -EINVAL; 531 arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK); 532 if (!arg) 533 return -EINVAL; 534 break; 535 536 case PIN_CONFIG_POWER_SOURCE: { 537 u32 pwr_reg = 0x0; 538 539 if (cfg & PIN_CFG_IO_VMC_SD0) 540 pwr_reg = SD_CH(0); 541 else if (cfg & PIN_CFG_IO_VMC_SD1) 542 pwr_reg = SD_CH(1); 543 else if (cfg & PIN_CFG_IO_VMC_QSPI) 544 pwr_reg = QSPI; 545 else 546 return -EINVAL; 547 548 spin_lock_irqsave(&pctrl->lock, flags); 549 addr = pctrl->base + pwr_reg; 550 arg = (readl(addr) & PVDD_MASK) ? 1800 : 3300; 551 spin_unlock_irqrestore(&pctrl->lock, flags); 552 break; 553 } 554 555 case PIN_CONFIG_DRIVE_STRENGTH: { 556 unsigned int index; 557 558 if (!(cfg & PIN_CFG_IOLH_A)) 559 return -EINVAL; 560 561 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); 562 arg = iolh_groupa_mA[index]; 563 break; 564 } 565 566 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 567 unsigned int index; 568 569 if (!(cfg & PIN_CFG_IOLH_B)) 570 return -EINVAL; 571 572 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); 573 arg = iolh_groupb_oi[index]; 574 break; 575 } 576 577 default: 578 return -ENOTSUPP; 579 } 580 581 *config = pinconf_to_config_packed(param, arg); 582 583 return 0; 584 }; 585 586 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 587 unsigned int _pin, 588 unsigned long *_configs, 589 unsigned int num_configs) 590 { 591 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 592 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 593 unsigned int *pin_data = pin->drv_data; 594 enum pin_config_param param; 595 unsigned long flags; 596 void __iomem *addr; 597 u32 port_offset; 598 unsigned int i; 599 u32 cfg = 0; 600 u8 bit = 0; 601 602 if (!pin_data) 603 return -EINVAL; 604 605 if (*pin_data & RZG2L_SINGLE_PIN) { 606 port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); 607 cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); 608 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); 609 } else { 610 cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); 611 port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); 612 bit = RZG2L_PIN_ID_TO_PIN(_pin); 613 614 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 615 return -EINVAL; 616 } 617 618 for (i = 0; i < num_configs; i++) { 619 param = pinconf_to_config_param(_configs[i]); 620 switch (param) { 621 case PIN_CONFIG_INPUT_ENABLE: { 622 unsigned int arg = 623 pinconf_to_config_argument(_configs[i]); 624 625 if (!(cfg & PIN_CFG_IEN)) 626 return -EINVAL; 627 628 rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg); 629 break; 630 } 631 632 case PIN_CONFIG_POWER_SOURCE: { 633 unsigned int mV = pinconf_to_config_argument(_configs[i]); 634 u32 pwr_reg = 0x0; 635 636 if (mV != 1800 && mV != 3300) 637 return -EINVAL; 638 639 if (cfg & PIN_CFG_IO_VMC_SD0) 640 pwr_reg = SD_CH(0); 641 else if (cfg & PIN_CFG_IO_VMC_SD1) 642 pwr_reg = SD_CH(1); 643 else if (cfg & PIN_CFG_IO_VMC_QSPI) 644 pwr_reg = QSPI; 645 else 646 return -EINVAL; 647 648 addr = pctrl->base + pwr_reg; 649 spin_lock_irqsave(&pctrl->lock, flags); 650 writel((mV == 1800) ? PVDD_1800 : PVDD_3300, addr); 651 spin_unlock_irqrestore(&pctrl->lock, flags); 652 break; 653 } 654 655 case PIN_CONFIG_DRIVE_STRENGTH: { 656 unsigned int arg = pinconf_to_config_argument(_configs[i]); 657 unsigned int index; 658 659 if (!(cfg & PIN_CFG_IOLH_A)) 660 return -EINVAL; 661 662 for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) { 663 if (arg == iolh_groupa_mA[index]) 664 break; 665 } 666 if (index >= ARRAY_SIZE(iolh_groupa_mA)) 667 return -EINVAL; 668 669 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); 670 break; 671 } 672 673 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 674 unsigned int arg = pinconf_to_config_argument(_configs[i]); 675 unsigned int index; 676 677 if (!(cfg & PIN_CFG_IOLH_B)) 678 return -EINVAL; 679 680 for (index = 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) { 681 if (arg == iolh_groupb_oi[index]) 682 break; 683 } 684 if (index >= ARRAY_SIZE(iolh_groupb_oi)) 685 return -EINVAL; 686 687 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); 688 break; 689 } 690 691 default: 692 return -EOPNOTSUPP; 693 } 694 } 695 696 return 0; 697 } 698 699 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, 700 unsigned int group, 701 unsigned long *configs, 702 unsigned int num_configs) 703 { 704 const unsigned int *pins; 705 unsigned int i, npins; 706 int ret; 707 708 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 709 if (ret) 710 return ret; 711 712 for (i = 0; i < npins; i++) { 713 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, 714 num_configs); 715 if (ret) 716 return ret; 717 } 718 719 return 0; 720 }; 721 722 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, 723 unsigned int group, 724 unsigned long *config) 725 { 726 const unsigned int *pins; 727 unsigned int i, npins, prev_config = 0; 728 int ret; 729 730 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 731 if (ret) 732 return ret; 733 734 for (i = 0; i < npins; i++) { 735 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); 736 if (ret) 737 return ret; 738 739 /* Check config matching between to pin */ 740 if (i && prev_config != *config) 741 return -EOPNOTSUPP; 742 743 prev_config = *config; 744 } 745 746 return 0; 747 }; 748 749 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { 750 .get_groups_count = pinctrl_generic_get_group_count, 751 .get_group_name = pinctrl_generic_get_group_name, 752 .get_group_pins = pinctrl_generic_get_group_pins, 753 .dt_node_to_map = rzg2l_dt_node_to_map, 754 .dt_free_map = rzg2l_dt_free_map, 755 }; 756 757 static const struct pinmux_ops rzg2l_pinctrl_pmxops = { 758 .get_functions_count = pinmux_generic_get_function_count, 759 .get_function_name = pinmux_generic_get_function_name, 760 .get_function_groups = pinmux_generic_get_function_groups, 761 .set_mux = rzg2l_pinctrl_set_mux, 762 .strict = true, 763 }; 764 765 static const struct pinconf_ops rzg2l_pinctrl_confops = { 766 .is_generic = true, 767 .pin_config_get = rzg2l_pinctrl_pinconf_get, 768 .pin_config_set = rzg2l_pinctrl_pinconf_set, 769 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set, 770 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get, 771 .pin_config_config_dbg_show = pinconf_generic_dump_config, 772 }; 773 774 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) 775 { 776 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 777 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 778 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 779 unsigned long flags; 780 u8 reg8; 781 int ret; 782 783 ret = pinctrl_gpio_request(chip->base + offset); 784 if (ret) 785 return ret; 786 787 spin_lock_irqsave(&pctrl->lock, flags); 788 789 /* Select GPIO mode in PMC Register */ 790 reg8 = readb(pctrl->base + PMC(port)); 791 reg8 &= ~BIT(bit); 792 writeb(reg8, pctrl->base + PMC(port)); 793 794 spin_unlock_irqrestore(&pctrl->lock, flags); 795 796 return 0; 797 } 798 799 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port, 800 u8 bit, bool output) 801 { 802 unsigned long flags; 803 u16 reg16; 804 805 spin_lock_irqsave(&pctrl->lock, flags); 806 807 reg16 = readw(pctrl->base + PM(port)); 808 reg16 &= ~(PM_MASK << (bit * 2)); 809 810 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); 811 writew(reg16, pctrl->base + PM(port)); 812 813 spin_unlock_irqrestore(&pctrl->lock, flags); 814 } 815 816 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 817 { 818 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 819 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 820 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 821 822 if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) { 823 u16 reg16; 824 825 reg16 = readw(pctrl->base + PM(port)); 826 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 827 if (reg16 == PM_OUTPUT) 828 return GPIO_LINE_DIRECTION_OUT; 829 } 830 831 return GPIO_LINE_DIRECTION_IN; 832 } 833 834 static int rzg2l_gpio_direction_input(struct gpio_chip *chip, 835 unsigned int offset) 836 { 837 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 838 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 839 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 840 841 rzg2l_gpio_set_direction(pctrl, port, bit, false); 842 843 return 0; 844 } 845 846 static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, 847 int value) 848 { 849 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 850 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 851 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 852 unsigned long flags; 853 u8 reg8; 854 855 spin_lock_irqsave(&pctrl->lock, flags); 856 857 reg8 = readb(pctrl->base + P(port)); 858 859 if (value) 860 writeb(reg8 | BIT(bit), pctrl->base + P(port)); 861 else 862 writeb(reg8 & ~BIT(bit), pctrl->base + P(port)); 863 864 spin_unlock_irqrestore(&pctrl->lock, flags); 865 } 866 867 static int rzg2l_gpio_direction_output(struct gpio_chip *chip, 868 unsigned int offset, int value) 869 { 870 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 871 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 872 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 873 874 rzg2l_gpio_set(chip, offset, value); 875 rzg2l_gpio_set_direction(pctrl, port, bit, true); 876 877 return 0; 878 } 879 880 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) 881 { 882 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 883 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 884 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 885 u16 reg16; 886 887 reg16 = readw(pctrl->base + PM(port)); 888 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 889 890 if (reg16 == PM_INPUT) 891 return !!(readb(pctrl->base + PIN(port)) & BIT(bit)); 892 else if (reg16 == PM_OUTPUT) 893 return !!(readb(pctrl->base + P(port)) & BIT(bit)); 894 else 895 return -EINVAL; 896 } 897 898 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) 899 { 900 unsigned int virq; 901 902 pinctrl_gpio_free(chip->base + offset); 903 904 virq = irq_find_mapping(chip->irq.domain, offset); 905 if (virq) 906 irq_dispose_mapping(virq); 907 908 /* 909 * Set the GPIO as an input to ensure that the next GPIO request won't 910 * drive the GPIO pin as an output. 911 */ 912 rzg2l_gpio_direction_input(chip, offset); 913 } 914 915 static const char * const rzg2l_gpio_names[] = { 916 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 917 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 918 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 919 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 920 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 921 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 922 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 923 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 924 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 925 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 926 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 927 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 928 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 929 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 930 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 931 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 932 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 933 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 934 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 935 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 936 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 937 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 938 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 939 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 940 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 941 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 942 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 943 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 944 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 945 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 946 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 947 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 948 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 949 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 950 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 951 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 952 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", 953 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", 954 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", 955 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", 956 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", 957 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", 958 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", 959 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", 960 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", 961 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", 962 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", 963 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", 964 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", 965 }; 966 967 static const u32 rzg2l_gpio_configs[] = { 968 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), 969 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), 970 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), 971 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), 972 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), 973 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), 974 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), 975 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), 976 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), 977 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), 978 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), 979 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), 980 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 981 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), 982 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), 983 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), 984 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 985 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), 986 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), 987 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), 988 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 989 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 990 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 991 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 992 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 993 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 994 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 995 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 996 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 997 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 998 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 999 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1000 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1001 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1002 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1003 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1004 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1005 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1006 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), 1007 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), 1008 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), 1009 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), 1010 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), 1011 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), 1012 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), 1013 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), 1014 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), 1015 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), 1016 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), 1017 }; 1018 1019 static const u32 r9a07g043_gpio_configs[] = { 1020 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), 1021 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1022 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1023 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1024 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1025 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), 1026 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), 1027 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1028 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1029 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1030 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1031 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1032 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1033 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1034 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1035 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1036 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1037 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), 1038 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), 1039 }; 1040 1041 static struct { 1042 struct rzg2l_dedicated_configs common[35]; 1043 struct rzg2l_dedicated_configs rzg2l_pins[7]; 1044 } rzg2l_dedicated_pins = { 1045 .common = { 1046 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, 1047 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, 1048 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, 1049 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1050 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, 1051 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1052 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, 1053 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, 1054 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, 1055 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1056 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 1057 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1058 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, 1059 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1060 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, 1061 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1062 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, 1063 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1064 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, 1065 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1066 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, 1067 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1068 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, 1069 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1070 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, 1071 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1072 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, 1073 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1074 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, 1075 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1076 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, 1077 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, 1078 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, 1079 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1080 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, 1081 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1082 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, 1083 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1084 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, 1085 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1086 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, 1087 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1088 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, 1089 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1090 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, 1091 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1092 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, 1093 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1094 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, 1095 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1096 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, 1097 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1098 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, 1099 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1100 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, 1101 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1102 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, 1103 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1104 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, 1105 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, 1106 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, 1107 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, 1108 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, 1109 }, 1110 .rzg2l_pins = { 1111 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1112 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, 1113 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1114 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, 1115 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1116 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, 1117 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1118 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, 1119 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1120 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, 1121 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1122 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, 1123 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1124 } 1125 }; 1126 1127 static int rzg2l_gpio_get_gpioint(unsigned int virq) 1128 { 1129 unsigned int gpioint; 1130 unsigned int i; 1131 u32 port, bit; 1132 1133 port = virq / 8; 1134 bit = virq % 8; 1135 1136 if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || 1137 bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) 1138 return -EINVAL; 1139 1140 gpioint = bit; 1141 for (i = 0; i < port; i++) 1142 gpioint += RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]); 1143 1144 return gpioint; 1145 } 1146 1147 static void rzg2l_gpio_irq_disable(struct irq_data *d) 1148 { 1149 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1150 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1151 unsigned int hwirq = irqd_to_hwirq(d); 1152 unsigned long flags; 1153 void __iomem *addr; 1154 u32 port; 1155 u8 bit; 1156 1157 port = RZG2L_PIN_ID_TO_PORT(hwirq); 1158 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 1159 1160 addr = pctrl->base + ISEL(port); 1161 if (bit >= 4) { 1162 bit -= 4; 1163 addr += 4; 1164 } 1165 1166 spin_lock_irqsave(&pctrl->lock, flags); 1167 writel(readl(addr) & ~BIT(bit * 8), addr); 1168 spin_unlock_irqrestore(&pctrl->lock, flags); 1169 1170 gpiochip_disable_irq(gc, hwirq); 1171 irq_chip_disable_parent(d); 1172 } 1173 1174 static void rzg2l_gpio_irq_enable(struct irq_data *d) 1175 { 1176 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1177 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1178 unsigned int hwirq = irqd_to_hwirq(d); 1179 unsigned long flags; 1180 void __iomem *addr; 1181 u32 port; 1182 u8 bit; 1183 1184 gpiochip_enable_irq(gc, hwirq); 1185 1186 port = RZG2L_PIN_ID_TO_PORT(hwirq); 1187 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 1188 1189 addr = pctrl->base + ISEL(port); 1190 if (bit >= 4) { 1191 bit -= 4; 1192 addr += 4; 1193 } 1194 1195 spin_lock_irqsave(&pctrl->lock, flags); 1196 writel(readl(addr) | BIT(bit * 8), addr); 1197 spin_unlock_irqrestore(&pctrl->lock, flags); 1198 1199 irq_chip_enable_parent(d); 1200 } 1201 1202 static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) 1203 { 1204 return irq_chip_set_type_parent(d, type); 1205 } 1206 1207 static void rzg2l_gpio_irqc_eoi(struct irq_data *d) 1208 { 1209 irq_chip_eoi_parent(d); 1210 } 1211 1212 static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) 1213 { 1214 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 1215 1216 seq_printf(p, dev_name(gc->parent)); 1217 } 1218 1219 static const struct irq_chip rzg2l_gpio_irqchip = { 1220 .name = "rzg2l-gpio", 1221 .irq_disable = rzg2l_gpio_irq_disable, 1222 .irq_enable = rzg2l_gpio_irq_enable, 1223 .irq_mask = irq_chip_mask_parent, 1224 .irq_unmask = irq_chip_unmask_parent, 1225 .irq_set_type = rzg2l_gpio_irq_set_type, 1226 .irq_eoi = rzg2l_gpio_irqc_eoi, 1227 .irq_print_chip = rzg2l_gpio_irq_print_chip, 1228 .flags = IRQCHIP_IMMUTABLE, 1229 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1230 }; 1231 1232 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 1233 unsigned int child, 1234 unsigned int child_type, 1235 unsigned int *parent, 1236 unsigned int *parent_type) 1237 { 1238 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 1239 unsigned long flags; 1240 int gpioint, irq; 1241 1242 gpioint = rzg2l_gpio_get_gpioint(child); 1243 if (gpioint < 0) 1244 return gpioint; 1245 1246 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 1247 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); 1248 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 1249 if (irq < 0) 1250 return -ENOSPC; 1251 pctrl->hwirq[irq] = child; 1252 irq += RZG2L_TINT_IRQ_START_INDEX; 1253 1254 /* All these interrupts are level high in the CPU */ 1255 *parent_type = IRQ_TYPE_LEVEL_HIGH; 1256 *parent = RZG2L_PACK_HWIRQ(gpioint, irq); 1257 return 0; 1258 } 1259 1260 static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, 1261 union gpio_irq_fwspec *gfwspec, 1262 unsigned int parent_hwirq, 1263 unsigned int parent_type) 1264 { 1265 struct irq_fwspec *fwspec = &gfwspec->fwspec; 1266 1267 fwspec->fwnode = chip->irq.parent_domain->fwnode; 1268 fwspec->param_count = 2; 1269 fwspec->param[0] = parent_hwirq; 1270 fwspec->param[1] = parent_type; 1271 1272 return 0; 1273 } 1274 1275 static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1276 unsigned int nr_irqs) 1277 { 1278 struct irq_data *d; 1279 1280 d = irq_domain_get_irq_data(domain, virq); 1281 if (d) { 1282 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1283 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1284 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1285 unsigned long flags; 1286 unsigned int i; 1287 1288 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 1289 if (pctrl->hwirq[i] == hwirq) { 1290 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 1291 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); 1292 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 1293 pctrl->hwirq[i] = 0; 1294 break; 1295 } 1296 } 1297 } 1298 irq_domain_free_irqs_common(domain, virq, nr_irqs); 1299 } 1300 1301 static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, 1302 unsigned long *valid_mask, 1303 unsigned int ngpios) 1304 { 1305 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 1306 struct gpio_chip *chip = &pctrl->gpio_chip; 1307 unsigned int offset; 1308 1309 /* Forbid unused lines to be mapped as IRQs */ 1310 for (offset = 0; offset < chip->ngpio; offset++) { 1311 u32 port, bit; 1312 1313 port = offset / 8; 1314 bit = offset % 8; 1315 1316 if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || 1317 bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) 1318 clear_bit(offset, valid_mask); 1319 } 1320 } 1321 1322 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) 1323 { 1324 struct device_node *np = pctrl->dev->of_node; 1325 struct gpio_chip *chip = &pctrl->gpio_chip; 1326 const char *name = dev_name(pctrl->dev); 1327 struct irq_domain *parent_domain; 1328 struct of_phandle_args of_args; 1329 struct device_node *parent_np; 1330 struct gpio_irq_chip *girq; 1331 int ret; 1332 1333 parent_np = of_irq_find_parent(np); 1334 if (!parent_np) 1335 return -ENXIO; 1336 1337 parent_domain = irq_find_host(parent_np); 1338 of_node_put(parent_np); 1339 if (!parent_domain) 1340 return -EPROBE_DEFER; 1341 1342 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); 1343 if (ret) { 1344 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); 1345 return ret; 1346 } 1347 1348 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 1349 of_args.args[2] != pctrl->data->n_port_pins) { 1350 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); 1351 return -EINVAL; 1352 } 1353 1354 chip->names = pctrl->data->port_pins; 1355 chip->request = rzg2l_gpio_request; 1356 chip->free = rzg2l_gpio_free; 1357 chip->get_direction = rzg2l_gpio_get_direction; 1358 chip->direction_input = rzg2l_gpio_direction_input; 1359 chip->direction_output = rzg2l_gpio_direction_output; 1360 chip->get = rzg2l_gpio_get; 1361 chip->set = rzg2l_gpio_set; 1362 chip->label = name; 1363 chip->parent = pctrl->dev; 1364 chip->owner = THIS_MODULE; 1365 chip->base = -1; 1366 chip->ngpio = of_args.args[2]; 1367 1368 girq = &chip->irq; 1369 gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip); 1370 girq->fwnode = of_node_to_fwnode(np); 1371 girq->parent_domain = parent_domain; 1372 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; 1373 girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec; 1374 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; 1375 girq->init_valid_mask = rzg2l_init_irq_valid_mask; 1376 1377 pctrl->gpio_range.id = 0; 1378 pctrl->gpio_range.pin_base = 0; 1379 pctrl->gpio_range.base = 0; 1380 pctrl->gpio_range.npins = chip->ngpio; 1381 pctrl->gpio_range.name = chip->label; 1382 pctrl->gpio_range.gc = chip; 1383 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 1384 if (ret) { 1385 dev_err(pctrl->dev, "failed to add GPIO controller\n"); 1386 return ret; 1387 } 1388 1389 dev_dbg(pctrl->dev, "Registered gpio controller\n"); 1390 1391 return 0; 1392 } 1393 1394 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) 1395 { 1396 struct pinctrl_pin_desc *pins; 1397 unsigned int i, j; 1398 u32 *pin_data; 1399 int ret; 1400 1401 pctrl->desc.name = DRV_NAME; 1402 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; 1403 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; 1404 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; 1405 pctrl->desc.confops = &rzg2l_pinctrl_confops; 1406 pctrl->desc.owner = THIS_MODULE; 1407 1408 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); 1409 if (!pins) 1410 return -ENOMEM; 1411 1412 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, 1413 sizeof(*pin_data), GFP_KERNEL); 1414 if (!pin_data) 1415 return -ENOMEM; 1416 1417 pctrl->pins = pins; 1418 pctrl->desc.pins = pins; 1419 1420 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 1421 pins[i].number = i; 1422 pins[i].name = pctrl->data->port_pins[i]; 1423 if (i && !(i % RZG2L_PINS_PER_PORT)) 1424 j++; 1425 pin_data[i] = pctrl->data->port_pin_configs[j]; 1426 pins[i].drv_data = &pin_data[i]; 1427 } 1428 1429 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { 1430 unsigned int index = pctrl->data->n_port_pins + i; 1431 1432 pins[index].number = index; 1433 pins[index].name = pctrl->data->dedicated_pins[i].name; 1434 pin_data[index] = pctrl->data->dedicated_pins[i].config; 1435 pins[index].drv_data = &pin_data[index]; 1436 } 1437 1438 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, 1439 &pctrl->pctl); 1440 if (ret) { 1441 dev_err(pctrl->dev, "pinctrl registration failed\n"); 1442 return ret; 1443 } 1444 1445 ret = pinctrl_enable(pctrl->pctl); 1446 if (ret) { 1447 dev_err(pctrl->dev, "pinctrl enable failed\n"); 1448 return ret; 1449 } 1450 1451 ret = rzg2l_gpio_register(pctrl); 1452 if (ret) { 1453 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); 1454 return ret; 1455 } 1456 1457 return 0; 1458 } 1459 1460 static void rzg2l_pinctrl_clk_disable(void *data) 1461 { 1462 clk_disable_unprepare(data); 1463 } 1464 1465 static int rzg2l_pinctrl_probe(struct platform_device *pdev) 1466 { 1467 struct rzg2l_pinctrl *pctrl; 1468 int ret; 1469 1470 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1471 if (!pctrl) 1472 return -ENOMEM; 1473 1474 pctrl->dev = &pdev->dev; 1475 1476 pctrl->data = of_device_get_match_data(&pdev->dev); 1477 if (!pctrl->data) 1478 return -EINVAL; 1479 1480 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 1481 if (IS_ERR(pctrl->base)) 1482 return PTR_ERR(pctrl->base); 1483 1484 pctrl->clk = devm_clk_get(pctrl->dev, NULL); 1485 if (IS_ERR(pctrl->clk)) { 1486 ret = PTR_ERR(pctrl->clk); 1487 dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); 1488 return ret; 1489 } 1490 1491 spin_lock_init(&pctrl->lock); 1492 spin_lock_init(&pctrl->bitmap_lock); 1493 1494 platform_set_drvdata(pdev, pctrl); 1495 1496 ret = clk_prepare_enable(pctrl->clk); 1497 if (ret) { 1498 dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); 1499 return ret; 1500 } 1501 1502 ret = devm_add_action_or_reset(&pdev->dev, rzg2l_pinctrl_clk_disable, 1503 pctrl->clk); 1504 if (ret) { 1505 dev_err(pctrl->dev, 1506 "failed to register GPIO clk disable action, %i\n", 1507 ret); 1508 return ret; 1509 } 1510 1511 ret = rzg2l_pinctrl_register(pctrl); 1512 if (ret) 1513 return ret; 1514 1515 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); 1516 return 0; 1517 } 1518 1519 static struct rzg2l_pinctrl_data r9a07g043_data = { 1520 .port_pins = rzg2l_gpio_names, 1521 .port_pin_configs = r9a07g043_gpio_configs, 1522 .dedicated_pins = rzg2l_dedicated_pins.common, 1523 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, 1524 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), 1525 }; 1526 1527 static struct rzg2l_pinctrl_data r9a07g044_data = { 1528 .port_pins = rzg2l_gpio_names, 1529 .port_pin_configs = rzg2l_gpio_configs, 1530 .dedicated_pins = rzg2l_dedicated_pins.common, 1531 .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), 1532 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + 1533 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), 1534 }; 1535 1536 static const struct of_device_id rzg2l_pinctrl_of_table[] = { 1537 { 1538 .compatible = "renesas,r9a07g043-pinctrl", 1539 .data = &r9a07g043_data, 1540 }, 1541 { 1542 .compatible = "renesas,r9a07g044-pinctrl", 1543 .data = &r9a07g044_data, 1544 }, 1545 { /* sentinel */ } 1546 }; 1547 1548 static struct platform_driver rzg2l_pinctrl_driver = { 1549 .driver = { 1550 .name = DRV_NAME, 1551 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), 1552 }, 1553 .probe = rzg2l_pinctrl_probe, 1554 }; 1555 1556 static int __init rzg2l_pinctrl_init(void) 1557 { 1558 return platform_driver_register(&rzg2l_pinctrl_driver); 1559 } 1560 core_initcall(rzg2l_pinctrl_init); 1561 1562 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 1563 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); 1564 MODULE_LICENSE("GPL v2"); 1565