1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC 4 * 5 * Copyright (C) 2018 Chris Brandt 6 */ 7 8 /* 9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A2 10 * family. 11 */ 12 13 #include <linux/bitops.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/mutex.h> 18 #include <linux/of_device.h> 19 #include <linux/pinctrl/pinmux.h> 20 21 #include "../core.h" 22 #include "../pinmux.h" 23 24 #define DRIVER_NAME "pinctrl-rza2" 25 26 #define RZA2_PINS_PER_PORT 8 27 #define RZA2_PIN_ID_TO_PORT(id) ((id) / RZA2_PINS_PER_PORT) 28 #define RZA2_PIN_ID_TO_PIN(id) ((id) % RZA2_PINS_PER_PORT) 29 30 /* 31 * Use 16 lower bits [15:0] for pin identifier 32 * Use 16 higher bits [31:16] for pin mux function 33 */ 34 #define MUX_PIN_ID_MASK GENMASK(15, 0) 35 #define MUX_FUNC_MASK GENMASK(31, 16) 36 #define MUX_FUNC_OFFS 16 37 #define MUX_FUNC(pinconf) ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) 38 39 static const char port_names[] = "0123456789ABCDEFGHJKLM"; 40 41 struct rza2_pinctrl_priv { 42 struct device *dev; 43 void __iomem *base; 44 45 struct pinctrl_pin_desc *pins; 46 struct pinctrl_desc desc; 47 struct pinctrl_dev *pctl; 48 struct pinctrl_gpio_range gpio_range; 49 int npins; 50 struct mutex mutex; /* serialize adding groups and functions */ 51 }; 52 53 #define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */ 54 #define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */ 55 #define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */ 56 #define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */ 57 #define RZA2_DSCR(port) (0x0140 + (port) * 2) /* Drive 16-bit */ 58 #define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */ 59 60 #define RZA2_PWPR 0x02ff /* Write Protect 8-bit */ 61 #define RZA2_PFENET 0x0820 /* Ethernet Pins 8-bit */ 62 #define RZA2_PPOC 0x0900 /* Dedicated Pins 32-bit */ 63 #define RZA2_PHMOMO 0x0980 /* Peripheral Pins 32-bit */ 64 #define RZA2_PCKIO 0x09d0 /* CKIO Drive 8-bit */ 65 66 #define RZA2_PDR_INPUT 0x02 67 #define RZA2_PDR_OUTPUT 0x03 68 #define RZA2_PDR_MASK 0x03 69 70 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ 71 #define PWPR_PFSWE BIT(6) /* PFS Register Write Enable */ 72 #define PFS_ISEL BIT(6) /* Interrupt Select */ 73 74 static void rza2_set_pin_function(void __iomem *pfc_base, u8 port, u8 pin, 75 u8 func) 76 { 77 u16 mask16; 78 u16 reg16; 79 u8 reg8; 80 81 /* Set pin to 'Non-use (Hi-z input protection)' */ 82 reg16 = readw(pfc_base + RZA2_PDR(port)); 83 mask16 = RZA2_PDR_MASK << (pin * 2); 84 reg16 &= ~mask16; 85 writew(reg16, pfc_base + RZA2_PDR(port)); 86 87 /* Temporarily switch to GPIO */ 88 reg8 = readb(pfc_base + RZA2_PMR(port)); 89 reg8 &= ~BIT(pin); 90 writeb(reg8, pfc_base + RZA2_PMR(port)); 91 92 /* PFS Register Write Protect : OFF */ 93 writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */ 94 writeb(PWPR_PFSWE, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=1 */ 95 96 /* Set Pin function (interrupt disabled, ISEL=0) */ 97 writeb(func, pfc_base + RZA2_PFS(port, pin)); 98 99 /* PFS Register Write Protect : ON */ 100 writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */ 101 writeb(0x80, pfc_base + RZA2_PWPR); /* B0WI=1, PFSWE=0 */ 102 103 /* Port Mode : Peripheral module pin functions */ 104 reg8 = readb(pfc_base + RZA2_PMR(port)); 105 reg8 |= BIT(pin); 106 writeb(reg8, pfc_base + RZA2_PMR(port)); 107 } 108 109 static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset, 110 u8 dir) 111 { 112 u8 port = RZA2_PIN_ID_TO_PORT(offset); 113 u8 pin = RZA2_PIN_ID_TO_PIN(offset); 114 u16 mask16; 115 u16 reg16; 116 117 reg16 = readw(pfc_base + RZA2_PDR(port)); 118 mask16 = RZA2_PDR_MASK << (pin * 2); 119 reg16 &= ~mask16; 120 121 if (dir) 122 reg16 |= RZA2_PDR_INPUT << (pin * 2); /* pin as input */ 123 else 124 reg16 |= RZA2_PDR_OUTPUT << (pin * 2); /* pin as output */ 125 126 writew(reg16, pfc_base + RZA2_PDR(port)); 127 } 128 129 static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset) 130 { 131 struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); 132 u8 port = RZA2_PIN_ID_TO_PORT(offset); 133 u8 pin = RZA2_PIN_ID_TO_PIN(offset); 134 u16 reg16; 135 136 reg16 = readw(priv->base + RZA2_PDR(port)); 137 reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK; 138 139 if (reg16 == RZA2_PDR_OUTPUT) 140 return GPIO_LINE_DIRECTION_OUT; 141 142 if (reg16 == RZA2_PDR_INPUT) 143 return GPIO_LINE_DIRECTION_IN; 144 145 /* 146 * This GPIO controller has a default Hi-Z state that is not input or 147 * output, so force the pin to input now. 148 */ 149 rza2_pin_to_gpio(priv->base, offset, 1); 150 151 return GPIO_LINE_DIRECTION_IN; 152 } 153 154 static int rza2_chip_direction_input(struct gpio_chip *chip, 155 unsigned int offset) 156 { 157 struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); 158 159 rza2_pin_to_gpio(priv->base, offset, 1); 160 161 return 0; 162 } 163 164 static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset) 165 { 166 struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); 167 u8 port = RZA2_PIN_ID_TO_PORT(offset); 168 u8 pin = RZA2_PIN_ID_TO_PIN(offset); 169 170 return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin)); 171 } 172 173 static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset, 174 int value) 175 { 176 struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); 177 u8 port = RZA2_PIN_ID_TO_PORT(offset); 178 u8 pin = RZA2_PIN_ID_TO_PIN(offset); 179 u8 new_value; 180 181 new_value = readb(priv->base + RZA2_PODR(port)); 182 183 if (value) 184 new_value |= BIT(pin); 185 else 186 new_value &= ~BIT(pin); 187 188 writeb(new_value, priv->base + RZA2_PODR(port)); 189 } 190 191 static int rza2_chip_direction_output(struct gpio_chip *chip, 192 unsigned int offset, int val) 193 { 194 struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); 195 196 rza2_chip_set(chip, offset, val); 197 rza2_pin_to_gpio(priv->base, offset, 0); 198 199 return 0; 200 } 201 202 static const char * const rza2_gpio_names[] = { 203 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 204 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 205 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 206 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 207 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 208 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 209 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 210 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 211 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 212 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 213 "PA_0", "PA_1", "PA_2", "PA_3", "PA_4", "PA_5", "PA_6", "PA_7", 214 "PB_0", "PB_1", "PB_2", "PB_3", "PB_4", "PB_5", "PB_6", "PB_7", 215 "PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7", 216 "PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7", 217 "PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7", 218 "PF_0", "PF_1", "PF_2", "PF_3", "PF_4", "PF_5", "PF_6", "PF_7", 219 "PG_0", "PG_1", "PG_2", "PG_3", "PG_4", "PG_5", "PG_6", "PG_7", 220 "PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7", 221 /* port I does not exist */ 222 "PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7", 223 "PK_0", "PK_1", "PK_2", "PK_3", "PK_4", "PK_5", "PK_6", "PK_7", 224 "PL_0", "PL_1", "PL_2", "PL_3", "PL_4", "PL_5", "PL_6", "PL_7", 225 "PM_0", "PM_1", "PM_2", "PM_3", "PM_4", "PM_5", "PM_6", "PM_7", 226 }; 227 228 static struct gpio_chip chip = { 229 .names = rza2_gpio_names, 230 .base = -1, 231 .get_direction = rza2_chip_get_direction, 232 .direction_input = rza2_chip_direction_input, 233 .direction_output = rza2_chip_direction_output, 234 .get = rza2_chip_get, 235 .set = rza2_chip_set, 236 }; 237 238 static int rza2_gpio_register(struct rza2_pinctrl_priv *priv) 239 { 240 struct device_node *np = priv->dev->of_node; 241 struct of_phandle_args of_args; 242 int ret; 243 244 chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np); 245 chip.parent = priv->dev; 246 chip.ngpio = priv->npins; 247 248 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, 249 &of_args); 250 if (ret) { 251 dev_err(priv->dev, "Unable to parse gpio-ranges\n"); 252 return ret; 253 } 254 255 if ((of_args.args[0] != 0) || 256 (of_args.args[1] != 0) || 257 (of_args.args[2] != priv->npins)) { 258 dev_err(priv->dev, "gpio-ranges does not match selected SOC\n"); 259 return -EINVAL; 260 } 261 priv->gpio_range.id = 0; 262 priv->gpio_range.pin_base = priv->gpio_range.base = 0; 263 priv->gpio_range.npins = priv->npins; 264 priv->gpio_range.name = chip.label; 265 priv->gpio_range.gc = &chip; 266 267 /* Register our gpio chip with gpiolib */ 268 ret = devm_gpiochip_add_data(priv->dev, &chip, priv); 269 if (ret) 270 return ret; 271 272 /* Register pin range with pinctrl core */ 273 pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range); 274 275 dev_dbg(priv->dev, "Registered gpio controller\n"); 276 277 return 0; 278 } 279 280 static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv) 281 { 282 struct pinctrl_pin_desc *pins; 283 unsigned int i; 284 int ret; 285 286 pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL); 287 if (!pins) 288 return -ENOMEM; 289 290 priv->pins = pins; 291 priv->desc.pins = pins; 292 priv->desc.npins = priv->npins; 293 294 for (i = 0; i < priv->npins; i++) { 295 pins[i].number = i; 296 pins[i].name = rza2_gpio_names[i]; 297 } 298 299 ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv, 300 &priv->pctl); 301 if (ret) { 302 dev_err(priv->dev, "pinctrl registration failed\n"); 303 return ret; 304 } 305 306 ret = pinctrl_enable(priv->pctl); 307 if (ret) { 308 dev_err(priv->dev, "pinctrl enable failed\n"); 309 return ret; 310 } 311 312 ret = rza2_gpio_register(priv); 313 if (ret) { 314 dev_err(priv->dev, "GPIO registration failed\n"); 315 return ret; 316 } 317 318 return 0; 319 } 320 321 /* 322 * For each DT node, create a single pin mapping. That pin mapping will only 323 * contain a single group of pins, and that group of pins will only have a 324 * single function that can be selected. 325 */ 326 static int rza2_dt_node_to_map(struct pinctrl_dev *pctldev, 327 struct device_node *np, 328 struct pinctrl_map **map, 329 unsigned int *num_maps) 330 { 331 struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 332 unsigned int *pins, *psel_val; 333 int i, ret, npins, gsel, fsel; 334 struct property *of_pins; 335 const char **pin_fn; 336 337 /* Find out how many pins to map */ 338 of_pins = of_find_property(np, "pinmux", NULL); 339 if (!of_pins) { 340 dev_info(priv->dev, "Missing pinmux property\n"); 341 return -ENOENT; 342 } 343 npins = of_pins->length / sizeof(u32); 344 345 pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL); 346 psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val), 347 GFP_KERNEL); 348 pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL); 349 if (!pins || !psel_val || !pin_fn) 350 return -ENOMEM; 351 352 /* Collect pin locations and mux settings from DT properties */ 353 for (i = 0; i < npins; ++i) { 354 u32 value; 355 356 ret = of_property_read_u32_index(np, "pinmux", i, &value); 357 if (ret) 358 return ret; 359 pins[i] = value & MUX_PIN_ID_MASK; 360 psel_val[i] = MUX_FUNC(value); 361 } 362 363 mutex_lock(&priv->mutex); 364 365 /* Register a single pin group listing all the pins we read from DT */ 366 gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL); 367 if (gsel < 0) { 368 ret = gsel; 369 goto unlock; 370 } 371 372 /* 373 * Register a single group function where the 'data' is an array PSEL 374 * register values read from DT. 375 */ 376 pin_fn[0] = np->name; 377 fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1, 378 psel_val); 379 if (fsel < 0) { 380 ret = fsel; 381 goto remove_group; 382 } 383 384 dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins); 385 386 /* Create map where to retrieve function and mux settings from */ 387 *num_maps = 0; 388 *map = kzalloc(sizeof(**map), GFP_KERNEL); 389 if (!*map) { 390 ret = -ENOMEM; 391 goto remove_function; 392 } 393 394 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; 395 (*map)->data.mux.group = np->name; 396 (*map)->data.mux.function = np->name; 397 *num_maps = 1; 398 399 mutex_unlock(&priv->mutex); 400 401 return 0; 402 403 remove_function: 404 pinmux_generic_remove_function(pctldev, fsel); 405 406 remove_group: 407 pinctrl_generic_remove_group(pctldev, gsel); 408 409 unlock: 410 mutex_unlock(&priv->mutex); 411 412 dev_err(priv->dev, "Unable to parse DT node %s\n", np->name); 413 414 return ret; 415 } 416 417 static void rza2_dt_free_map(struct pinctrl_dev *pctldev, 418 struct pinctrl_map *map, unsigned int num_maps) 419 { 420 kfree(map); 421 } 422 423 static const struct pinctrl_ops rza2_pinctrl_ops = { 424 .get_groups_count = pinctrl_generic_get_group_count, 425 .get_group_name = pinctrl_generic_get_group_name, 426 .get_group_pins = pinctrl_generic_get_group_pins, 427 .dt_node_to_map = rza2_dt_node_to_map, 428 .dt_free_map = rza2_dt_free_map, 429 }; 430 431 static int rza2_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, 432 unsigned int group) 433 { 434 struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); 435 struct function_desc *func; 436 unsigned int i, *psel_val; 437 struct group_desc *grp; 438 439 grp = pinctrl_generic_get_group(pctldev, group); 440 if (!grp) 441 return -EINVAL; 442 443 func = pinmux_generic_get_function(pctldev, selector); 444 if (!func) 445 return -EINVAL; 446 447 psel_val = func->data; 448 449 for (i = 0; i < grp->num_pins; ++i) { 450 dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n", 451 port_names[RZA2_PIN_ID_TO_PORT(grp->pins[i])], 452 RZA2_PIN_ID_TO_PIN(grp->pins[i]), 453 psel_val[i]); 454 rza2_set_pin_function( 455 priv->base, 456 RZA2_PIN_ID_TO_PORT(grp->pins[i]), 457 RZA2_PIN_ID_TO_PIN(grp->pins[i]), 458 psel_val[i]); 459 } 460 461 return 0; 462 } 463 464 static const struct pinmux_ops rza2_pinmux_ops = { 465 .get_functions_count = pinmux_generic_get_function_count, 466 .get_function_name = pinmux_generic_get_function_name, 467 .get_function_groups = pinmux_generic_get_function_groups, 468 .set_mux = rza2_set_mux, 469 .strict = true, 470 }; 471 472 static int rza2_pinctrl_probe(struct platform_device *pdev) 473 { 474 struct rza2_pinctrl_priv *priv; 475 int ret; 476 477 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 478 if (!priv) 479 return -ENOMEM; 480 481 priv->dev = &pdev->dev; 482 483 priv->base = devm_platform_ioremap_resource(pdev, 0); 484 if (IS_ERR(priv->base)) 485 return PTR_ERR(priv->base); 486 487 mutex_init(&priv->mutex); 488 489 platform_set_drvdata(pdev, priv); 490 491 priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) * 492 RZA2_PINS_PER_PORT; 493 494 priv->desc.name = DRIVER_NAME; 495 priv->desc.pctlops = &rza2_pinctrl_ops; 496 priv->desc.pmxops = &rza2_pinmux_ops; 497 priv->desc.owner = THIS_MODULE; 498 499 ret = rza2_pinctrl_register(priv); 500 if (ret) 501 return ret; 502 503 dev_info(&pdev->dev, "Registered ports P0 - P%c\n", 504 port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]); 505 506 return 0; 507 } 508 509 static const struct of_device_id rza2_pinctrl_of_match[] = { 510 { .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, }, 511 { /* sentinel */ } 512 }; 513 514 static struct platform_driver rza2_pinctrl_driver = { 515 .driver = { 516 .name = DRIVER_NAME, 517 .of_match_table = rza2_pinctrl_of_match, 518 }, 519 .probe = rza2_pinctrl_probe, 520 }; 521 522 static int __init rza2_pinctrl_init(void) 523 { 524 return platform_driver_register(&rza2_pinctrl_driver); 525 } 526 core_initcall(rza2_pinctrl_init); 527 528 MODULE_AUTHOR("Chris Brandt <chris.brandt@renesas.com>"); 529 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC"); 530