1077365a9SGeert Uytterhoeven // SPDX-License-Identifier: GPL-2.0 2077365a9SGeert Uytterhoeven /* 3077365a9SGeert Uytterhoeven * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC 4077365a9SGeert Uytterhoeven * 5077365a9SGeert Uytterhoeven * Copyright (C) 2017 Jacopo Mondi 6077365a9SGeert Uytterhoeven */ 7077365a9SGeert Uytterhoeven 8077365a9SGeert Uytterhoeven /* 9077365a9SGeert Uytterhoeven * This pin controller/gpio combined driver supports Renesas devices of RZ/A1 10077365a9SGeert Uytterhoeven * family. 11077365a9SGeert Uytterhoeven * This includes SoCs which are sub- or super- sets of this particular line, 12077365a9SGeert Uytterhoeven * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020). 13077365a9SGeert Uytterhoeven */ 14077365a9SGeert Uytterhoeven 15077365a9SGeert Uytterhoeven #include <linux/bitops.h> 16077365a9SGeert Uytterhoeven #include <linux/err.h> 17077365a9SGeert Uytterhoeven #include <linux/gpio/driver.h> 18077365a9SGeert Uytterhoeven #include <linux/init.h> 19077365a9SGeert Uytterhoeven #include <linux/ioport.h> 20077365a9SGeert Uytterhoeven #include <linux/module.h> 21077365a9SGeert Uytterhoeven #include <linux/of.h> 22077365a9SGeert Uytterhoeven #include <linux/pinctrl/pinconf-generic.h> 23077365a9SGeert Uytterhoeven #include <linux/pinctrl/pinctrl.h> 24077365a9SGeert Uytterhoeven #include <linux/pinctrl/pinmux.h> 25060f03e9SRob Herring #include <linux/platform_device.h> 265e455dd9SAndy Shevchenko #include <linux/property.h> 27077365a9SGeert Uytterhoeven #include <linux/slab.h> 28077365a9SGeert Uytterhoeven 29077365a9SGeert Uytterhoeven #include "../core.h" 30077365a9SGeert Uytterhoeven #include "../devicetree.h" 31077365a9SGeert Uytterhoeven #include "../pinconf.h" 32077365a9SGeert Uytterhoeven #include "../pinmux.h" 33077365a9SGeert Uytterhoeven 34077365a9SGeert Uytterhoeven #define DRIVER_NAME "pinctrl-rza1" 35077365a9SGeert Uytterhoeven 36077365a9SGeert Uytterhoeven #define RZA1_P_REG 0x0000 37077365a9SGeert Uytterhoeven #define RZA1_PPR_REG 0x0200 38077365a9SGeert Uytterhoeven #define RZA1_PM_REG 0x0300 39077365a9SGeert Uytterhoeven #define RZA1_PMC_REG 0x0400 40077365a9SGeert Uytterhoeven #define RZA1_PFC_REG 0x0500 41077365a9SGeert Uytterhoeven #define RZA1_PFCE_REG 0x0600 42077365a9SGeert Uytterhoeven #define RZA1_PFCEA_REG 0x0a00 43077365a9SGeert Uytterhoeven #define RZA1_PIBC_REG 0x4000 44077365a9SGeert Uytterhoeven #define RZA1_PBDC_REG 0x4100 45077365a9SGeert Uytterhoeven #define RZA1_PIPC_REG 0x4200 46077365a9SGeert Uytterhoeven 47077365a9SGeert Uytterhoeven #define RZA1_ADDR(mem, reg, port) ((mem) + (reg) + ((port) * 4)) 48077365a9SGeert Uytterhoeven 49077365a9SGeert Uytterhoeven #define RZA1_NPORTS 12 50077365a9SGeert Uytterhoeven #define RZA1_PINS_PER_PORT 16 51077365a9SGeert Uytterhoeven #define RZA1_NPINS (RZA1_PINS_PER_PORT * RZA1_NPORTS) 52077365a9SGeert Uytterhoeven #define RZA1_PIN_ID_TO_PORT(id) ((id) / RZA1_PINS_PER_PORT) 53077365a9SGeert Uytterhoeven #define RZA1_PIN_ID_TO_PIN(id) ((id) % RZA1_PINS_PER_PORT) 54077365a9SGeert Uytterhoeven 55077365a9SGeert Uytterhoeven /* 56077365a9SGeert Uytterhoeven * Use 16 lower bits [15:0] for pin identifier 57077365a9SGeert Uytterhoeven * Use 16 higher bits [31:16] for pin mux function 58077365a9SGeert Uytterhoeven */ 59077365a9SGeert Uytterhoeven #define MUX_PIN_ID_MASK GENMASK(15, 0) 60077365a9SGeert Uytterhoeven #define MUX_FUNC_MASK GENMASK(31, 16) 61077365a9SGeert Uytterhoeven 62077365a9SGeert Uytterhoeven #define MUX_FUNC_OFFS 16 63077365a9SGeert Uytterhoeven #define MUX_FUNC(pinconf) \ 64077365a9SGeert Uytterhoeven ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) 65077365a9SGeert Uytterhoeven #define MUX_FUNC_PFC_MASK BIT(0) 66077365a9SGeert Uytterhoeven #define MUX_FUNC_PFCE_MASK BIT(1) 67077365a9SGeert Uytterhoeven #define MUX_FUNC_PFCEA_MASK BIT(2) 68077365a9SGeert Uytterhoeven 69077365a9SGeert Uytterhoeven /* Pin mux flags */ 70077365a9SGeert Uytterhoeven #define MUX_FLAGS_BIDIR BIT(0) 71077365a9SGeert Uytterhoeven #define MUX_FLAGS_SWIO_INPUT BIT(1) 72077365a9SGeert Uytterhoeven #define MUX_FLAGS_SWIO_OUTPUT BIT(2) 73077365a9SGeert Uytterhoeven 74077365a9SGeert Uytterhoeven /* ---------------------------------------------------------------------------- 75077365a9SGeert Uytterhoeven * RZ/A1 pinmux flags 76077365a9SGeert Uytterhoeven */ 77077365a9SGeert Uytterhoeven 78077365a9SGeert Uytterhoeven /* 79077365a9SGeert Uytterhoeven * rza1_bidir_pin - describe a single pin that needs bidir flag applied. 80077365a9SGeert Uytterhoeven */ 81077365a9SGeert Uytterhoeven struct rza1_bidir_pin { 82077365a9SGeert Uytterhoeven u8 pin: 4; 83077365a9SGeert Uytterhoeven u8 func: 4; 84077365a9SGeert Uytterhoeven }; 85077365a9SGeert Uytterhoeven 86077365a9SGeert Uytterhoeven /* 87077365a9SGeert Uytterhoeven * rza1_bidir_entry - describe a list of pins that needs bidir flag applied. 88077365a9SGeert Uytterhoeven * Each struct rza1_bidir_entry describes a port. 89077365a9SGeert Uytterhoeven */ 90077365a9SGeert Uytterhoeven struct rza1_bidir_entry { 91077365a9SGeert Uytterhoeven const unsigned int npins; 92077365a9SGeert Uytterhoeven const struct rza1_bidir_pin *pins; 93077365a9SGeert Uytterhoeven }; 94077365a9SGeert Uytterhoeven 95077365a9SGeert Uytterhoeven /* 96077365a9SGeert Uytterhoeven * rza1_swio_pin - describe a single pin that needs swio flag applied. 97077365a9SGeert Uytterhoeven */ 98077365a9SGeert Uytterhoeven struct rza1_swio_pin { 99077365a9SGeert Uytterhoeven u16 pin: 4; 100077365a9SGeert Uytterhoeven u16 port: 4; 101077365a9SGeert Uytterhoeven u16 func: 4; 102077365a9SGeert Uytterhoeven u16 input: 1; 103077365a9SGeert Uytterhoeven }; 104077365a9SGeert Uytterhoeven 105077365a9SGeert Uytterhoeven /* 106077365a9SGeert Uytterhoeven * rza1_swio_entry - describe a list of pins that needs swio flag applied 107077365a9SGeert Uytterhoeven */ 108077365a9SGeert Uytterhoeven struct rza1_swio_entry { 109077365a9SGeert Uytterhoeven const unsigned int npins; 110077365a9SGeert Uytterhoeven const struct rza1_swio_pin *pins; 111077365a9SGeert Uytterhoeven }; 112077365a9SGeert Uytterhoeven 113077365a9SGeert Uytterhoeven /* 114077365a9SGeert Uytterhoeven * rza1_pinmux_conf - group together bidir and swio pinmux flag tables 115077365a9SGeert Uytterhoeven */ 116077365a9SGeert Uytterhoeven struct rza1_pinmux_conf { 117077365a9SGeert Uytterhoeven const struct rza1_bidir_entry *bidir_entries; 118077365a9SGeert Uytterhoeven const struct rza1_swio_entry *swio_entries; 119077365a9SGeert Uytterhoeven }; 120077365a9SGeert Uytterhoeven 121077365a9SGeert Uytterhoeven /* ---------------------------------------------------------------------------- 122077365a9SGeert Uytterhoeven * RZ/A1H (r7s72100) pinmux flags 123077365a9SGeert Uytterhoeven */ 124077365a9SGeert Uytterhoeven 125077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = { 126077365a9SGeert Uytterhoeven { .pin = 0, .func = 1 }, 127077365a9SGeert Uytterhoeven { .pin = 1, .func = 1 }, 128077365a9SGeert Uytterhoeven { .pin = 2, .func = 1 }, 129077365a9SGeert Uytterhoeven { .pin = 3, .func = 1 }, 130077365a9SGeert Uytterhoeven { .pin = 4, .func = 1 }, 131077365a9SGeert Uytterhoeven { .pin = 5, .func = 1 }, 132077365a9SGeert Uytterhoeven { .pin = 6, .func = 1 }, 133077365a9SGeert Uytterhoeven { .pin = 7, .func = 1 }, 134077365a9SGeert Uytterhoeven }; 135077365a9SGeert Uytterhoeven 136077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = { 137077365a9SGeert Uytterhoeven { .pin = 0, .func = 1 }, 138077365a9SGeert Uytterhoeven { .pin = 1, .func = 1 }, 139077365a9SGeert Uytterhoeven { .pin = 2, .func = 1 }, 140077365a9SGeert Uytterhoeven { .pin = 3, .func = 1 }, 141077365a9SGeert Uytterhoeven { .pin = 4, .func = 1 }, 142077365a9SGeert Uytterhoeven { .pin = 0, .func = 4 }, 143077365a9SGeert Uytterhoeven { .pin = 1, .func = 4 }, 144077365a9SGeert Uytterhoeven { .pin = 2, .func = 4 }, 145077365a9SGeert Uytterhoeven { .pin = 3, .func = 4 }, 146077365a9SGeert Uytterhoeven { .pin = 5, .func = 1 }, 147077365a9SGeert Uytterhoeven { .pin = 6, .func = 1 }, 148077365a9SGeert Uytterhoeven { .pin = 7, .func = 1 }, 149077365a9SGeert Uytterhoeven { .pin = 8, .func = 1 }, 150077365a9SGeert Uytterhoeven { .pin = 9, .func = 1 }, 151077365a9SGeert Uytterhoeven { .pin = 10, .func = 1 }, 152077365a9SGeert Uytterhoeven { .pin = 11, .func = 1 }, 153077365a9SGeert Uytterhoeven { .pin = 12, .func = 1 }, 154077365a9SGeert Uytterhoeven { .pin = 13, .func = 1 }, 155077365a9SGeert Uytterhoeven { .pin = 14, .func = 1 }, 156077365a9SGeert Uytterhoeven { .pin = 15, .func = 1 }, 157077365a9SGeert Uytterhoeven { .pin = 12, .func = 4 }, 158077365a9SGeert Uytterhoeven { .pin = 13, .func = 4 }, 159077365a9SGeert Uytterhoeven { .pin = 14, .func = 4 }, 160077365a9SGeert Uytterhoeven { .pin = 15, .func = 4 }, 161077365a9SGeert Uytterhoeven }; 162077365a9SGeert Uytterhoeven 163077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = { 164077365a9SGeert Uytterhoeven { .pin = 3, .func = 2 }, 165077365a9SGeert Uytterhoeven { .pin = 10, .func = 7 }, 166077365a9SGeert Uytterhoeven { .pin = 11, .func = 7 }, 167077365a9SGeert Uytterhoeven { .pin = 13, .func = 7 }, 168077365a9SGeert Uytterhoeven { .pin = 14, .func = 7 }, 169077365a9SGeert Uytterhoeven { .pin = 15, .func = 7 }, 170077365a9SGeert Uytterhoeven { .pin = 10, .func = 8 }, 171077365a9SGeert Uytterhoeven { .pin = 11, .func = 8 }, 172077365a9SGeert Uytterhoeven { .pin = 13, .func = 8 }, 173077365a9SGeert Uytterhoeven { .pin = 14, .func = 8 }, 174077365a9SGeert Uytterhoeven { .pin = 15, .func = 8 }, 175077365a9SGeert Uytterhoeven }; 176077365a9SGeert Uytterhoeven 177077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = { 178077365a9SGeert Uytterhoeven { .pin = 0, .func = 8 }, 179077365a9SGeert Uytterhoeven { .pin = 1, .func = 8 }, 180077365a9SGeert Uytterhoeven { .pin = 2, .func = 8 }, 181077365a9SGeert Uytterhoeven { .pin = 3, .func = 8 }, 182077365a9SGeert Uytterhoeven { .pin = 10, .func = 3 }, 183077365a9SGeert Uytterhoeven { .pin = 11, .func = 3 }, 184077365a9SGeert Uytterhoeven { .pin = 13, .func = 3 }, 185077365a9SGeert Uytterhoeven { .pin = 14, .func = 3 }, 186077365a9SGeert Uytterhoeven { .pin = 15, .func = 3 }, 187077365a9SGeert Uytterhoeven { .pin = 10, .func = 4 }, 188077365a9SGeert Uytterhoeven { .pin = 11, .func = 4 }, 189077365a9SGeert Uytterhoeven { .pin = 13, .func = 4 }, 190077365a9SGeert Uytterhoeven { .pin = 14, .func = 4 }, 191077365a9SGeert Uytterhoeven { .pin = 15, .func = 4 }, 192077365a9SGeert Uytterhoeven { .pin = 12, .func = 5 }, 193077365a9SGeert Uytterhoeven { .pin = 13, .func = 5 }, 194077365a9SGeert Uytterhoeven { .pin = 14, .func = 5 }, 195077365a9SGeert Uytterhoeven { .pin = 15, .func = 5 }, 196077365a9SGeert Uytterhoeven }; 197077365a9SGeert Uytterhoeven 198077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = { 199077365a9SGeert Uytterhoeven { .pin = 0, .func = 1 }, 200077365a9SGeert Uytterhoeven { .pin = 1, .func = 1 }, 201077365a9SGeert Uytterhoeven { .pin = 2, .func = 1 }, 202077365a9SGeert Uytterhoeven { .pin = 3, .func = 1 }, 203077365a9SGeert Uytterhoeven { .pin = 4, .func = 1 }, 204077365a9SGeert Uytterhoeven { .pin = 5, .func = 1 }, 205077365a9SGeert Uytterhoeven { .pin = 6, .func = 1 }, 206077365a9SGeert Uytterhoeven { .pin = 7, .func = 1 }, 207077365a9SGeert Uytterhoeven { .pin = 8, .func = 1 }, 208077365a9SGeert Uytterhoeven { .pin = 9, .func = 1 }, 209077365a9SGeert Uytterhoeven { .pin = 10, .func = 1 }, 210077365a9SGeert Uytterhoeven { .pin = 11, .func = 1 }, 211077365a9SGeert Uytterhoeven { .pin = 12, .func = 1 }, 212077365a9SGeert Uytterhoeven { .pin = 13, .func = 1 }, 213077365a9SGeert Uytterhoeven { .pin = 14, .func = 1 }, 214077365a9SGeert Uytterhoeven { .pin = 15, .func = 1 }, 215077365a9SGeert Uytterhoeven }; 216077365a9SGeert Uytterhoeven 217077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = { 218077365a9SGeert Uytterhoeven { .pin = 13, .func = 3 }, 219077365a9SGeert Uytterhoeven }; 220077365a9SGeert Uytterhoeven 221077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = { 222077365a9SGeert Uytterhoeven { .pin = 8, .func = 3 }, 223077365a9SGeert Uytterhoeven { .pin = 9, .func = 3 }, 224077365a9SGeert Uytterhoeven { .pin = 10, .func = 3 }, 225077365a9SGeert Uytterhoeven { .pin = 11, .func = 3 }, 226077365a9SGeert Uytterhoeven { .pin = 14, .func = 2 }, 227077365a9SGeert Uytterhoeven { .pin = 15, .func = 2 }, 228077365a9SGeert Uytterhoeven { .pin = 14, .func = 3 }, 229077365a9SGeert Uytterhoeven { .pin = 15, .func = 3 }, 230077365a9SGeert Uytterhoeven }; 231077365a9SGeert Uytterhoeven 232077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = { 233077365a9SGeert Uytterhoeven { .pin = 0, .func = 2 }, 234077365a9SGeert Uytterhoeven { .pin = 1, .func = 2 }, 235077365a9SGeert Uytterhoeven { .pin = 4, .func = 2 }, 236077365a9SGeert Uytterhoeven { .pin = 5, .func = 2 }, 237077365a9SGeert Uytterhoeven { .pin = 6, .func = 2 }, 238077365a9SGeert Uytterhoeven { .pin = 7, .func = 2 }, 239077365a9SGeert Uytterhoeven }; 240077365a9SGeert Uytterhoeven 241077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = { 242077365a9SGeert Uytterhoeven { .pin = 6, .func = 2 }, 243077365a9SGeert Uytterhoeven { .pin = 7, .func = 2 }, 244077365a9SGeert Uytterhoeven { .pin = 9, .func = 2 }, 245077365a9SGeert Uytterhoeven { .pin = 6, .func = 4 }, 246077365a9SGeert Uytterhoeven { .pin = 7, .func = 4 }, 247077365a9SGeert Uytterhoeven { .pin = 9, .func = 4 }, 248077365a9SGeert Uytterhoeven { .pin = 10, .func = 2 }, 249077365a9SGeert Uytterhoeven { .pin = 11, .func = 2 }, 250077365a9SGeert Uytterhoeven { .pin = 10, .func = 4 }, 251077365a9SGeert Uytterhoeven { .pin = 11, .func = 4 }, 252077365a9SGeert Uytterhoeven { .pin = 12, .func = 4 }, 253077365a9SGeert Uytterhoeven { .pin = 13, .func = 4 }, 254077365a9SGeert Uytterhoeven { .pin = 14, .func = 4 }, 255077365a9SGeert Uytterhoeven { .pin = 15, .func = 4 }, 256077365a9SGeert Uytterhoeven }; 257077365a9SGeert Uytterhoeven 258077365a9SGeert Uytterhoeven static const struct rza1_swio_pin rza1h_swio_pins[] = { 259077365a9SGeert Uytterhoeven { .port = 2, .pin = 7, .func = 4, .input = 0 }, 260077365a9SGeert Uytterhoeven { .port = 2, .pin = 11, .func = 4, .input = 0 }, 261077365a9SGeert Uytterhoeven { .port = 3, .pin = 7, .func = 3, .input = 0 }, 262077365a9SGeert Uytterhoeven { .port = 3, .pin = 7, .func = 8, .input = 0 }, 263077365a9SGeert Uytterhoeven { .port = 4, .pin = 7, .func = 5, .input = 0 }, 264077365a9SGeert Uytterhoeven { .port = 4, .pin = 7, .func = 11, .input = 0 }, 265077365a9SGeert Uytterhoeven { .port = 4, .pin = 15, .func = 6, .input = 0 }, 266077365a9SGeert Uytterhoeven { .port = 5, .pin = 0, .func = 1, .input = 1 }, 267077365a9SGeert Uytterhoeven { .port = 5, .pin = 1, .func = 1, .input = 1 }, 268077365a9SGeert Uytterhoeven { .port = 5, .pin = 2, .func = 1, .input = 1 }, 269077365a9SGeert Uytterhoeven { .port = 5, .pin = 3, .func = 1, .input = 1 }, 270077365a9SGeert Uytterhoeven { .port = 5, .pin = 4, .func = 1, .input = 1 }, 271077365a9SGeert Uytterhoeven { .port = 5, .pin = 5, .func = 1, .input = 1 }, 272077365a9SGeert Uytterhoeven { .port = 5, .pin = 6, .func = 1, .input = 1 }, 273077365a9SGeert Uytterhoeven { .port = 5, .pin = 7, .func = 1, .input = 1 }, 274077365a9SGeert Uytterhoeven { .port = 7, .pin = 4, .func = 6, .input = 0 }, 275077365a9SGeert Uytterhoeven { .port = 7, .pin = 11, .func = 2, .input = 0 }, 276077365a9SGeert Uytterhoeven { .port = 8, .pin = 10, .func = 8, .input = 0 }, 277077365a9SGeert Uytterhoeven { .port = 10, .pin = 15, .func = 2, .input = 0 }, 278077365a9SGeert Uytterhoeven }; 279077365a9SGeert Uytterhoeven 280077365a9SGeert Uytterhoeven static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = { 281077365a9SGeert Uytterhoeven [1] = { ARRAY_SIZE(rza1h_bidir_pins_p1), rza1h_bidir_pins_p1 }, 282077365a9SGeert Uytterhoeven [2] = { ARRAY_SIZE(rza1h_bidir_pins_p2), rza1h_bidir_pins_p2 }, 283077365a9SGeert Uytterhoeven [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 }, 284077365a9SGeert Uytterhoeven [4] = { ARRAY_SIZE(rza1h_bidir_pins_p4), rza1h_bidir_pins_p4 }, 285077365a9SGeert Uytterhoeven [6] = { ARRAY_SIZE(rza1h_bidir_pins_p6), rza1h_bidir_pins_p6 }, 286077365a9SGeert Uytterhoeven [7] = { ARRAY_SIZE(rza1h_bidir_pins_p7), rza1h_bidir_pins_p7 }, 287077365a9SGeert Uytterhoeven [8] = { ARRAY_SIZE(rza1h_bidir_pins_p8), rza1h_bidir_pins_p8 }, 288077365a9SGeert Uytterhoeven [9] = { ARRAY_SIZE(rza1h_bidir_pins_p9), rza1h_bidir_pins_p9 }, 289077365a9SGeert Uytterhoeven [11] = { ARRAY_SIZE(rza1h_bidir_pins_p11), rza1h_bidir_pins_p11 }, 290077365a9SGeert Uytterhoeven }; 291077365a9SGeert Uytterhoeven 292077365a9SGeert Uytterhoeven static const struct rza1_swio_entry rza1h_swio_entries[] = { 293077365a9SGeert Uytterhoeven [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins }, 294077365a9SGeert Uytterhoeven }; 295077365a9SGeert Uytterhoeven 296077365a9SGeert Uytterhoeven /* RZ/A1H (r7s72100x) pinmux flags table */ 297077365a9SGeert Uytterhoeven static const struct rza1_pinmux_conf rza1h_pmx_conf = { 298077365a9SGeert Uytterhoeven .bidir_entries = rza1h_bidir_entries, 299077365a9SGeert Uytterhoeven .swio_entries = rza1h_swio_entries, 300077365a9SGeert Uytterhoeven }; 301077365a9SGeert Uytterhoeven 302077365a9SGeert Uytterhoeven /* ---------------------------------------------------------------------------- 303077365a9SGeert Uytterhoeven * RZ/A1L (r7s72102) pinmux flags 304077365a9SGeert Uytterhoeven */ 305077365a9SGeert Uytterhoeven 306077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = { 307077365a9SGeert Uytterhoeven { .pin = 0, .func = 1 }, 308077365a9SGeert Uytterhoeven { .pin = 1, .func = 1 }, 309077365a9SGeert Uytterhoeven { .pin = 2, .func = 1 }, 310077365a9SGeert Uytterhoeven { .pin = 3, .func = 1 }, 311077365a9SGeert Uytterhoeven { .pin = 4, .func = 1 }, 312077365a9SGeert Uytterhoeven { .pin = 5, .func = 1 }, 313077365a9SGeert Uytterhoeven { .pin = 6, .func = 1 }, 314077365a9SGeert Uytterhoeven { .pin = 7, .func = 1 }, 315077365a9SGeert Uytterhoeven }; 316077365a9SGeert Uytterhoeven 317077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = { 318077365a9SGeert Uytterhoeven { .pin = 0, .func = 2 }, 319077365a9SGeert Uytterhoeven { .pin = 1, .func = 2 }, 320077365a9SGeert Uytterhoeven { .pin = 2, .func = 2 }, 321077365a9SGeert Uytterhoeven { .pin = 4, .func = 2 }, 322077365a9SGeert Uytterhoeven { .pin = 5, .func = 2 }, 323077365a9SGeert Uytterhoeven { .pin = 10, .func = 2 }, 324077365a9SGeert Uytterhoeven { .pin = 11, .func = 2 }, 325077365a9SGeert Uytterhoeven { .pin = 12, .func = 2 }, 326077365a9SGeert Uytterhoeven { .pin = 13, .func = 2 }, 327077365a9SGeert Uytterhoeven }; 328077365a9SGeert Uytterhoeven 329077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = { 330077365a9SGeert Uytterhoeven { .pin = 1, .func = 4 }, 331077365a9SGeert Uytterhoeven { .pin = 2, .func = 2 }, 332077365a9SGeert Uytterhoeven { .pin = 3, .func = 2 }, 333077365a9SGeert Uytterhoeven { .pin = 6, .func = 2 }, 334077365a9SGeert Uytterhoeven { .pin = 7, .func = 2 }, 335077365a9SGeert Uytterhoeven }; 336077365a9SGeert Uytterhoeven 337077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = { 338077365a9SGeert Uytterhoeven { .pin = 0, .func = 1 }, 339077365a9SGeert Uytterhoeven { .pin = 1, .func = 1 }, 340077365a9SGeert Uytterhoeven { .pin = 2, .func = 1 }, 341077365a9SGeert Uytterhoeven { .pin = 3, .func = 1 }, 342077365a9SGeert Uytterhoeven { .pin = 4, .func = 1 }, 343077365a9SGeert Uytterhoeven { .pin = 5, .func = 1 }, 344077365a9SGeert Uytterhoeven { .pin = 6, .func = 1 }, 345077365a9SGeert Uytterhoeven { .pin = 7, .func = 1 }, 346077365a9SGeert Uytterhoeven { .pin = 8, .func = 1 }, 347077365a9SGeert Uytterhoeven { .pin = 9, .func = 1 }, 348077365a9SGeert Uytterhoeven { .pin = 10, .func = 1 }, 349077365a9SGeert Uytterhoeven { .pin = 11, .func = 1 }, 350077365a9SGeert Uytterhoeven { .pin = 12, .func = 1 }, 351077365a9SGeert Uytterhoeven { .pin = 13, .func = 1 }, 352077365a9SGeert Uytterhoeven { .pin = 14, .func = 1 }, 353077365a9SGeert Uytterhoeven { .pin = 15, .func = 1 }, 354077365a9SGeert Uytterhoeven { .pin = 0, .func = 2 }, 355077365a9SGeert Uytterhoeven { .pin = 1, .func = 2 }, 356077365a9SGeert Uytterhoeven { .pin = 2, .func = 2 }, 357077365a9SGeert Uytterhoeven { .pin = 3, .func = 2 }, 358077365a9SGeert Uytterhoeven }; 359077365a9SGeert Uytterhoeven 360077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = { 361077365a9SGeert Uytterhoeven { .pin = 0, .func = 1 }, 362077365a9SGeert Uytterhoeven { .pin = 1, .func = 1 }, 363077365a9SGeert Uytterhoeven { .pin = 2, .func = 1 }, 364077365a9SGeert Uytterhoeven { .pin = 3, .func = 1 }, 365077365a9SGeert Uytterhoeven { .pin = 4, .func = 1 }, 366077365a9SGeert Uytterhoeven { .pin = 5, .func = 1 }, 367077365a9SGeert Uytterhoeven { .pin = 6, .func = 1 }, 368077365a9SGeert Uytterhoeven { .pin = 7, .func = 1 }, 369077365a9SGeert Uytterhoeven { .pin = 8, .func = 1 }, 370077365a9SGeert Uytterhoeven { .pin = 9, .func = 1 }, 371077365a9SGeert Uytterhoeven { .pin = 10, .func = 1 }, 372077365a9SGeert Uytterhoeven { .pin = 11, .func = 1 }, 373077365a9SGeert Uytterhoeven { .pin = 12, .func = 1 }, 374077365a9SGeert Uytterhoeven { .pin = 13, .func = 1 }, 375077365a9SGeert Uytterhoeven { .pin = 14, .func = 1 }, 376077365a9SGeert Uytterhoeven { .pin = 15, .func = 1 }, 377077365a9SGeert Uytterhoeven }; 378077365a9SGeert Uytterhoeven 379077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = { 380077365a9SGeert Uytterhoeven { .pin = 2, .func = 2 }, 381077365a9SGeert Uytterhoeven { .pin = 3, .func = 2 }, 382077365a9SGeert Uytterhoeven { .pin = 5, .func = 2 }, 383077365a9SGeert Uytterhoeven { .pin = 6, .func = 2 }, 384077365a9SGeert Uytterhoeven { .pin = 7, .func = 2 }, 385077365a9SGeert Uytterhoeven { .pin = 2, .func = 3 }, 386077365a9SGeert Uytterhoeven { .pin = 3, .func = 3 }, 387077365a9SGeert Uytterhoeven { .pin = 5, .func = 3 }, 388077365a9SGeert Uytterhoeven { .pin = 6, .func = 3 }, 389077365a9SGeert Uytterhoeven { .pin = 7, .func = 3 }, 390077365a9SGeert Uytterhoeven }; 391077365a9SGeert Uytterhoeven 392077365a9SGeert Uytterhoeven static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = { 393077365a9SGeert Uytterhoeven { .pin = 1, .func = 2 }, 394077365a9SGeert Uytterhoeven { .pin = 0, .func = 3 }, 395077365a9SGeert Uytterhoeven { .pin = 1, .func = 3 }, 396077365a9SGeert Uytterhoeven { .pin = 3, .func = 3 }, 397077365a9SGeert Uytterhoeven { .pin = 4, .func = 3 }, 398077365a9SGeert Uytterhoeven { .pin = 5, .func = 3 }, 399077365a9SGeert Uytterhoeven }; 400077365a9SGeert Uytterhoeven 401077365a9SGeert Uytterhoeven static const struct rza1_swio_pin rza1l_swio_pins[] = { 402077365a9SGeert Uytterhoeven { .port = 2, .pin = 8, .func = 2, .input = 0 }, 403077365a9SGeert Uytterhoeven { .port = 5, .pin = 6, .func = 3, .input = 0 }, 404077365a9SGeert Uytterhoeven { .port = 6, .pin = 6, .func = 3, .input = 0 }, 405077365a9SGeert Uytterhoeven { .port = 6, .pin = 10, .func = 3, .input = 0 }, 406077365a9SGeert Uytterhoeven { .port = 7, .pin = 10, .func = 2, .input = 0 }, 407077365a9SGeert Uytterhoeven { .port = 8, .pin = 2, .func = 3, .input = 0 }, 408077365a9SGeert Uytterhoeven }; 409077365a9SGeert Uytterhoeven 410077365a9SGeert Uytterhoeven static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = { 411077365a9SGeert Uytterhoeven [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 }, 412077365a9SGeert Uytterhoeven [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 }, 413077365a9SGeert Uytterhoeven [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 }, 414077365a9SGeert Uytterhoeven [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 }, 415077365a9SGeert Uytterhoeven [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 }, 416077365a9SGeert Uytterhoeven [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 }, 417077365a9SGeert Uytterhoeven [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 }, 418077365a9SGeert Uytterhoeven }; 419077365a9SGeert Uytterhoeven 420077365a9SGeert Uytterhoeven static const struct rza1_swio_entry rza1l_swio_entries[] = { 421077365a9SGeert Uytterhoeven [0] = { ARRAY_SIZE(rza1l_swio_pins), rza1l_swio_pins }, 422077365a9SGeert Uytterhoeven }; 423077365a9SGeert Uytterhoeven 424077365a9SGeert Uytterhoeven /* RZ/A1L (r7s72102x) pinmux flags table */ 425077365a9SGeert Uytterhoeven static const struct rza1_pinmux_conf rza1l_pmx_conf = { 426077365a9SGeert Uytterhoeven .bidir_entries = rza1l_bidir_entries, 427077365a9SGeert Uytterhoeven .swio_entries = rza1l_swio_entries, 428077365a9SGeert Uytterhoeven }; 429077365a9SGeert Uytterhoeven 430077365a9SGeert Uytterhoeven /* ---------------------------------------------------------------------------- 431077365a9SGeert Uytterhoeven * RZ/A1 types 432077365a9SGeert Uytterhoeven */ 433077365a9SGeert Uytterhoeven /** 434077365a9SGeert Uytterhoeven * struct rza1_mux_conf - describes a pin multiplexing operation 435077365a9SGeert Uytterhoeven * 436077365a9SGeert Uytterhoeven * @id: the pin identifier from 0 to RZA1_NPINS 437077365a9SGeert Uytterhoeven * @port: the port where pin sits on 438077365a9SGeert Uytterhoeven * @pin: pin id 439077365a9SGeert Uytterhoeven * @mux_func: alternate function id number 440077365a9SGeert Uytterhoeven * @mux_flags: alternate function flags 441077365a9SGeert Uytterhoeven * @value: output value to set the pin to 442077365a9SGeert Uytterhoeven */ 443077365a9SGeert Uytterhoeven struct rza1_mux_conf { 444077365a9SGeert Uytterhoeven u16 id; 445077365a9SGeert Uytterhoeven u8 port; 446077365a9SGeert Uytterhoeven u8 pin; 447077365a9SGeert Uytterhoeven u8 mux_func; 448077365a9SGeert Uytterhoeven u8 mux_flags; 449077365a9SGeert Uytterhoeven u8 value; 450077365a9SGeert Uytterhoeven }; 451077365a9SGeert Uytterhoeven 452077365a9SGeert Uytterhoeven /** 453077365a9SGeert Uytterhoeven * struct rza1_port - describes a pin port 454077365a9SGeert Uytterhoeven * 455077365a9SGeert Uytterhoeven * This is mostly useful to lock register writes per-bank and not globally. 456077365a9SGeert Uytterhoeven * 457077365a9SGeert Uytterhoeven * @lock: protect access to HW registers 458077365a9SGeert Uytterhoeven * @id: port number 459077365a9SGeert Uytterhoeven * @base: logical address base 460077365a9SGeert Uytterhoeven * @pins: pins sitting on this port 461077365a9SGeert Uytterhoeven */ 462077365a9SGeert Uytterhoeven struct rza1_port { 463077365a9SGeert Uytterhoeven spinlock_t lock; 464077365a9SGeert Uytterhoeven unsigned int id; 465077365a9SGeert Uytterhoeven void __iomem *base; 466077365a9SGeert Uytterhoeven struct pinctrl_pin_desc *pins; 467077365a9SGeert Uytterhoeven }; 468077365a9SGeert Uytterhoeven 469077365a9SGeert Uytterhoeven /** 470077365a9SGeert Uytterhoeven * struct rza1_pinctrl - RZ pincontroller device 471077365a9SGeert Uytterhoeven * 472077365a9SGeert Uytterhoeven * @dev: parent device structure 473077365a9SGeert Uytterhoeven * @mutex: protect [pinctrl|pinmux]_generic functions 474077365a9SGeert Uytterhoeven * @base: logical address base 475077365a9SGeert Uytterhoeven * @nport: number of pin controller ports 476077365a9SGeert Uytterhoeven * @ports: pin controller banks 477077365a9SGeert Uytterhoeven * @pins: pin array for pinctrl core 478077365a9SGeert Uytterhoeven * @desc: pincontroller desc for pinctrl core 479077365a9SGeert Uytterhoeven * @pctl: pinctrl device 480077365a9SGeert Uytterhoeven * @data: device specific data 481077365a9SGeert Uytterhoeven */ 482077365a9SGeert Uytterhoeven struct rza1_pinctrl { 483077365a9SGeert Uytterhoeven struct device *dev; 484077365a9SGeert Uytterhoeven 485077365a9SGeert Uytterhoeven struct mutex mutex; 486077365a9SGeert Uytterhoeven 487077365a9SGeert Uytterhoeven void __iomem *base; 488077365a9SGeert Uytterhoeven 489077365a9SGeert Uytterhoeven unsigned int nport; 490077365a9SGeert Uytterhoeven struct rza1_port *ports; 491077365a9SGeert Uytterhoeven 492077365a9SGeert Uytterhoeven struct pinctrl_pin_desc *pins; 493077365a9SGeert Uytterhoeven struct pinctrl_desc desc; 494077365a9SGeert Uytterhoeven struct pinctrl_dev *pctl; 495077365a9SGeert Uytterhoeven 496077365a9SGeert Uytterhoeven const void *data; 497077365a9SGeert Uytterhoeven }; 498077365a9SGeert Uytterhoeven 499077365a9SGeert Uytterhoeven /* ---------------------------------------------------------------------------- 500077365a9SGeert Uytterhoeven * RZ/A1 pinmux flags 501077365a9SGeert Uytterhoeven */ 502077365a9SGeert Uytterhoeven static inline bool rza1_pinmux_get_bidir(unsigned int port, 503077365a9SGeert Uytterhoeven unsigned int pin, 504077365a9SGeert Uytterhoeven unsigned int func, 505077365a9SGeert Uytterhoeven const struct rza1_bidir_entry *table) 506077365a9SGeert Uytterhoeven { 507077365a9SGeert Uytterhoeven const struct rza1_bidir_entry *entry = &table[port]; 508077365a9SGeert Uytterhoeven const struct rza1_bidir_pin *bidir_pin; 509077365a9SGeert Uytterhoeven unsigned int i; 510077365a9SGeert Uytterhoeven 511077365a9SGeert Uytterhoeven for (i = 0; i < entry->npins; ++i) { 512077365a9SGeert Uytterhoeven bidir_pin = &entry->pins[i]; 513077365a9SGeert Uytterhoeven if (bidir_pin->pin == pin && bidir_pin->func == func) 514077365a9SGeert Uytterhoeven return true; 515077365a9SGeert Uytterhoeven } 516077365a9SGeert Uytterhoeven 517077365a9SGeert Uytterhoeven return false; 518077365a9SGeert Uytterhoeven } 519077365a9SGeert Uytterhoeven 520077365a9SGeert Uytterhoeven static inline int rza1_pinmux_get_swio(unsigned int port, 521077365a9SGeert Uytterhoeven unsigned int pin, 522077365a9SGeert Uytterhoeven unsigned int func, 523077365a9SGeert Uytterhoeven const struct rza1_swio_entry *table) 524077365a9SGeert Uytterhoeven { 525077365a9SGeert Uytterhoeven const struct rza1_swio_pin *swio_pin; 526077365a9SGeert Uytterhoeven unsigned int i; 527077365a9SGeert Uytterhoeven 528077365a9SGeert Uytterhoeven 529077365a9SGeert Uytterhoeven for (i = 0; i < table->npins; ++i) { 530077365a9SGeert Uytterhoeven swio_pin = &table->pins[i]; 531077365a9SGeert Uytterhoeven if (swio_pin->port == port && swio_pin->pin == pin && 532077365a9SGeert Uytterhoeven swio_pin->func == func) 533077365a9SGeert Uytterhoeven return swio_pin->input; 534077365a9SGeert Uytterhoeven } 535077365a9SGeert Uytterhoeven 536077365a9SGeert Uytterhoeven return -ENOENT; 537077365a9SGeert Uytterhoeven } 538077365a9SGeert Uytterhoeven 539077365a9SGeert Uytterhoeven /* 540077365a9SGeert Uytterhoeven * rza1_pinmux_get_flags() - return pinmux flags associated to a pin 541077365a9SGeert Uytterhoeven */ 542077365a9SGeert Uytterhoeven static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin, 543077365a9SGeert Uytterhoeven unsigned int func, 544077365a9SGeert Uytterhoeven struct rza1_pinctrl *rza1_pctl) 545077365a9SGeert Uytterhoeven 546077365a9SGeert Uytterhoeven { 547077365a9SGeert Uytterhoeven const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data; 548077365a9SGeert Uytterhoeven const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries; 549077365a9SGeert Uytterhoeven const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries; 550077365a9SGeert Uytterhoeven unsigned int pmx_flags = 0; 551077365a9SGeert Uytterhoeven int ret; 552077365a9SGeert Uytterhoeven 553077365a9SGeert Uytterhoeven if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries)) 554077365a9SGeert Uytterhoeven pmx_flags |= MUX_FLAGS_BIDIR; 555077365a9SGeert Uytterhoeven 556077365a9SGeert Uytterhoeven ret = rza1_pinmux_get_swio(port, pin, func, swio_entries); 557077365a9SGeert Uytterhoeven if (ret == 0) 558077365a9SGeert Uytterhoeven pmx_flags |= MUX_FLAGS_SWIO_OUTPUT; 559077365a9SGeert Uytterhoeven else if (ret > 0) 560077365a9SGeert Uytterhoeven pmx_flags |= MUX_FLAGS_SWIO_INPUT; 561077365a9SGeert Uytterhoeven 562077365a9SGeert Uytterhoeven return pmx_flags; 563077365a9SGeert Uytterhoeven } 564077365a9SGeert Uytterhoeven 565077365a9SGeert Uytterhoeven /* ---------------------------------------------------------------------------- 566077365a9SGeert Uytterhoeven * RZ/A1 SoC operations 567077365a9SGeert Uytterhoeven */ 568077365a9SGeert Uytterhoeven 569077365a9SGeert Uytterhoeven /* 570077365a9SGeert Uytterhoeven * rza1_set_bit() - un-locked set/clear a single bit in pin configuration 571077365a9SGeert Uytterhoeven * registers 572077365a9SGeert Uytterhoeven */ 573077365a9SGeert Uytterhoeven static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg, 574077365a9SGeert Uytterhoeven unsigned int bit, bool set) 575077365a9SGeert Uytterhoeven { 576077365a9SGeert Uytterhoeven void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); 577077365a9SGeert Uytterhoeven u16 val = ioread16(mem); 578077365a9SGeert Uytterhoeven 579077365a9SGeert Uytterhoeven if (set) 580077365a9SGeert Uytterhoeven val |= BIT(bit); 581077365a9SGeert Uytterhoeven else 582077365a9SGeert Uytterhoeven val &= ~BIT(bit); 583077365a9SGeert Uytterhoeven 584077365a9SGeert Uytterhoeven iowrite16(val, mem); 585077365a9SGeert Uytterhoeven } 586077365a9SGeert Uytterhoeven 587077365a9SGeert Uytterhoeven static inline unsigned int rza1_get_bit(struct rza1_port *port, 588077365a9SGeert Uytterhoeven unsigned int reg, unsigned int bit) 589077365a9SGeert Uytterhoeven { 590077365a9SGeert Uytterhoeven void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); 591077365a9SGeert Uytterhoeven 592077365a9SGeert Uytterhoeven return ioread16(mem) & BIT(bit); 593077365a9SGeert Uytterhoeven } 594077365a9SGeert Uytterhoeven 595077365a9SGeert Uytterhoeven /** 596077365a9SGeert Uytterhoeven * rza1_pin_reset() - reset a pin to default initial state 597077365a9SGeert Uytterhoeven * 598077365a9SGeert Uytterhoeven * Reset pin state disabling input buffer and bi-directional control, 599077365a9SGeert Uytterhoeven * and configure it as input port. 600077365a9SGeert Uytterhoeven * Note that pin is now configured with direction as input but with input 601077365a9SGeert Uytterhoeven * buffer disabled. This implies the pin value cannot be read in this state. 602077365a9SGeert Uytterhoeven * 603077365a9SGeert Uytterhoeven * @port: port where pin sits on 604077365a9SGeert Uytterhoeven * @pin: pin offset 605077365a9SGeert Uytterhoeven */ 606077365a9SGeert Uytterhoeven static void rza1_pin_reset(struct rza1_port *port, unsigned int pin) 607077365a9SGeert Uytterhoeven { 608077365a9SGeert Uytterhoeven unsigned long irqflags; 609077365a9SGeert Uytterhoeven 610077365a9SGeert Uytterhoeven spin_lock_irqsave(&port->lock, irqflags); 611077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PIBC_REG, pin, 0); 612077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PBDC_REG, pin, 0); 613077365a9SGeert Uytterhoeven 614077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PM_REG, pin, 1); 615077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PMC_REG, pin, 0); 616077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PIPC_REG, pin, 0); 617077365a9SGeert Uytterhoeven spin_unlock_irqrestore(&port->lock, irqflags); 618077365a9SGeert Uytterhoeven } 619077365a9SGeert Uytterhoeven 620077365a9SGeert Uytterhoeven /** 621077365a9SGeert Uytterhoeven * rza1_pin_set_direction() - set I/O direction on a pin in port mode 622077365a9SGeert Uytterhoeven * 623077365a9SGeert Uytterhoeven * When running in output port mode keep PBDC enabled to allow reading the 624077365a9SGeert Uytterhoeven * pin value from PPR. 625077365a9SGeert Uytterhoeven * 626077365a9SGeert Uytterhoeven * @port: port where pin sits on 627077365a9SGeert Uytterhoeven * @pin: pin offset 628077365a9SGeert Uytterhoeven * @input: input enable/disable flag 629077365a9SGeert Uytterhoeven */ 630077365a9SGeert Uytterhoeven static inline void rza1_pin_set_direction(struct rza1_port *port, 631077365a9SGeert Uytterhoeven unsigned int pin, bool input) 632077365a9SGeert Uytterhoeven { 633077365a9SGeert Uytterhoeven unsigned long irqflags; 634077365a9SGeert Uytterhoeven 635077365a9SGeert Uytterhoeven spin_lock_irqsave(&port->lock, irqflags); 636077365a9SGeert Uytterhoeven 637077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PIBC_REG, pin, 1); 638077365a9SGeert Uytterhoeven if (input) { 639077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PM_REG, pin, 1); 640077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PBDC_REG, pin, 0); 641077365a9SGeert Uytterhoeven } else { 642077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PM_REG, pin, 0); 643077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PBDC_REG, pin, 1); 644077365a9SGeert Uytterhoeven } 645077365a9SGeert Uytterhoeven 646077365a9SGeert Uytterhoeven spin_unlock_irqrestore(&port->lock, irqflags); 647077365a9SGeert Uytterhoeven } 648077365a9SGeert Uytterhoeven 649077365a9SGeert Uytterhoeven static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin, 650077365a9SGeert Uytterhoeven unsigned int value) 651077365a9SGeert Uytterhoeven { 652077365a9SGeert Uytterhoeven unsigned long irqflags; 653077365a9SGeert Uytterhoeven 654077365a9SGeert Uytterhoeven spin_lock_irqsave(&port->lock, irqflags); 655077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_P_REG, pin, !!value); 656077365a9SGeert Uytterhoeven spin_unlock_irqrestore(&port->lock, irqflags); 657077365a9SGeert Uytterhoeven } 658077365a9SGeert Uytterhoeven 659077365a9SGeert Uytterhoeven static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin) 660077365a9SGeert Uytterhoeven { 661077365a9SGeert Uytterhoeven return rza1_get_bit(port, RZA1_PPR_REG, pin); 662077365a9SGeert Uytterhoeven } 663077365a9SGeert Uytterhoeven 664077365a9SGeert Uytterhoeven /** 665077365a9SGeert Uytterhoeven * rza1_pin_mux_single() - configure pin multiplexing on a single pin 666077365a9SGeert Uytterhoeven * 667077365a9SGeert Uytterhoeven * @rza1_pctl: RZ/A1 pin controller device 668077365a9SGeert Uytterhoeven * @mux_conf: pin multiplexing descriptor 669077365a9SGeert Uytterhoeven */ 670077365a9SGeert Uytterhoeven static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl, 671077365a9SGeert Uytterhoeven struct rza1_mux_conf *mux_conf) 672077365a9SGeert Uytterhoeven { 673077365a9SGeert Uytterhoeven struct rza1_port *port = &rza1_pctl->ports[mux_conf->port]; 674077365a9SGeert Uytterhoeven unsigned int pin = mux_conf->pin; 675077365a9SGeert Uytterhoeven u8 mux_func = mux_conf->mux_func; 676077365a9SGeert Uytterhoeven u8 mux_flags = mux_conf->mux_flags; 677077365a9SGeert Uytterhoeven u8 mux_flags_from_table; 678077365a9SGeert Uytterhoeven 679077365a9SGeert Uytterhoeven rza1_pin_reset(port, pin); 680077365a9SGeert Uytterhoeven 681077365a9SGeert Uytterhoeven /* SWIO pinmux flags coming from DT are high precedence */ 682077365a9SGeert Uytterhoeven mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func, 683077365a9SGeert Uytterhoeven rza1_pctl); 684077365a9SGeert Uytterhoeven if (mux_flags) 685077365a9SGeert Uytterhoeven mux_flags |= (mux_flags_from_table & MUX_FLAGS_BIDIR); 686077365a9SGeert Uytterhoeven else 687077365a9SGeert Uytterhoeven mux_flags = mux_flags_from_table; 688077365a9SGeert Uytterhoeven 689077365a9SGeert Uytterhoeven if (mux_flags & MUX_FLAGS_BIDIR) 690077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PBDC_REG, pin, 1); 691077365a9SGeert Uytterhoeven 692077365a9SGeert Uytterhoeven /* 693077365a9SGeert Uytterhoeven * Enable alternate function mode and select it. 694077365a9SGeert Uytterhoeven * 695077365a9SGeert Uytterhoeven * Be careful here: the pin mux sub-nodes in device tree 696077365a9SGeert Uytterhoeven * enumerate alternate functions from 1 to 8; 697077365a9SGeert Uytterhoeven * subtract 1 before using macros to match registers configuration 698077365a9SGeert Uytterhoeven * which expects numbers from 0 to 7 instead. 699077365a9SGeert Uytterhoeven * 700077365a9SGeert Uytterhoeven * ---------------------------------------------------- 701077365a9SGeert Uytterhoeven * Alternate mode selection table: 702077365a9SGeert Uytterhoeven * 703077365a9SGeert Uytterhoeven * PMC PFC PFCE PFCAE (mux_func - 1) 704077365a9SGeert Uytterhoeven * 1 0 0 0 0 705077365a9SGeert Uytterhoeven * 1 1 0 0 1 706077365a9SGeert Uytterhoeven * 1 0 1 0 2 707077365a9SGeert Uytterhoeven * 1 1 1 0 3 708077365a9SGeert Uytterhoeven * 1 0 0 1 4 709077365a9SGeert Uytterhoeven * 1 1 0 1 5 710077365a9SGeert Uytterhoeven * 1 0 1 1 6 711077365a9SGeert Uytterhoeven * 1 1 1 1 7 712077365a9SGeert Uytterhoeven * ---------------------------------------------------- 713077365a9SGeert Uytterhoeven */ 714077365a9SGeert Uytterhoeven mux_func -= 1; 715077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK); 716077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK); 717077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK); 718077365a9SGeert Uytterhoeven 719077365a9SGeert Uytterhoeven /* 720077365a9SGeert Uytterhoeven * All alternate functions except a few need PIPCn = 1. 721077365a9SGeert Uytterhoeven * If PIPCn has to stay disabled (SW IO mode), configure PMn according 722077365a9SGeert Uytterhoeven * to I/O direction specified by pin configuration -after- PMC has been 723077365a9SGeert Uytterhoeven * set to one. 724077365a9SGeert Uytterhoeven */ 725077365a9SGeert Uytterhoeven if (mux_flags & (MUX_FLAGS_SWIO_INPUT | MUX_FLAGS_SWIO_OUTPUT)) 726077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PM_REG, pin, 727077365a9SGeert Uytterhoeven mux_flags & MUX_FLAGS_SWIO_INPUT); 728077365a9SGeert Uytterhoeven else 729077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PIPC_REG, pin, 1); 730077365a9SGeert Uytterhoeven 731077365a9SGeert Uytterhoeven rza1_set_bit(port, RZA1_PMC_REG, pin, 1); 732077365a9SGeert Uytterhoeven 733077365a9SGeert Uytterhoeven return 0; 734077365a9SGeert Uytterhoeven } 735077365a9SGeert Uytterhoeven 736077365a9SGeert Uytterhoeven /* ---------------------------------------------------------------------------- 737077365a9SGeert Uytterhoeven * gpio operations 738077365a9SGeert Uytterhoeven */ 739077365a9SGeert Uytterhoeven 740077365a9SGeert Uytterhoeven /** 741077365a9SGeert Uytterhoeven * rza1_gpio_request() - configure pin in port mode 742077365a9SGeert Uytterhoeven * 743077365a9SGeert Uytterhoeven * Configure a pin as gpio (port mode). 744077365a9SGeert Uytterhoeven * After reset, the pin is in input mode with input buffer disabled. 745077365a9SGeert Uytterhoeven * To use the pin as input or output, set_direction shall be called first 746077365a9SGeert Uytterhoeven * 747077365a9SGeert Uytterhoeven * @chip: gpio chip where the gpio sits on 748077365a9SGeert Uytterhoeven * @gpio: gpio offset 749077365a9SGeert Uytterhoeven */ 750077365a9SGeert Uytterhoeven static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio) 751077365a9SGeert Uytterhoeven { 752077365a9SGeert Uytterhoeven struct rza1_port *port = gpiochip_get_data(chip); 753077365a9SGeert Uytterhoeven 754077365a9SGeert Uytterhoeven rza1_pin_reset(port, gpio); 755077365a9SGeert Uytterhoeven 756077365a9SGeert Uytterhoeven return 0; 757077365a9SGeert Uytterhoeven } 758077365a9SGeert Uytterhoeven 759077365a9SGeert Uytterhoeven /** 760fea25380SGeert Uytterhoeven * rza1_gpio_free() - reset a pin 761077365a9SGeert Uytterhoeven * 762fea25380SGeert Uytterhoeven * Surprisingly, freeing a gpio is equivalent to requesting it. 763077365a9SGeert Uytterhoeven * Reset pin to port mode, with input buffer disabled. This overwrites all 764077365a9SGeert Uytterhoeven * port direction settings applied with set_direction 765077365a9SGeert Uytterhoeven * 766077365a9SGeert Uytterhoeven * @chip: gpio chip where the gpio sits on 767077365a9SGeert Uytterhoeven * @gpio: gpio offset 768077365a9SGeert Uytterhoeven */ 769077365a9SGeert Uytterhoeven static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio) 770077365a9SGeert Uytterhoeven { 771077365a9SGeert Uytterhoeven struct rza1_port *port = gpiochip_get_data(chip); 772077365a9SGeert Uytterhoeven 773077365a9SGeert Uytterhoeven rza1_pin_reset(port, gpio); 774077365a9SGeert Uytterhoeven } 775077365a9SGeert Uytterhoeven 776077365a9SGeert Uytterhoeven static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) 777077365a9SGeert Uytterhoeven { 778077365a9SGeert Uytterhoeven struct rza1_port *port = gpiochip_get_data(chip); 779077365a9SGeert Uytterhoeven 780077365a9SGeert Uytterhoeven if (rza1_get_bit(port, RZA1_PM_REG, gpio)) 781077365a9SGeert Uytterhoeven return GPIO_LINE_DIRECTION_IN; 782077365a9SGeert Uytterhoeven 783077365a9SGeert Uytterhoeven return GPIO_LINE_DIRECTION_OUT; 784077365a9SGeert Uytterhoeven } 785077365a9SGeert Uytterhoeven 786077365a9SGeert Uytterhoeven static int rza1_gpio_direction_input(struct gpio_chip *chip, 787077365a9SGeert Uytterhoeven unsigned int gpio) 788077365a9SGeert Uytterhoeven { 789077365a9SGeert Uytterhoeven struct rza1_port *port = gpiochip_get_data(chip); 790077365a9SGeert Uytterhoeven 791077365a9SGeert Uytterhoeven rza1_pin_set_direction(port, gpio, true); 792077365a9SGeert Uytterhoeven 793077365a9SGeert Uytterhoeven return 0; 794077365a9SGeert Uytterhoeven } 795077365a9SGeert Uytterhoeven 796077365a9SGeert Uytterhoeven static int rza1_gpio_direction_output(struct gpio_chip *chip, 797077365a9SGeert Uytterhoeven unsigned int gpio, 798077365a9SGeert Uytterhoeven int value) 799077365a9SGeert Uytterhoeven { 800077365a9SGeert Uytterhoeven struct rza1_port *port = gpiochip_get_data(chip); 801077365a9SGeert Uytterhoeven 802077365a9SGeert Uytterhoeven /* Set value before driving pin direction */ 803077365a9SGeert Uytterhoeven rza1_pin_set(port, gpio, value); 804077365a9SGeert Uytterhoeven rza1_pin_set_direction(port, gpio, false); 805077365a9SGeert Uytterhoeven 806077365a9SGeert Uytterhoeven return 0; 807077365a9SGeert Uytterhoeven } 808077365a9SGeert Uytterhoeven 809077365a9SGeert Uytterhoeven /** 810077365a9SGeert Uytterhoeven * rza1_gpio_get() - read a gpio pin value 811077365a9SGeert Uytterhoeven * 812077365a9SGeert Uytterhoeven * Read gpio pin value through PPR register. 813077365a9SGeert Uytterhoeven * Requires bi-directional mode to work when reading the value of a pin 814077365a9SGeert Uytterhoeven * in output mode 815077365a9SGeert Uytterhoeven * 816077365a9SGeert Uytterhoeven * @chip: gpio chip where the gpio sits on 817077365a9SGeert Uytterhoeven * @gpio: gpio offset 818077365a9SGeert Uytterhoeven */ 819077365a9SGeert Uytterhoeven static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio) 820077365a9SGeert Uytterhoeven { 821077365a9SGeert Uytterhoeven struct rza1_port *port = gpiochip_get_data(chip); 822077365a9SGeert Uytterhoeven 823077365a9SGeert Uytterhoeven return rza1_pin_get(port, gpio); 824077365a9SGeert Uytterhoeven } 825077365a9SGeert Uytterhoeven 826077365a9SGeert Uytterhoeven static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio, 827077365a9SGeert Uytterhoeven int value) 828077365a9SGeert Uytterhoeven { 829077365a9SGeert Uytterhoeven struct rza1_port *port = gpiochip_get_data(chip); 830077365a9SGeert Uytterhoeven 831077365a9SGeert Uytterhoeven rza1_pin_set(port, gpio, value); 832077365a9SGeert Uytterhoeven } 833077365a9SGeert Uytterhoeven 834077365a9SGeert Uytterhoeven static const struct gpio_chip rza1_gpiochip_template = { 835077365a9SGeert Uytterhoeven .request = rza1_gpio_request, 836077365a9SGeert Uytterhoeven .free = rza1_gpio_free, 837077365a9SGeert Uytterhoeven .get_direction = rza1_gpio_get_direction, 838077365a9SGeert Uytterhoeven .direction_input = rza1_gpio_direction_input, 839077365a9SGeert Uytterhoeven .direction_output = rza1_gpio_direction_output, 840077365a9SGeert Uytterhoeven .get = rza1_gpio_get, 841077365a9SGeert Uytterhoeven .set = rza1_gpio_set, 842077365a9SGeert Uytterhoeven }; 843077365a9SGeert Uytterhoeven /* ---------------------------------------------------------------------------- 844077365a9SGeert Uytterhoeven * pinctrl operations 845077365a9SGeert Uytterhoeven */ 846077365a9SGeert Uytterhoeven 847077365a9SGeert Uytterhoeven /** 848077365a9SGeert Uytterhoeven * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its 849077365a9SGeert Uytterhoeven * children sub-nodes 850077365a9SGeert Uytterhoeven * 851077365a9SGeert Uytterhoeven * @np: device tree node to parse 852077365a9SGeert Uytterhoeven */ 853077365a9SGeert Uytterhoeven static int rza1_dt_node_pin_count(struct device_node *np) 854077365a9SGeert Uytterhoeven { 855077365a9SGeert Uytterhoeven struct property *of_pins; 856077365a9SGeert Uytterhoeven unsigned int npins; 857077365a9SGeert Uytterhoeven 858077365a9SGeert Uytterhoeven of_pins = of_find_property(np, "pinmux", NULL); 859077365a9SGeert Uytterhoeven if (of_pins) 860077365a9SGeert Uytterhoeven return of_pins->length / sizeof(u32); 861077365a9SGeert Uytterhoeven 862077365a9SGeert Uytterhoeven npins = 0; 863*c45c3f5fSPeng Fan for_each_child_of_node_scoped(np, child) { 864077365a9SGeert Uytterhoeven of_pins = of_find_property(child, "pinmux", NULL); 865*c45c3f5fSPeng Fan if (!of_pins) 866077365a9SGeert Uytterhoeven return -EINVAL; 867077365a9SGeert Uytterhoeven 868077365a9SGeert Uytterhoeven npins += of_pins->length / sizeof(u32); 869077365a9SGeert Uytterhoeven } 870077365a9SGeert Uytterhoeven 871077365a9SGeert Uytterhoeven return npins; 872077365a9SGeert Uytterhoeven } 873077365a9SGeert Uytterhoeven 874077365a9SGeert Uytterhoeven /** 875fea25380SGeert Uytterhoeven * rza1_parse_pinmux_node() - parse a pin mux sub-node 876077365a9SGeert Uytterhoeven * 877077365a9SGeert Uytterhoeven * @rza1_pctl: RZ/A1 pin controller device 878077365a9SGeert Uytterhoeven * @np: of pmx sub-node 879077365a9SGeert Uytterhoeven * @mux_confs: array of pin mux configurations to fill with parsed info 880077365a9SGeert Uytterhoeven * @grpins: array of pin ids to mux 881077365a9SGeert Uytterhoeven */ 882077365a9SGeert Uytterhoeven static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl, 883077365a9SGeert Uytterhoeven struct device_node *np, 884077365a9SGeert Uytterhoeven struct rza1_mux_conf *mux_confs, 885077365a9SGeert Uytterhoeven unsigned int *grpins) 886077365a9SGeert Uytterhoeven { 887077365a9SGeert Uytterhoeven struct pinctrl_dev *pctldev = rza1_pctl->pctl; 888077365a9SGeert Uytterhoeven char const *prop_name = "pinmux"; 889077365a9SGeert Uytterhoeven unsigned long *pin_configs; 890077365a9SGeert Uytterhoeven unsigned int npin_configs; 891077365a9SGeert Uytterhoeven struct property *of_pins; 892077365a9SGeert Uytterhoeven unsigned int npins; 893077365a9SGeert Uytterhoeven u8 pinmux_flags; 894077365a9SGeert Uytterhoeven unsigned int i; 895077365a9SGeert Uytterhoeven int ret; 896077365a9SGeert Uytterhoeven 897077365a9SGeert Uytterhoeven of_pins = of_find_property(np, prop_name, NULL); 898077365a9SGeert Uytterhoeven if (!of_pins) { 899077365a9SGeert Uytterhoeven dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name); 900077365a9SGeert Uytterhoeven return -ENOENT; 901077365a9SGeert Uytterhoeven } 902077365a9SGeert Uytterhoeven npins = of_pins->length / sizeof(u32); 903077365a9SGeert Uytterhoeven 904077365a9SGeert Uytterhoeven /* 905077365a9SGeert Uytterhoeven * Collect pin configuration properties: they apply to all pins in 906077365a9SGeert Uytterhoeven * this sub-node 907077365a9SGeert Uytterhoeven */ 908077365a9SGeert Uytterhoeven ret = pinconf_generic_parse_dt_config(np, pctldev, &pin_configs, 909077365a9SGeert Uytterhoeven &npin_configs); 910077365a9SGeert Uytterhoeven if (ret) { 911077365a9SGeert Uytterhoeven dev_err(rza1_pctl->dev, 912077365a9SGeert Uytterhoeven "Unable to parse pin configuration options for %pOFn\n", 913077365a9SGeert Uytterhoeven np); 914077365a9SGeert Uytterhoeven return ret; 915077365a9SGeert Uytterhoeven } 916077365a9SGeert Uytterhoeven 917077365a9SGeert Uytterhoeven /* 918077365a9SGeert Uytterhoeven * Create a mask with pinmux flags from pin configuration; 919077365a9SGeert Uytterhoeven * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction 920077365a9SGeert Uytterhoeven * specified in device tree. 921077365a9SGeert Uytterhoeven */ 922077365a9SGeert Uytterhoeven pinmux_flags = 0; 923077365a9SGeert Uytterhoeven for (i = 0; i < npin_configs && pinmux_flags == 0; i++) 924077365a9SGeert Uytterhoeven switch (pinconf_to_config_param(pin_configs[i])) { 925077365a9SGeert Uytterhoeven case PIN_CONFIG_INPUT_ENABLE: 926077365a9SGeert Uytterhoeven pinmux_flags |= MUX_FLAGS_SWIO_INPUT; 927077365a9SGeert Uytterhoeven break; 928077365a9SGeert Uytterhoeven case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */ 929077365a9SGeert Uytterhoeven case PIN_CONFIG_OUTPUT_ENABLE: 930077365a9SGeert Uytterhoeven pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT; 9317ba4a959SGustavo A. R. Silva break; 932077365a9SGeert Uytterhoeven default: 933077365a9SGeert Uytterhoeven break; 934077365a9SGeert Uytterhoeven 935077365a9SGeert Uytterhoeven } 936077365a9SGeert Uytterhoeven 937077365a9SGeert Uytterhoeven kfree(pin_configs); 938077365a9SGeert Uytterhoeven 939077365a9SGeert Uytterhoeven /* Collect pin positions and their mux settings. */ 940077365a9SGeert Uytterhoeven for (i = 0; i < npins; ++i) { 941077365a9SGeert Uytterhoeven u32 of_pinconf; 942077365a9SGeert Uytterhoeven struct rza1_mux_conf *mux_conf = &mux_confs[i]; 943077365a9SGeert Uytterhoeven 944077365a9SGeert Uytterhoeven ret = of_property_read_u32_index(np, prop_name, i, &of_pinconf); 945077365a9SGeert Uytterhoeven if (ret) 946077365a9SGeert Uytterhoeven return ret; 947077365a9SGeert Uytterhoeven 948077365a9SGeert Uytterhoeven mux_conf->id = of_pinconf & MUX_PIN_ID_MASK; 949077365a9SGeert Uytterhoeven mux_conf->port = RZA1_PIN_ID_TO_PORT(mux_conf->id); 950077365a9SGeert Uytterhoeven mux_conf->pin = RZA1_PIN_ID_TO_PIN(mux_conf->id); 951077365a9SGeert Uytterhoeven mux_conf->mux_func = MUX_FUNC(of_pinconf); 952077365a9SGeert Uytterhoeven mux_conf->mux_flags = pinmux_flags; 953077365a9SGeert Uytterhoeven 954077365a9SGeert Uytterhoeven if (mux_conf->port >= RZA1_NPORTS || 955077365a9SGeert Uytterhoeven mux_conf->pin >= RZA1_PINS_PER_PORT) { 956077365a9SGeert Uytterhoeven dev_err(rza1_pctl->dev, 957077365a9SGeert Uytterhoeven "Wrong port %u pin %u for %s property\n", 958077365a9SGeert Uytterhoeven mux_conf->port, mux_conf->pin, prop_name); 959077365a9SGeert Uytterhoeven return -EINVAL; 960077365a9SGeert Uytterhoeven } 961077365a9SGeert Uytterhoeven 962077365a9SGeert Uytterhoeven grpins[i] = mux_conf->id; 963077365a9SGeert Uytterhoeven } 964077365a9SGeert Uytterhoeven 965077365a9SGeert Uytterhoeven return npins; 966077365a9SGeert Uytterhoeven } 967077365a9SGeert Uytterhoeven 968077365a9SGeert Uytterhoeven /** 969077365a9SGeert Uytterhoeven * rza1_dt_node_to_map() - map a pin mux node to a function/group 970077365a9SGeert Uytterhoeven * 971077365a9SGeert Uytterhoeven * Parse and register a pin mux function. 972077365a9SGeert Uytterhoeven * 973077365a9SGeert Uytterhoeven * @pctldev: pin controller device 974077365a9SGeert Uytterhoeven * @np: device tree node to parse 975077365a9SGeert Uytterhoeven * @map: pointer to pin map (output) 976077365a9SGeert Uytterhoeven * @num_maps: number of collected maps (output) 977077365a9SGeert Uytterhoeven */ 978077365a9SGeert Uytterhoeven static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev, 979077365a9SGeert Uytterhoeven struct device_node *np, 980077365a9SGeert Uytterhoeven struct pinctrl_map **map, 981077365a9SGeert Uytterhoeven unsigned int *num_maps) 982077365a9SGeert Uytterhoeven { 983077365a9SGeert Uytterhoeven struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev); 984077365a9SGeert Uytterhoeven struct rza1_mux_conf *mux_confs, *mux_conf; 985077365a9SGeert Uytterhoeven unsigned int *grpins, *grpin; 986077365a9SGeert Uytterhoeven const char *grpname; 987077365a9SGeert Uytterhoeven const char **fngrps; 988077365a9SGeert Uytterhoeven int ret, npins; 989077365a9SGeert Uytterhoeven int gsel, fsel; 990077365a9SGeert Uytterhoeven 991077365a9SGeert Uytterhoeven npins = rza1_dt_node_pin_count(np); 992077365a9SGeert Uytterhoeven if (npins < 0) { 993077365a9SGeert Uytterhoeven dev_err(rza1_pctl->dev, "invalid pinmux node structure\n"); 994077365a9SGeert Uytterhoeven return -EINVAL; 995077365a9SGeert Uytterhoeven } 996077365a9SGeert Uytterhoeven 997077365a9SGeert Uytterhoeven /* 998077365a9SGeert Uytterhoeven * Functions are made of 1 group only; 999077365a9SGeert Uytterhoeven * in fact, functions and groups are identical for this pin controller 1000077365a9SGeert Uytterhoeven * except that functions carry an array of per-pin mux configuration 1001077365a9SGeert Uytterhoeven * settings. 1002077365a9SGeert Uytterhoeven */ 1003077365a9SGeert Uytterhoeven mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs), 1004077365a9SGeert Uytterhoeven GFP_KERNEL); 1005077365a9SGeert Uytterhoeven grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins), 1006077365a9SGeert Uytterhoeven GFP_KERNEL); 1007077365a9SGeert Uytterhoeven fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL); 1008077365a9SGeert Uytterhoeven 1009077365a9SGeert Uytterhoeven if (!mux_confs || !grpins || !fngrps) 1010077365a9SGeert Uytterhoeven return -ENOMEM; 1011077365a9SGeert Uytterhoeven 1012077365a9SGeert Uytterhoeven /* 1013077365a9SGeert Uytterhoeven * Parse the pinmux node. 1014077365a9SGeert Uytterhoeven * If the node does not contain "pinmux" property (-ENOENT) 1015077365a9SGeert Uytterhoeven * that property shall be specified in all its children sub-nodes. 1016077365a9SGeert Uytterhoeven */ 1017077365a9SGeert Uytterhoeven mux_conf = &mux_confs[0]; 1018077365a9SGeert Uytterhoeven grpin = &grpins[0]; 1019077365a9SGeert Uytterhoeven 1020077365a9SGeert Uytterhoeven ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin); 1021077365a9SGeert Uytterhoeven if (ret == -ENOENT) 1022*c45c3f5fSPeng Fan for_each_child_of_node_scoped(np, child) { 1023077365a9SGeert Uytterhoeven ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf, 1024077365a9SGeert Uytterhoeven grpin); 1025*c45c3f5fSPeng Fan if (ret < 0) 1026077365a9SGeert Uytterhoeven return ret; 1027077365a9SGeert Uytterhoeven 1028077365a9SGeert Uytterhoeven grpin += ret; 1029077365a9SGeert Uytterhoeven mux_conf += ret; 1030077365a9SGeert Uytterhoeven } 1031077365a9SGeert Uytterhoeven else if (ret < 0) 1032077365a9SGeert Uytterhoeven return ret; 1033077365a9SGeert Uytterhoeven 1034077365a9SGeert Uytterhoeven /* Register pin group and function name to pinctrl_generic */ 1035077365a9SGeert Uytterhoeven grpname = np->name; 1036077365a9SGeert Uytterhoeven fngrps[0] = grpname; 1037077365a9SGeert Uytterhoeven 1038077365a9SGeert Uytterhoeven mutex_lock(&rza1_pctl->mutex); 1039077365a9SGeert Uytterhoeven gsel = pinctrl_generic_add_group(pctldev, grpname, grpins, npins, 1040077365a9SGeert Uytterhoeven NULL); 1041077365a9SGeert Uytterhoeven if (gsel < 0) { 1042077365a9SGeert Uytterhoeven mutex_unlock(&rza1_pctl->mutex); 1043077365a9SGeert Uytterhoeven return gsel; 1044077365a9SGeert Uytterhoeven } 1045077365a9SGeert Uytterhoeven 1046077365a9SGeert Uytterhoeven fsel = pinmux_generic_add_function(pctldev, grpname, fngrps, 1, 1047077365a9SGeert Uytterhoeven mux_confs); 1048077365a9SGeert Uytterhoeven if (fsel < 0) { 1049077365a9SGeert Uytterhoeven ret = fsel; 1050077365a9SGeert Uytterhoeven goto remove_group; 1051077365a9SGeert Uytterhoeven } 1052077365a9SGeert Uytterhoeven 1053077365a9SGeert Uytterhoeven dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n", 1054077365a9SGeert Uytterhoeven grpname, npins); 1055077365a9SGeert Uytterhoeven 1056077365a9SGeert Uytterhoeven /* Create map where to retrieve function and mux settings from */ 1057077365a9SGeert Uytterhoeven *num_maps = 0; 1058077365a9SGeert Uytterhoeven *map = kzalloc(sizeof(**map), GFP_KERNEL); 1059077365a9SGeert Uytterhoeven if (!*map) { 1060077365a9SGeert Uytterhoeven ret = -ENOMEM; 1061077365a9SGeert Uytterhoeven goto remove_function; 1062077365a9SGeert Uytterhoeven } 1063077365a9SGeert Uytterhoeven 1064077365a9SGeert Uytterhoeven (*map)->type = PIN_MAP_TYPE_MUX_GROUP; 1065077365a9SGeert Uytterhoeven (*map)->data.mux.group = np->name; 1066077365a9SGeert Uytterhoeven (*map)->data.mux.function = np->name; 1067077365a9SGeert Uytterhoeven *num_maps = 1; 1068077365a9SGeert Uytterhoeven mutex_unlock(&rza1_pctl->mutex); 1069077365a9SGeert Uytterhoeven 1070077365a9SGeert Uytterhoeven return 0; 1071077365a9SGeert Uytterhoeven 1072077365a9SGeert Uytterhoeven remove_function: 1073077365a9SGeert Uytterhoeven pinmux_generic_remove_function(pctldev, fsel); 1074077365a9SGeert Uytterhoeven 1075077365a9SGeert Uytterhoeven remove_group: 1076077365a9SGeert Uytterhoeven pinctrl_generic_remove_group(pctldev, gsel); 1077077365a9SGeert Uytterhoeven mutex_unlock(&rza1_pctl->mutex); 1078077365a9SGeert Uytterhoeven 1079077365a9SGeert Uytterhoeven dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n", 1080077365a9SGeert Uytterhoeven grpname); 1081077365a9SGeert Uytterhoeven 1082077365a9SGeert Uytterhoeven return ret; 1083077365a9SGeert Uytterhoeven } 1084077365a9SGeert Uytterhoeven 1085077365a9SGeert Uytterhoeven static void rza1_dt_free_map(struct pinctrl_dev *pctldev, 1086077365a9SGeert Uytterhoeven struct pinctrl_map *map, unsigned int num_maps) 1087077365a9SGeert Uytterhoeven { 1088077365a9SGeert Uytterhoeven kfree(map); 1089077365a9SGeert Uytterhoeven } 1090077365a9SGeert Uytterhoeven 1091077365a9SGeert Uytterhoeven static const struct pinctrl_ops rza1_pinctrl_ops = { 1092077365a9SGeert Uytterhoeven .get_groups_count = pinctrl_generic_get_group_count, 1093077365a9SGeert Uytterhoeven .get_group_name = pinctrl_generic_get_group_name, 1094077365a9SGeert Uytterhoeven .get_group_pins = pinctrl_generic_get_group_pins, 1095077365a9SGeert Uytterhoeven .dt_node_to_map = rza1_dt_node_to_map, 1096077365a9SGeert Uytterhoeven .dt_free_map = rza1_dt_free_map, 1097077365a9SGeert Uytterhoeven }; 1098077365a9SGeert Uytterhoeven 1099077365a9SGeert Uytterhoeven /* ---------------------------------------------------------------------------- 1100077365a9SGeert Uytterhoeven * pinmux operations 1101077365a9SGeert Uytterhoeven */ 1102077365a9SGeert Uytterhoeven 1103077365a9SGeert Uytterhoeven /** 1104077365a9SGeert Uytterhoeven * rza1_set_mux() - retrieve pins from a group and apply their mux settings 1105077365a9SGeert Uytterhoeven * 1106077365a9SGeert Uytterhoeven * @pctldev: pin controller device 1107077365a9SGeert Uytterhoeven * @selector: function selector 1108077365a9SGeert Uytterhoeven * @group: group selector 1109077365a9SGeert Uytterhoeven */ 1110077365a9SGeert Uytterhoeven static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, 1111077365a9SGeert Uytterhoeven unsigned int group) 1112077365a9SGeert Uytterhoeven { 1113077365a9SGeert Uytterhoeven struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev); 1114077365a9SGeert Uytterhoeven struct rza1_mux_conf *mux_confs; 1115077365a9SGeert Uytterhoeven struct function_desc *func; 1116077365a9SGeert Uytterhoeven struct group_desc *grp; 1117077365a9SGeert Uytterhoeven int i; 1118077365a9SGeert Uytterhoeven 1119077365a9SGeert Uytterhoeven grp = pinctrl_generic_get_group(pctldev, group); 1120077365a9SGeert Uytterhoeven if (!grp) 1121077365a9SGeert Uytterhoeven return -EINVAL; 1122077365a9SGeert Uytterhoeven 1123077365a9SGeert Uytterhoeven func = pinmux_generic_get_function(pctldev, selector); 1124077365a9SGeert Uytterhoeven if (!func) 1125077365a9SGeert Uytterhoeven return -EINVAL; 1126077365a9SGeert Uytterhoeven 1127077365a9SGeert Uytterhoeven mux_confs = (struct rza1_mux_conf *)func->data; 1128fc7d3b60SAndy Shevchenko for (i = 0; i < grp->grp.npins; ++i) { 1129077365a9SGeert Uytterhoeven int ret; 1130077365a9SGeert Uytterhoeven 1131077365a9SGeert Uytterhoeven ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]); 1132077365a9SGeert Uytterhoeven if (ret) 1133077365a9SGeert Uytterhoeven return ret; 1134077365a9SGeert Uytterhoeven } 1135077365a9SGeert Uytterhoeven 1136077365a9SGeert Uytterhoeven return 0; 1137077365a9SGeert Uytterhoeven } 1138077365a9SGeert Uytterhoeven 1139077365a9SGeert Uytterhoeven static const struct pinmux_ops rza1_pinmux_ops = { 1140077365a9SGeert Uytterhoeven .get_functions_count = pinmux_generic_get_function_count, 1141077365a9SGeert Uytterhoeven .get_function_name = pinmux_generic_get_function_name, 1142077365a9SGeert Uytterhoeven .get_function_groups = pinmux_generic_get_function_groups, 1143077365a9SGeert Uytterhoeven .set_mux = rza1_set_mux, 1144077365a9SGeert Uytterhoeven .strict = true, 1145077365a9SGeert Uytterhoeven }; 1146077365a9SGeert Uytterhoeven 1147077365a9SGeert Uytterhoeven /* ---------------------------------------------------------------------------- 1148077365a9SGeert Uytterhoeven * RZ/A1 pin controller driver operations 1149077365a9SGeert Uytterhoeven */ 1150077365a9SGeert Uytterhoeven 1151077365a9SGeert Uytterhoeven /** 1152077365a9SGeert Uytterhoeven * rza1_parse_gpiochip() - parse and register a gpio chip and pin range 1153077365a9SGeert Uytterhoeven * 1154077365a9SGeert Uytterhoeven * The gpio controller subnode shall provide a "gpio-ranges" list property as 1155077365a9SGeert Uytterhoeven * defined by gpio device tree binding documentation. 1156077365a9SGeert Uytterhoeven * 1157077365a9SGeert Uytterhoeven * @rza1_pctl: RZ/A1 pin controller device 11585e455dd9SAndy Shevchenko * @fwnode: gpio-controller firmware node 1159077365a9SGeert Uytterhoeven * @chip: gpio chip to register to gpiolib 1160077365a9SGeert Uytterhoeven * @range: pin range to register to pinctrl core 1161077365a9SGeert Uytterhoeven */ 1162077365a9SGeert Uytterhoeven static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl, 11635e455dd9SAndy Shevchenko struct fwnode_handle *fwnode, 1164077365a9SGeert Uytterhoeven struct gpio_chip *chip, 1165077365a9SGeert Uytterhoeven struct pinctrl_gpio_range *range) 1166077365a9SGeert Uytterhoeven { 1167077365a9SGeert Uytterhoeven const char *list_name = "gpio-ranges"; 11685e455dd9SAndy Shevchenko struct fwnode_reference_args args; 1169077365a9SGeert Uytterhoeven unsigned int gpioport; 1170077365a9SGeert Uytterhoeven u32 pinctrl_base; 1171077365a9SGeert Uytterhoeven int ret; 1172077365a9SGeert Uytterhoeven 11735e455dd9SAndy Shevchenko ret = fwnode_property_get_reference_args(fwnode, list_name, NULL, 3, 0, &args); 1174077365a9SGeert Uytterhoeven if (ret) { 1175077365a9SGeert Uytterhoeven dev_err(rza1_pctl->dev, "Unable to parse %s list property\n", 1176077365a9SGeert Uytterhoeven list_name); 1177077365a9SGeert Uytterhoeven return ret; 1178077365a9SGeert Uytterhoeven } 1179077365a9SGeert Uytterhoeven 1180077365a9SGeert Uytterhoeven /* 1181077365a9SGeert Uytterhoeven * Find out on which port this gpio-chip maps to by inspecting the 1182077365a9SGeert Uytterhoeven * second argument of the "gpio-ranges" property. 1183077365a9SGeert Uytterhoeven */ 11845e455dd9SAndy Shevchenko pinctrl_base = args.args[1]; 1185077365a9SGeert Uytterhoeven gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base); 1186077365a9SGeert Uytterhoeven if (gpioport >= RZA1_NPORTS) { 1187077365a9SGeert Uytterhoeven dev_err(rza1_pctl->dev, 1188077365a9SGeert Uytterhoeven "Invalid values in property %s\n", list_name); 1189077365a9SGeert Uytterhoeven return -EINVAL; 1190077365a9SGeert Uytterhoeven } 1191077365a9SGeert Uytterhoeven 1192077365a9SGeert Uytterhoeven *chip = rza1_gpiochip_template; 1193077365a9SGeert Uytterhoeven chip->base = -1; 11945e455dd9SAndy Shevchenko chip->ngpio = args.args[2]; 11955e455dd9SAndy Shevchenko chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%pfwP", fwnode); 1196077365a9SGeert Uytterhoeven if (!chip->label) 1197077365a9SGeert Uytterhoeven return -ENOMEM; 1198077365a9SGeert Uytterhoeven 11995e455dd9SAndy Shevchenko chip->fwnode = fwnode; 1200077365a9SGeert Uytterhoeven chip->parent = rza1_pctl->dev; 1201077365a9SGeert Uytterhoeven 1202077365a9SGeert Uytterhoeven range->id = gpioport; 1203077365a9SGeert Uytterhoeven range->name = chip->label; 1204077365a9SGeert Uytterhoeven range->pin_base = range->base = pinctrl_base; 12055e455dd9SAndy Shevchenko range->npins = args.args[2]; 1206077365a9SGeert Uytterhoeven range->gc = chip; 1207077365a9SGeert Uytterhoeven 1208077365a9SGeert Uytterhoeven ret = devm_gpiochip_add_data(rza1_pctl->dev, chip, 1209077365a9SGeert Uytterhoeven &rza1_pctl->ports[gpioport]); 1210077365a9SGeert Uytterhoeven if (ret) 1211077365a9SGeert Uytterhoeven return ret; 1212077365a9SGeert Uytterhoeven 1213077365a9SGeert Uytterhoeven pinctrl_add_gpio_range(rza1_pctl->pctl, range); 1214077365a9SGeert Uytterhoeven 1215077365a9SGeert Uytterhoeven dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n", 1216077365a9SGeert Uytterhoeven chip->label, chip->ngpio); 1217077365a9SGeert Uytterhoeven 1218077365a9SGeert Uytterhoeven return 0; 1219077365a9SGeert Uytterhoeven } 1220077365a9SGeert Uytterhoeven 1221077365a9SGeert Uytterhoeven /** 1222077365a9SGeert Uytterhoeven * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges 1223077365a9SGeert Uytterhoeven * 1224077365a9SGeert Uytterhoeven * @rza1_pctl: RZ/A1 pin controller device 1225077365a9SGeert Uytterhoeven */ 1226077365a9SGeert Uytterhoeven static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl) 1227077365a9SGeert Uytterhoeven { 1228077365a9SGeert Uytterhoeven struct pinctrl_gpio_range *gpio_ranges; 1229077365a9SGeert Uytterhoeven struct gpio_chip *gpio_chips; 12305e455dd9SAndy Shevchenko struct fwnode_handle *child; 1231077365a9SGeert Uytterhoeven unsigned int ngpiochips; 1232077365a9SGeert Uytterhoeven unsigned int i; 1233077365a9SGeert Uytterhoeven int ret; 1234077365a9SGeert Uytterhoeven 12351e0afd47SAndy Shevchenko ngpiochips = gpiochip_node_count(rza1_pctl->dev); 1236077365a9SGeert Uytterhoeven if (ngpiochips == 0) { 1237077365a9SGeert Uytterhoeven dev_dbg(rza1_pctl->dev, "No gpiochip registered\n"); 1238077365a9SGeert Uytterhoeven return 0; 1239077365a9SGeert Uytterhoeven } 1240077365a9SGeert Uytterhoeven 1241077365a9SGeert Uytterhoeven gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips, 1242077365a9SGeert Uytterhoeven sizeof(*gpio_chips), GFP_KERNEL); 1243077365a9SGeert Uytterhoeven gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips, 1244077365a9SGeert Uytterhoeven sizeof(*gpio_ranges), GFP_KERNEL); 1245077365a9SGeert Uytterhoeven if (!gpio_chips || !gpio_ranges) 1246077365a9SGeert Uytterhoeven return -ENOMEM; 1247077365a9SGeert Uytterhoeven 1248077365a9SGeert Uytterhoeven i = 0; 12495e455dd9SAndy Shevchenko for_each_gpiochip_node(rza1_pctl->dev, child) { 1250077365a9SGeert Uytterhoeven ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i], 1251077365a9SGeert Uytterhoeven &gpio_ranges[i]); 1252077365a9SGeert Uytterhoeven if (ret) { 12535e455dd9SAndy Shevchenko fwnode_handle_put(child); 1254077365a9SGeert Uytterhoeven return ret; 1255077365a9SGeert Uytterhoeven } 1256077365a9SGeert Uytterhoeven 1257077365a9SGeert Uytterhoeven ++i; 1258077365a9SGeert Uytterhoeven } 1259077365a9SGeert Uytterhoeven 1260077365a9SGeert Uytterhoeven dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i); 1261077365a9SGeert Uytterhoeven 1262077365a9SGeert Uytterhoeven return 0; 1263077365a9SGeert Uytterhoeven } 1264077365a9SGeert Uytterhoeven 1265077365a9SGeert Uytterhoeven /** 1266077365a9SGeert Uytterhoeven * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register 1267077365a9SGeert Uytterhoeven * them to pinctrl and gpio cores. 1268077365a9SGeert Uytterhoeven * 1269077365a9SGeert Uytterhoeven * @rza1_pctl: RZ/A1 pin controller device 1270077365a9SGeert Uytterhoeven */ 1271077365a9SGeert Uytterhoeven static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl) 1272077365a9SGeert Uytterhoeven { 1273077365a9SGeert Uytterhoeven struct pinctrl_pin_desc *pins; 1274077365a9SGeert Uytterhoeven struct rza1_port *ports; 1275077365a9SGeert Uytterhoeven unsigned int i; 1276077365a9SGeert Uytterhoeven int ret; 1277077365a9SGeert Uytterhoeven 1278077365a9SGeert Uytterhoeven pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins), 1279077365a9SGeert Uytterhoeven GFP_KERNEL); 1280077365a9SGeert Uytterhoeven ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports), 1281077365a9SGeert Uytterhoeven GFP_KERNEL); 1282077365a9SGeert Uytterhoeven if (!pins || !ports) 1283077365a9SGeert Uytterhoeven return -ENOMEM; 1284077365a9SGeert Uytterhoeven 1285077365a9SGeert Uytterhoeven rza1_pctl->pins = pins; 1286077365a9SGeert Uytterhoeven rza1_pctl->desc.pins = pins; 1287077365a9SGeert Uytterhoeven rza1_pctl->desc.npins = RZA1_NPINS; 1288077365a9SGeert Uytterhoeven rza1_pctl->ports = ports; 1289077365a9SGeert Uytterhoeven 1290077365a9SGeert Uytterhoeven for (i = 0; i < RZA1_NPINS; ++i) { 1291077365a9SGeert Uytterhoeven unsigned int pin = RZA1_PIN_ID_TO_PIN(i); 1292077365a9SGeert Uytterhoeven unsigned int port = RZA1_PIN_ID_TO_PORT(i); 1293077365a9SGeert Uytterhoeven 1294077365a9SGeert Uytterhoeven pins[i].number = i; 1295077365a9SGeert Uytterhoeven pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, 1296077365a9SGeert Uytterhoeven "P%u-%u", port, pin); 1297077365a9SGeert Uytterhoeven if (!pins[i].name) 1298077365a9SGeert Uytterhoeven return -ENOMEM; 1299077365a9SGeert Uytterhoeven 1300077365a9SGeert Uytterhoeven if (i % RZA1_PINS_PER_PORT == 0) { 1301077365a9SGeert Uytterhoeven /* 1302077365a9SGeert Uytterhoeven * Setup ports; 1303077365a9SGeert Uytterhoeven * they provide per-port lock and logical base address. 1304077365a9SGeert Uytterhoeven */ 1305077365a9SGeert Uytterhoeven unsigned int port_id = RZA1_PIN_ID_TO_PORT(i); 1306077365a9SGeert Uytterhoeven 1307077365a9SGeert Uytterhoeven ports[port_id].id = port_id; 1308077365a9SGeert Uytterhoeven ports[port_id].base = rza1_pctl->base; 1309077365a9SGeert Uytterhoeven ports[port_id].pins = &pins[i]; 1310077365a9SGeert Uytterhoeven spin_lock_init(&ports[port_id].lock); 1311077365a9SGeert Uytterhoeven } 1312077365a9SGeert Uytterhoeven } 1313077365a9SGeert Uytterhoeven 1314077365a9SGeert Uytterhoeven ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc, 1315077365a9SGeert Uytterhoeven rza1_pctl, &rza1_pctl->pctl); 1316077365a9SGeert Uytterhoeven if (ret) { 1317077365a9SGeert Uytterhoeven dev_err(rza1_pctl->dev, 1318077365a9SGeert Uytterhoeven "RZ/A1 pin controller registration failed\n"); 1319077365a9SGeert Uytterhoeven return ret; 1320077365a9SGeert Uytterhoeven } 1321077365a9SGeert Uytterhoeven 1322077365a9SGeert Uytterhoeven ret = pinctrl_enable(rza1_pctl->pctl); 1323077365a9SGeert Uytterhoeven if (ret) { 1324077365a9SGeert Uytterhoeven dev_err(rza1_pctl->dev, 1325077365a9SGeert Uytterhoeven "RZ/A1 pin controller failed to start\n"); 1326077365a9SGeert Uytterhoeven return ret; 1327077365a9SGeert Uytterhoeven } 1328077365a9SGeert Uytterhoeven 1329077365a9SGeert Uytterhoeven ret = rza1_gpio_register(rza1_pctl); 1330077365a9SGeert Uytterhoeven if (ret) { 1331077365a9SGeert Uytterhoeven dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n"); 1332077365a9SGeert Uytterhoeven return ret; 1333077365a9SGeert Uytterhoeven } 1334077365a9SGeert Uytterhoeven 1335077365a9SGeert Uytterhoeven return 0; 1336077365a9SGeert Uytterhoeven } 1337077365a9SGeert Uytterhoeven 1338077365a9SGeert Uytterhoeven static int rza1_pinctrl_probe(struct platform_device *pdev) 1339077365a9SGeert Uytterhoeven { 1340077365a9SGeert Uytterhoeven struct rza1_pinctrl *rza1_pctl; 1341077365a9SGeert Uytterhoeven int ret; 1342077365a9SGeert Uytterhoeven 1343077365a9SGeert Uytterhoeven rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL); 1344077365a9SGeert Uytterhoeven if (!rza1_pctl) 1345077365a9SGeert Uytterhoeven return -ENOMEM; 1346077365a9SGeert Uytterhoeven 1347077365a9SGeert Uytterhoeven rza1_pctl->dev = &pdev->dev; 1348077365a9SGeert Uytterhoeven 1349077365a9SGeert Uytterhoeven rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0); 1350077365a9SGeert Uytterhoeven if (IS_ERR(rza1_pctl->base)) 1351077365a9SGeert Uytterhoeven return PTR_ERR(rza1_pctl->base); 1352077365a9SGeert Uytterhoeven 1353077365a9SGeert Uytterhoeven mutex_init(&rza1_pctl->mutex); 1354077365a9SGeert Uytterhoeven 1355077365a9SGeert Uytterhoeven platform_set_drvdata(pdev, rza1_pctl); 1356077365a9SGeert Uytterhoeven 1357077365a9SGeert Uytterhoeven rza1_pctl->desc.name = DRIVER_NAME; 1358077365a9SGeert Uytterhoeven rza1_pctl->desc.pctlops = &rza1_pinctrl_ops; 1359077365a9SGeert Uytterhoeven rza1_pctl->desc.pmxops = &rza1_pinmux_ops; 1360077365a9SGeert Uytterhoeven rza1_pctl->desc.owner = THIS_MODULE; 1361077365a9SGeert Uytterhoeven rza1_pctl->data = of_device_get_match_data(&pdev->dev); 1362077365a9SGeert Uytterhoeven 1363077365a9SGeert Uytterhoeven ret = rza1_pinctrl_register(rza1_pctl); 1364077365a9SGeert Uytterhoeven if (ret) 1365077365a9SGeert Uytterhoeven return ret; 1366077365a9SGeert Uytterhoeven 1367077365a9SGeert Uytterhoeven dev_info(&pdev->dev, 1368077365a9SGeert Uytterhoeven "RZ/A1 pin controller and gpio successfully registered\n"); 1369077365a9SGeert Uytterhoeven 1370077365a9SGeert Uytterhoeven return 0; 1371077365a9SGeert Uytterhoeven } 1372077365a9SGeert Uytterhoeven 1373077365a9SGeert Uytterhoeven static const struct of_device_id rza1_pinctrl_of_match[] = { 1374077365a9SGeert Uytterhoeven { 1375077365a9SGeert Uytterhoeven /* RZ/A1H, RZ/A1M */ 1376077365a9SGeert Uytterhoeven .compatible = "renesas,r7s72100-ports", 1377077365a9SGeert Uytterhoeven .data = &rza1h_pmx_conf, 1378077365a9SGeert Uytterhoeven }, 1379077365a9SGeert Uytterhoeven { 1380077365a9SGeert Uytterhoeven /* RZ/A1L */ 1381077365a9SGeert Uytterhoeven .compatible = "renesas,r7s72102-ports", 1382077365a9SGeert Uytterhoeven .data = &rza1l_pmx_conf, 1383077365a9SGeert Uytterhoeven }, 13840256b6aeSGeert Uytterhoeven { /* sentinel */ } 1385077365a9SGeert Uytterhoeven }; 1386077365a9SGeert Uytterhoeven 1387077365a9SGeert Uytterhoeven static struct platform_driver rza1_pinctrl_driver = { 1388077365a9SGeert Uytterhoeven .driver = { 1389077365a9SGeert Uytterhoeven .name = DRIVER_NAME, 1390077365a9SGeert Uytterhoeven .of_match_table = rza1_pinctrl_of_match, 1391077365a9SGeert Uytterhoeven }, 1392077365a9SGeert Uytterhoeven .probe = rza1_pinctrl_probe, 1393077365a9SGeert Uytterhoeven }; 1394077365a9SGeert Uytterhoeven 1395077365a9SGeert Uytterhoeven static int __init rza1_pinctrl_init(void) 1396077365a9SGeert Uytterhoeven { 1397077365a9SGeert Uytterhoeven return platform_driver_register(&rza1_pinctrl_driver); 1398077365a9SGeert Uytterhoeven } 1399077365a9SGeert Uytterhoeven core_initcall(rza1_pinctrl_init); 1400077365a9SGeert Uytterhoeven 1401077365a9SGeert Uytterhoeven MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org"); 1402077365a9SGeert Uytterhoeven MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC"); 1403