1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A779H0 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 * 7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c 8 */ 9 10 #include <linux/errno.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 14 #include "sh_pfc.h" 15 16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 17 18 #define CPU_ALL_GP(fn, sfx) \ 19 PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 20 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 21 PORT_GP_CFG_1(1, 29, fn, sfx, CFG_FLAGS), \ 22 PORT_GP_CFG_16(2, fn, sfx, CFG_FLAGS), \ 23 PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \ 24 PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \ 25 PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 26 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 27 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 28 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_1(3, 16, fn, sfx, CFG_FLAGS), \ 30 PORT_GP_CFG_1(3, 17, fn, sfx, CFG_FLAGS), \ 31 PORT_GP_CFG_1(3, 18, fn, sfx, CFG_FLAGS), \ 32 PORT_GP_CFG_1(3, 19, fn, sfx, CFG_FLAGS), \ 33 PORT_GP_CFG_1(3, 20, fn, sfx, CFG_FLAGS), \ 34 PORT_GP_CFG_1(3, 21, fn, sfx, CFG_FLAGS), \ 35 PORT_GP_CFG_1(3, 22, fn, sfx, CFG_FLAGS), \ 36 PORT_GP_CFG_1(3, 23, fn, sfx, CFG_FLAGS), \ 37 PORT_GP_CFG_1(3, 24, fn, sfx, CFG_FLAGS), \ 38 PORT_GP_CFG_1(3, 25, fn, sfx, CFG_FLAGS), \ 39 PORT_GP_CFG_1(3, 26, fn, sfx, CFG_FLAGS), \ 40 PORT_GP_CFG_1(3, 27, fn, sfx, CFG_FLAGS), \ 41 PORT_GP_CFG_1(3, 28, fn, sfx, CFG_FLAGS), \ 42 PORT_GP_CFG_1(3, 29, fn, sfx, CFG_FLAGS), \ 43 PORT_GP_CFG_1(3, 30, fn, sfx, CFG_FLAGS), \ 44 PORT_GP_CFG_1(3, 31, fn, sfx, CFG_FLAGS), \ 45 PORT_GP_CFG_14(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 46 PORT_GP_CFG_1(4, 14, fn, sfx, CFG_FLAGS), \ 47 PORT_GP_CFG_1(4, 15, fn, sfx, CFG_FLAGS), \ 48 PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS), \ 49 PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS), \ 50 PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS), \ 51 PORT_GP_CFG_21(5, fn, sfx, CFG_FLAGS), \ 52 PORT_GP_CFG_21(6, fn, sfx, CFG_FLAGS), \ 53 PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS) 54 55 #define CPU_ALL_NOGP(fn) \ 56 PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \ 57 PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \ 58 PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25) 59 60 /* 61 * F_() : just information 62 * FM() : macro for FN_xxx / xxx_MARK 63 */ 64 65 /* GPSR0 */ 66 #define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8) 67 #define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4) 68 #define GPSR0_16 F_(MSIOF2_TXD, IP2SR0_3_0) 69 #define GPSR0_15 F_(MSIOF2_SYNC, IP1SR0_31_28) 70 #define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24) 71 #define GPSR0_13 F_(MSIOF2_SS2, IP1SR0_23_20) 72 #define GPSR0_12 F_(MSIOF5_RXD, IP1SR0_19_16) 73 #define GPSR0_11 F_(MSIOF5_SCK, IP1SR0_15_12) 74 #define GPSR0_10 F_(MSIOF5_TXD, IP1SR0_11_8) 75 #define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4) 76 #define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0) 77 #define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28) 78 #define GPSR0_6 F_(IRQ0_A, IP0SR0_27_24) 79 #define GPSR0_5 F_(IRQ1_A, IP0SR0_23_20) 80 #define GPSR0_4 F_(IRQ2_A, IP0SR0_19_16) 81 #define GPSR0_3 F_(IRQ3_A, IP0SR0_15_12) 82 #define GPSR0_2 F_(GP0_02, IP0SR0_11_8) 83 #define GPSR0_1 F_(GP0_01, IP0SR0_7_4) 84 #define GPSR0_0 F_(GP0_00, IP0SR0_3_0) 85 86 /* GPSR1 */ 87 #define GPSR1_29 F_(ERROROUTC_N_A, IP3SR1_23_20) 88 #define GPSR1_28 F_(HTX3, IP3SR1_19_16) 89 #define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12) 90 #define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8) 91 #define GPSR1_25 F_(HSCK3, IP3SR1_7_4) 92 #define GPSR1_24 F_(HRX3, IP3SR1_3_0) 93 #define GPSR1_23 F_(GP1_23, IP2SR1_31_28) 94 #define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24) 95 #define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20) 96 #define GPSR1_20 F_(SSI_SD, IP2SR1_19_16) 97 #define GPSR1_19 F_(SSI_WS, IP2SR1_15_12) 98 #define GPSR1_18 F_(SSI_SCK, IP2SR1_11_8) 99 #define GPSR1_17 F_(SCIF_CLK, IP2SR1_7_4) 100 #define GPSR1_16 F_(HRX0, IP2SR1_3_0) 101 #define GPSR1_15 F_(HSCK0, IP1SR1_31_28) 102 #define GPSR1_14 F_(HRTS0_N, IP1SR1_27_24) 103 #define GPSR1_13 F_(HCTS0_N, IP1SR1_23_20) 104 #define GPSR1_12 F_(HTX0, IP1SR1_19_16) 105 #define GPSR1_11 F_(MSIOF0_RXD, IP1SR1_15_12) 106 #define GPSR1_10 F_(MSIOF0_SCK, IP1SR1_11_8) 107 #define GPSR1_9 F_(MSIOF0_TXD, IP1SR1_7_4) 108 #define GPSR1_8 F_(MSIOF0_SYNC, IP1SR1_3_0) 109 #define GPSR1_7 F_(MSIOF0_SS1, IP0SR1_31_28) 110 #define GPSR1_6 F_(MSIOF0_SS2, IP0SR1_27_24) 111 #define GPSR1_5 F_(MSIOF1_RXD, IP0SR1_23_20) 112 #define GPSR1_4 F_(MSIOF1_TXD, IP0SR1_19_16) 113 #define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12) 114 #define GPSR1_2 F_(MSIOF1_SYNC, IP0SR1_11_8) 115 #define GPSR1_1 F_(MSIOF1_SS1, IP0SR1_7_4) 116 #define GPSR1_0 F_(MSIOF1_SS2, IP0SR1_3_0) 117 118 /* GPSR2 */ 119 #define GPSR2_19 F_(CANFD1_RX, IP2SR2_15_12) 120 #define GPSR2_17 F_(CANFD1_TX, IP2SR2_7_4) 121 #define GPSR2_15 F_(CANFD3_RX, IP1SR2_31_28) 122 #define GPSR2_14 F_(CANFD3_TX, IP1SR2_27_24) 123 #define GPSR2_13 F_(CANFD2_RX, IP1SR2_23_20) 124 #define GPSR2_12 F_(CANFD2_TX, IP1SR2_19_16) 125 #define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12) 126 #define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8) 127 #define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4) 128 #define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0) 129 #define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28) 130 #define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24) 131 #define GPSR2_5 F_(FXR_TXENB_N_A, IP0SR2_23_20) 132 #define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16) 133 #define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12) 134 #define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8) 135 #define GPSR2_1 F_(FXR_TXENA_N_A, IP0SR2_7_4) 136 #define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0) 137 138 /* GPSR3 */ 139 #define GPSR3_31 F_(TCLK4, IP3SR3_31_28) 140 #define GPSR3_30 F_(TCLK3, IP3SR3_27_24) 141 #define GPSR3_29 F_(RPC_INT_N, IP3SR3_23_20) 142 #define GPSR3_28 F_(RPC_WP_N, IP3SR3_19_16) 143 #define GPSR3_27 F_(RPC_RESET_N, IP3SR3_15_12) 144 #define GPSR3_26 F_(QSPI1_IO3, IP3SR3_11_8) 145 #define GPSR3_25 F_(QSPI1_SSL, IP3SR3_7_4) 146 #define GPSR3_24 F_(QSPI1_IO2, IP3SR3_3_0) 147 #define GPSR3_23 F_(QSPI1_MISO_IO1, IP2SR3_31_28) 148 #define GPSR3_22 F_(QSPI1_SPCLK, IP2SR3_27_24) 149 #define GPSR3_21 F_(QSPI1_MOSI_IO0, IP2SR3_23_20) 150 #define GPSR3_20 F_(QSPI0_SPCLK, IP2SR3_19_16) 151 #define GPSR3_19 F_(QSPI0_MOSI_IO0, IP2SR3_15_12) 152 #define GPSR3_18 F_(QSPI0_MISO_IO1, IP2SR3_11_8) 153 #define GPSR3_17 F_(QSPI0_IO2, IP2SR3_7_4) 154 #define GPSR3_16 F_(QSPI0_IO3, IP2SR3_3_0) 155 #define GPSR3_15 F_(QSPI0_SSL, IP1SR3_31_28) 156 #define GPSR3_14 F_(PWM2, IP1SR3_27_24) 157 #define GPSR3_13 F_(PWM1, IP1SR3_23_20) 158 #define GPSR3_12 F_(SD_WP, IP1SR3_19_16) 159 #define GPSR3_11 F_(SD_CD, IP1SR3_15_12) 160 #define GPSR3_10 F_(MMC_SD_CMD, IP1SR3_11_8) 161 #define GPSR3_9 F_(MMC_D6, IP1SR3_7_4) 162 #define GPSR3_8 F_(MMC_D7, IP1SR3_3_0) 163 #define GPSR3_7 F_(MMC_D4, IP0SR3_31_28) 164 #define GPSR3_6 F_(MMC_D5, IP0SR3_27_24) 165 #define GPSR3_5 F_(MMC_SD_D3, IP0SR3_23_20) 166 #define GPSR3_4 F_(MMC_DS, IP0SR3_19_16) 167 #define GPSR3_3 F_(MMC_SD_CLK, IP0SR3_15_12) 168 #define GPSR3_2 F_(MMC_SD_D2, IP0SR3_11_8) 169 #define GPSR3_1 F_(MMC_SD_D0, IP0SR3_7_4) 170 #define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0) 171 172 /* GPSR4 */ 173 #define GPSR4_24 F_(AVS1, IP3SR4_3_0) 174 #define GPSR4_23 F_(AVS0, IP2SR4_31_28) 175 #define GPSR4_21 F_(PCIE0_CLKREQ_N, IP2SR4_23_20) 176 #define GPSR4_15 F_(PWM4, IP1SR4_31_28) 177 #define GPSR4_14 F_(PWM3, IP1SR4_27_24) 178 #define GPSR4_13 F_(HSCK2, IP1SR4_23_20) 179 #define GPSR4_12 F_(HCTS2_N, IP1SR4_19_16) 180 #define GPSR4_11 F_(SCIF_CLK2, IP1SR4_15_12) 181 #define GPSR4_10 F_(HRTS2_N, IP1SR4_11_8) 182 #define GPSR4_9 F_(HTX2, IP1SR4_7_4) 183 #define GPSR4_8 F_(HRX2, IP1SR4_3_0) 184 #define GPSR4_7 F_(SDA3, IP0SR4_31_28) 185 #define GPSR4_6 F_(SCL3, IP0SR4_27_24) 186 #define GPSR4_5 F_(SDA2, IP0SR4_23_20) 187 #define GPSR4_4 F_(SCL2, IP0SR4_19_16) 188 #define GPSR4_3 F_(SDA1, IP0SR4_15_12) 189 #define GPSR4_2 F_(SCL1, IP0SR4_11_8) 190 #define GPSR4_1 F_(SDA0, IP0SR4_7_4) 191 #define GPSR4_0 F_(SCL0, IP0SR4_3_0) 192 193 /* GPSR 5 */ 194 #define GPSR5_20 F_(AVB2_RX_CTL, IP2SR5_19_16) 195 #define GPSR5_19 F_(AVB2_TX_CTL, IP2SR5_15_12) 196 #define GPSR5_18 F_(AVB2_RXC, IP2SR5_11_8) 197 #define GPSR5_17 F_(AVB2_RD0, IP2SR5_7_4) 198 #define GPSR5_16 F_(AVB2_TXC, IP2SR5_3_0) 199 #define GPSR5_15 F_(AVB2_TD0, IP1SR5_31_28) 200 #define GPSR5_14 F_(AVB2_RD1, IP1SR5_27_24) 201 #define GPSR5_13 F_(AVB2_RD2, IP1SR5_23_20) 202 #define GPSR5_12 F_(AVB2_TD1, IP1SR5_19_16) 203 #define GPSR5_11 F_(AVB2_TD2, IP1SR5_15_12) 204 #define GPSR5_10 F_(AVB2_MDIO, IP1SR5_11_8) 205 #define GPSR5_9 F_(AVB2_RD3, IP1SR5_7_4) 206 #define GPSR5_8 F_(AVB2_TD3, IP1SR5_3_0) 207 #define GPSR5_7 F_(AVB2_TXCREFCLK, IP0SR5_31_28) 208 #define GPSR5_6 F_(AVB2_MDC, IP0SR5_27_24) 209 #define GPSR5_5 F_(AVB2_MAGIC, IP0SR5_23_20) 210 #define GPSR5_4 F_(AVB2_PHY_INT, IP0SR5_19_16) 211 #define GPSR5_3 F_(AVB2_LINK, IP0SR5_15_12) 212 #define GPSR5_2 F_(AVB2_AVTP_MATCH, IP0SR5_11_8) 213 #define GPSR5_1 F_(AVB2_AVTP_CAPTURE, IP0SR5_7_4) 214 #define GPSR5_0 F_(AVB2_AVTP_PPS, IP0SR5_3_0) 215 216 /* GPSR 6 */ 217 #define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16) 218 #define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12) 219 #define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8) 220 #define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4) 221 #define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0) 222 #define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28) 223 #define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24) 224 #define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20) 225 #define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16) 226 #define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12) 227 #define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8) 228 #define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4) 229 #define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0) 230 #define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28) 231 #define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24) 232 #define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20) 233 #define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16) 234 #define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12) 235 #define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8) 236 #define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4) 237 #define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0) 238 239 /* GPSR7 */ 240 #define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16) 241 #define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12) 242 #define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8) 243 #define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4) 244 #define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0) 245 #define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28) 246 #define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24) 247 #define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20) 248 #define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16) 249 #define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12) 250 #define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8) 251 #define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4) 252 #define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0) 253 #define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28) 254 #define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24) 255 #define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20) 256 #define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16) 257 #define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12) 258 #define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8) 259 #define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4) 260 #define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0) 261 262 /* SR0 */ 263 /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 264 #define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP0SR0_15_12 FM(IRQ3_A) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP0SR0_19_16 FM(IRQ2_A) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP0SR0_23_20 FM(IRQ1_A) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP0SR0_27_24 FM(IRQ0_A) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 273 /* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 274 #define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275 #define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276 #define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1_A) FM(IRQ2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1_A) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 #define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1_A) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 283 /* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 284 #define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N_A) FM(CTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285 #define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N_A) FM(RTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286 #define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1_A) FM(SCK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287 288 /* SR1 */ 289 /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 290 #define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_B) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291 #define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_B) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_B) FM(RTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_B) FM(CTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_B) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 299 /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 300 #define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_B) FM(CTS1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301 #define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_B) FM(RTS1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302 #define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_B) FM(SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303 #define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 #define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306 #define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307 #define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 309 /* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 310 #define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311 #define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312 #define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313 #define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314 #define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315 #define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316 #define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317 #define IP2SR1_31_28 F_(0, 0) FM(TCLK2_A) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318 319 /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 320 #define IP3SR1_3_0 FM(HRX3_A) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321 #define IP3SR1_7_4 FM(HSCK3_A) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322 #define IP3SR1_11_8 FM(HRTS3_N_A) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323 #define IP3SR1_15_12 FM(HCTS3_N_A) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324 #define IP3SR1_19_16 FM(HTX3_A) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325 #define IP3SR1_23_20 FM(ERROROUTC_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326 327 /* SR2 */ 328 /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 329 #define IP0SR2_3_0 FM(FXR_TXDA) F_(0, 0) FM(TPU0TO2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330 #define IP0SR2_7_4 FM(FXR_TXENA_N_A) F_(0, 0) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331 #define IP0SR2_11_8 FM(RXDA_EXTFXR) F_(0, 0) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332 #define IP0SR2_15_12 FM(CLK_EXTFXR) F_(0, 0) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333 #define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334 #define IP0SR2_23_20 FM(FXR_TXENB_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335 #define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336 #define IP0SR2_31_28 FM(TPU0TO1_A) F_(0, 0) F_(0, 0) FM(TCLK2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337 338 /* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 339 #define IP1SR2_3_0 FM(TPU0TO0_A) F_(0, 0) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340 #define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341 #define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 #define IP1SR2_15_12 FM(CANFD0_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343 #define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344 #define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345 #define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346 #define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347 348 /* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 349 #define IP2SR2_7_4 FM(CANFD1_TX) F_(0, 0) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 350 #define IP2SR2_15_12 FM(CANFD1_RX) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 351 352 /* SR3 */ 353 /* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 354 #define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 355 #define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 356 #define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357 #define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358 #define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359 #define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360 #define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361 #define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362 363 /* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 364 #define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 365 #define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 366 #define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 367 #define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 368 #define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 369 #define IP1SR3_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 370 #define IP1SR3_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 371 #define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 372 373 /* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 374 #define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 375 #define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 376 #define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 377 #define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 378 #define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 379 #define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 380 #define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 381 #define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 382 383 /* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 384 #define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 385 #define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 386 #define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 387 #define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 388 #define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 389 #define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 390 #define IP3SR3_27_24 FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 391 #define IP3SR3_31_28 FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 392 393 /* SR4 */ 394 /* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 395 #define IP0SR4_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 396 #define IP0SR4_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 397 #define IP0SR4_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 398 #define IP0SR4_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 399 #define IP0SR4_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 400 #define IP0SR4_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 401 #define IP0SR4_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 402 #define IP0SR4_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 403 404 /* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 405 #define IP1SR4_3_0 FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 406 #define IP1SR4_7_4 FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 407 #define IP1SR4_11_8 FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 408 #define IP1SR4_15_12 FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 409 #define IP1SR4_19_16 FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 410 #define IP1SR4_23_20 FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 411 #define IP1SR4_27_24 FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 412 #define IP1SR4_31_28 FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 413 414 /* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 415 #define IP2SR4_23_20 FM(PCIE0_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 416 #define IP2SR4_31_28 FM(AVS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 417 418 /* IP3SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 419 #define IP3SR4_3_0 FM(AVS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 420 421 /* SR5 */ 422 /* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 423 #define IP0SR5_3_0 FM(AVB2_AVTP_PPS) FM(Ether_GPTP_PPS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 424 #define IP0SR5_7_4 FM(AVB2_AVTP_CAPTURE) FM(Ether_GPTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 425 #define IP0SR5_11_8 FM(AVB2_AVTP_MATCH) FM(Ether_GPTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 426 #define IP0SR5_15_12 FM(AVB2_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 427 #define IP0SR5_19_16 FM(AVB2_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 428 #define IP0SR5_23_20 FM(AVB2_MAGIC) FM(Ether_GPTP_PPS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 429 #define IP0SR5_27_24 FM(AVB2_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 430 #define IP0SR5_31_28 FM(AVB2_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 431 432 /* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 433 #define IP1SR5_3_0 FM(AVB2_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 434 #define IP1SR5_7_4 FM(AVB2_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 435 #define IP1SR5_11_8 FM(AVB2_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 436 #define IP1SR5_15_12 FM(AVB2_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 437 #define IP1SR5_19_16 FM(AVB2_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 438 #define IP1SR5_23_20 FM(AVB2_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 439 #define IP1SR5_27_24 FM(AVB2_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 440 #define IP1SR5_31_28 FM(AVB2_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 441 442 /* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 443 #define IP2SR5_3_0 FM(AVB2_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 444 #define IP2SR5_7_4 FM(AVB2_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 445 #define IP2SR5_11_8 FM(AVB2_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 446 #define IP2SR5_15_12 FM(AVB2_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 447 #define IP2SR5_19_16 FM(AVB2_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 448 449 /* SR6 */ 450 /* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 451 #define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 452 #define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 453 #define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 454 #define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 455 #define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 456 #define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 457 #define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 458 #define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 459 460 /* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 461 #define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 462 #define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 463 #define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 464 #define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 465 #define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 466 #define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 467 #define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 468 #define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 469 470 /* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 471 #define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 472 #define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 473 #define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 474 #define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 475 #define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 476 477 /* SR7 */ 478 /* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 479 #define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 480 #define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 481 #define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 482 #define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 483 #define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 484 #define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 485 #define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 486 #define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 487 488 /* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 489 #define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 490 #define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 491 #define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 492 #define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 493 #define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 494 #define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 495 #define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 496 #define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 497 498 /* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 499 #define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 500 #define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 501 #define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 502 #define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 503 #define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 504 505 #define PINMUX_GPSR \ 506 GPSR3_31 \ 507 GPSR3_30 \ 508 GPSR1_29 GPSR3_29 \ 509 GPSR1_28 GPSR3_28 \ 510 GPSR1_27 GPSR3_27 \ 511 GPSR1_26 GPSR3_26 \ 512 GPSR1_25 GPSR3_25 \ 513 GPSR1_24 GPSR3_24 GPSR4_24 \ 514 GPSR1_23 GPSR3_23 GPSR4_23 \ 515 GPSR1_22 GPSR3_22 \ 516 GPSR1_21 GPSR3_21 GPSR4_21 \ 517 GPSR1_20 GPSR3_20 GPSR5_20 GPSR6_20 GPSR7_20 \ 518 GPSR1_19 GPSR2_19 GPSR3_19 GPSR5_19 GPSR6_19 GPSR7_19 \ 519 GPSR0_18 GPSR1_18 GPSR3_18 GPSR5_18 GPSR6_18 GPSR7_18 \ 520 GPSR0_17 GPSR1_17 GPSR2_17 GPSR3_17 GPSR5_17 GPSR6_17 GPSR7_17 \ 521 GPSR0_16 GPSR1_16 GPSR3_16 GPSR5_16 GPSR6_16 GPSR7_16 \ 522 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 \ 523 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 \ 524 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 \ 525 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 \ 526 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 \ 527 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 \ 528 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 \ 529 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 \ 530 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 \ 531 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 \ 532 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 \ 533 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 \ 534 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ 535 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ 536 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ 537 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 538 539 #define PINMUX_IPSR \ 540 \ 541 FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \ 542 FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \ 543 FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \ 544 FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 \ 545 FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 \ 546 FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \ 547 FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \ 548 FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \ 549 \ 550 FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \ 551 FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \ 552 FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \ 553 FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \ 554 FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \ 555 FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \ 556 FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 \ 557 FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \ 558 \ 559 FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 \ 560 FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \ 561 FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 \ 562 FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \ 563 FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 \ 564 FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 \ 565 FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 \ 566 FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 \ 567 \ 568 FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 FM(IP2SR3_3_0) IP2SR3_3_0 FM(IP3SR3_3_0) IP3SR3_3_0 \ 569 FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 FM(IP2SR3_7_4) IP2SR3_7_4 FM(IP3SR3_7_4) IP3SR3_7_4 \ 570 FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 FM(IP2SR3_11_8) IP2SR3_11_8 FM(IP3SR3_11_8) IP3SR3_11_8 \ 571 FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 FM(IP2SR3_15_12) IP2SR3_15_12 FM(IP3SR3_15_12) IP3SR3_15_12 \ 572 FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 FM(IP2SR3_19_16) IP2SR3_19_16 FM(IP3SR3_19_16) IP3SR3_19_16 \ 573 FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 FM(IP2SR3_23_20) IP2SR3_23_20 FM(IP3SR3_23_20) IP3SR3_23_20 \ 574 FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 FM(IP3SR3_27_24) IP3SR3_27_24 \ 575 FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 FM(IP3SR3_31_28) IP3SR3_31_28 \ 576 \ 577 FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP3SR4_3_0) IP3SR4_3_0 \ 578 FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 \ 579 FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 \ 580 FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 \ 581 FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 \ 582 FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \ 583 FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 \ 584 FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \ 585 \ 586 FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \ 587 FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \ 588 FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \ 589 FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \ 590 FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \ 591 FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \ 592 FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \ 593 FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 \ 594 \ 595 FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \ 596 FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \ 597 FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \ 598 FM(IP0SR6_15_12) IP0SR6_15_12 FM(IP1SR6_15_12) IP1SR6_15_12 FM(IP2SR6_15_12) IP2SR6_15_12 \ 599 FM(IP0SR6_19_16) IP0SR6_19_16 FM(IP1SR6_19_16) IP1SR6_19_16 FM(IP2SR6_19_16) IP2SR6_19_16 \ 600 FM(IP0SR6_23_20) IP0SR6_23_20 FM(IP1SR6_23_20) IP1SR6_23_20 \ 601 FM(IP0SR6_27_24) IP0SR6_27_24 FM(IP1SR6_27_24) IP1SR6_27_24 \ 602 FM(IP0SR6_31_28) IP0SR6_31_28 FM(IP1SR6_31_28) IP1SR6_31_28 \ 603 \ 604 FM(IP0SR7_3_0) IP0SR7_3_0 FM(IP1SR7_3_0) IP1SR7_3_0 FM(IP2SR7_3_0) IP2SR7_3_0 \ 605 FM(IP0SR7_7_4) IP0SR7_7_4 FM(IP1SR7_7_4) IP1SR7_7_4 FM(IP2SR7_7_4) IP2SR7_7_4 \ 606 FM(IP0SR7_11_8) IP0SR7_11_8 FM(IP1SR7_11_8) IP1SR7_11_8 FM(IP2SR7_11_8) IP2SR7_11_8 \ 607 FM(IP0SR7_15_12) IP0SR7_15_12 FM(IP1SR7_15_12) IP1SR7_15_12 FM(IP2SR7_15_12) IP2SR7_15_12 \ 608 FM(IP0SR7_19_16) IP0SR7_19_16 FM(IP1SR7_19_16) IP1SR7_19_16 FM(IP2SR7_19_16) IP2SR7_19_16 \ 609 FM(IP0SR7_23_20) IP0SR7_23_20 FM(IP1SR7_23_20) IP1SR7_23_20 \ 610 FM(IP0SR7_27_24) IP0SR7_27_24 FM(IP1SR7_27_24) IP1SR7_27_24 \ 611 FM(IP0SR7_31_28) IP0SR7_31_28 FM(IP1SR7_31_28) IP1SR7_31_28 \ 612 613 /* MOD_SEL4 */ /* 0 */ /* 1 */ 614 #define MOD_SEL4_7 FM(SEL_SDA3_0) FM(SEL_SDA3_1) 615 #define MOD_SEL4_6 FM(SEL_SCL3_0) FM(SEL_SCL3_1) 616 #define MOD_SEL4_5 FM(SEL_SDA2_0) FM(SEL_SDA2_1) 617 #define MOD_SEL4_4 FM(SEL_SCL2_0) FM(SEL_SCL2_1) 618 #define MOD_SEL4_3 FM(SEL_SDA1_0) FM(SEL_SDA1_1) 619 #define MOD_SEL4_2 FM(SEL_SCL1_0) FM(SEL_SCL1_1) 620 #define MOD_SEL4_1 FM(SEL_SDA0_0) FM(SEL_SDA0_1) 621 #define MOD_SEL4_0 FM(SEL_SCL0_0) FM(SEL_SCL0_1) 622 623 #define PINMUX_MOD_SELS \ 624 \ 625 MOD_SEL4_7 \ 626 MOD_SEL4_6 \ 627 MOD_SEL4_5 \ 628 MOD_SEL4_4 \ 629 MOD_SEL4_3 \ 630 MOD_SEL4_2 \ 631 MOD_SEL4_1 \ 632 MOD_SEL4_0 633 634 enum { 635 PINMUX_RESERVED = 0, 636 637 PINMUX_DATA_BEGIN, 638 GP_ALL(DATA), 639 PINMUX_DATA_END, 640 641 #define F_(x, y) 642 #define FM(x) FN_##x, 643 PINMUX_FUNCTION_BEGIN, 644 GP_ALL(FN), 645 PINMUX_GPSR 646 PINMUX_IPSR 647 PINMUX_MOD_SELS 648 PINMUX_FUNCTION_END, 649 #undef F_ 650 #undef FM 651 652 #define F_(x, y) 653 #define FM(x) x##_MARK, 654 PINMUX_MARK_BEGIN, 655 PINMUX_GPSR 656 PINMUX_IPSR 657 PINMUX_MOD_SELS 658 PINMUX_MARK_END, 659 #undef F_ 660 #undef FM 661 }; 662 663 static const u16 pinmux_data[] = { 664 PINMUX_DATA_GP_ALL(), 665 666 /* IP0SR0 */ 667 PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B), 668 PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_B), 669 670 PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1), 671 672 PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2), 673 674 PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3_A), 675 PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK), 676 677 PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2_A), 678 PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD), 679 680 PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1_A), 681 PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD), 682 683 PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0_A), 684 PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC), 685 686 PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2), 687 688 /* IP1SR0 */ 689 PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF5_SS1), 690 691 PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF5_SYNC), 692 693 PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF5_TXD), 694 695 PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF5_SCK), 696 697 PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD), 698 699 PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2), 700 PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1_A), 701 PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_B), 702 703 PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1), 704 PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1_A), 705 PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1_A), 706 707 PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC), 708 PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1_A), 709 PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1_A), 710 711 /* IP2SR0 */ 712 PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD), 713 PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N_A), 714 PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N_A), 715 716 PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK), 717 PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N_A), 718 PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N_A), 719 720 PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD), 721 PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1_A), 722 PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1_A), 723 724 /* IP0SR1 */ 725 PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2), 726 PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_B), 727 PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3_B), 728 729 PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1), 730 PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_B), 731 PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3_B), 732 733 PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC), 734 PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_B), 735 PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N_B), 736 737 PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK), 738 PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_B), 739 PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N_B), 740 741 PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD), 742 PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_B), 743 PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3_B), 744 745 PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD), 746 747 PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2), 748 PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_B), 749 PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_B), 750 751 PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1), 752 PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_B), 753 PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_B), 754 755 /* IP1SR1 */ 756 PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC), 757 PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_B), 758 PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_B), 759 760 PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD), 761 PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_B), 762 PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_B), 763 764 PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK), 765 PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_B), 766 PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_B), 767 768 PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD), 769 770 PINMUX_IPSR_GPSR(IP1SR1_19_16, HTX0), 771 PINMUX_IPSR_GPSR(IP1SR1_19_16, TX0), 772 773 PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N), 774 PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N), 775 776 PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N), 777 PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N), 778 PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM0_B), 779 780 PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0), 781 PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0), 782 PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A), 783 784 /* IP2SR1 */ 785 PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0), 786 PINMUX_IPSR_GPSR(IP2SR1_3_0, RX0), 787 788 PINMUX_IPSR_GPSR(IP2SR1_7_4, SCIF_CLK), 789 PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A), 790 791 PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK), 792 PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3_B), 793 794 PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS), 795 PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4_B), 796 797 PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD), 798 PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_B), 799 800 PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT), 801 PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_B), 802 803 PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN), 804 PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_C), 805 806 PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2_A), 807 PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1), 808 PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B), 809 810 /* IP3SR1 */ 811 PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3_A), 812 PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A), 813 PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2), 814 815 PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3_A), 816 PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A), 817 PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK), 818 PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_B), 819 820 PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N_A), 821 PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A), 822 PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD), 823 PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_B), 824 825 PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N_A), 826 PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A), 827 PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD), 828 829 PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3_A), 830 PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A), 831 PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC), 832 833 PINMUX_IPSR_GPSR(IP3SR1_23_20, ERROROUTC_N_A), 834 835 /* IP0SR2 */ 836 PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA), 837 PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_B), 838 839 PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N_A), 840 PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_B), 841 842 PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR), 843 PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5), 844 845 PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR), 846 PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B), 847 848 PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR), 849 850 PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N_A), 851 852 PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB), 853 854 PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1_A), 855 PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_C), 856 857 /* IP1SR2 */ 858 PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0_A), 859 PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_B), 860 861 PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK), 862 PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_B), 863 864 PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX), 865 PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B), 866 867 PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX), 868 869 PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX), 870 PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A), 871 PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_C), 872 873 PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX), 874 PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3_A), 875 PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B), 876 PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_C), 877 878 PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX), 879 PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2_B), 880 881 PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX), 882 PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B), 883 884 /* IP2SR2 */ 885 PINMUX_IPSR_GPSR(IP2SR2_7_4, CANFD1_TX), 886 PINMUX_IPSR_GPSR(IP2SR2_7_4, PWM1_C), 887 888 PINMUX_IPSR_GPSR(IP2SR2_15_12, CANFD1_RX), 889 PINMUX_IPSR_GPSR(IP2SR2_15_12, PWM2_C), 890 891 /* IP0SR3 */ 892 PINMUX_IPSR_GPSR(IP0SR3_3_0, MMC_SD_D1), 893 894 PINMUX_IPSR_GPSR(IP0SR3_7_4, MMC_SD_D0), 895 896 PINMUX_IPSR_GPSR(IP0SR3_11_8, MMC_SD_D2), 897 898 PINMUX_IPSR_GPSR(IP0SR3_15_12, MMC_SD_CLK), 899 900 PINMUX_IPSR_GPSR(IP0SR3_19_16, MMC_DS), 901 902 PINMUX_IPSR_GPSR(IP0SR3_23_20, MMC_SD_D3), 903 904 PINMUX_IPSR_GPSR(IP0SR3_27_24, MMC_D5), 905 906 PINMUX_IPSR_GPSR(IP0SR3_31_28, MMC_D4), 907 908 /* IP1SR3 */ 909 PINMUX_IPSR_GPSR(IP1SR3_3_0, MMC_D7), 910 911 PINMUX_IPSR_GPSR(IP1SR3_7_4, MMC_D6), 912 913 PINMUX_IPSR_GPSR(IP1SR3_11_8, MMC_SD_CMD), 914 915 PINMUX_IPSR_GPSR(IP1SR3_15_12, SD_CD), 916 917 PINMUX_IPSR_GPSR(IP1SR3_19_16, SD_WP), 918 919 PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A), 920 921 PINMUX_IPSR_GPSR(IP1SR3_27_24, PWM2_A), 922 923 PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL), 924 925 /* IP2SR3 */ 926 PINMUX_IPSR_GPSR(IP2SR3_3_0, QSPI0_IO3), 927 928 PINMUX_IPSR_GPSR(IP2SR3_7_4, QSPI0_IO2), 929 930 PINMUX_IPSR_GPSR(IP2SR3_11_8, QSPI0_MISO_IO1), 931 932 PINMUX_IPSR_GPSR(IP2SR3_15_12, QSPI0_MOSI_IO0), 933 934 PINMUX_IPSR_GPSR(IP2SR3_19_16, QSPI0_SPCLK), 935 936 PINMUX_IPSR_GPSR(IP2SR3_23_20, QSPI1_MOSI_IO0), 937 938 PINMUX_IPSR_GPSR(IP2SR3_27_24, QSPI1_SPCLK), 939 940 PINMUX_IPSR_GPSR(IP2SR3_31_28, QSPI1_MISO_IO1), 941 942 /* IP3SR3 */ 943 PINMUX_IPSR_GPSR(IP3SR3_3_0, QSPI1_IO2), 944 945 PINMUX_IPSR_GPSR(IP3SR3_7_4, QSPI1_SSL), 946 947 PINMUX_IPSR_GPSR(IP3SR3_11_8, QSPI1_IO3), 948 949 PINMUX_IPSR_GPSR(IP3SR3_15_12, RPC_RESET_N), 950 951 PINMUX_IPSR_GPSR(IP3SR3_19_16, RPC_WP_N), 952 953 PINMUX_IPSR_GPSR(IP3SR3_23_20, RPC_INT_N), 954 955 PINMUX_IPSR_GPSR(IP3SR3_27_24, TCLK3_A), 956 957 PINMUX_IPSR_GPSR(IP3SR3_31_28, TCLK4_A), 958 959 /* IP0SR4 */ 960 PINMUX_IPSR_MSEL(IP0SR4_3_0, SCL0, SEL_SCL0_0), 961 962 PINMUX_IPSR_MSEL(IP0SR4_7_4, SDA0, SEL_SDA0_0), 963 964 PINMUX_IPSR_MSEL(IP0SR4_11_8, SCL1, SEL_SCL1_0), 965 966 PINMUX_IPSR_MSEL(IP0SR4_15_12, SDA1, SEL_SDA1_0), 967 968 PINMUX_IPSR_MSEL(IP0SR4_19_16, SCL2, SEL_SCL2_0), 969 970 PINMUX_IPSR_MSEL(IP0SR4_23_20, SDA2, SEL_SDA2_0), 971 972 PINMUX_IPSR_MSEL(IP0SR4_27_24, SCL3, SEL_SCL3_0), 973 974 PINMUX_IPSR_MSEL(IP0SR4_31_28, SDA3, SEL_SDA3_0), 975 976 /* IP1SR4 */ 977 PINMUX_IPSR_GPSR(IP1SR4_3_0, HRX2), 978 PINMUX_IPSR_GPSR(IP1SR4_3_0, SCK4), 979 980 PINMUX_IPSR_GPSR(IP1SR4_7_4, HTX2), 981 PINMUX_IPSR_GPSR(IP1SR4_7_4, CTS4_N), 982 983 PINMUX_IPSR_GPSR(IP1SR4_11_8, HRTS2_N), 984 PINMUX_IPSR_GPSR(IP1SR4_11_8, RTS4_N), 985 986 PINMUX_IPSR_GPSR(IP1SR4_15_12, SCIF_CLK2), 987 988 PINMUX_IPSR_GPSR(IP1SR4_19_16, HCTS2_N), 989 PINMUX_IPSR_GPSR(IP1SR4_19_16, TX4), 990 991 PINMUX_IPSR_GPSR(IP1SR4_23_20, HSCK2), 992 PINMUX_IPSR_GPSR(IP1SR4_23_20, RX4), 993 994 PINMUX_IPSR_GPSR(IP1SR4_27_24, PWM3_A), 995 996 PINMUX_IPSR_GPSR(IP1SR4_31_28, PWM4), 997 998 /* IP2SR4 */ 999 PINMUX_IPSR_GPSR(IP2SR4_23_20, PCIE0_CLKREQ_N), 1000 1001 PINMUX_IPSR_GPSR(IP2SR4_31_28, AVS0), 1002 1003 /* IP3SR4 */ 1004 PINMUX_IPSR_GPSR(IP3SR4_3_0, AVS1), 1005 1006 /* IP0SR5 */ 1007 PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB2_AVTP_PPS), 1008 PINMUX_IPSR_GPSR(IP0SR5_3_0, Ether_GPTP_PPS0), 1009 1010 PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB2_AVTP_CAPTURE), 1011 PINMUX_IPSR_GPSR(IP0SR5_7_4, Ether_GPTP_CAPTURE), 1012 1013 PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB2_AVTP_MATCH), 1014 PINMUX_IPSR_GPSR(IP0SR5_11_8, Ether_GPTP_MATCH), 1015 1016 PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB2_LINK), 1017 1018 PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB2_PHY_INT), 1019 1020 PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB2_MAGIC), 1021 PINMUX_IPSR_GPSR(IP0SR5_23_20, Ether_GPTP_PPS1), 1022 1023 PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB2_MDC), 1024 1025 PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB2_TXCREFCLK), 1026 1027 /* IP1SR5 */ 1028 PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB2_TD3), 1029 1030 PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB2_RD3), 1031 1032 PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB2_MDIO), 1033 1034 PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB2_TD2), 1035 1036 PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB2_TD1), 1037 1038 PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB2_RD2), 1039 1040 PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB2_RD1), 1041 1042 PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB2_TD0), 1043 1044 /* IP2SR5 */ 1045 PINMUX_IPSR_GPSR(IP2SR5_3_0, AVB2_TXC), 1046 1047 PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB2_RD0), 1048 1049 PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB2_RXC), 1050 1051 PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB2_TX_CTL), 1052 1053 PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB2_RX_CTL), 1054 1055 /* IP0SR6 */ 1056 PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO), 1057 1058 PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC), 1059 1060 PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC), 1061 1062 PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT), 1063 1064 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK), 1065 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER), 1066 1067 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH), 1068 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER), 1069 1070 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC), 1071 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC), 1072 1073 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL), 1074 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN), 1075 1076 /* IP1SR6 */ 1077 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC), 1078 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC), 1079 1080 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL), 1081 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV), 1082 1083 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS), 1084 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL), 1085 1086 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE), 1087 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS), 1088 1089 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1), 1090 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1), 1091 1092 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0), 1093 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0), 1094 1095 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1), 1096 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1), 1097 1098 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0), 1099 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0), 1100 1101 /* IP2SR6 */ 1102 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2), 1103 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2), 1104 1105 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2), 1106 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2), 1107 1108 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3), 1109 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3), 1110 1111 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3), 1112 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3), 1113 1114 PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK), 1115 1116 /* IP0SR7 */ 1117 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS), 1118 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL), 1119 1120 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE), 1121 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS), 1122 1123 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH), 1124 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER), 1125 1126 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3), 1127 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3), 1128 1129 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK), 1130 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER), 1131 1132 PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT), 1133 1134 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2), 1135 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2), 1136 1137 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1), 1138 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1), 1139 1140 /* IP1SR7 */ 1141 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3), 1142 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3), 1143 1144 PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK), 1145 1146 PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC), 1147 1148 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0), 1149 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0), 1150 1151 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2), 1152 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2), 1153 1154 PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC), 1155 1156 PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO), 1157 1158 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC), 1159 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC), 1160 1161 /* IP2SR7 */ 1162 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL), 1163 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN), 1164 1165 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1), 1166 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1), 1167 1168 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0), 1169 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0), 1170 1171 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC), 1172 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC), 1173 1174 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL), 1175 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV), 1176 }; 1177 1178 /* 1179 * Pins not associated with a GPIO port. 1180 */ 1181 enum { 1182 GP_ASSIGN_LAST(), 1183 NOGP_ALL(), 1184 }; 1185 1186 static const struct sh_pfc_pin pinmux_pins[] = { 1187 PINMUX_GPIO_GP_ALL(), 1188 PINMUX_NOGP_ALL(), 1189 }; 1190 1191 /* - AUDIO CLOCK ----------------------------------------- */ 1192 static const unsigned int audio_clkin_pins[] = { 1193 /* CLK IN */ 1194 RCAR_GP_PIN(1, 22), 1195 }; 1196 static const unsigned int audio_clkin_mux[] = { 1197 AUDIO_CLKIN_MARK, 1198 }; 1199 static const unsigned int audio_clkout_pins[] = { 1200 /* CLK OUT */ 1201 RCAR_GP_PIN(1, 21), 1202 }; 1203 static const unsigned int audio_clkout_mux[] = { 1204 AUDIO_CLKOUT_MARK, 1205 }; 1206 1207 /* - AVB0 ------------------------------------------------ */ 1208 static const unsigned int avb0_link_pins[] = { 1209 /* AVB0_LINK */ 1210 RCAR_GP_PIN(7, 4), 1211 }; 1212 static const unsigned int avb0_link_mux[] = { 1213 AVB0_LINK_MARK, 1214 }; 1215 static const unsigned int avb0_magic_pins[] = { 1216 /* AVB0_MAGIC */ 1217 RCAR_GP_PIN(7, 10), 1218 }; 1219 static const unsigned int avb0_magic_mux[] = { 1220 AVB0_MAGIC_MARK, 1221 }; 1222 static const unsigned int avb0_phy_int_pins[] = { 1223 /* AVB0_PHY_INT */ 1224 RCAR_GP_PIN(7, 5), 1225 }; 1226 static const unsigned int avb0_phy_int_mux[] = { 1227 AVB0_PHY_INT_MARK, 1228 }; 1229 static const unsigned int avb0_mdio_pins[] = { 1230 /* AVB0_MDC, AVB0_MDIO */ 1231 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14), 1232 }; 1233 static const unsigned int avb0_mdio_mux[] = { 1234 AVB0_MDC_MARK, AVB0_MDIO_MARK, 1235 }; 1236 static const unsigned int avb0_mii_pins[] = { 1237 /* 1238 * AVB0_MII_TD0, AVB0_MII_TD1, AVB0_MII_TD2, 1239 * AVB0_MII_TD3, AVB0_MII_RD0, AVB0_MII_RD1, 1240 * AVB0_MII_RD2, AVB0_MII_RD3, AVB0_MII_TXC, 1241 * AVB0_MII_TX_EN, AVB0_MII_TX_ER, AVB0_MII_RXC, 1242 * AVB0_MII_RX_DV, AVB0_MII_RX_ER, AVB0_MII_CRS, 1243 * AVB0_MII_COL 1244 */ 1245 RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 6), 1246 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17), 1247 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 15), 1248 RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 19), 1249 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 1), 1250 RCAR_GP_PIN(7, 0), 1251 }; 1252 static const unsigned int avb0_mii_mux[] = { 1253 AVB0_MII_TD0_MARK, AVB0_MII_TD1_MARK, AVB0_MII_TD2_MARK, 1254 AVB0_MII_TD3_MARK, AVB0_MII_RD0_MARK, AVB0_MII_RD1_MARK, 1255 AVB0_MII_RD2_MARK, AVB0_MII_RD3_MARK, AVB0_MII_TXC_MARK, 1256 AVB0_MII_TX_EN_MARK, AVB0_MII_TX_ER_MARK, AVB0_MII_RXC_MARK, 1257 AVB0_MII_RX_DV_MARK, AVB0_MII_RX_ER_MARK, AVB0_MII_CRS_MARK, 1258 AVB0_MII_COL_MARK, 1259 }; 1260 static const unsigned int avb0_rgmii_pins[] = { 1261 /* 1262 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3, 1263 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3, 1264 */ 1265 RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15), 1266 RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7), 1267 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3), 1268 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19), 1269 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17), 1270 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8), 1271 }; 1272 static const unsigned int avb0_rgmii_mux[] = { 1273 AVB0_TX_CTL_MARK, AVB0_TXC_MARK, 1274 AVB0_TD0_MARK, AVB0_TD1_MARK, 1275 AVB0_TD2_MARK, AVB0_TD3_MARK, 1276 AVB0_RX_CTL_MARK, AVB0_RXC_MARK, 1277 AVB0_RD0_MARK, AVB0_RD1_MARK, 1278 AVB0_RD2_MARK, AVB0_RD3_MARK, 1279 }; 1280 static const unsigned int avb0_txcrefclk_pins[] = { 1281 /* AVB0_TXCREFCLK */ 1282 RCAR_GP_PIN(7, 9), 1283 }; 1284 static const unsigned int avb0_txcrefclk_mux[] = { 1285 AVB0_TXCREFCLK_MARK, 1286 }; 1287 static const unsigned int avb0_avtp_pps_pins[] = { 1288 /* AVB0_AVTP_PPS */ 1289 RCAR_GP_PIN(7, 0), 1290 }; 1291 static const unsigned int avb0_avtp_pps_mux[] = { 1292 AVB0_AVTP_PPS_MARK, 1293 }; 1294 static const unsigned int avb0_avtp_capture_pins[] = { 1295 /* AVB0_AVTP_CAPTURE */ 1296 RCAR_GP_PIN(7, 1), 1297 }; 1298 static const unsigned int avb0_avtp_capture_mux[] = { 1299 AVB0_AVTP_CAPTURE_MARK, 1300 }; 1301 static const unsigned int avb0_avtp_match_pins[] = { 1302 /* AVB0_AVTP_MATCH */ 1303 RCAR_GP_PIN(7, 2), 1304 }; 1305 static const unsigned int avb0_avtp_match_mux[] = { 1306 AVB0_AVTP_MATCH_MARK, 1307 }; 1308 1309 /* - AVB1 ------------------------------------------------ */ 1310 static const unsigned int avb1_link_pins[] = { 1311 /* AVB1_LINK */ 1312 RCAR_GP_PIN(6, 4), 1313 }; 1314 static const unsigned int avb1_link_mux[] = { 1315 AVB1_LINK_MARK, 1316 }; 1317 static const unsigned int avb1_magic_pins[] = { 1318 /* AVB1_MAGIC */ 1319 RCAR_GP_PIN(6, 1), 1320 }; 1321 static const unsigned int avb1_magic_mux[] = { 1322 AVB1_MAGIC_MARK, 1323 }; 1324 static const unsigned int avb1_phy_int_pins[] = { 1325 /* AVB1_PHY_INT */ 1326 RCAR_GP_PIN(6, 3), 1327 }; 1328 static const unsigned int avb1_phy_int_mux[] = { 1329 AVB1_PHY_INT_MARK, 1330 }; 1331 static const unsigned int avb1_mdio_pins[] = { 1332 /* AVB1_MDC, AVB1_MDIO */ 1333 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0), 1334 }; 1335 static const unsigned int avb1_mdio_mux[] = { 1336 AVB1_MDC_MARK, AVB1_MDIO_MARK, 1337 }; 1338 static const unsigned int avb1_mii_pins[] = { 1339 /* 1340 * AVB1_MII_TD0, AVB1_MII_TD1, AVB1_MII_TD2, 1341 * AVB1_MII_TD3, AVB1_MII_RD0, AVB1_MII_RD1, 1342 * AVB1_MII_RD2, AVB1_MII_RD3, AVB1_MII_TXC, 1343 * AVB1_MII_TX_EN, AVB1_MII_TX_ER, AVB1_MII_RXC, 1344 * AVB1_MII_RX_DV, AVB1_MII_RX_ER, AVB1_MII_CRS, 1345 * AVB1_MII_COL 1346 */ 1347 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 16), 1348 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14), 1349 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 6), 1350 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 8), 1351 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11), 1352 RCAR_GP_PIN(6, 10), 1353 }; 1354 static const unsigned int avb1_mii_mux[] = { 1355 AVB1_MII_TD0_MARK, AVB1_MII_TD1_MARK, AVB1_MII_TD2_MARK, 1356 AVB1_MII_TD3_MARK, AVB1_MII_RD0_MARK, AVB1_MII_RD1_MARK, 1357 AVB1_MII_RD2_MARK, AVB1_MII_RD3_MARK, AVB1_MII_TXC_MARK, 1358 AVB1_MII_TX_EN_MARK, AVB1_MII_TX_ER_MARK, AVB1_MII_RXC_MARK, 1359 AVB1_MII_RX_DV_MARK, AVB1_MII_RX_ER_MARK, AVB1_MII_CRS_MARK, 1360 AVB1_MII_COL_MARK, 1361 }; 1362 static const unsigned int avb1_rgmii_pins[] = { 1363 /* 1364 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3, 1365 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3, 1366 */ 1367 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 1368 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12), 1369 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18), 1370 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8), 1371 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14), 1372 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19), 1373 }; 1374 static const unsigned int avb1_rgmii_mux[] = { 1375 AVB1_TX_CTL_MARK, AVB1_TXC_MARK, 1376 AVB1_TD0_MARK, AVB1_TD1_MARK, 1377 AVB1_TD2_MARK, AVB1_TD3_MARK, 1378 AVB1_RX_CTL_MARK, AVB1_RXC_MARK, 1379 AVB1_RD0_MARK, AVB1_RD1_MARK, 1380 AVB1_RD2_MARK, AVB1_RD3_MARK, 1381 }; 1382 static const unsigned int avb1_txcrefclk_pins[] = { 1383 /* AVB1_TXCREFCLK */ 1384 RCAR_GP_PIN(6, 20), 1385 }; 1386 static const unsigned int avb1_txcrefclk_mux[] = { 1387 AVB1_TXCREFCLK_MARK, 1388 }; 1389 static const unsigned int avb1_avtp_pps_pins[] = { 1390 /* AVB1_AVTP_PPS */ 1391 RCAR_GP_PIN(6, 10), 1392 }; 1393 static const unsigned int avb1_avtp_pps_mux[] = { 1394 AVB1_AVTP_PPS_MARK, 1395 }; 1396 static const unsigned int avb1_avtp_capture_pins[] = { 1397 /* AVB1_AVTP_CAPTURE */ 1398 RCAR_GP_PIN(6, 11), 1399 }; 1400 static const unsigned int avb1_avtp_capture_mux[] = { 1401 AVB1_AVTP_CAPTURE_MARK, 1402 }; 1403 static const unsigned int avb1_avtp_match_pins[] = { 1404 /* AVB1_AVTP_MATCH */ 1405 RCAR_GP_PIN(6, 5), 1406 }; 1407 static const unsigned int avb1_avtp_match_mux[] = { 1408 AVB1_AVTP_MATCH_MARK, 1409 }; 1410 1411 /* - AVB2 ------------------------------------------------ */ 1412 static const unsigned int avb2_link_pins[] = { 1413 /* AVB2_LINK */ 1414 RCAR_GP_PIN(5, 3), 1415 }; 1416 static const unsigned int avb2_link_mux[] = { 1417 AVB2_LINK_MARK, 1418 }; 1419 static const unsigned int avb2_magic_pins[] = { 1420 /* AVB2_MAGIC */ 1421 RCAR_GP_PIN(5, 5), 1422 }; 1423 static const unsigned int avb2_magic_mux[] = { 1424 AVB2_MAGIC_MARK, 1425 }; 1426 static const unsigned int avb2_phy_int_pins[] = { 1427 /* AVB2_PHY_INT */ 1428 RCAR_GP_PIN(5, 4), 1429 }; 1430 static const unsigned int avb2_phy_int_mux[] = { 1431 AVB2_PHY_INT_MARK, 1432 }; 1433 static const unsigned int avb2_mdio_pins[] = { 1434 /* AVB2_MDC, AVB2_MDIO */ 1435 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10), 1436 }; 1437 static const unsigned int avb2_mdio_mux[] = { 1438 AVB2_MDC_MARK, AVB2_MDIO_MARK, 1439 }; 1440 static const unsigned int avb2_rgmii_pins[] = { 1441 /* 1442 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3, 1443 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3, 1444 */ 1445 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16), 1446 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12), 1447 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8), 1448 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18), 1449 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14), 1450 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9), 1451 }; 1452 static const unsigned int avb2_rgmii_mux[] = { 1453 AVB2_TX_CTL_MARK, AVB2_TXC_MARK, 1454 AVB2_TD0_MARK, AVB2_TD1_MARK, 1455 AVB2_TD2_MARK, AVB2_TD3_MARK, 1456 AVB2_RX_CTL_MARK, AVB2_RXC_MARK, 1457 AVB2_RD0_MARK, AVB2_RD1_MARK, 1458 AVB2_RD2_MARK, AVB2_RD3_MARK, 1459 }; 1460 static const unsigned int avb2_txcrefclk_pins[] = { 1461 /* AVB2_TXCREFCLK */ 1462 RCAR_GP_PIN(5, 7), 1463 }; 1464 static const unsigned int avb2_txcrefclk_mux[] = { 1465 AVB2_TXCREFCLK_MARK, 1466 }; 1467 static const unsigned int avb2_avtp_pps_pins[] = { 1468 /* AVB2_AVTP_PPS */ 1469 RCAR_GP_PIN(5, 0), 1470 }; 1471 static const unsigned int avb2_avtp_pps_mux[] = { 1472 AVB2_AVTP_PPS_MARK, 1473 }; 1474 static const unsigned int avb2_avtp_capture_pins[] = { 1475 /* AVB2_AVTP_CAPTURE */ 1476 RCAR_GP_PIN(5, 1), 1477 }; 1478 static const unsigned int avb2_avtp_capture_mux[] = { 1479 AVB2_AVTP_CAPTURE_MARK, 1480 }; 1481 static const unsigned int avb2_avtp_match_pins[] = { 1482 /* AVB2_AVTP_MATCH */ 1483 RCAR_GP_PIN(5, 2), 1484 }; 1485 static const unsigned int avb2_avtp_match_mux[] = { 1486 AVB2_AVTP_MATCH_MARK, 1487 }; 1488 1489 /* - CANFD0 ----------------------------------------------------------------- */ 1490 static const unsigned int canfd0_data_pins[] = { 1491 /* CANFD0_TX, CANFD0_RX */ 1492 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 1493 }; 1494 static const unsigned int canfd0_data_mux[] = { 1495 CANFD0_TX_MARK, CANFD0_RX_MARK, 1496 }; 1497 1498 /* - CANFD1 ----------------------------------------------------------------- */ 1499 static const unsigned int canfd1_data_pins[] = { 1500 /* CANFD1_TX, CANFD1_RX */ 1501 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 19), 1502 }; 1503 static const unsigned int canfd1_data_mux[] = { 1504 CANFD1_TX_MARK, CANFD1_RX_MARK, 1505 }; 1506 1507 /* - CANFD2 ----------------------------------------------------------------- */ 1508 static const unsigned int canfd2_data_pins[] = { 1509 /* CANFD2_TX, CANFD2_RX */ 1510 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 1511 }; 1512 static const unsigned int canfd2_data_mux[] = { 1513 CANFD2_TX_MARK, CANFD2_RX_MARK, 1514 }; 1515 1516 /* - CANFD3 ----------------------------------------------------------------- */ 1517 static const unsigned int canfd3_data_pins[] = { 1518 /* CANFD3_TX, CANFD3_RX */ 1519 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 1520 }; 1521 static const unsigned int canfd3_data_mux[] = { 1522 CANFD3_TX_MARK, CANFD3_RX_MARK, 1523 }; 1524 1525 /* - CANFD Clock ------------------------------------------------------------ */ 1526 static const unsigned int can_clk_pins[] = { 1527 /* CAN_CLK */ 1528 RCAR_GP_PIN(2, 9), 1529 }; 1530 static const unsigned int can_clk_mux[] = { 1531 CAN_CLK_MARK, 1532 }; 1533 1534 /* - HSCIF0 ----------------------------------------------------------------- */ 1535 static const unsigned int hscif0_data_pins[] = { 1536 /* HRX0, HTX0 */ 1537 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12), 1538 }; 1539 static const unsigned int hscif0_data_mux[] = { 1540 HRX0_MARK, HTX0_MARK, 1541 }; 1542 static const unsigned int hscif0_clk_pins[] = { 1543 /* HSCK0 */ 1544 RCAR_GP_PIN(1, 15), 1545 }; 1546 static const unsigned int hscif0_clk_mux[] = { 1547 HSCK0_MARK, 1548 }; 1549 static const unsigned int hscif0_ctrl_pins[] = { 1550 /* HRTS0_N, HCTS0_N */ 1551 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 1552 }; 1553 static const unsigned int hscif0_ctrl_mux[] = { 1554 HRTS0_N_MARK, HCTS0_N_MARK, 1555 }; 1556 1557 /* - HSCIF1 ------------------------------------------------------------------- */ 1558 static const unsigned int hscif1_data_a_pins[] = { 1559 /* HRX1_A, HTX1_A */ 1560 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 1561 }; 1562 static const unsigned int hscif1_data_a_mux[] = { 1563 HRX1_A_MARK, HTX1_A_MARK, 1564 }; 1565 static const unsigned int hscif1_clk_a_pins[] = { 1566 /* HSCK1_A */ 1567 RCAR_GP_PIN(0, 18), 1568 }; 1569 static const unsigned int hscif1_clk_a_mux[] = { 1570 HSCK1_A_MARK, 1571 }; 1572 static const unsigned int hscif1_ctrl_a_pins[] = { 1573 /* HRTS1_N_A, HCTS1_N_A */ 1574 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), 1575 }; 1576 static const unsigned int hscif1_ctrl_a_mux[] = { 1577 HRTS1_N_A_MARK, HCTS1_N_A_MARK, 1578 }; 1579 1580 static const unsigned int hscif1_data_b_pins[] = { 1581 /* HRX1_B, HTX1_B */ 1582 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), 1583 }; 1584 static const unsigned int hscif1_data_b_mux[] = { 1585 HRX1_B_MARK, HTX1_B_MARK, 1586 }; 1587 static const unsigned int hscif1_clk_b_pins[] = { 1588 /* HSCK1_B */ 1589 RCAR_GP_PIN(1, 10), 1590 }; 1591 static const unsigned int hscif1_clk_b_mux[] = { 1592 HSCK1_B_MARK, 1593 }; 1594 static const unsigned int hscif1_ctrl_b_pins[] = { 1595 /* HRTS1_N_B, HCTS1_N_B */ 1596 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), 1597 }; 1598 static const unsigned int hscif1_ctrl_b_mux[] = { 1599 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 1600 }; 1601 1602 /* - HSCIF2 ----------------------------------------------------------------- */ 1603 static const unsigned int hscif2_data_pins[] = { 1604 /* HRX2, HTX2 */ 1605 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 1606 }; 1607 static const unsigned int hscif2_data_mux[] = { 1608 HRX2_MARK, HTX2_MARK, 1609 }; 1610 static const unsigned int hscif2_clk_pins[] = { 1611 /* HSCK2 */ 1612 RCAR_GP_PIN(4, 13), 1613 }; 1614 static const unsigned int hscif2_clk_mux[] = { 1615 HSCK2_MARK, 1616 }; 1617 static const unsigned int hscif2_ctrl_pins[] = { 1618 /* HRTS2_N, HCTS2_N */ 1619 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 12), 1620 }; 1621 static const unsigned int hscif2_ctrl_mux[] = { 1622 HRTS2_N_MARK, HCTS2_N_MARK, 1623 }; 1624 1625 /* - HSCIF3 ------------------------------------------------------------------- */ 1626 static const unsigned int hscif3_data_a_pins[] = { 1627 /* HRX3_A, HTX3_A */ 1628 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28), 1629 }; 1630 static const unsigned int hscif3_data_a_mux[] = { 1631 HRX3_A_MARK, HTX3_A_MARK, 1632 }; 1633 static const unsigned int hscif3_clk_a_pins[] = { 1634 /* HSCK3_A */ 1635 RCAR_GP_PIN(1, 25), 1636 }; 1637 static const unsigned int hscif3_clk_a_mux[] = { 1638 HSCK3_A_MARK, 1639 }; 1640 static const unsigned int hscif3_ctrl_a_pins[] = { 1641 /* HRTS3_N_A, HCTS3_N_A */ 1642 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27), 1643 }; 1644 static const unsigned int hscif3_ctrl_a_mux[] = { 1645 HRTS3_N_A_MARK, HCTS3_N_A_MARK, 1646 }; 1647 1648 static const unsigned int hscif3_data_b_pins[] = { 1649 /* HRX3_B, HTX3_B */ 1650 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), 1651 }; 1652 static const unsigned int hscif3_data_b_mux[] = { 1653 HRX3_B_MARK, HTX3_B_MARK, 1654 }; 1655 static const unsigned int hscif3_clk_b_pins[] = { 1656 /* HSCK3_B */ 1657 RCAR_GP_PIN(1, 3), 1658 }; 1659 static const unsigned int hscif3_clk_b_mux[] = { 1660 HSCK3_B_MARK, 1661 }; 1662 static const unsigned int hscif3_ctrl_b_pins[] = { 1663 /* HRTS3_N_B, HCTS3_N_B */ 1664 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), 1665 }; 1666 static const unsigned int hscif3_ctrl_b_mux[] = { 1667 HRTS3_N_B_MARK, HCTS3_N_B_MARK, 1668 }; 1669 1670 /* - I2C0 ------------------------------------------------------------------- */ 1671 static const unsigned int i2c0_pins[] = { 1672 /* SDA0, SCL0 */ 1673 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0), 1674 }; 1675 static const unsigned int i2c0_mux[] = { 1676 SDA0_MARK, SCL0_MARK, 1677 }; 1678 1679 /* - I2C1 ------------------------------------------------------------------- */ 1680 static const unsigned int i2c1_pins[] = { 1681 /* SDA1, SCL1 */ 1682 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1683 }; 1684 static const unsigned int i2c1_mux[] = { 1685 SDA1_MARK, SCL1_MARK, 1686 }; 1687 1688 /* - I2C2 ------------------------------------------------------------------- */ 1689 static const unsigned int i2c2_pins[] = { 1690 /* SDA2, SCL2 */ 1691 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4), 1692 }; 1693 static const unsigned int i2c2_mux[] = { 1694 SDA2_MARK, SCL2_MARK, 1695 }; 1696 1697 /* - I2C3 ------------------------------------------------------------------- */ 1698 static const unsigned int i2c3_pins[] = { 1699 /* SDA3, SCL3 */ 1700 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), 1701 }; 1702 static const unsigned int i2c3_mux[] = { 1703 SDA3_MARK, SCL3_MARK, 1704 }; 1705 1706 /* - INTC-EX ---------------------------------------------------------------- */ 1707 static const unsigned int intc_ex_irq0_a_pins[] = { 1708 /* IRQ0_A */ 1709 RCAR_GP_PIN(0, 6), 1710 }; 1711 static const unsigned int intc_ex_irq0_a_mux[] = { 1712 IRQ0_A_MARK, 1713 }; 1714 static const unsigned int intc_ex_irq0_b_pins[] = { 1715 /* IRQ0_B */ 1716 RCAR_GP_PIN(1, 20), 1717 }; 1718 static const unsigned int intc_ex_irq0_b_mux[] = { 1719 IRQ0_B_MARK, 1720 }; 1721 1722 static const unsigned int intc_ex_irq1_a_pins[] = { 1723 /* IRQ1_A */ 1724 RCAR_GP_PIN(0, 5), 1725 }; 1726 static const unsigned int intc_ex_irq1_a_mux[] = { 1727 IRQ1_A_MARK, 1728 }; 1729 static const unsigned int intc_ex_irq1_b_pins[] = { 1730 /* IRQ1_B */ 1731 RCAR_GP_PIN(1, 21), 1732 }; 1733 static const unsigned int intc_ex_irq1_b_mux[] = { 1734 IRQ1_B_MARK, 1735 }; 1736 1737 static const unsigned int intc_ex_irq2_a_pins[] = { 1738 /* IRQ2_A */ 1739 RCAR_GP_PIN(0, 4), 1740 }; 1741 static const unsigned int intc_ex_irq2_a_mux[] = { 1742 IRQ2_A_MARK, 1743 }; 1744 static const unsigned int intc_ex_irq2_b_pins[] = { 1745 /* IRQ2_B */ 1746 RCAR_GP_PIN(0, 13), 1747 }; 1748 static const unsigned int intc_ex_irq2_b_mux[] = { 1749 IRQ2_B_MARK, 1750 }; 1751 1752 static const unsigned int intc_ex_irq3_a_pins[] = { 1753 /* IRQ3_A */ 1754 RCAR_GP_PIN(0, 3), 1755 }; 1756 static const unsigned int intc_ex_irq3_a_mux[] = { 1757 IRQ3_A_MARK, 1758 }; 1759 static const unsigned int intc_ex_irq3_b_pins[] = { 1760 /* IRQ3_B */ 1761 RCAR_GP_PIN(1, 23), 1762 }; 1763 static const unsigned int intc_ex_irq3_b_mux[] = { 1764 IRQ3_B_MARK, 1765 }; 1766 1767 static const unsigned int intc_ex_irq4_a_pins[] = { 1768 /* IRQ4_A */ 1769 RCAR_GP_PIN(1, 17), 1770 }; 1771 static const unsigned int intc_ex_irq4_a_mux[] = { 1772 IRQ4_A_MARK, 1773 }; 1774 static const unsigned int intc_ex_irq4_b_pins[] = { 1775 /* IRQ4_B */ 1776 RCAR_GP_PIN(2, 3), 1777 }; 1778 static const unsigned int intc_ex_irq4_b_mux[] = { 1779 IRQ4_B_MARK, 1780 }; 1781 1782 static const unsigned int intc_ex_irq5_pins[] = { 1783 /* IRQ5 */ 1784 RCAR_GP_PIN(2, 2), 1785 }; 1786 static const unsigned int intc_ex_irq5_mux[] = { 1787 IRQ5_MARK, 1788 }; 1789 1790 /* - MMC -------------------------------------------------------------------- */ 1791 static const unsigned int mmc_data_pins[] = { 1792 /* MMC_SD_D[0:3], MMC_D[4:7] */ 1793 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 1794 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5), 1795 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), 1796 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), 1797 }; 1798 static const unsigned int mmc_data_mux[] = { 1799 MMC_SD_D0_MARK, MMC_SD_D1_MARK, 1800 MMC_SD_D2_MARK, MMC_SD_D3_MARK, 1801 MMC_D4_MARK, MMC_D5_MARK, 1802 MMC_D6_MARK, MMC_D7_MARK, 1803 }; 1804 static const unsigned int mmc_ctrl_pins[] = { 1805 /* MMC_SD_CLK, MMC_SD_CMD */ 1806 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10), 1807 }; 1808 static const unsigned int mmc_ctrl_mux[] = { 1809 MMC_SD_CLK_MARK, MMC_SD_CMD_MARK, 1810 }; 1811 static const unsigned int mmc_cd_pins[] = { 1812 /* SD_CD */ 1813 RCAR_GP_PIN(3, 11), 1814 }; 1815 static const unsigned int mmc_cd_mux[] = { 1816 SD_CD_MARK, 1817 }; 1818 static const unsigned int mmc_wp_pins[] = { 1819 /* SD_WP */ 1820 RCAR_GP_PIN(3, 12), 1821 }; 1822 static const unsigned int mmc_wp_mux[] = { 1823 SD_WP_MARK, 1824 }; 1825 static const unsigned int mmc_ds_pins[] = { 1826 /* MMC_DS */ 1827 RCAR_GP_PIN(3, 4), 1828 }; 1829 static const unsigned int mmc_ds_mux[] = { 1830 MMC_DS_MARK, 1831 }; 1832 1833 /* - MSIOF0 ----------------------------------------------------------------- */ 1834 static const unsigned int msiof0_clk_pins[] = { 1835 /* MSIOF0_SCK */ 1836 RCAR_GP_PIN(1, 10), 1837 }; 1838 static const unsigned int msiof0_clk_mux[] = { 1839 MSIOF0_SCK_MARK, 1840 }; 1841 static const unsigned int msiof0_sync_pins[] = { 1842 /* MSIOF0_SYNC */ 1843 RCAR_GP_PIN(1, 8), 1844 }; 1845 static const unsigned int msiof0_sync_mux[] = { 1846 MSIOF0_SYNC_MARK, 1847 }; 1848 static const unsigned int msiof0_ss1_pins[] = { 1849 /* MSIOF0_SS1 */ 1850 RCAR_GP_PIN(1, 7), 1851 }; 1852 static const unsigned int msiof0_ss1_mux[] = { 1853 MSIOF0_SS1_MARK, 1854 }; 1855 static const unsigned int msiof0_ss2_pins[] = { 1856 /* MSIOF0_SS2 */ 1857 RCAR_GP_PIN(1, 6), 1858 }; 1859 static const unsigned int msiof0_ss2_mux[] = { 1860 MSIOF0_SS2_MARK, 1861 }; 1862 static const unsigned int msiof0_txd_pins[] = { 1863 /* MSIOF0_TXD */ 1864 RCAR_GP_PIN(1, 9), 1865 }; 1866 static const unsigned int msiof0_txd_mux[] = { 1867 MSIOF0_TXD_MARK, 1868 }; 1869 static const unsigned int msiof0_rxd_pins[] = { 1870 /* MSIOF0_RXD */ 1871 RCAR_GP_PIN(1, 11), 1872 }; 1873 static const unsigned int msiof0_rxd_mux[] = { 1874 MSIOF0_RXD_MARK, 1875 }; 1876 1877 /* - MSIOF1 ----------------------------------------------------------------- */ 1878 static const unsigned int msiof1_clk_pins[] = { 1879 /* MSIOF1_SCK */ 1880 RCAR_GP_PIN(1, 3), 1881 }; 1882 static const unsigned int msiof1_clk_mux[] = { 1883 MSIOF1_SCK_MARK, 1884 }; 1885 static const unsigned int msiof1_sync_pins[] = { 1886 /* MSIOF1_SYNC */ 1887 RCAR_GP_PIN(1, 2), 1888 }; 1889 static const unsigned int msiof1_sync_mux[] = { 1890 MSIOF1_SYNC_MARK, 1891 }; 1892 static const unsigned int msiof1_ss1_pins[] = { 1893 /* MSIOF1_SS1 */ 1894 RCAR_GP_PIN(1, 1), 1895 }; 1896 static const unsigned int msiof1_ss1_mux[] = { 1897 MSIOF1_SS1_MARK, 1898 }; 1899 static const unsigned int msiof1_ss2_pins[] = { 1900 /* MSIOF1_SS2 */ 1901 RCAR_GP_PIN(1, 0), 1902 }; 1903 static const unsigned int msiof1_ss2_mux[] = { 1904 MSIOF1_SS2_MARK, 1905 }; 1906 static const unsigned int msiof1_txd_pins[] = { 1907 /* MSIOF1_TXD */ 1908 RCAR_GP_PIN(1, 4), 1909 }; 1910 static const unsigned int msiof1_txd_mux[] = { 1911 MSIOF1_TXD_MARK, 1912 }; 1913 static const unsigned int msiof1_rxd_pins[] = { 1914 /* MSIOF1_RXD */ 1915 RCAR_GP_PIN(1, 5), 1916 }; 1917 static const unsigned int msiof1_rxd_mux[] = { 1918 MSIOF1_RXD_MARK, 1919 }; 1920 1921 /* - MSIOF2 ----------------------------------------------------------------- */ 1922 static const unsigned int msiof2_clk_pins[] = { 1923 /* MSIOF2_SCK */ 1924 RCAR_GP_PIN(0, 17), 1925 }; 1926 static const unsigned int msiof2_clk_mux[] = { 1927 MSIOF2_SCK_MARK, 1928 }; 1929 static const unsigned int msiof2_sync_pins[] = { 1930 /* MSIOF2_SYNC */ 1931 RCAR_GP_PIN(0, 15), 1932 }; 1933 static const unsigned int msiof2_sync_mux[] = { 1934 MSIOF2_SYNC_MARK, 1935 }; 1936 static const unsigned int msiof2_ss1_pins[] = { 1937 /* MSIOF2_SS1 */ 1938 RCAR_GP_PIN(0, 14), 1939 }; 1940 static const unsigned int msiof2_ss1_mux[] = { 1941 MSIOF2_SS1_MARK, 1942 }; 1943 static const unsigned int msiof2_ss2_pins[] = { 1944 /* MSIOF2_SS2 */ 1945 RCAR_GP_PIN(0, 13), 1946 }; 1947 static const unsigned int msiof2_ss2_mux[] = { 1948 MSIOF2_SS2_MARK, 1949 }; 1950 static const unsigned int msiof2_txd_pins[] = { 1951 /* MSIOF2_TXD */ 1952 RCAR_GP_PIN(0, 16), 1953 }; 1954 static const unsigned int msiof2_txd_mux[] = { 1955 MSIOF2_TXD_MARK, 1956 }; 1957 static const unsigned int msiof2_rxd_pins[] = { 1958 /* MSIOF2_RXD */ 1959 RCAR_GP_PIN(0, 18), 1960 }; 1961 static const unsigned int msiof2_rxd_mux[] = { 1962 MSIOF2_RXD_MARK, 1963 }; 1964 1965 /* - MSIOF3 ----------------------------------------------------------------- */ 1966 static const unsigned int msiof3_clk_pins[] = { 1967 /* MSIOF3_SCK */ 1968 RCAR_GP_PIN(0, 3), 1969 }; 1970 static const unsigned int msiof3_clk_mux[] = { 1971 MSIOF3_SCK_MARK, 1972 }; 1973 static const unsigned int msiof3_sync_pins[] = { 1974 /* MSIOF3_SYNC */ 1975 RCAR_GP_PIN(0, 6), 1976 }; 1977 static const unsigned int msiof3_sync_mux[] = { 1978 MSIOF3_SYNC_MARK, 1979 }; 1980 static const unsigned int msiof3_ss1_pins[] = { 1981 /* MSIOF3_SS1 */ 1982 RCAR_GP_PIN(0, 1), 1983 }; 1984 static const unsigned int msiof3_ss1_mux[] = { 1985 MSIOF3_SS1_MARK, 1986 }; 1987 static const unsigned int msiof3_ss2_pins[] = { 1988 /* MSIOF3_SS2 */ 1989 RCAR_GP_PIN(0, 2), 1990 }; 1991 static const unsigned int msiof3_ss2_mux[] = { 1992 MSIOF3_SS2_MARK, 1993 }; 1994 static const unsigned int msiof3_txd_pins[] = { 1995 /* MSIOF3_TXD */ 1996 RCAR_GP_PIN(0, 4), 1997 }; 1998 static const unsigned int msiof3_txd_mux[] = { 1999 MSIOF3_TXD_MARK, 2000 }; 2001 static const unsigned int msiof3_rxd_pins[] = { 2002 /* MSIOF3_RXD */ 2003 RCAR_GP_PIN(0, 5), 2004 }; 2005 static const unsigned int msiof3_rxd_mux[] = { 2006 MSIOF3_RXD_MARK, 2007 }; 2008 2009 /* - MSIOF4 ----------------------------------------------------------------- */ 2010 static const unsigned int msiof4_clk_pins[] = { 2011 /* MSIOF4_SCK */ 2012 RCAR_GP_PIN(1, 25), 2013 }; 2014 static const unsigned int msiof4_clk_mux[] = { 2015 MSIOF4_SCK_MARK, 2016 }; 2017 static const unsigned int msiof4_sync_pins[] = { 2018 /* MSIOF4_SYNC */ 2019 RCAR_GP_PIN(1, 28), 2020 }; 2021 static const unsigned int msiof4_sync_mux[] = { 2022 MSIOF4_SYNC_MARK, 2023 }; 2024 static const unsigned int msiof4_ss1_pins[] = { 2025 /* MSIOF4_SS1 */ 2026 RCAR_GP_PIN(1, 23), 2027 }; 2028 static const unsigned int msiof4_ss1_mux[] = { 2029 MSIOF4_SS1_MARK, 2030 }; 2031 static const unsigned int msiof4_ss2_pins[] = { 2032 /* MSIOF4_SS2 */ 2033 RCAR_GP_PIN(1, 24), 2034 }; 2035 static const unsigned int msiof4_ss2_mux[] = { 2036 MSIOF4_SS2_MARK, 2037 }; 2038 static const unsigned int msiof4_txd_pins[] = { 2039 /* MSIOF4_TXD */ 2040 RCAR_GP_PIN(1, 26), 2041 }; 2042 static const unsigned int msiof4_txd_mux[] = { 2043 MSIOF4_TXD_MARK, 2044 }; 2045 static const unsigned int msiof4_rxd_pins[] = { 2046 /* MSIOF4_RXD */ 2047 RCAR_GP_PIN(1, 27), 2048 }; 2049 static const unsigned int msiof4_rxd_mux[] = { 2050 MSIOF4_RXD_MARK, 2051 }; 2052 2053 /* - MSIOF5 ----------------------------------------------------------------- */ 2054 static const unsigned int msiof5_clk_pins[] = { 2055 /* MSIOF5_SCK */ 2056 RCAR_GP_PIN(0, 11), 2057 }; 2058 static const unsigned int msiof5_clk_mux[] = { 2059 MSIOF5_SCK_MARK, 2060 }; 2061 static const unsigned int msiof5_sync_pins[] = { 2062 /* MSIOF5_SYNC */ 2063 RCAR_GP_PIN(0, 9), 2064 }; 2065 static const unsigned int msiof5_sync_mux[] = { 2066 MSIOF5_SYNC_MARK, 2067 }; 2068 static const unsigned int msiof5_ss1_pins[] = { 2069 /* MSIOF5_SS1 */ 2070 RCAR_GP_PIN(0, 8), 2071 }; 2072 static const unsigned int msiof5_ss1_mux[] = { 2073 MSIOF5_SS1_MARK, 2074 }; 2075 static const unsigned int msiof5_ss2_pins[] = { 2076 /* MSIOF5_SS2 */ 2077 RCAR_GP_PIN(0, 7), 2078 }; 2079 static const unsigned int msiof5_ss2_mux[] = { 2080 MSIOF5_SS2_MARK, 2081 }; 2082 static const unsigned int msiof5_txd_pins[] = { 2083 /* MSIOF5_TXD */ 2084 RCAR_GP_PIN(0, 10), 2085 }; 2086 static const unsigned int msiof5_txd_mux[] = { 2087 MSIOF5_TXD_MARK, 2088 }; 2089 static const unsigned int msiof5_rxd_pins[] = { 2090 /* MSIOF5_RXD */ 2091 RCAR_GP_PIN(0, 12), 2092 }; 2093 static const unsigned int msiof5_rxd_mux[] = { 2094 MSIOF5_RXD_MARK, 2095 }; 2096 2097 /* - PCIE ------------------------------------------------------------------- */ 2098 static const unsigned int pcie0_clkreq_n_pins[] = { 2099 /* PCIE0_CLKREQ_N */ 2100 RCAR_GP_PIN(4, 21), 2101 }; 2102 2103 static const unsigned int pcie0_clkreq_n_mux[] = { 2104 PCIE0_CLKREQ_N_MARK, 2105 }; 2106 2107 /* - PWM0 --------------------------------------------------------------------- */ 2108 static const unsigned int pwm0_a_pins[] = { 2109 /* PWM0_A */ 2110 RCAR_GP_PIN(1, 15), 2111 }; 2112 static const unsigned int pwm0_a_mux[] = { 2113 PWM0_A_MARK, 2114 }; 2115 2116 static const unsigned int pwm0_b_pins[] = { 2117 /* PWM0_B */ 2118 RCAR_GP_PIN(1, 14), 2119 }; 2120 static const unsigned int pwm0_b_mux[] = { 2121 PWM0_B_MARK, 2122 }; 2123 2124 /* - PWM1 --------------------------------------------------------------------- */ 2125 static const unsigned int pwm1_a_pins[] = { 2126 /* PWM1_A */ 2127 RCAR_GP_PIN(3, 13), 2128 }; 2129 static const unsigned int pwm1_a_mux[] = { 2130 PWM1_A_MARK, 2131 }; 2132 2133 static const unsigned int pwm1_b_pins[] = { 2134 /* PWM1_B */ 2135 RCAR_GP_PIN(2, 13), 2136 }; 2137 static const unsigned int pwm1_b_mux[] = { 2138 PWM1_B_MARK, 2139 }; 2140 2141 static const unsigned int pwm1_c_pins[] = { 2142 /* PWM1_C */ 2143 RCAR_GP_PIN(2, 17), 2144 }; 2145 static const unsigned int pwm1_c_mux[] = { 2146 PWM1_C_MARK, 2147 }; 2148 2149 /* - PWM2 --------------------------------------------------------------------- */ 2150 static const unsigned int pwm2_a_pins[] = { 2151 /* PWM2_A */ 2152 RCAR_GP_PIN(3, 14), 2153 }; 2154 static const unsigned int pwm2_a_mux[] = { 2155 PWM2_A_MARK, 2156 }; 2157 2158 static const unsigned int pwm2_b_pins[] = { 2159 /* PWM2_B */ 2160 RCAR_GP_PIN(2, 14), 2161 }; 2162 static const unsigned int pwm2_b_mux[] = { 2163 PWM2_B_MARK, 2164 }; 2165 2166 static const unsigned int pwm2_c_pins[] = { 2167 /* PWM2_C */ 2168 RCAR_GP_PIN(2, 19), 2169 }; 2170 static const unsigned int pwm2_c_mux[] = { 2171 PWM2_C_MARK, 2172 }; 2173 2174 /* - PWM3 --------------------------------------------------------------------- */ 2175 static const unsigned int pwm3_a_pins[] = { 2176 /* PWM3_A */ 2177 RCAR_GP_PIN(4, 14), 2178 }; 2179 static const unsigned int pwm3_a_mux[] = { 2180 PWM3_A_MARK, 2181 }; 2182 2183 static const unsigned int pwm3_b_pins[] = { 2184 /* PWM3_B */ 2185 RCAR_GP_PIN(2, 15), 2186 }; 2187 static const unsigned int pwm3_b_mux[] = { 2188 PWM3_B_MARK, 2189 }; 2190 2191 static const unsigned int pwm3_c_pins[] = { 2192 /* PWM3_C */ 2193 RCAR_GP_PIN(1, 22), 2194 }; 2195 static const unsigned int pwm3_c_mux[] = { 2196 PWM3_C_MARK, 2197 }; 2198 2199 /* - PWM4 ------------------------------------------------------------------- */ 2200 static const unsigned int pwm4_pins[] = { 2201 /* PWM4 */ 2202 RCAR_GP_PIN(4, 15), 2203 }; 2204 static const unsigned int pwm4_mux[] = { 2205 PWM4_MARK, 2206 }; 2207 2208 /* - QSPI0 ------------------------------------------------------------------ */ 2209 static const unsigned int qspi0_ctrl_pins[] = { 2210 /* SPCLK, SSL */ 2211 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15), 2212 }; 2213 static const unsigned int qspi0_ctrl_mux[] = { 2214 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 2215 }; 2216 static const unsigned int qspi0_data_pins[] = { 2217 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 2218 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18), 2219 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), 2220 }; 2221 static const unsigned int qspi0_data_mux[] = { 2222 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 2223 QSPI0_IO2_MARK, QSPI0_IO3_MARK 2224 }; 2225 2226 /* - QSPI1 ------------------------------------------------------------------ */ 2227 static const unsigned int qspi1_ctrl_pins[] = { 2228 /* SPCLK, SSL */ 2229 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25), 2230 }; 2231 static const unsigned int qspi1_ctrl_mux[] = { 2232 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 2233 }; 2234 static const unsigned int qspi1_data_pins[] = { 2235 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 2236 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23), 2237 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26), 2238 }; 2239 static const unsigned int qspi1_data_mux[] = { 2240 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 2241 QSPI1_IO2_MARK, QSPI1_IO3_MARK 2242 }; 2243 2244 /* - SCIF0 ------------------------------------------------------------------ */ 2245 static const unsigned int scif0_data_pins[] = { 2246 /* RX0, TX0 */ 2247 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12), 2248 }; 2249 static const unsigned int scif0_data_mux[] = { 2250 RX0_MARK, TX0_MARK, 2251 }; 2252 static const unsigned int scif0_clk_pins[] = { 2253 /* SCK0 */ 2254 RCAR_GP_PIN(1, 15), 2255 }; 2256 static const unsigned int scif0_clk_mux[] = { 2257 SCK0_MARK, 2258 }; 2259 static const unsigned int scif0_ctrl_pins[] = { 2260 /* RTS0_N, CTS0_N */ 2261 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2262 }; 2263 static const unsigned int scif0_ctrl_mux[] = { 2264 RTS0_N_MARK, CTS0_N_MARK, 2265 }; 2266 2267 /* - SCIF1 -------------------------------------------------------------------- */ 2268 static const unsigned int scif1_data_a_pins[] = { 2269 /* RX1_A, TX1_A */ 2270 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 2271 }; 2272 static const unsigned int scif1_data_a_mux[] = { 2273 RX1_A_MARK, TX1_A_MARK, 2274 }; 2275 static const unsigned int scif1_clk_a_pins[] = { 2276 /* SCK1_A */ 2277 RCAR_GP_PIN(0, 18), 2278 }; 2279 static const unsigned int scif1_clk_a_mux[] = { 2280 SCK1_A_MARK, 2281 }; 2282 static const unsigned int scif1_ctrl_a_pins[] = { 2283 /* RTS1_N_A, CTS1_N_A */ 2284 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), 2285 }; 2286 static const unsigned int scif1_ctrl_a_mux[] = { 2287 RTS1_N_A_MARK, CTS1_N_A_MARK, 2288 }; 2289 2290 static const unsigned int scif1_data_b_pins[] = { 2291 /* RX1_B, TX1_B */ 2292 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), 2293 }; 2294 static const unsigned int scif1_data_b_mux[] = { 2295 RX1_B_MARK, TX1_B_MARK, 2296 }; 2297 static const unsigned int scif1_clk_b_pins[] = { 2298 /* SCK1_B */ 2299 RCAR_GP_PIN(1, 10), 2300 }; 2301 static const unsigned int scif1_clk_b_mux[] = { 2302 SCK1_B_MARK, 2303 }; 2304 static const unsigned int scif1_ctrl_b_pins[] = { 2305 /* RTS1_N_B, CTS1_N_B */ 2306 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), 2307 }; 2308 static const unsigned int scif1_ctrl_b_mux[] = { 2309 RTS1_N_B_MARK, CTS1_N_B_MARK, 2310 }; 2311 2312 /* - SCIF3 -------------------------------------------------------------------- */ 2313 static const unsigned int scif3_data_a_pins[] = { 2314 /* RX3_A, TX3_A */ 2315 RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28), 2316 }; 2317 static const unsigned int scif3_data_a_mux[] = { 2318 RX3_A_MARK, TX3_A_MARK, 2319 }; 2320 static const unsigned int scif3_clk_a_pins[] = { 2321 /* SCK3_A */ 2322 RCAR_GP_PIN(1, 24), 2323 }; 2324 static const unsigned int scif3_clk_a_mux[] = { 2325 SCK3_A_MARK, 2326 }; 2327 static const unsigned int scif3_ctrl_a_pins[] = { 2328 /* RTS3_N_A, CTS3_N_A */ 2329 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2330 }; 2331 static const unsigned int scif3_ctrl_a_mux[] = { 2332 RTS3_N_A_MARK, CTS3_N_A_MARK, 2333 }; 2334 2335 static const unsigned int scif3_data_b_pins[] = { 2336 /* RX3_B, TX3_B */ 2337 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 2338 }; 2339 static const unsigned int scif3_data_b_mux[] = { 2340 RX3_B_MARK, TX3_B_MARK, 2341 }; 2342 static const unsigned int scif3_clk_b_pins[] = { 2343 /* SCK3_B */ 2344 RCAR_GP_PIN(1, 4), 2345 }; 2346 static const unsigned int scif3_clk_b_mux[] = { 2347 SCK3_B_MARK, 2348 }; 2349 static const unsigned int scif3_ctrl_b_pins[] = { 2350 /* RTS3_N_B, CTS3_N_B */ 2351 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 2352 }; 2353 static const unsigned int scif3_ctrl_b_mux[] = { 2354 RTS3_N_B_MARK, CTS3_N_B_MARK, 2355 }; 2356 2357 /* - SCIF4 ------------------------------------------------------------------ */ 2358 static const unsigned int scif4_data_pins[] = { 2359 /* RX4, TX4 */ 2360 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12), 2361 }; 2362 static const unsigned int scif4_data_mux[] = { 2363 RX4_MARK, TX4_MARK, 2364 }; 2365 static const unsigned int scif4_clk_pins[] = { 2366 /* SCK4 */ 2367 RCAR_GP_PIN(4, 8), 2368 }; 2369 static const unsigned int scif4_clk_mux[] = { 2370 SCK4_MARK, 2371 }; 2372 static const unsigned int scif4_ctrl_pins[] = { 2373 /* RTS4_N, CTS4_N */ 2374 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 9), 2375 }; 2376 static const unsigned int scif4_ctrl_mux[] = { 2377 RTS4_N_MARK, CTS4_N_MARK, 2378 }; 2379 2380 /* - SCIF Clock ------------------------------------------------------------- */ 2381 static const unsigned int scif_clk_pins[] = { 2382 /* SCIF_CLK */ 2383 RCAR_GP_PIN(1, 17), 2384 }; 2385 static const unsigned int scif_clk_mux[] = { 2386 SCIF_CLK_MARK, 2387 }; 2388 2389 static const unsigned int scif_clk2_pins[] = { 2390 /* SCIF_CLK2 */ 2391 RCAR_GP_PIN(4, 11), 2392 }; 2393 static const unsigned int scif_clk2_mux[] = { 2394 SCIF_CLK2_MARK, 2395 }; 2396 2397 /* - SSI ------------------------------------------------- */ 2398 static const unsigned int ssi_data_pins[] = { 2399 /* SSI_SD */ 2400 RCAR_GP_PIN(1, 20), 2401 }; 2402 static const unsigned int ssi_data_mux[] = { 2403 SSI_SD_MARK, 2404 }; 2405 static const unsigned int ssi_ctrl_pins[] = { 2406 /* SSI_SCK, SSI_WS */ 2407 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), 2408 }; 2409 static const unsigned int ssi_ctrl_mux[] = { 2410 SSI_SCK_MARK, SSI_WS_MARK, 2411 }; 2412 2413 /* - TPU --------------------------------------------------------------------- */ 2414 static const unsigned int tpu_to0_a_pins[] = { 2415 /* TPU0TO0_A */ 2416 RCAR_GP_PIN(2, 8), 2417 }; 2418 static const unsigned int tpu_to0_a_mux[] = { 2419 TPU0TO0_A_MARK, 2420 }; 2421 static const unsigned int tpu_to1_a_pins[] = { 2422 /* TPU0TO1_A */ 2423 RCAR_GP_PIN(2, 7), 2424 }; 2425 static const unsigned int tpu_to1_a_mux[] = { 2426 TPU0TO1_A_MARK, 2427 }; 2428 static const unsigned int tpu_to2_a_pins[] = { 2429 /* TPU0TO2_A */ 2430 RCAR_GP_PIN(2, 12), 2431 }; 2432 static const unsigned int tpu_to2_a_mux[] = { 2433 TPU0TO2_A_MARK, 2434 }; 2435 static const unsigned int tpu_to3_a_pins[] = { 2436 /* TPU0TO3_A */ 2437 RCAR_GP_PIN(2, 13), 2438 }; 2439 static const unsigned int tpu_to3_a_mux[] = { 2440 TPU0TO3_A_MARK, 2441 }; 2442 2443 static const unsigned int tpu_to0_b_pins[] = { 2444 /* TPU0TO0_B */ 2445 RCAR_GP_PIN(1, 25), 2446 }; 2447 static const unsigned int tpu_to0_b_mux[] = { 2448 TPU0TO0_B_MARK, 2449 }; 2450 static const unsigned int tpu_to1_b_pins[] = { 2451 /* TPU0TO1_B */ 2452 RCAR_GP_PIN(1, 26), 2453 }; 2454 static const unsigned int tpu_to1_b_mux[] = { 2455 TPU0TO1_B_MARK, 2456 }; 2457 static const unsigned int tpu_to2_b_pins[] = { 2458 /* TPU0TO2_B */ 2459 RCAR_GP_PIN(2, 0), 2460 }; 2461 static const unsigned int tpu_to2_b_mux[] = { 2462 TPU0TO2_B_MARK, 2463 }; 2464 static const unsigned int tpu_to3_b_pins[] = { 2465 /* TPU0TO3_B */ 2466 RCAR_GP_PIN(2, 1), 2467 }; 2468 static const unsigned int tpu_to3_b_mux[] = { 2469 TPU0TO3_B_MARK, 2470 }; 2471 2472 static const struct sh_pfc_pin_group pinmux_groups[] = { 2473 SH_PFC_PIN_GROUP(audio_clkin), 2474 SH_PFC_PIN_GROUP(audio_clkout), 2475 2476 SH_PFC_PIN_GROUP(avb0_link), 2477 SH_PFC_PIN_GROUP(avb0_magic), 2478 SH_PFC_PIN_GROUP(avb0_phy_int), 2479 SH_PFC_PIN_GROUP(avb0_mdio), 2480 SH_PFC_PIN_GROUP(avb0_mii), 2481 SH_PFC_PIN_GROUP(avb0_rgmii), 2482 SH_PFC_PIN_GROUP(avb0_txcrefclk), 2483 SH_PFC_PIN_GROUP(avb0_avtp_pps), 2484 SH_PFC_PIN_GROUP(avb0_avtp_capture), 2485 SH_PFC_PIN_GROUP(avb0_avtp_match), 2486 2487 SH_PFC_PIN_GROUP(avb1_link), 2488 SH_PFC_PIN_GROUP(avb1_magic), 2489 SH_PFC_PIN_GROUP(avb1_phy_int), 2490 SH_PFC_PIN_GROUP(avb1_mdio), 2491 SH_PFC_PIN_GROUP(avb1_mii), 2492 SH_PFC_PIN_GROUP(avb1_rgmii), 2493 SH_PFC_PIN_GROUP(avb1_txcrefclk), 2494 SH_PFC_PIN_GROUP(avb1_avtp_pps), 2495 SH_PFC_PIN_GROUP(avb1_avtp_capture), 2496 SH_PFC_PIN_GROUP(avb1_avtp_match), 2497 2498 SH_PFC_PIN_GROUP(avb2_link), 2499 SH_PFC_PIN_GROUP(avb2_magic), 2500 SH_PFC_PIN_GROUP(avb2_phy_int), 2501 SH_PFC_PIN_GROUP(avb2_mdio), 2502 SH_PFC_PIN_GROUP(avb2_rgmii), 2503 SH_PFC_PIN_GROUP(avb2_txcrefclk), 2504 SH_PFC_PIN_GROUP(avb2_avtp_pps), 2505 SH_PFC_PIN_GROUP(avb2_avtp_capture), 2506 SH_PFC_PIN_GROUP(avb2_avtp_match), 2507 2508 SH_PFC_PIN_GROUP(canfd0_data), 2509 SH_PFC_PIN_GROUP(canfd1_data), 2510 SH_PFC_PIN_GROUP(canfd2_data), 2511 SH_PFC_PIN_GROUP(canfd3_data), 2512 SH_PFC_PIN_GROUP(can_clk), 2513 2514 SH_PFC_PIN_GROUP(hscif0_data), 2515 SH_PFC_PIN_GROUP(hscif0_clk), 2516 SH_PFC_PIN_GROUP(hscif0_ctrl), 2517 SH_PFC_PIN_GROUP(hscif1_data_a), 2518 SH_PFC_PIN_GROUP(hscif1_clk_a), 2519 SH_PFC_PIN_GROUP(hscif1_ctrl_a), 2520 SH_PFC_PIN_GROUP(hscif1_data_b), 2521 SH_PFC_PIN_GROUP(hscif1_clk_b), 2522 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 2523 SH_PFC_PIN_GROUP(hscif2_data), 2524 SH_PFC_PIN_GROUP(hscif2_clk), 2525 SH_PFC_PIN_GROUP(hscif2_ctrl), 2526 SH_PFC_PIN_GROUP(hscif3_data_a), 2527 SH_PFC_PIN_GROUP(hscif3_clk_a), 2528 SH_PFC_PIN_GROUP(hscif3_ctrl_a), 2529 SH_PFC_PIN_GROUP(hscif3_data_b), 2530 SH_PFC_PIN_GROUP(hscif3_clk_b), 2531 SH_PFC_PIN_GROUP(hscif3_ctrl_b), 2532 2533 SH_PFC_PIN_GROUP(i2c0), 2534 SH_PFC_PIN_GROUP(i2c1), 2535 SH_PFC_PIN_GROUP(i2c2), 2536 SH_PFC_PIN_GROUP(i2c3), 2537 2538 SH_PFC_PIN_GROUP(intc_ex_irq0_a), 2539 SH_PFC_PIN_GROUP(intc_ex_irq0_b), 2540 SH_PFC_PIN_GROUP(intc_ex_irq1_a), 2541 SH_PFC_PIN_GROUP(intc_ex_irq1_b), 2542 SH_PFC_PIN_GROUP(intc_ex_irq2_a), 2543 SH_PFC_PIN_GROUP(intc_ex_irq2_b), 2544 SH_PFC_PIN_GROUP(intc_ex_irq3_a), 2545 SH_PFC_PIN_GROUP(intc_ex_irq3_b), 2546 SH_PFC_PIN_GROUP(intc_ex_irq4_a), 2547 SH_PFC_PIN_GROUP(intc_ex_irq4_b), 2548 SH_PFC_PIN_GROUP(intc_ex_irq5), 2549 2550 BUS_DATA_PIN_GROUP(mmc_data, 1), 2551 BUS_DATA_PIN_GROUP(mmc_data, 4), 2552 BUS_DATA_PIN_GROUP(mmc_data, 8), 2553 SH_PFC_PIN_GROUP(mmc_ctrl), 2554 SH_PFC_PIN_GROUP(mmc_cd), 2555 SH_PFC_PIN_GROUP(mmc_wp), 2556 SH_PFC_PIN_GROUP(mmc_ds), 2557 2558 SH_PFC_PIN_GROUP(msiof0_clk), 2559 SH_PFC_PIN_GROUP(msiof0_sync), 2560 SH_PFC_PIN_GROUP(msiof0_ss1), 2561 SH_PFC_PIN_GROUP(msiof0_ss2), 2562 SH_PFC_PIN_GROUP(msiof0_txd), 2563 SH_PFC_PIN_GROUP(msiof0_rxd), 2564 2565 SH_PFC_PIN_GROUP(msiof1_clk), 2566 SH_PFC_PIN_GROUP(msiof1_sync), 2567 SH_PFC_PIN_GROUP(msiof1_ss1), 2568 SH_PFC_PIN_GROUP(msiof1_ss2), 2569 SH_PFC_PIN_GROUP(msiof1_txd), 2570 SH_PFC_PIN_GROUP(msiof1_rxd), 2571 2572 SH_PFC_PIN_GROUP(msiof2_clk), 2573 SH_PFC_PIN_GROUP(msiof2_sync), 2574 SH_PFC_PIN_GROUP(msiof2_ss1), 2575 SH_PFC_PIN_GROUP(msiof2_ss2), 2576 SH_PFC_PIN_GROUP(msiof2_txd), 2577 SH_PFC_PIN_GROUP(msiof2_rxd), 2578 2579 SH_PFC_PIN_GROUP(msiof3_clk), 2580 SH_PFC_PIN_GROUP(msiof3_sync), 2581 SH_PFC_PIN_GROUP(msiof3_ss1), 2582 SH_PFC_PIN_GROUP(msiof3_ss2), 2583 SH_PFC_PIN_GROUP(msiof3_txd), 2584 SH_PFC_PIN_GROUP(msiof3_rxd), 2585 2586 SH_PFC_PIN_GROUP(msiof4_clk), 2587 SH_PFC_PIN_GROUP(msiof4_sync), 2588 SH_PFC_PIN_GROUP(msiof4_ss1), 2589 SH_PFC_PIN_GROUP(msiof4_ss2), 2590 SH_PFC_PIN_GROUP(msiof4_txd), 2591 SH_PFC_PIN_GROUP(msiof4_rxd), 2592 2593 SH_PFC_PIN_GROUP(msiof5_clk), 2594 SH_PFC_PIN_GROUP(msiof5_sync), 2595 SH_PFC_PIN_GROUP(msiof5_ss1), 2596 SH_PFC_PIN_GROUP(msiof5_ss2), 2597 SH_PFC_PIN_GROUP(msiof5_txd), 2598 SH_PFC_PIN_GROUP(msiof5_rxd), 2599 2600 SH_PFC_PIN_GROUP(pcie0_clkreq_n), 2601 2602 SH_PFC_PIN_GROUP(pwm0_a), 2603 SH_PFC_PIN_GROUP(pwm0_b), 2604 SH_PFC_PIN_GROUP(pwm1_a), 2605 SH_PFC_PIN_GROUP(pwm1_b), 2606 SH_PFC_PIN_GROUP(pwm1_c), 2607 SH_PFC_PIN_GROUP(pwm2_a), 2608 SH_PFC_PIN_GROUP(pwm2_b), 2609 SH_PFC_PIN_GROUP(pwm2_c), 2610 SH_PFC_PIN_GROUP(pwm3_a), 2611 SH_PFC_PIN_GROUP(pwm3_b), 2612 SH_PFC_PIN_GROUP(pwm3_c), 2613 SH_PFC_PIN_GROUP(pwm4), 2614 2615 SH_PFC_PIN_GROUP(qspi0_ctrl), 2616 BUS_DATA_PIN_GROUP(qspi0_data, 2), 2617 BUS_DATA_PIN_GROUP(qspi0_data, 4), 2618 SH_PFC_PIN_GROUP(qspi1_ctrl), 2619 BUS_DATA_PIN_GROUP(qspi1_data, 2), 2620 BUS_DATA_PIN_GROUP(qspi1_data, 4), 2621 2622 SH_PFC_PIN_GROUP(scif0_data), 2623 SH_PFC_PIN_GROUP(scif0_clk), 2624 SH_PFC_PIN_GROUP(scif0_ctrl), 2625 SH_PFC_PIN_GROUP(scif1_data_a), 2626 SH_PFC_PIN_GROUP(scif1_clk_a), 2627 SH_PFC_PIN_GROUP(scif1_ctrl_a), 2628 SH_PFC_PIN_GROUP(scif1_data_b), 2629 SH_PFC_PIN_GROUP(scif1_clk_b), 2630 SH_PFC_PIN_GROUP(scif1_ctrl_b), 2631 SH_PFC_PIN_GROUP(scif3_data_a), 2632 SH_PFC_PIN_GROUP(scif3_clk_a), 2633 SH_PFC_PIN_GROUP(scif3_ctrl_a), 2634 SH_PFC_PIN_GROUP(scif3_data_b), 2635 SH_PFC_PIN_GROUP(scif3_clk_b), 2636 SH_PFC_PIN_GROUP(scif3_ctrl_b), 2637 SH_PFC_PIN_GROUP(scif4_data), 2638 SH_PFC_PIN_GROUP(scif4_clk), 2639 SH_PFC_PIN_GROUP(scif4_ctrl), 2640 SH_PFC_PIN_GROUP(scif_clk), 2641 SH_PFC_PIN_GROUP(scif_clk2), 2642 2643 SH_PFC_PIN_GROUP(ssi_data), 2644 SH_PFC_PIN_GROUP(ssi_ctrl), 2645 2646 SH_PFC_PIN_GROUP(tpu_to0_a), 2647 SH_PFC_PIN_GROUP(tpu_to0_b), 2648 SH_PFC_PIN_GROUP(tpu_to1_a), 2649 SH_PFC_PIN_GROUP(tpu_to1_b), 2650 SH_PFC_PIN_GROUP(tpu_to2_a), 2651 SH_PFC_PIN_GROUP(tpu_to2_b), 2652 SH_PFC_PIN_GROUP(tpu_to3_a), 2653 SH_PFC_PIN_GROUP(tpu_to3_b), 2654 }; 2655 2656 static const char * const audio_clk_groups[] = { 2657 "audio_clkin", 2658 "audio_clkout", 2659 }; 2660 2661 static const char * const avb0_groups[] = { 2662 "avb0_link", 2663 "avb0_magic", 2664 "avb0_phy_int", 2665 "avb0_mdio", 2666 "avb0_mii", 2667 "avb0_rgmii", 2668 "avb0_txcrefclk", 2669 "avb0_avtp_pps", 2670 "avb0_avtp_capture", 2671 "avb0_avtp_match", 2672 }; 2673 2674 static const char * const avb1_groups[] = { 2675 "avb1_link", 2676 "avb1_magic", 2677 "avb1_phy_int", 2678 "avb1_mdio", 2679 "avb1_mii", 2680 "avb1_rgmii", 2681 "avb1_txcrefclk", 2682 "avb1_avtp_pps", 2683 "avb1_avtp_capture", 2684 "avb1_avtp_match", 2685 }; 2686 2687 static const char * const avb2_groups[] = { 2688 "avb2_link", 2689 "avb2_magic", 2690 "avb2_phy_int", 2691 "avb2_mdio", 2692 "avb2_rgmii", 2693 "avb2_txcrefclk", 2694 "avb2_avtp_pps", 2695 "avb2_avtp_capture", 2696 "avb2_avtp_match", 2697 }; 2698 2699 static const char * const canfd0_groups[] = { 2700 "canfd0_data", 2701 }; 2702 2703 static const char * const canfd1_groups[] = { 2704 "canfd1_data", 2705 }; 2706 2707 static const char * const canfd2_groups[] = { 2708 "canfd2_data", 2709 }; 2710 2711 static const char * const canfd3_groups[] = { 2712 "canfd3_data", 2713 }; 2714 2715 static const char * const can_clk_groups[] = { 2716 "can_clk", 2717 }; 2718 2719 static const char * const hscif0_groups[] = { 2720 "hscif0_data", 2721 "hscif0_clk", 2722 "hscif0_ctrl", 2723 }; 2724 2725 static const char * const hscif1_groups[] = { 2726 "hscif1_data_a", 2727 "hscif1_clk_a", 2728 "hscif1_ctrl_a", 2729 "hscif1_data_b", 2730 "hscif1_clk_b", 2731 "hscif1_ctrl_b", 2732 }; 2733 2734 static const char * const hscif2_groups[] = { 2735 "hscif2_data", 2736 "hscif2_clk", 2737 "hscif2_ctrl", 2738 }; 2739 2740 static const char * const hscif3_groups[] = { 2741 "hscif3_data_a", 2742 "hscif3_clk_a", 2743 "hscif3_ctrl_a", 2744 "hscif3_data_b", 2745 "hscif3_clk_b", 2746 "hscif3_ctrl_b", 2747 }; 2748 2749 static const char * const i2c0_groups[] = { 2750 "i2c0", 2751 }; 2752 2753 static const char * const i2c1_groups[] = { 2754 "i2c1", 2755 }; 2756 2757 static const char * const i2c2_groups[] = { 2758 "i2c2", 2759 }; 2760 2761 static const char * const i2c3_groups[] = { 2762 "i2c3", 2763 }; 2764 2765 static const char * const intc_ex_groups[] = { 2766 "intc_ex_irq0_a", 2767 "intc_ex_irq0_b", 2768 "intc_ex_irq1_a", 2769 "intc_ex_irq1_b", 2770 "intc_ex_irq2_a", 2771 "intc_ex_irq2_b", 2772 "intc_ex_irq3_a", 2773 "intc_ex_irq3_b", 2774 "intc_ex_irq4_a", 2775 "intc_ex_irq4_b", 2776 "intc_ex_irq5", 2777 }; 2778 2779 static const char * const mmc_groups[] = { 2780 "mmc_data1", 2781 "mmc_data4", 2782 "mmc_data8", 2783 "mmc_ctrl", 2784 "mmc_cd", 2785 "mmc_wp", 2786 "mmc_ds", 2787 }; 2788 2789 static const char * const msiof0_groups[] = { 2790 "msiof0_clk", 2791 "msiof0_sync", 2792 "msiof0_ss1", 2793 "msiof0_ss2", 2794 "msiof0_txd", 2795 "msiof0_rxd", 2796 }; 2797 2798 static const char * const msiof1_groups[] = { 2799 "msiof1_clk", 2800 "msiof1_sync", 2801 "msiof1_ss1", 2802 "msiof1_ss2", 2803 "msiof1_txd", 2804 "msiof1_rxd", 2805 }; 2806 2807 static const char * const msiof2_groups[] = { 2808 "msiof2_clk", 2809 "msiof2_sync", 2810 "msiof2_ss1", 2811 "msiof2_ss2", 2812 "msiof2_txd", 2813 "msiof2_rxd", 2814 }; 2815 2816 static const char * const msiof3_groups[] = { 2817 "msiof3_clk", 2818 "msiof3_sync", 2819 "msiof3_ss1", 2820 "msiof3_ss2", 2821 "msiof3_txd", 2822 "msiof3_rxd", 2823 }; 2824 2825 static const char * const msiof4_groups[] = { 2826 "msiof4_clk", 2827 "msiof4_sync", 2828 "msiof4_ss1", 2829 "msiof4_ss2", 2830 "msiof4_txd", 2831 "msiof4_rxd", 2832 }; 2833 2834 static const char * const msiof5_groups[] = { 2835 "msiof5_clk", 2836 "msiof5_sync", 2837 "msiof5_ss1", 2838 "msiof5_ss2", 2839 "msiof5_txd", 2840 "msiof5_rxd", 2841 }; 2842 2843 static const char * const pcie_groups[] = { 2844 "pcie0_clkreq_n", 2845 }; 2846 2847 static const char * const pwm0_groups[] = { 2848 "pwm0_a", 2849 "pwm0_b", 2850 }; 2851 2852 static const char * const pwm1_groups[] = { 2853 "pwm1_a", 2854 "pwm1_b", 2855 "pwm1_c", 2856 }; 2857 2858 static const char * const pwm2_groups[] = { 2859 "pwm2_a", 2860 "pwm2_b", 2861 "pwm2_c", 2862 }; 2863 2864 static const char * const pwm3_groups[] = { 2865 "pwm3_a", 2866 "pwm3_b", 2867 "pwm3_c", 2868 }; 2869 2870 static const char * const pwm4_groups[] = { 2871 "pwm4", 2872 }; 2873 2874 static const char * const qspi0_groups[] = { 2875 "qspi0_ctrl", 2876 "qspi0_data2", 2877 "qspi0_data4", 2878 }; 2879 2880 static const char * const qspi1_groups[] = { 2881 "qspi1_ctrl", 2882 "qspi1_data2", 2883 "qspi1_data4", 2884 }; 2885 2886 static const char * const scif0_groups[] = { 2887 "scif0_data", 2888 "scif0_clk", 2889 "scif0_ctrl", 2890 }; 2891 2892 static const char * const scif1_groups[] = { 2893 "scif1_data_a", 2894 "scif1_clk_a", 2895 "scif1_ctrl_a", 2896 "scif1_data_b", 2897 "scif1_clk_b", 2898 "scif1_ctrl_b", 2899 }; 2900 2901 static const char * const scif3_groups[] = { 2902 "scif3_data_a", 2903 "scif3_clk_a", 2904 "scif3_ctrl_a", 2905 "scif3_data_b", 2906 "scif3_clk_b", 2907 "scif3_ctrl_b", 2908 }; 2909 2910 static const char * const scif4_groups[] = { 2911 "scif4_data", 2912 "scif4_clk", 2913 "scif4_ctrl", 2914 }; 2915 2916 static const char * const scif_clk_groups[] = { 2917 "scif_clk", 2918 }; 2919 2920 static const char * const scif_clk2_groups[] = { 2921 "scif_clk2", 2922 }; 2923 2924 static const char * const ssi_groups[] = { 2925 "ssi_data", 2926 "ssi_ctrl", 2927 }; 2928 2929 static const char * const tpu_groups[] = { 2930 "tpu_to0_a", 2931 "tpu_to0_b", 2932 "tpu_to1_a", 2933 "tpu_to1_b", 2934 "tpu_to2_a", 2935 "tpu_to2_b", 2936 "tpu_to3_a", 2937 "tpu_to3_b", 2938 }; 2939 2940 static const struct sh_pfc_function pinmux_functions[] = { 2941 SH_PFC_FUNCTION(audio_clk), 2942 2943 SH_PFC_FUNCTION(avb0), 2944 SH_PFC_FUNCTION(avb1), 2945 SH_PFC_FUNCTION(avb2), 2946 2947 SH_PFC_FUNCTION(canfd0), 2948 SH_PFC_FUNCTION(canfd1), 2949 SH_PFC_FUNCTION(canfd2), 2950 SH_PFC_FUNCTION(canfd3), 2951 SH_PFC_FUNCTION(can_clk), 2952 2953 SH_PFC_FUNCTION(hscif0), 2954 SH_PFC_FUNCTION(hscif1), 2955 SH_PFC_FUNCTION(hscif2), 2956 SH_PFC_FUNCTION(hscif3), 2957 2958 SH_PFC_FUNCTION(i2c0), 2959 SH_PFC_FUNCTION(i2c1), 2960 SH_PFC_FUNCTION(i2c2), 2961 SH_PFC_FUNCTION(i2c3), 2962 2963 SH_PFC_FUNCTION(intc_ex), 2964 2965 SH_PFC_FUNCTION(mmc), 2966 2967 SH_PFC_FUNCTION(msiof0), 2968 SH_PFC_FUNCTION(msiof1), 2969 SH_PFC_FUNCTION(msiof2), 2970 SH_PFC_FUNCTION(msiof3), 2971 SH_PFC_FUNCTION(msiof4), 2972 SH_PFC_FUNCTION(msiof5), 2973 2974 SH_PFC_FUNCTION(pcie), 2975 2976 SH_PFC_FUNCTION(pwm0), 2977 SH_PFC_FUNCTION(pwm1), 2978 SH_PFC_FUNCTION(pwm2), 2979 SH_PFC_FUNCTION(pwm3), 2980 SH_PFC_FUNCTION(pwm4), 2981 2982 SH_PFC_FUNCTION(qspi0), 2983 SH_PFC_FUNCTION(qspi1), 2984 2985 SH_PFC_FUNCTION(scif0), 2986 SH_PFC_FUNCTION(scif1), 2987 SH_PFC_FUNCTION(scif3), 2988 SH_PFC_FUNCTION(scif4), 2989 SH_PFC_FUNCTION(scif_clk), 2990 SH_PFC_FUNCTION(scif_clk2), 2991 2992 SH_PFC_FUNCTION(ssi), 2993 2994 SH_PFC_FUNCTION(tpu), 2995 }; 2996 2997 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2998 #define F_(x, y) FN_##y 2999 #define FM(x) FN_##x 3000 { PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32, 3001 GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3002 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3003 GROUP( 3004 /* GP0_31_19 RESERVED */ 3005 GP_0_18_FN, GPSR0_18, 3006 GP_0_17_FN, GPSR0_17, 3007 GP_0_16_FN, GPSR0_16, 3008 GP_0_15_FN, GPSR0_15, 3009 GP_0_14_FN, GPSR0_14, 3010 GP_0_13_FN, GPSR0_13, 3011 GP_0_12_FN, GPSR0_12, 3012 GP_0_11_FN, GPSR0_11, 3013 GP_0_10_FN, GPSR0_10, 3014 GP_0_9_FN, GPSR0_9, 3015 GP_0_8_FN, GPSR0_8, 3016 GP_0_7_FN, GPSR0_7, 3017 GP_0_6_FN, GPSR0_6, 3018 GP_0_5_FN, GPSR0_5, 3019 GP_0_4_FN, GPSR0_4, 3020 GP_0_3_FN, GPSR0_3, 3021 GP_0_2_FN, GPSR0_2, 3022 GP_0_1_FN, GPSR0_1, 3023 GP_0_0_FN, GPSR0_0, )) 3024 }, 3025 { PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP( 3026 0, 0, 3027 0, 0, 3028 GP_1_29_FN, GPSR1_29, 3029 GP_1_28_FN, GPSR1_28, 3030 GP_1_27_FN, GPSR1_27, 3031 GP_1_26_FN, GPSR1_26, 3032 GP_1_25_FN, GPSR1_25, 3033 GP_1_24_FN, GPSR1_24, 3034 GP_1_23_FN, GPSR1_23, 3035 GP_1_22_FN, GPSR1_22, 3036 GP_1_21_FN, GPSR1_21, 3037 GP_1_20_FN, GPSR1_20, 3038 GP_1_19_FN, GPSR1_19, 3039 GP_1_18_FN, GPSR1_18, 3040 GP_1_17_FN, GPSR1_17, 3041 GP_1_16_FN, GPSR1_16, 3042 GP_1_15_FN, GPSR1_15, 3043 GP_1_14_FN, GPSR1_14, 3044 GP_1_13_FN, GPSR1_13, 3045 GP_1_12_FN, GPSR1_12, 3046 GP_1_11_FN, GPSR1_11, 3047 GP_1_10_FN, GPSR1_10, 3048 GP_1_9_FN, GPSR1_9, 3049 GP_1_8_FN, GPSR1_8, 3050 GP_1_7_FN, GPSR1_7, 3051 GP_1_6_FN, GPSR1_6, 3052 GP_1_5_FN, GPSR1_5, 3053 GP_1_4_FN, GPSR1_4, 3054 GP_1_3_FN, GPSR1_3, 3055 GP_1_2_FN, GPSR1_2, 3056 GP_1_1_FN, GPSR1_1, 3057 GP_1_0_FN, GPSR1_0, )) 3058 }, 3059 { PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32, 3060 GROUP(-12, 1, -1, 1, -1, 1, 1, 1, 1, 1, 1, 3061 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3062 GROUP( 3063 /* GP2_31_20 RESERVED */ 3064 GP_2_19_FN, GPSR2_19, 3065 /* GP2_18 RESERVED */ 3066 GP_2_17_FN, GPSR2_17, 3067 /* GP2_16 RESERVED */ 3068 GP_2_15_FN, GPSR2_15, 3069 GP_2_14_FN, GPSR2_14, 3070 GP_2_13_FN, GPSR2_13, 3071 GP_2_12_FN, GPSR2_12, 3072 GP_2_11_FN, GPSR2_11, 3073 GP_2_10_FN, GPSR2_10, 3074 GP_2_9_FN, GPSR2_9, 3075 GP_2_8_FN, GPSR2_8, 3076 GP_2_7_FN, GPSR2_7, 3077 GP_2_6_FN, GPSR2_6, 3078 GP_2_5_FN, GPSR2_5, 3079 GP_2_4_FN, GPSR2_4, 3080 GP_2_3_FN, GPSR2_3, 3081 GP_2_2_FN, GPSR2_2, 3082 GP_2_1_FN, GPSR2_1, 3083 GP_2_0_FN, GPSR2_0, )) 3084 }, 3085 { PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP( 3086 GP_3_31_FN, GPSR3_31, 3087 GP_3_30_FN, GPSR3_30, 3088 GP_3_29_FN, GPSR3_29, 3089 GP_3_28_FN, GPSR3_28, 3090 GP_3_27_FN, GPSR3_27, 3091 GP_3_26_FN, GPSR3_26, 3092 GP_3_25_FN, GPSR3_25, 3093 GP_3_24_FN, GPSR3_24, 3094 GP_3_23_FN, GPSR3_23, 3095 GP_3_22_FN, GPSR3_22, 3096 GP_3_21_FN, GPSR3_21, 3097 GP_3_20_FN, GPSR3_20, 3098 GP_3_19_FN, GPSR3_19, 3099 GP_3_18_FN, GPSR3_18, 3100 GP_3_17_FN, GPSR3_17, 3101 GP_3_16_FN, GPSR3_16, 3102 GP_3_15_FN, GPSR3_15, 3103 GP_3_14_FN, GPSR3_14, 3104 GP_3_13_FN, GPSR3_13, 3105 GP_3_12_FN, GPSR3_12, 3106 GP_3_11_FN, GPSR3_11, 3107 GP_3_10_FN, GPSR3_10, 3108 GP_3_9_FN, GPSR3_9, 3109 GP_3_8_FN, GPSR3_8, 3110 GP_3_7_FN, GPSR3_7, 3111 GP_3_6_FN, GPSR3_6, 3112 GP_3_5_FN, GPSR3_5, 3113 GP_3_4_FN, GPSR3_4, 3114 GP_3_3_FN, GPSR3_3, 3115 GP_3_2_FN, GPSR3_2, 3116 GP_3_1_FN, GPSR3_1, 3117 GP_3_0_FN, GPSR3_0, )) 3118 }, 3119 { PINMUX_CFG_REG_VAR("GPSR4", 0xE6060040, 32, 3120 GROUP(-7, 1, 1, -1, 1, -5, 1, 1, 1, 1, 1, 3121 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3122 GROUP( 3123 /* GP4_31_25 RESERVED */ 3124 GP_4_24_FN, GPSR4_24, 3125 GP_4_23_FN, GPSR4_23, 3126 /* GP4_22 RESERVED */ 3127 GP_4_21_FN, GPSR4_21, 3128 /* GP4_20_16 RESERVED */ 3129 GP_4_15_FN, GPSR4_15, 3130 GP_4_14_FN, GPSR4_14, 3131 GP_4_13_FN, GPSR4_13, 3132 GP_4_12_FN, GPSR4_12, 3133 GP_4_11_FN, GPSR4_11, 3134 GP_4_10_FN, GPSR4_10, 3135 GP_4_9_FN, GPSR4_9, 3136 GP_4_8_FN, GPSR4_8, 3137 GP_4_7_FN, GPSR4_7, 3138 GP_4_6_FN, GPSR4_6, 3139 GP_4_5_FN, GPSR4_5, 3140 GP_4_4_FN, GPSR4_4, 3141 GP_4_3_FN, GPSR4_3, 3142 GP_4_2_FN, GPSR4_2, 3143 GP_4_1_FN, GPSR4_1, 3144 GP_4_0_FN, GPSR4_0, )) 3145 }, 3146 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32, 3147 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3148 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3149 GROUP( 3150 /* GP5_31_21 RESERVED */ 3151 GP_5_20_FN, GPSR5_20, 3152 GP_5_19_FN, GPSR5_19, 3153 GP_5_18_FN, GPSR5_18, 3154 GP_5_17_FN, GPSR5_17, 3155 GP_5_16_FN, GPSR5_16, 3156 GP_5_15_FN, GPSR5_15, 3157 GP_5_14_FN, GPSR5_14, 3158 GP_5_13_FN, GPSR5_13, 3159 GP_5_12_FN, GPSR5_12, 3160 GP_5_11_FN, GPSR5_11, 3161 GP_5_10_FN, GPSR5_10, 3162 GP_5_9_FN, GPSR5_9, 3163 GP_5_8_FN, GPSR5_8, 3164 GP_5_7_FN, GPSR5_7, 3165 GP_5_6_FN, GPSR5_6, 3166 GP_5_5_FN, GPSR5_5, 3167 GP_5_4_FN, GPSR5_4, 3168 GP_5_3_FN, GPSR5_3, 3169 GP_5_2_FN, GPSR5_2, 3170 GP_5_1_FN, GPSR5_1, 3171 GP_5_0_FN, GPSR5_0, )) 3172 }, 3173 { PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32, 3174 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3175 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3176 GROUP( 3177 /* GP6_31_21 RESERVED */ 3178 GP_6_20_FN, GPSR6_20, 3179 GP_6_19_FN, GPSR6_19, 3180 GP_6_18_FN, GPSR6_18, 3181 GP_6_17_FN, GPSR6_17, 3182 GP_6_16_FN, GPSR6_16, 3183 GP_6_15_FN, GPSR6_15, 3184 GP_6_14_FN, GPSR6_14, 3185 GP_6_13_FN, GPSR6_13, 3186 GP_6_12_FN, GPSR6_12, 3187 GP_6_11_FN, GPSR6_11, 3188 GP_6_10_FN, GPSR6_10, 3189 GP_6_9_FN, GPSR6_9, 3190 GP_6_8_FN, GPSR6_8, 3191 GP_6_7_FN, GPSR6_7, 3192 GP_6_6_FN, GPSR6_6, 3193 GP_6_5_FN, GPSR6_5, 3194 GP_6_4_FN, GPSR6_4, 3195 GP_6_3_FN, GPSR6_3, 3196 GP_6_2_FN, GPSR6_2, 3197 GP_6_1_FN, GPSR6_1, 3198 GP_6_0_FN, GPSR6_0, )) 3199 }, 3200 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32, 3201 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3202 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3203 GROUP( 3204 /* GP7_31_21 RESERVED */ 3205 GP_7_20_FN, GPSR7_20, 3206 GP_7_19_FN, GPSR7_19, 3207 GP_7_18_FN, GPSR7_18, 3208 GP_7_17_FN, GPSR7_17, 3209 GP_7_16_FN, GPSR7_16, 3210 GP_7_15_FN, GPSR7_15, 3211 GP_7_14_FN, GPSR7_14, 3212 GP_7_13_FN, GPSR7_13, 3213 GP_7_12_FN, GPSR7_12, 3214 GP_7_11_FN, GPSR7_11, 3215 GP_7_10_FN, GPSR7_10, 3216 GP_7_9_FN, GPSR7_9, 3217 GP_7_8_FN, GPSR7_8, 3218 GP_7_7_FN, GPSR7_7, 3219 GP_7_6_FN, GPSR7_6, 3220 GP_7_5_FN, GPSR7_5, 3221 GP_7_4_FN, GPSR7_4, 3222 GP_7_3_FN, GPSR7_3, 3223 GP_7_2_FN, GPSR7_2, 3224 GP_7_1_FN, GPSR7_1, 3225 GP_7_0_FN, GPSR7_0, )) 3226 }, 3227 #undef F_ 3228 #undef FM 3229 3230 #define F_(x, y) x, 3231 #define FM(x) FN_##x, 3232 { PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP( 3233 IP0SR0_31_28 3234 IP0SR0_27_24 3235 IP0SR0_23_20 3236 IP0SR0_19_16 3237 IP0SR0_15_12 3238 IP0SR0_11_8 3239 IP0SR0_7_4 3240 IP0SR0_3_0)) 3241 }, 3242 { PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP( 3243 IP1SR0_31_28 3244 IP1SR0_27_24 3245 IP1SR0_23_20 3246 IP1SR0_19_16 3247 IP1SR0_15_12 3248 IP1SR0_11_8 3249 IP1SR0_7_4 3250 IP1SR0_3_0)) 3251 }, 3252 { PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32, 3253 GROUP(-20, 4, 4, 4), 3254 GROUP( 3255 /* IP2SR0_31_12 RESERVED */ 3256 IP2SR0_11_8 3257 IP2SR0_7_4 3258 IP2SR0_3_0)) 3259 }, 3260 { PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP( 3261 IP0SR1_31_28 3262 IP0SR1_27_24 3263 IP0SR1_23_20 3264 IP0SR1_19_16 3265 IP0SR1_15_12 3266 IP0SR1_11_8 3267 IP0SR1_7_4 3268 IP0SR1_3_0)) 3269 }, 3270 { PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP( 3271 IP1SR1_31_28 3272 IP1SR1_27_24 3273 IP1SR1_23_20 3274 IP1SR1_19_16 3275 IP1SR1_15_12 3276 IP1SR1_11_8 3277 IP1SR1_7_4 3278 IP1SR1_3_0)) 3279 }, 3280 { PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP( 3281 IP2SR1_31_28 3282 IP2SR1_27_24 3283 IP2SR1_23_20 3284 IP2SR1_19_16 3285 IP2SR1_15_12 3286 IP2SR1_11_8 3287 IP2SR1_7_4 3288 IP2SR1_3_0)) 3289 }, 3290 { PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32, 3291 GROUP(-8, 4, 4, 4, 4, 4, 4), 3292 GROUP( 3293 /* IP3SR1_31_24 RESERVED */ 3294 IP3SR1_23_20 3295 IP3SR1_19_16 3296 IP3SR1_15_12 3297 IP3SR1_11_8 3298 IP3SR1_7_4 3299 IP3SR1_3_0)) 3300 }, 3301 { PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP( 3302 IP0SR2_31_28 3303 IP0SR2_27_24 3304 IP0SR2_23_20 3305 IP0SR2_19_16 3306 IP0SR2_15_12 3307 IP0SR2_11_8 3308 IP0SR2_7_4 3309 IP0SR2_3_0)) 3310 }, 3311 { PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP( 3312 IP1SR2_31_28 3313 IP1SR2_27_24 3314 IP1SR2_23_20 3315 IP1SR2_19_16 3316 IP1SR2_15_12 3317 IP1SR2_11_8 3318 IP1SR2_7_4 3319 IP1SR2_3_0)) 3320 }, 3321 { PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32, 3322 GROUP(-16, 4, -4, 4, -4), 3323 GROUP( 3324 /* IP2SR2_31_16 RESERVED */ 3325 IP2SR2_15_12 3326 /* IP2SR2_11_8 RESERVED */ 3327 IP2SR2_7_4 3328 /* IP2SR2_3_0 RESERVED */)) 3329 }, 3330 { PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP( 3331 IP0SR3_31_28 3332 IP0SR3_27_24 3333 IP0SR3_23_20 3334 IP0SR3_19_16 3335 IP0SR3_15_12 3336 IP0SR3_11_8 3337 IP0SR3_7_4 3338 IP0SR3_3_0)) 3339 }, 3340 { PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP( 3341 IP1SR3_31_28 3342 IP1SR3_27_24 3343 IP1SR3_23_20 3344 IP1SR3_19_16 3345 IP1SR3_15_12 3346 IP1SR3_11_8 3347 IP1SR3_7_4 3348 IP1SR3_3_0)) 3349 }, 3350 { PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP( 3351 IP2SR3_31_28 3352 IP2SR3_27_24 3353 IP2SR3_23_20 3354 IP2SR3_19_16 3355 IP2SR3_15_12 3356 IP2SR3_11_8 3357 IP2SR3_7_4 3358 IP2SR3_3_0)) 3359 }, 3360 { PINMUX_CFG_REG("IP3SR3", 0xE605886C, 32, 4, GROUP( 3361 IP3SR3_31_28 3362 IP3SR3_27_24 3363 IP3SR3_23_20 3364 IP3SR3_19_16 3365 IP3SR3_15_12 3366 IP3SR3_11_8 3367 IP3SR3_7_4 3368 IP3SR3_3_0)) 3369 }, 3370 { PINMUX_CFG_REG("IP0SR4", 0xE6060060, 32, 4, GROUP( 3371 IP0SR4_31_28 3372 IP0SR4_27_24 3373 IP0SR4_23_20 3374 IP0SR4_19_16 3375 IP0SR4_15_12 3376 IP0SR4_11_8 3377 IP0SR4_7_4 3378 IP0SR4_3_0)) 3379 }, 3380 { PINMUX_CFG_REG("IP1SR4", 0xE6060064, 32, 4, GROUP( 3381 IP1SR4_31_28 3382 IP1SR4_27_24 3383 IP1SR4_23_20 3384 IP1SR4_19_16 3385 IP1SR4_15_12 3386 IP1SR4_11_8 3387 IP1SR4_7_4 3388 IP1SR4_3_0)) 3389 }, 3390 { PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32, 3391 GROUP(4, -4, 4, -20), 3392 GROUP( 3393 IP2SR4_31_28 3394 /* IP2SR4_27_24 RESERVED */ 3395 IP2SR4_23_20 3396 /* IP2SR4_19_0 RESERVED */)) 3397 }, 3398 { PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32, 3399 GROUP(-28, 4), 3400 GROUP( 3401 /* IP3SR4_31_4 RESERVED */ 3402 IP3SR4_3_0)) 3403 }, 3404 { PINMUX_CFG_REG("IP0SR5", 0xE6060860, 32, 4, GROUP( 3405 IP0SR5_31_28 3406 IP0SR5_27_24 3407 IP0SR5_23_20 3408 IP0SR5_19_16 3409 IP0SR5_15_12 3410 IP0SR5_11_8 3411 IP0SR5_7_4 3412 IP0SR5_3_0)) 3413 }, 3414 { PINMUX_CFG_REG("IP1SR5", 0xE6060864, 32, 4, GROUP( 3415 IP1SR5_31_28 3416 IP1SR5_27_24 3417 IP1SR5_23_20 3418 IP1SR5_19_16 3419 IP1SR5_15_12 3420 IP1SR5_11_8 3421 IP1SR5_7_4 3422 IP1SR5_3_0)) 3423 }, 3424 { PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32, 3425 GROUP(-12, 4, 4, 4, 4, 4), 3426 GROUP( 3427 /* IP2SR5_31_20 RESERVED */ 3428 IP2SR5_19_16 3429 IP2SR5_15_12 3430 IP2SR5_11_8 3431 IP2SR5_7_4 3432 IP2SR5_3_0)) 3433 }, 3434 { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP( 3435 IP0SR6_31_28 3436 IP0SR6_27_24 3437 IP0SR6_23_20 3438 IP0SR6_19_16 3439 IP0SR6_15_12 3440 IP0SR6_11_8 3441 IP0SR6_7_4 3442 IP0SR6_3_0)) 3443 }, 3444 { PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP( 3445 IP1SR6_31_28 3446 IP1SR6_27_24 3447 IP1SR6_23_20 3448 IP1SR6_19_16 3449 IP1SR6_15_12 3450 IP1SR6_11_8 3451 IP1SR6_7_4 3452 IP1SR6_3_0)) 3453 }, 3454 { PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32, 3455 GROUP(-12, 4, 4, 4, 4, 4), 3456 GROUP( 3457 /* IP2SR6_31_20 RESERVED */ 3458 IP2SR6_19_16 3459 IP2SR6_15_12 3460 IP2SR6_11_8 3461 IP2SR6_7_4 3462 IP2SR6_3_0)) 3463 }, 3464 { PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP( 3465 IP0SR7_31_28 3466 IP0SR7_27_24 3467 IP0SR7_23_20 3468 IP0SR7_19_16 3469 IP0SR7_15_12 3470 IP0SR7_11_8 3471 IP0SR7_7_4 3472 IP0SR7_3_0)) 3473 }, 3474 { PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP( 3475 IP1SR7_31_28 3476 IP1SR7_27_24 3477 IP1SR7_23_20 3478 IP1SR7_19_16 3479 IP1SR7_15_12 3480 IP1SR7_11_8 3481 IP1SR7_7_4 3482 IP1SR7_3_0)) 3483 }, 3484 { PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32, 3485 GROUP(-12, 4, 4, 4, 4, 4), 3486 GROUP( 3487 /* IP2SR7_31_20 RESERVED */ 3488 IP2SR7_19_16 3489 IP2SR7_15_12 3490 IP2SR7_11_8 3491 IP2SR7_7_4 3492 IP2SR7_3_0)) 3493 }, 3494 #undef F_ 3495 #undef FM 3496 3497 #define F_(x, y) x, 3498 #define FM(x) FN_##x, 3499 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE6060100, 32, 3500 GROUP(-24, 1, 1, 1, 1, 1, 1, 1, 1), 3501 GROUP( 3502 /* RESERVED 31-8 */ 3503 MOD_SEL4_7 3504 MOD_SEL4_6 3505 MOD_SEL4_5 3506 MOD_SEL4_4 3507 MOD_SEL4_3 3508 MOD_SEL4_2 3509 MOD_SEL4_1 3510 MOD_SEL4_0)) 3511 }, 3512 { }, 3513 }; 3514 3515 static const struct pinmux_drive_reg pinmux_drive_regs[] = { 3516 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) { 3517 { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */ 3518 { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */ 3519 { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */ 3520 { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */ 3521 { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */ 3522 { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */ 3523 { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */ 3524 { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */ 3525 } }, 3526 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) { 3527 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */ 3528 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */ 3529 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */ 3530 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */ 3531 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */ 3532 { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */ 3533 { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */ 3534 { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */ 3535 } }, 3536 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) { 3537 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */ 3538 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */ 3539 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */ 3540 } }, 3541 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) { 3542 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */ 3543 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */ 3544 { RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */ 3545 { RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */ 3546 { RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */ 3547 { RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */ 3548 { RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */ 3549 { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */ 3550 } }, 3551 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) { 3552 { RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */ 3553 { RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */ 3554 { RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */ 3555 { RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */ 3556 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */ 3557 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */ 3558 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */ 3559 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */ 3560 } }, 3561 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) { 3562 { RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */ 3563 { RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */ 3564 { RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */ 3565 { RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */ 3566 { RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */ 3567 { RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */ 3568 { RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */ 3569 { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */ 3570 } }, 3571 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) { 3572 { RCAR_GP_PIN(1, 29), 20, 2 }, /* ERROROUTC_N */ 3573 { RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */ 3574 { RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */ 3575 { RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */ 3576 { RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */ 3577 { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */ 3578 } }, 3579 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) { 3580 { RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */ 3581 { RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */ 3582 { RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */ 3583 { RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */ 3584 { RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */ 3585 { RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */ 3586 { RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */ 3587 { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */ 3588 } }, 3589 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) { 3590 { RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */ 3591 { RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */ 3592 { RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */ 3593 { RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */ 3594 { RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */ 3595 { RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */ 3596 { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */ 3597 { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */ 3598 } }, 3599 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) { 3600 { RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD1_RX */ 3601 { RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD1_TX */ 3602 } }, 3603 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) { 3604 { RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */ 3605 { RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */ 3606 { RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */ 3607 { RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */ 3608 { RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */ 3609 { RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */ 3610 { RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */ 3611 { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */ 3612 } }, 3613 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) { 3614 { RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */ 3615 { RCAR_GP_PIN(3, 14), 24, 2 }, /* PWM2 */ 3616 { RCAR_GP_PIN(3, 13), 20, 2 }, /* PWM1 */ 3617 { RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */ 3618 { RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */ 3619 { RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */ 3620 { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/ 3621 { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */ 3622 } }, 3623 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) { 3624 { RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */ 3625 { RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */ 3626 { RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */ 3627 { RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */ 3628 { RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */ 3629 { RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */ 3630 { RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */ 3631 { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */ 3632 } }, 3633 { PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) { 3634 { RCAR_GP_PIN(3, 31), 28, 2 }, /* TCLK4 */ 3635 { RCAR_GP_PIN(3, 30), 24, 2 }, /* TCLK3 */ 3636 { RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */ 3637 { RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */ 3638 { RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */ 3639 { RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */ 3640 { RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */ 3641 { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */ 3642 } }, 3643 { PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) { 3644 { RCAR_GP_PIN(4, 7), 28, 3 }, /* SDA3 */ 3645 { RCAR_GP_PIN(4, 6), 24, 3 }, /* SCL3 */ 3646 { RCAR_GP_PIN(4, 5), 20, 3 }, /* SDA2 */ 3647 { RCAR_GP_PIN(4, 4), 16, 3 }, /* SCL2 */ 3648 { RCAR_GP_PIN(4, 3), 12, 3 }, /* SDA1 */ 3649 { RCAR_GP_PIN(4, 2), 8, 3 }, /* SCL1 */ 3650 { RCAR_GP_PIN(4, 1), 4, 3 }, /* SDA0 */ 3651 { RCAR_GP_PIN(4, 0), 0, 3 }, /* SCL0 */ 3652 } }, 3653 { PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) { 3654 { RCAR_GP_PIN(4, 15), 28, 3 }, /* PWM4 */ 3655 { RCAR_GP_PIN(4, 14), 24, 3 }, /* PWM3 */ 3656 { RCAR_GP_PIN(4, 13), 20, 3 }, /* HSCK2 */ 3657 { RCAR_GP_PIN(4, 12), 16, 3 }, /* HCTS2_N */ 3658 { RCAR_GP_PIN(4, 11), 12, 3 }, /* SCIF_CLK2 */ 3659 { RCAR_GP_PIN(4, 10), 8, 3 }, /* HRTS2_N */ 3660 { RCAR_GP_PIN(4, 9), 4, 3 }, /* HTX2 */ 3661 { RCAR_GP_PIN(4, 8), 0, 3 }, /* HRX2 */ 3662 } }, 3663 { PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) { 3664 { RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */ 3665 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */ 3666 } }, 3667 { PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) { 3668 { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */ 3669 } }, 3670 { PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) { 3671 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */ 3672 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */ 3673 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */ 3674 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */ 3675 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */ 3676 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */ 3677 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */ 3678 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */ 3679 } }, 3680 { PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) { 3681 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */ 3682 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */ 3683 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */ 3684 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */ 3685 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */ 3686 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */ 3687 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */ 3688 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */ 3689 } }, 3690 { PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) { 3691 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */ 3692 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */ 3693 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */ 3694 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */ 3695 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */ 3696 } }, 3697 { PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) { 3698 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */ 3699 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */ 3700 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */ 3701 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */ 3702 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */ 3703 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */ 3704 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */ 3705 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */ 3706 } }, 3707 { PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) { 3708 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */ 3709 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */ 3710 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */ 3711 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */ 3712 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */ 3713 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */ 3714 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */ 3715 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */ 3716 } }, 3717 { PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) { 3718 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */ 3719 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */ 3720 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */ 3721 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */ 3722 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */ 3723 } }, 3724 { PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) { 3725 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */ 3726 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */ 3727 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */ 3728 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */ 3729 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */ 3730 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */ 3731 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */ 3732 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */ 3733 } }, 3734 { PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) { 3735 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */ 3736 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */ 3737 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */ 3738 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */ 3739 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */ 3740 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */ 3741 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */ 3742 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */ 3743 } }, 3744 { PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) { 3745 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */ 3746 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */ 3747 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */ 3748 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */ 3749 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */ 3750 } }, 3751 { }, 3752 }; 3753 3754 enum ioctrl_regs { 3755 POC0, 3756 POC1, 3757 POC3, 3758 POC4, 3759 POC5, 3760 POC6, 3761 POC7, 3762 }; 3763 3764 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 3765 [POC0] = { 0xE60500A0, }, 3766 [POC1] = { 0xE60508A0, }, 3767 [POC3] = { 0xE60588A0, }, 3768 [POC4] = { 0xE60600A0, }, 3769 [POC5] = { 0xE60608A0, }, 3770 [POC6] = { 0xE60610A0, }, 3771 [POC7] = { 0xE60618A0, }, 3772 { /* sentinel */ }, 3773 }; 3774 3775 static int r8a779h0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) 3776 { 3777 int bit = pin & 0x1f; 3778 3779 switch (pin) { 3780 case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18): 3781 *pocctrl = pinmux_ioctrl_regs[POC0].reg; 3782 return bit; 3783 3784 case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 28): 3785 *pocctrl = pinmux_ioctrl_regs[POC1].reg; 3786 return bit; 3787 3788 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12): 3789 *pocctrl = pinmux_ioctrl_regs[POC3].reg; 3790 return bit; 3791 3792 case RCAR_GP_PIN(4, 0) ... RCAR_GP_PIN(4, 13): 3793 *pocctrl = pinmux_ioctrl_regs[POC4].reg; 3794 return bit; 3795 3796 case PIN_VDDQ_AVB2: 3797 *pocctrl = pinmux_ioctrl_regs[POC5].reg; 3798 return 0; 3799 3800 case PIN_VDDQ_AVB1: 3801 *pocctrl = pinmux_ioctrl_regs[POC6].reg; 3802 return 0; 3803 3804 case PIN_VDDQ_AVB0: 3805 *pocctrl = pinmux_ioctrl_regs[POC7].reg; 3806 return 0; 3807 3808 default: 3809 return -EINVAL; 3810 } 3811 } 3812 3813 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 3814 { PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) { 3815 [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */ 3816 [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */ 3817 [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */ 3818 [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */ 3819 [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */ 3820 [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */ 3821 [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */ 3822 [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */ 3823 [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */ 3824 [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */ 3825 [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */ 3826 [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */ 3827 [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */ 3828 [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */ 3829 [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */ 3830 [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */ 3831 [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */ 3832 [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */ 3833 [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */ 3834 [19] = SH_PFC_PIN_NONE, 3835 [20] = SH_PFC_PIN_NONE, 3836 [21] = SH_PFC_PIN_NONE, 3837 [22] = SH_PFC_PIN_NONE, 3838 [23] = SH_PFC_PIN_NONE, 3839 [24] = SH_PFC_PIN_NONE, 3840 [25] = SH_PFC_PIN_NONE, 3841 [26] = SH_PFC_PIN_NONE, 3842 [27] = SH_PFC_PIN_NONE, 3843 [28] = SH_PFC_PIN_NONE, 3844 [29] = SH_PFC_PIN_NONE, 3845 [30] = SH_PFC_PIN_NONE, 3846 [31] = SH_PFC_PIN_NONE, 3847 } }, 3848 { PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) { 3849 [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */ 3850 [ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */ 3851 [ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */ 3852 [ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */ 3853 [ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */ 3854 [ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */ 3855 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */ 3856 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */ 3857 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */ 3858 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */ 3859 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */ 3860 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */ 3861 [12] = RCAR_GP_PIN(1, 12), /* HTX0 */ 3862 [13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */ 3863 [14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */ 3864 [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */ 3865 [16] = RCAR_GP_PIN(1, 16), /* HRX0 */ 3866 [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */ 3867 [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */ 3868 [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */ 3869 [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */ 3870 [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */ 3871 [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */ 3872 [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */ 3873 [24] = RCAR_GP_PIN(1, 24), /* HRX3 */ 3874 [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */ 3875 [26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */ 3876 [27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */ 3877 [28] = RCAR_GP_PIN(1, 28), /* HTX3 */ 3878 [29] = RCAR_GP_PIN(1, 29), /* ERROROUTC_N */ 3879 [30] = SH_PFC_PIN_NONE, 3880 [31] = SH_PFC_PIN_NONE, 3881 } }, 3882 { PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) { 3883 [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */ 3884 [ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */ 3885 [ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */ 3886 [ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */ 3887 [ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */ 3888 [ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */ 3889 [ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */ 3890 [ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */ 3891 [ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */ 3892 [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */ 3893 [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */ 3894 [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */ 3895 [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */ 3896 [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */ 3897 [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */ 3898 [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */ 3899 [16] = SH_PFC_PIN_NONE, 3900 [17] = RCAR_GP_PIN(2, 17), /* CANFD1_TX */ 3901 [18] = SH_PFC_PIN_NONE, 3902 [19] = RCAR_GP_PIN(2, 19), /* CANFD1_RX */ 3903 [20] = SH_PFC_PIN_NONE, 3904 [21] = SH_PFC_PIN_NONE, 3905 [22] = SH_PFC_PIN_NONE, 3906 [23] = SH_PFC_PIN_NONE, 3907 [24] = SH_PFC_PIN_NONE, 3908 [25] = SH_PFC_PIN_NONE, 3909 [26] = SH_PFC_PIN_NONE, 3910 [27] = SH_PFC_PIN_NONE, 3911 [28] = SH_PFC_PIN_NONE, 3912 [29] = SH_PFC_PIN_NONE, 3913 [30] = SH_PFC_PIN_NONE, 3914 [31] = SH_PFC_PIN_NONE, 3915 } }, 3916 { PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) { 3917 [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */ 3918 [ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */ 3919 [ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */ 3920 [ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */ 3921 [ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */ 3922 [ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */ 3923 [ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */ 3924 [ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */ 3925 [ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */ 3926 [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */ 3927 [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */ 3928 [11] = RCAR_GP_PIN(3, 11), /* SD_CD */ 3929 [12] = RCAR_GP_PIN(3, 12), /* SD_WP */ 3930 [13] = RCAR_GP_PIN(3, 13), /* PWM1 */ 3931 [14] = RCAR_GP_PIN(3, 14), /* PWM2 */ 3932 [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */ 3933 [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */ 3934 [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */ 3935 [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */ 3936 [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */ 3937 [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */ 3938 [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */ 3939 [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */ 3940 [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */ 3941 [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */ 3942 [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */ 3943 [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */ 3944 [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */ 3945 [28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */ 3946 [29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */ 3947 [30] = RCAR_GP_PIN(3, 30), /* TCLK3 */ 3948 [31] = RCAR_GP_PIN(3, 31), /* TCLK4 */ 3949 } }, 3950 { PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) { 3951 [ 0] = RCAR_GP_PIN(4, 0), /* SCL0 */ 3952 [ 1] = RCAR_GP_PIN(4, 1), /* SDA0 */ 3953 [ 2] = RCAR_GP_PIN(4, 2), /* SCL1 */ 3954 [ 3] = RCAR_GP_PIN(4, 3), /* SDA1 */ 3955 [ 4] = RCAR_GP_PIN(4, 4), /* SCL2 */ 3956 [ 5] = RCAR_GP_PIN(4, 5), /* SDA2 */ 3957 [ 6] = RCAR_GP_PIN(4, 6), /* SCL3 */ 3958 [ 7] = RCAR_GP_PIN(4, 7), /* SDA3 */ 3959 [ 8] = RCAR_GP_PIN(4, 8), /* HRX2 */ 3960 [ 9] = RCAR_GP_PIN(4, 9), /* HTX2 */ 3961 [10] = RCAR_GP_PIN(4, 10), /* HRTS2_N */ 3962 [11] = RCAR_GP_PIN(4, 11), /* SCIF_CLK2 */ 3963 [12] = RCAR_GP_PIN(4, 12), /* HCTS2_N */ 3964 [13] = RCAR_GP_PIN(4, 13), /* HSCK2 */ 3965 [14] = RCAR_GP_PIN(4, 14), /* PWM3 */ 3966 [15] = RCAR_GP_PIN(4, 15), /* PWM4 */ 3967 [16] = SH_PFC_PIN_NONE, 3968 [17] = SH_PFC_PIN_NONE, 3969 [18] = SH_PFC_PIN_NONE, 3970 [19] = SH_PFC_PIN_NONE, 3971 [20] = SH_PFC_PIN_NONE, 3972 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */ 3973 [22] = SH_PFC_PIN_NONE, 3974 [23] = RCAR_GP_PIN(4, 23), /* AVS0 */ 3975 [24] = RCAR_GP_PIN(4, 24), /* AVS1 */ 3976 [25] = SH_PFC_PIN_NONE, 3977 [26] = SH_PFC_PIN_NONE, 3978 [27] = SH_PFC_PIN_NONE, 3979 [28] = SH_PFC_PIN_NONE, 3980 [29] = SH_PFC_PIN_NONE, 3981 [30] = SH_PFC_PIN_NONE, 3982 [31] = SH_PFC_PIN_NONE, 3983 } }, 3984 { PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) { 3985 [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */ 3986 [ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */ 3987 [ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */ 3988 [ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */ 3989 [ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */ 3990 [ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */ 3991 [ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */ 3992 [ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */ 3993 [ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */ 3994 [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */ 3995 [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */ 3996 [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */ 3997 [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */ 3998 [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */ 3999 [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */ 4000 [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */ 4001 [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */ 4002 [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */ 4003 [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */ 4004 [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */ 4005 [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */ 4006 [21] = SH_PFC_PIN_NONE, 4007 [22] = SH_PFC_PIN_NONE, 4008 [23] = SH_PFC_PIN_NONE, 4009 [24] = SH_PFC_PIN_NONE, 4010 [25] = SH_PFC_PIN_NONE, 4011 [26] = SH_PFC_PIN_NONE, 4012 [27] = SH_PFC_PIN_NONE, 4013 [28] = SH_PFC_PIN_NONE, 4014 [29] = SH_PFC_PIN_NONE, 4015 [30] = SH_PFC_PIN_NONE, 4016 [31] = SH_PFC_PIN_NONE, 4017 } }, 4018 { PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) { 4019 [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */ 4020 [ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */ 4021 [ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */ 4022 [ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */ 4023 [ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */ 4024 [ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */ 4025 [ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */ 4026 [ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */ 4027 [ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */ 4028 [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */ 4029 [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */ 4030 [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */ 4031 [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */ 4032 [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */ 4033 [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/ 4034 [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */ 4035 [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */ 4036 [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */ 4037 [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */ 4038 [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */ 4039 [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */ 4040 [21] = SH_PFC_PIN_NONE, 4041 [22] = SH_PFC_PIN_NONE, 4042 [23] = SH_PFC_PIN_NONE, 4043 [24] = SH_PFC_PIN_NONE, 4044 [25] = SH_PFC_PIN_NONE, 4045 [26] = SH_PFC_PIN_NONE, 4046 [27] = SH_PFC_PIN_NONE, 4047 [28] = SH_PFC_PIN_NONE, 4048 [29] = SH_PFC_PIN_NONE, 4049 [30] = SH_PFC_PIN_NONE, 4050 [31] = SH_PFC_PIN_NONE, 4051 } }, 4052 { PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) { 4053 [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */ 4054 [ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */ 4055 [ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */ 4056 [ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */ 4057 [ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */ 4058 [ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */ 4059 [ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */ 4060 [ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */ 4061 [ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */ 4062 [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */ 4063 [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */ 4064 [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */ 4065 [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */ 4066 [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */ 4067 [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */ 4068 [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */ 4069 [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */ 4070 [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */ 4071 [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */ 4072 [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */ 4073 [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */ 4074 [21] = SH_PFC_PIN_NONE, 4075 [22] = SH_PFC_PIN_NONE, 4076 [23] = SH_PFC_PIN_NONE, 4077 [24] = SH_PFC_PIN_NONE, 4078 [25] = SH_PFC_PIN_NONE, 4079 [26] = SH_PFC_PIN_NONE, 4080 [27] = SH_PFC_PIN_NONE, 4081 [28] = SH_PFC_PIN_NONE, 4082 [29] = SH_PFC_PIN_NONE, 4083 [30] = SH_PFC_PIN_NONE, 4084 [31] = SH_PFC_PIN_NONE, 4085 } }, 4086 { /* sentinel */ }, 4087 }; 4088 4089 static const struct sh_pfc_soc_operations r8a779h0_pin_ops = { 4090 .pin_to_pocctrl = r8a779h0_pin_to_pocctrl, 4091 .get_bias = rcar_pinmux_get_bias, 4092 .set_bias = rcar_pinmux_set_bias, 4093 }; 4094 4095 const struct sh_pfc_soc_info r8a779h0_pinmux_info = { 4096 .name = "r8a779h0_pfc", 4097 .ops = &r8a779h0_pin_ops, 4098 .unlock_reg = 0x1ff, /* PMMRn mask */ 4099 4100 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 4101 4102 .pins = pinmux_pins, 4103 .nr_pins = ARRAY_SIZE(pinmux_pins), 4104 .groups = pinmux_groups, 4105 .nr_groups = ARRAY_SIZE(pinmux_groups), 4106 .functions = pinmux_functions, 4107 .nr_functions = ARRAY_SIZE(pinmux_functions), 4108 4109 .cfg_regs = pinmux_config_regs, 4110 .drive_regs = pinmux_drive_regs, 4111 .bias_regs = pinmux_bias_regs, 4112 .ioctrl_regs = pinmux_ioctrl_regs, 4113 4114 .pinmux_data = pinmux_data, 4115 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 4116 }; 4117