1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A779H0 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 * 7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c 8 */ 9 10 #include <linux/errno.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 14 #include "sh_pfc.h" 15 16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 17 18 #define CPU_ALL_GP(fn, sfx) \ 19 PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 20 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 21 PORT_GP_CFG_1(1, 29, fn, sfx, CFG_FLAGS), \ 22 PORT_GP_CFG_16(2, fn, sfx, CFG_FLAGS), \ 23 PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \ 24 PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \ 25 PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 26 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 27 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 28 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_1(3, 16, fn, sfx, CFG_FLAGS), \ 30 PORT_GP_CFG_1(3, 17, fn, sfx, CFG_FLAGS), \ 31 PORT_GP_CFG_1(3, 18, fn, sfx, CFG_FLAGS), \ 32 PORT_GP_CFG_1(3, 19, fn, sfx, CFG_FLAGS), \ 33 PORT_GP_CFG_1(3, 20, fn, sfx, CFG_FLAGS), \ 34 PORT_GP_CFG_1(3, 21, fn, sfx, CFG_FLAGS), \ 35 PORT_GP_CFG_1(3, 22, fn, sfx, CFG_FLAGS), \ 36 PORT_GP_CFG_1(3, 23, fn, sfx, CFG_FLAGS), \ 37 PORT_GP_CFG_1(3, 24, fn, sfx, CFG_FLAGS), \ 38 PORT_GP_CFG_1(3, 25, fn, sfx, CFG_FLAGS), \ 39 PORT_GP_CFG_1(3, 26, fn, sfx, CFG_FLAGS), \ 40 PORT_GP_CFG_1(3, 27, fn, sfx, CFG_FLAGS), \ 41 PORT_GP_CFG_1(3, 28, fn, sfx, CFG_FLAGS), \ 42 PORT_GP_CFG_1(3, 29, fn, sfx, CFG_FLAGS), \ 43 PORT_GP_CFG_1(3, 30, fn, sfx, CFG_FLAGS), \ 44 PORT_GP_CFG_1(3, 31, fn, sfx, CFG_FLAGS), \ 45 PORT_GP_CFG_14(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 46 PORT_GP_CFG_1(4, 14, fn, sfx, CFG_FLAGS), \ 47 PORT_GP_CFG_1(4, 15, fn, sfx, CFG_FLAGS), \ 48 PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS), \ 49 PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS), \ 50 PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS), \ 51 PORT_GP_CFG_21(5, fn, sfx, CFG_FLAGS), \ 52 PORT_GP_CFG_21(6, fn, sfx, CFG_FLAGS), \ 53 PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS) 54 55 #define CPU_ALL_NOGP(fn) \ 56 PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \ 57 PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \ 58 PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25) 59 60 /* 61 * F_() : just information 62 * FM() : macro for FN_xxx / xxx_MARK 63 */ 64 65 /* GPSR0 */ 66 #define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8) 67 #define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4) 68 #define GPSR0_16 F_(MSIOF2_TXD, IP2SR0_3_0) 69 #define GPSR0_15 F_(MSIOF2_SYNC, IP1SR0_31_28) 70 #define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24) 71 #define GPSR0_13 F_(MSIOF2_SS2, IP1SR0_23_20) 72 #define GPSR0_12 F_(MSIOF5_RXD, IP1SR0_19_16) 73 #define GPSR0_11 F_(MSIOF5_SCK, IP1SR0_15_12) 74 #define GPSR0_10 F_(MSIOF5_TXD, IP1SR0_11_8) 75 #define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4) 76 #define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0) 77 #define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28) 78 #define GPSR0_6 F_(IRQ0_A, IP0SR0_27_24) 79 #define GPSR0_5 F_(IRQ1_A, IP0SR0_23_20) 80 #define GPSR0_4 F_(IRQ2_A, IP0SR0_19_16) 81 #define GPSR0_3 F_(IRQ3_A, IP0SR0_15_12) 82 #define GPSR0_2 F_(GP0_02, IP0SR0_11_8) 83 #define GPSR0_1 F_(GP0_01, IP0SR0_7_4) 84 #define GPSR0_0 F_(GP0_00, IP0SR0_3_0) 85 86 /* GPSR1 */ 87 #define GPSR1_29 F_(ERROROUTC_N_A, IP3SR1_23_20) 88 #define GPSR1_28 F_(HTX3, IP3SR1_19_16) 89 #define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12) 90 #define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8) 91 #define GPSR1_25 F_(HSCK3, IP3SR1_7_4) 92 #define GPSR1_24 F_(HRX3, IP3SR1_3_0) 93 #define GPSR1_23 F_(GP1_23, IP2SR1_31_28) 94 #define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24) 95 #define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20) 96 #define GPSR1_20 F_(SSI_SD, IP2SR1_19_16) 97 #define GPSR1_19 F_(SSI_WS, IP2SR1_15_12) 98 #define GPSR1_18 F_(SSI_SCK, IP2SR1_11_8) 99 #define GPSR1_17 F_(SCIF_CLK, IP2SR1_7_4) 100 #define GPSR1_16 F_(HRX0, IP2SR1_3_0) 101 #define GPSR1_15 F_(HSCK0, IP1SR1_31_28) 102 #define GPSR1_14 F_(HRTS0_N, IP1SR1_27_24) 103 #define GPSR1_13 F_(HCTS0_N, IP1SR1_23_20) 104 #define GPSR1_12 F_(HTX0, IP1SR1_19_16) 105 #define GPSR1_11 F_(MSIOF0_RXD, IP1SR1_15_12) 106 #define GPSR1_10 F_(MSIOF0_SCK, IP1SR1_11_8) 107 #define GPSR1_9 F_(MSIOF0_TXD, IP1SR1_7_4) 108 #define GPSR1_8 F_(MSIOF0_SYNC, IP1SR1_3_0) 109 #define GPSR1_7 F_(MSIOF0_SS1, IP0SR1_31_28) 110 #define GPSR1_6 F_(MSIOF0_SS2, IP0SR1_27_24) 111 #define GPSR1_5 F_(MSIOF1_RXD, IP0SR1_23_20) 112 #define GPSR1_4 F_(MSIOF1_TXD, IP0SR1_19_16) 113 #define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12) 114 #define GPSR1_2 F_(MSIOF1_SYNC, IP0SR1_11_8) 115 #define GPSR1_1 F_(MSIOF1_SS1, IP0SR1_7_4) 116 #define GPSR1_0 F_(MSIOF1_SS2, IP0SR1_3_0) 117 118 /* GPSR2 */ 119 #define GPSR2_19 F_(CANFD1_RX, IP2SR2_15_12) 120 #define GPSR2_17 F_(CANFD1_TX, IP2SR2_7_4) 121 #define GPSR2_15 F_(CANFD3_RX, IP1SR2_31_28) 122 #define GPSR2_14 F_(CANFD3_TX, IP1SR2_27_24) 123 #define GPSR2_13 F_(CANFD2_RX, IP1SR2_23_20) 124 #define GPSR2_12 F_(CANFD2_TX, IP1SR2_19_16) 125 #define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12) 126 #define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8) 127 #define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4) 128 #define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0) 129 #define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28) 130 #define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24) 131 #define GPSR2_5 F_(FXR_TXENB_N_A, IP0SR2_23_20) 132 #define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16) 133 #define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12) 134 #define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8) 135 #define GPSR2_1 F_(FXR_TXENA_N_A, IP0SR2_7_4) 136 #define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0) 137 138 /* GPSR3 */ 139 #define GPSR3_31 F_(TCLK4, IP3SR3_31_28) 140 #define GPSR3_30 F_(TCLK3, IP3SR3_27_24) 141 #define GPSR3_29 F_(RPC_INT_N, IP3SR3_23_20) 142 #define GPSR3_28 F_(RPC_WP_N, IP3SR3_19_16) 143 #define GPSR3_27 F_(RPC_RESET_N, IP3SR3_15_12) 144 #define GPSR3_26 F_(QSPI1_IO3, IP3SR3_11_8) 145 #define GPSR3_25 F_(QSPI1_SSL, IP3SR3_7_4) 146 #define GPSR3_24 F_(QSPI1_IO2, IP3SR3_3_0) 147 #define GPSR3_23 F_(QSPI1_MISO_IO1, IP2SR3_31_28) 148 #define GPSR3_22 F_(QSPI1_SPCLK, IP2SR3_27_24) 149 #define GPSR3_21 F_(QSPI1_MOSI_IO0, IP2SR3_23_20) 150 #define GPSR3_20 F_(QSPI0_SPCLK, IP2SR3_19_16) 151 #define GPSR3_19 F_(QSPI0_MOSI_IO0, IP2SR3_15_12) 152 #define GPSR3_18 F_(QSPI0_MISO_IO1, IP2SR3_11_8) 153 #define GPSR3_17 F_(QSPI0_IO2, IP2SR3_7_4) 154 #define GPSR3_16 F_(QSPI0_IO3, IP2SR3_3_0) 155 #define GPSR3_15 F_(QSPI0_SSL, IP1SR3_31_28) 156 #define GPSR3_14 F_(PWM2, IP1SR3_27_24) 157 #define GPSR3_13 F_(PWM1, IP1SR3_23_20) 158 #define GPSR3_12 F_(SD_WP, IP1SR3_19_16) 159 #define GPSR3_11 F_(SD_CD, IP1SR3_15_12) 160 #define GPSR3_10 F_(MMC_SD_CMD, IP1SR3_11_8) 161 #define GPSR3_9 F_(MMC_D6, IP1SR3_7_4) 162 #define GPSR3_8 F_(MMC_D7, IP1SR3_3_0) 163 #define GPSR3_7 F_(MMC_D4, IP0SR3_31_28) 164 #define GPSR3_6 F_(MMC_D5, IP0SR3_27_24) 165 #define GPSR3_5 F_(MMC_SD_D3, IP0SR3_23_20) 166 #define GPSR3_4 F_(MMC_DS, IP0SR3_19_16) 167 #define GPSR3_3 F_(MMC_SD_CLK, IP0SR3_15_12) 168 #define GPSR3_2 F_(MMC_SD_D2, IP0SR3_11_8) 169 #define GPSR3_1 F_(MMC_SD_D0, IP0SR3_7_4) 170 #define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0) 171 172 /* GPSR4 */ 173 #define GPSR4_24 F_(AVS1, IP3SR4_3_0) 174 #define GPSR4_23 F_(AVS0, IP2SR4_31_28) 175 #define GPSR4_21 F_(PCIE0_CLKREQ_N, IP2SR4_23_20) 176 #define GPSR4_15 F_(PWM4, IP1SR4_31_28) 177 #define GPSR4_14 F_(PWM3, IP1SR4_27_24) 178 #define GPSR4_13 F_(HSCK2, IP1SR4_23_20) 179 #define GPSR4_12 F_(HCTS2_N, IP1SR4_19_16) 180 #define GPSR4_11 F_(SCIF_CLK2, IP1SR4_15_12) 181 #define GPSR4_10 F_(HRTS2_N, IP1SR4_11_8) 182 #define GPSR4_9 F_(HTX2, IP1SR4_7_4) 183 #define GPSR4_8 F_(HRX2, IP1SR4_3_0) 184 #define GPSR4_7 F_(SDA3, IP0SR4_31_28) 185 #define GPSR4_6 F_(SCL3, IP0SR4_27_24) 186 #define GPSR4_5 F_(SDA2, IP0SR4_23_20) 187 #define GPSR4_4 F_(SCL2, IP0SR4_19_16) 188 #define GPSR4_3 F_(SDA1, IP0SR4_15_12) 189 #define GPSR4_2 F_(SCL1, IP0SR4_11_8) 190 #define GPSR4_1 F_(SDA0, IP0SR4_7_4) 191 #define GPSR4_0 F_(SCL0, IP0SR4_3_0) 192 193 /* GPSR 5 */ 194 #define GPSR5_20 F_(AVB2_RX_CTL, IP2SR5_19_16) 195 #define GPSR5_19 F_(AVB2_TX_CTL, IP2SR5_15_12) 196 #define GPSR5_18 F_(AVB2_RXC, IP2SR5_11_8) 197 #define GPSR5_17 F_(AVB2_RD0, IP2SR5_7_4) 198 #define GPSR5_16 F_(AVB2_TXC, IP2SR5_3_0) 199 #define GPSR5_15 F_(AVB2_TD0, IP1SR5_31_28) 200 #define GPSR5_14 F_(AVB2_RD1, IP1SR5_27_24) 201 #define GPSR5_13 F_(AVB2_RD2, IP1SR5_23_20) 202 #define GPSR5_12 F_(AVB2_TD1, IP1SR5_19_16) 203 #define GPSR5_11 F_(AVB2_TD2, IP1SR5_15_12) 204 #define GPSR5_10 F_(AVB2_MDIO, IP1SR5_11_8) 205 #define GPSR5_9 F_(AVB2_RD3, IP1SR5_7_4) 206 #define GPSR5_8 F_(AVB2_TD3, IP1SR5_3_0) 207 #define GPSR5_7 F_(AVB2_TXCREFCLK, IP0SR5_31_28) 208 #define GPSR5_6 F_(AVB2_MDC, IP0SR5_27_24) 209 #define GPSR5_5 F_(AVB2_MAGIC, IP0SR5_23_20) 210 #define GPSR5_4 F_(AVB2_PHY_INT, IP0SR5_19_16) 211 #define GPSR5_3 F_(AVB2_LINK, IP0SR5_15_12) 212 #define GPSR5_2 F_(AVB2_AVTP_MATCH, IP0SR5_11_8) 213 #define GPSR5_1 F_(AVB2_AVTP_CAPTURE, IP0SR5_7_4) 214 #define GPSR5_0 F_(AVB2_AVTP_PPS, IP0SR5_3_0) 215 216 /* GPSR 6 */ 217 #define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16) 218 #define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12) 219 #define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8) 220 #define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4) 221 #define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0) 222 #define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28) 223 #define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24) 224 #define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20) 225 #define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16) 226 #define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12) 227 #define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8) 228 #define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4) 229 #define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0) 230 #define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28) 231 #define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24) 232 #define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20) 233 #define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16) 234 #define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12) 235 #define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8) 236 #define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4) 237 #define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0) 238 239 /* GPSR7 */ 240 #define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16) 241 #define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12) 242 #define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8) 243 #define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4) 244 #define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0) 245 #define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28) 246 #define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24) 247 #define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20) 248 #define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16) 249 #define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12) 250 #define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8) 251 #define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4) 252 #define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0) 253 #define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28) 254 #define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24) 255 #define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20) 256 #define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16) 257 #define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12) 258 #define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8) 259 #define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4) 260 #define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0) 261 262 263 /* SR0 */ 264 /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 265 #define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP0SR0_15_12 FM(IRQ3_A) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP0SR0_19_16 FM(IRQ2_A) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP0SR0_23_20 FM(IRQ1_A) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP0SR0_27_24 FM(IRQ0_A) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 274 /* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 275 #define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276 #define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1_A) FM(IRQ2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 #define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1_A) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 #define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1_A) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 284 /* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 285 #define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N_A) FM(CTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286 #define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N_A) FM(RTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287 #define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1_A) FM(SCK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 288 289 /* SR1 */ 290 /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 291 #define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_B) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_B) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_B) FM(RTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_B) FM(CTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_B) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 #define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299 300 /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 301 #define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_B) FM(CTS1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302 #define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_B) FM(RTS1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303 #define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_B) FM(SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 #define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306 #define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307 #define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 #define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309 310 /* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 311 #define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312 #define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313 #define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314 #define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315 #define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316 #define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317 #define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318 #define IP2SR1_31_28 F_(0, 0) FM(TCLK2_A) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 319 320 /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 321 #define IP3SR1_3_0 FM(HRX3_A) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322 #define IP3SR1_7_4 FM(HSCK3_A) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323 #define IP3SR1_11_8 FM(HRTS3_N_A) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324 #define IP3SR1_15_12 FM(HCTS3_N_A) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325 #define IP3SR1_19_16 FM(HTX3_A) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326 #define IP3SR1_23_20 FM(ERROROUTC_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327 328 /* SR2 */ 329 /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 330 #define IP0SR2_3_0 FM(FXR_TXDA) F_(0, 0) FM(TPU0TO2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331 #define IP0SR2_7_4 FM(FXR_TXENA_N_A) F_(0, 0) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332 #define IP0SR2_11_8 FM(RXDA_EXTFXR) F_(0, 0) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333 #define IP0SR2_15_12 FM(CLK_EXTFXR) F_(0, 0) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334 #define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335 #define IP0SR2_23_20 FM(FXR_TXENB_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336 #define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337 #define IP0SR2_31_28 FM(TPU0TO1_A) F_(0, 0) F_(0, 0) FM(TCLK2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338 339 /* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 340 #define IP1SR2_3_0 FM(TPU0TO0_A) F_(0, 0) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341 #define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 #define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343 #define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344 #define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345 #define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346 #define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347 #define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348 349 /* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 350 #define IP2SR2_7_4 FM(CANFD1_TX) F_(0, 0) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 351 #define IP2SR2_15_12 FM(CANFD1_RX) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 352 353 /* SR3 */ 354 /* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 355 #define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 356 #define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357 #define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358 #define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359 #define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360 #define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361 #define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362 #define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 363 364 /* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 365 #define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 366 #define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 367 #define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 368 #define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 369 #define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 370 #define IP1SR3_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 371 #define IP1SR3_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 372 #define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 373 374 /* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 375 #define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 376 #define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 377 #define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 378 #define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 379 #define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 380 #define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 381 #define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 382 #define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 383 384 /* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 385 #define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 386 #define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 387 #define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 388 #define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 389 #define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 390 #define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 391 #define IP3SR3_27_24 FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 392 #define IP3SR3_31_28 FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 393 394 /* SR4 */ 395 /* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 396 #define IP0SR4_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 397 #define IP0SR4_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 398 #define IP0SR4_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 399 #define IP0SR4_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 400 #define IP0SR4_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 401 #define IP0SR4_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 402 #define IP0SR4_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 403 #define IP0SR4_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 404 405 /* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 406 #define IP1SR4_3_0 FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 407 #define IP1SR4_7_4 FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 408 #define IP1SR4_11_8 FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 409 #define IP1SR4_15_12 FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 410 #define IP1SR4_19_16 FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 411 #define IP1SR4_23_20 FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 412 #define IP1SR4_27_24 FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 413 #define IP1SR4_31_28 FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 414 415 /* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 416 #define IP2SR4_23_20 FM(PCIE0_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 417 #define IP2SR4_31_28 FM(AVS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 418 419 /* IP3SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 420 #define IP3SR4_3_0 FM(AVS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 421 422 /* SR5 */ 423 /* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 424 #define IP0SR5_3_0 FM(AVB2_AVTP_PPS) FM(Ether_GPTP_PPS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 425 #define IP0SR5_7_4 FM(AVB2_AVTP_CAPTURE) FM(Ether_GPTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 426 #define IP0SR5_11_8 FM(AVB2_AVTP_MATCH) FM(Ether_GPTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 427 #define IP0SR5_15_12 FM(AVB2_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 428 #define IP0SR5_19_16 FM(AVB2_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 429 #define IP0SR5_23_20 FM(AVB2_MAGIC) FM(Ether_GPTP_PPS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 430 #define IP0SR5_27_24 FM(AVB2_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 431 #define IP0SR5_31_28 FM(AVB2_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 432 433 /* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 434 #define IP1SR5_3_0 FM(AVB2_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 435 #define IP1SR5_7_4 FM(AVB2_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 436 #define IP1SR5_11_8 FM(AVB2_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 437 #define IP1SR5_15_12 FM(AVB2_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 438 #define IP1SR5_19_16 FM(AVB2_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 439 #define IP1SR5_23_20 FM(AVB2_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 440 #define IP1SR5_27_24 FM(AVB2_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 441 #define IP1SR5_31_28 FM(AVB2_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 442 443 /* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 444 #define IP2SR5_3_0 FM(AVB2_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 445 #define IP2SR5_7_4 FM(AVB2_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 446 #define IP2SR5_11_8 FM(AVB2_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 447 #define IP2SR5_15_12 FM(AVB2_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 448 #define IP2SR5_19_16 FM(AVB2_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 449 450 /* SR6 */ 451 /* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 452 #define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 453 #define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 454 #define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 455 #define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 456 #define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 457 #define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 458 #define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 459 #define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 460 461 /* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 462 #define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 463 #define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 464 #define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 465 #define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 466 #define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 467 #define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 468 #define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 469 #define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 470 471 /* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 472 #define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 473 #define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 474 #define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 475 #define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 476 #define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 477 478 /* SR7 */ 479 /* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 480 #define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 481 #define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 482 #define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 483 #define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 484 #define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 485 #define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 486 #define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 487 #define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 488 489 /* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 490 #define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 491 #define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 492 #define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 493 #define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 494 #define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 495 #define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 496 #define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 497 #define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 498 499 /* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 500 #define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 501 #define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 502 #define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 503 #define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 504 #define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 505 506 #define PINMUX_GPSR \ 507 GPSR3_31 \ 508 GPSR3_30 \ 509 GPSR1_29 GPSR3_29 \ 510 GPSR1_28 GPSR3_28 \ 511 GPSR1_27 GPSR3_27 \ 512 GPSR1_26 GPSR3_26 \ 513 GPSR1_25 GPSR3_25 \ 514 GPSR1_24 GPSR3_24 GPSR4_24 \ 515 GPSR1_23 GPSR3_23 GPSR4_23 \ 516 GPSR1_22 GPSR3_22 \ 517 GPSR1_21 GPSR3_21 GPSR4_21 \ 518 GPSR1_20 GPSR3_20 GPSR5_20 GPSR6_20 GPSR7_20 \ 519 GPSR1_19 GPSR2_19 GPSR3_19 GPSR5_19 GPSR6_19 GPSR7_19 \ 520 GPSR0_18 GPSR1_18 GPSR3_18 GPSR5_18 GPSR6_18 GPSR7_18 \ 521 GPSR0_17 GPSR1_17 GPSR2_17 GPSR3_17 GPSR5_17 GPSR6_17 GPSR7_17 \ 522 GPSR0_16 GPSR1_16 GPSR3_16 GPSR5_16 GPSR6_16 GPSR7_16 \ 523 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 \ 524 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 \ 525 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 \ 526 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 \ 527 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 \ 528 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 \ 529 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 \ 530 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 \ 531 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 \ 532 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 \ 533 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 \ 534 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 \ 535 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ 536 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ 537 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ 538 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 539 540 #define PINMUX_IPSR \ 541 \ 542 FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \ 543 FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \ 544 FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \ 545 FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 \ 546 FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 \ 547 FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \ 548 FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \ 549 FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \ 550 \ 551 FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \ 552 FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \ 553 FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \ 554 FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \ 555 FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \ 556 FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \ 557 FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 \ 558 FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \ 559 \ 560 FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 \ 561 FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \ 562 FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 \ 563 FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \ 564 FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 \ 565 FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 \ 566 FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 \ 567 FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 \ 568 \ 569 FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 FM(IP2SR3_3_0) IP2SR3_3_0 FM(IP3SR3_3_0) IP3SR3_3_0 \ 570 FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 FM(IP2SR3_7_4) IP2SR3_7_4 FM(IP3SR3_7_4) IP3SR3_7_4 \ 571 FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 FM(IP2SR3_11_8) IP2SR3_11_8 FM(IP3SR3_11_8) IP3SR3_11_8 \ 572 FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 FM(IP2SR3_15_12) IP2SR3_15_12 FM(IP3SR3_15_12) IP3SR3_15_12 \ 573 FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 FM(IP2SR3_19_16) IP2SR3_19_16 FM(IP3SR3_19_16) IP3SR3_19_16 \ 574 FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 FM(IP2SR3_23_20) IP2SR3_23_20 FM(IP3SR3_23_20) IP3SR3_23_20 \ 575 FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 FM(IP3SR3_27_24) IP3SR3_27_24 \ 576 FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 FM(IP3SR3_31_28) IP3SR3_31_28 \ 577 \ 578 FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP3SR4_3_0) IP3SR4_3_0 \ 579 FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 \ 580 FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 \ 581 FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 \ 582 FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 \ 583 FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \ 584 FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 \ 585 FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \ 586 \ 587 FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \ 588 FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \ 589 FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \ 590 FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \ 591 FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \ 592 FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \ 593 FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \ 594 FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 \ 595 \ 596 FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \ 597 FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \ 598 FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \ 599 FM(IP0SR6_15_12) IP0SR6_15_12 FM(IP1SR6_15_12) IP1SR6_15_12 FM(IP2SR6_15_12) IP2SR6_15_12 \ 600 FM(IP0SR6_19_16) IP0SR6_19_16 FM(IP1SR6_19_16) IP1SR6_19_16 FM(IP2SR6_19_16) IP2SR6_19_16 \ 601 FM(IP0SR6_23_20) IP0SR6_23_20 FM(IP1SR6_23_20) IP1SR6_23_20 \ 602 FM(IP0SR6_27_24) IP0SR6_27_24 FM(IP1SR6_27_24) IP1SR6_27_24 \ 603 FM(IP0SR6_31_28) IP0SR6_31_28 FM(IP1SR6_31_28) IP1SR6_31_28 \ 604 \ 605 FM(IP0SR7_3_0) IP0SR7_3_0 FM(IP1SR7_3_0) IP1SR7_3_0 FM(IP2SR7_3_0) IP2SR7_3_0 \ 606 FM(IP0SR7_7_4) IP0SR7_7_4 FM(IP1SR7_7_4) IP1SR7_7_4 FM(IP2SR7_7_4) IP2SR7_7_4 \ 607 FM(IP0SR7_11_8) IP0SR7_11_8 FM(IP1SR7_11_8) IP1SR7_11_8 FM(IP2SR7_11_8) IP2SR7_11_8 \ 608 FM(IP0SR7_15_12) IP0SR7_15_12 FM(IP1SR7_15_12) IP1SR7_15_12 FM(IP2SR7_15_12) IP2SR7_15_12 \ 609 FM(IP0SR7_19_16) IP0SR7_19_16 FM(IP1SR7_19_16) IP1SR7_19_16 FM(IP2SR7_19_16) IP2SR7_19_16 \ 610 FM(IP0SR7_23_20) IP0SR7_23_20 FM(IP1SR7_23_20) IP1SR7_23_20 \ 611 FM(IP0SR7_27_24) IP0SR7_27_24 FM(IP1SR7_27_24) IP1SR7_27_24 \ 612 FM(IP0SR7_31_28) IP0SR7_31_28 FM(IP1SR7_31_28) IP1SR7_31_28 \ 613 614 /* MOD_SEL4 */ /* 0 */ /* 1 */ 615 #define MOD_SEL4_7 FM(SEL_SDA3_0) FM(SEL_SDA3_1) 616 #define MOD_SEL4_6 FM(SEL_SCL3_0) FM(SEL_SCL3_1) 617 #define MOD_SEL4_5 FM(SEL_SDA2_0) FM(SEL_SDA2_1) 618 #define MOD_SEL4_4 FM(SEL_SCL2_0) FM(SEL_SCL2_1) 619 #define MOD_SEL4_3 FM(SEL_SDA1_0) FM(SEL_SDA1_1) 620 #define MOD_SEL4_2 FM(SEL_SCL1_0) FM(SEL_SCL1_1) 621 #define MOD_SEL4_1 FM(SEL_SDA0_0) FM(SEL_SDA0_1) 622 #define MOD_SEL4_0 FM(SEL_SCL0_0) FM(SEL_SCL0_1) 623 624 #define PINMUX_MOD_SELS \ 625 \ 626 MOD_SEL4_7 \ 627 MOD_SEL4_6 \ 628 MOD_SEL4_5 \ 629 MOD_SEL4_4 \ 630 MOD_SEL4_3 \ 631 MOD_SEL4_2 \ 632 MOD_SEL4_1 \ 633 MOD_SEL4_0 634 635 enum { 636 PINMUX_RESERVED = 0, 637 638 PINMUX_DATA_BEGIN, 639 GP_ALL(DATA), 640 PINMUX_DATA_END, 641 642 #define F_(x, y) 643 #define FM(x) FN_##x, 644 PINMUX_FUNCTION_BEGIN, 645 GP_ALL(FN), 646 PINMUX_GPSR 647 PINMUX_IPSR 648 PINMUX_MOD_SELS 649 PINMUX_FUNCTION_END, 650 #undef F_ 651 #undef FM 652 653 #define F_(x, y) 654 #define FM(x) x##_MARK, 655 PINMUX_MARK_BEGIN, 656 PINMUX_GPSR 657 PINMUX_IPSR 658 PINMUX_MOD_SELS 659 PINMUX_MARK_END, 660 #undef F_ 661 #undef FM 662 }; 663 664 static const u16 pinmux_data[] = { 665 PINMUX_DATA_GP_ALL(), 666 667 /* IP0SR0 */ 668 PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B), 669 PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_B), 670 671 PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1), 672 673 PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2), 674 675 PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3_A), 676 PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK), 677 678 PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2_A), 679 PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD), 680 681 PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1_A), 682 PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD), 683 684 PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0_A), 685 PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC), 686 687 PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2), 688 689 /* IP1SR0 */ 690 PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF5_SS1), 691 692 PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF5_SYNC), 693 694 PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF5_TXD), 695 696 PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF5_SCK), 697 698 PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD), 699 700 PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2), 701 PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1_A), 702 PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_B), 703 704 PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1), 705 PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1_A), 706 PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1_A), 707 708 PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC), 709 PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1_A), 710 PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1_A), 711 712 /* IP2SR0 */ 713 PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD), 714 PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N_A), 715 PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N_A), 716 717 PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK), 718 PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N_A), 719 PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N_A), 720 721 PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD), 722 PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1_A), 723 PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1_A), 724 725 /* IP0SR1 */ 726 PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2), 727 PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_B), 728 PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3_B), 729 730 PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1), 731 PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_B), 732 PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3_B), 733 734 PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC), 735 PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_B), 736 PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N_B), 737 738 PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK), 739 PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_B), 740 PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N_B), 741 742 PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD), 743 PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_B), 744 PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3_B), 745 746 PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD), 747 748 PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2), 749 PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_B), 750 PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_B), 751 752 PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1), 753 PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_B), 754 PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_B), 755 756 /* IP1SR1 */ 757 PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC), 758 PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_B), 759 PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_B), 760 761 PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD), 762 PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_B), 763 PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_B), 764 765 PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK), 766 PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_B), 767 PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_B), 768 769 PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD), 770 771 PINMUX_IPSR_GPSR(IP1SR1_19_16, HTX0), 772 PINMUX_IPSR_GPSR(IP1SR1_19_16, TX0), 773 774 PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N), 775 PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N), 776 777 PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N), 778 PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N), 779 PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM0_B), 780 781 PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0), 782 PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0), 783 PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A), 784 785 /* IP2SR1 */ 786 PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0), 787 PINMUX_IPSR_GPSR(IP2SR1_3_0, RX0), 788 789 PINMUX_IPSR_GPSR(IP2SR1_7_4, SCIF_CLK), 790 PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A), 791 792 PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK), 793 PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3_B), 794 795 PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS), 796 PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4_B), 797 798 PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD), 799 PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_B), 800 801 PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT), 802 PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_B), 803 804 PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN), 805 PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_C), 806 807 PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2_A), 808 PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1), 809 PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B), 810 811 /* IP3SR1 */ 812 PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3_A), 813 PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A), 814 PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2), 815 816 PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3_A), 817 PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A), 818 PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK), 819 PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_B), 820 821 PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N_A), 822 PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A), 823 PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD), 824 PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_B), 825 826 PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N_A), 827 PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A), 828 PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD), 829 830 PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3_A), 831 PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A), 832 PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC), 833 834 PINMUX_IPSR_GPSR(IP3SR1_23_20, ERROROUTC_N_A), 835 836 /* IP0SR2 */ 837 PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA), 838 PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_B), 839 840 PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N_A), 841 PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_B), 842 843 PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR), 844 PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5), 845 846 PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR), 847 PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B), 848 849 PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR), 850 851 PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N_A), 852 853 PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB), 854 855 PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1_A), 856 PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_C), 857 858 /* IP1SR2 */ 859 PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0_A), 860 PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_B), 861 862 PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK), 863 PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_B), 864 865 PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX), 866 PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B), 867 868 PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX), 869 PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR), 870 871 PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX), 872 PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A), 873 PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_C), 874 875 PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX), 876 PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3_A), 877 PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B), 878 PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_C), 879 880 PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX), 881 PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2_B), 882 883 PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX), 884 PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B), 885 886 /* IP2SR2 */ 887 PINMUX_IPSR_GPSR(IP2SR2_7_4, CANFD1_TX), 888 PINMUX_IPSR_GPSR(IP2SR2_7_4, PWM1_C), 889 890 PINMUX_IPSR_GPSR(IP2SR2_15_12, CANFD1_RX), 891 PINMUX_IPSR_GPSR(IP2SR2_15_12, PWM2_C), 892 893 /* IP0SR3 */ 894 PINMUX_IPSR_GPSR(IP0SR3_3_0, MMC_SD_D1), 895 896 PINMUX_IPSR_GPSR(IP0SR3_7_4, MMC_SD_D0), 897 898 PINMUX_IPSR_GPSR(IP0SR3_11_8, MMC_SD_D2), 899 900 PINMUX_IPSR_GPSR(IP0SR3_15_12, MMC_SD_CLK), 901 902 PINMUX_IPSR_GPSR(IP0SR3_19_16, MMC_DS), 903 904 PINMUX_IPSR_GPSR(IP0SR3_23_20, MMC_SD_D3), 905 906 PINMUX_IPSR_GPSR(IP0SR3_27_24, MMC_D5), 907 908 PINMUX_IPSR_GPSR(IP0SR3_31_28, MMC_D4), 909 910 /* IP1SR3 */ 911 PINMUX_IPSR_GPSR(IP1SR3_3_0, MMC_D7), 912 913 PINMUX_IPSR_GPSR(IP1SR3_7_4, MMC_D6), 914 915 PINMUX_IPSR_GPSR(IP1SR3_11_8, MMC_SD_CMD), 916 917 PINMUX_IPSR_GPSR(IP1SR3_15_12, SD_CD), 918 919 PINMUX_IPSR_GPSR(IP1SR3_19_16, SD_WP), 920 921 PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A), 922 923 PINMUX_IPSR_GPSR(IP1SR3_27_24, PWM2_A), 924 925 PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL), 926 927 /* IP2SR3 */ 928 PINMUX_IPSR_GPSR(IP2SR3_3_0, QSPI0_IO3), 929 930 PINMUX_IPSR_GPSR(IP2SR3_7_4, QSPI0_IO2), 931 932 PINMUX_IPSR_GPSR(IP2SR3_11_8, QSPI0_MISO_IO1), 933 934 PINMUX_IPSR_GPSR(IP2SR3_15_12, QSPI0_MOSI_IO0), 935 936 PINMUX_IPSR_GPSR(IP2SR3_19_16, QSPI0_SPCLK), 937 938 PINMUX_IPSR_GPSR(IP2SR3_23_20, QSPI1_MOSI_IO0), 939 940 PINMUX_IPSR_GPSR(IP2SR3_27_24, QSPI1_SPCLK), 941 942 PINMUX_IPSR_GPSR(IP2SR3_31_28, QSPI1_MISO_IO1), 943 944 /* IP3SR3 */ 945 PINMUX_IPSR_GPSR(IP3SR3_3_0, QSPI1_IO2), 946 947 PINMUX_IPSR_GPSR(IP3SR3_7_4, QSPI1_SSL), 948 949 PINMUX_IPSR_GPSR(IP3SR3_11_8, QSPI1_IO3), 950 951 PINMUX_IPSR_GPSR(IP3SR3_15_12, RPC_RESET_N), 952 953 PINMUX_IPSR_GPSR(IP3SR3_19_16, RPC_WP_N), 954 955 PINMUX_IPSR_GPSR(IP3SR3_23_20, RPC_INT_N), 956 957 PINMUX_IPSR_GPSR(IP3SR3_27_24, TCLK3_A), 958 959 PINMUX_IPSR_GPSR(IP3SR3_31_28, TCLK4_A), 960 961 /* IP0SR4 */ 962 PINMUX_IPSR_MSEL(IP0SR4_3_0, SCL0, SEL_SCL0_0), 963 964 PINMUX_IPSR_MSEL(IP0SR4_7_4, SDA0, SEL_SDA0_0), 965 966 PINMUX_IPSR_MSEL(IP0SR4_11_8, SCL1, SEL_SCL1_0), 967 968 PINMUX_IPSR_MSEL(IP0SR4_15_12, SDA1, SEL_SDA1_0), 969 970 PINMUX_IPSR_MSEL(IP0SR4_19_16, SCL2, SEL_SCL2_0), 971 972 PINMUX_IPSR_MSEL(IP0SR4_23_20, SDA2, SEL_SDA2_0), 973 974 PINMUX_IPSR_MSEL(IP0SR4_27_24, SCL3, SEL_SCL3_0), 975 976 PINMUX_IPSR_MSEL(IP0SR4_31_28, SDA3, SEL_SDA3_0), 977 978 /* IP1SR4 */ 979 PINMUX_IPSR_GPSR(IP1SR4_3_0, HRX2), 980 PINMUX_IPSR_GPSR(IP1SR4_3_0, SCK4), 981 982 PINMUX_IPSR_GPSR(IP1SR4_7_4, HTX2), 983 PINMUX_IPSR_GPSR(IP1SR4_7_4, CTS4_N), 984 985 PINMUX_IPSR_GPSR(IP1SR4_11_8, HRTS2_N), 986 PINMUX_IPSR_GPSR(IP1SR4_11_8, RTS4_N), 987 988 PINMUX_IPSR_GPSR(IP1SR4_15_12, SCIF_CLK2), 989 990 PINMUX_IPSR_GPSR(IP1SR4_19_16, HCTS2_N), 991 PINMUX_IPSR_GPSR(IP1SR4_19_16, TX4), 992 993 PINMUX_IPSR_GPSR(IP1SR4_23_20, HSCK2), 994 PINMUX_IPSR_GPSR(IP1SR4_23_20, RX4), 995 996 PINMUX_IPSR_GPSR(IP1SR4_27_24, PWM3_A), 997 998 PINMUX_IPSR_GPSR(IP1SR4_31_28, PWM4), 999 1000 /* IP2SR4 */ 1001 PINMUX_IPSR_GPSR(IP2SR4_23_20, PCIE0_CLKREQ_N), 1002 1003 PINMUX_IPSR_GPSR(IP2SR4_31_28, AVS0), 1004 1005 /* IP3SR4 */ 1006 PINMUX_IPSR_GPSR(IP3SR4_3_0, AVS1), 1007 1008 /* IP0SR5 */ 1009 PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB2_AVTP_PPS), 1010 PINMUX_IPSR_GPSR(IP0SR5_3_0, Ether_GPTP_PPS0), 1011 1012 PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB2_AVTP_CAPTURE), 1013 PINMUX_IPSR_GPSR(IP0SR5_7_4, Ether_GPTP_CAPTURE), 1014 1015 PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB2_AVTP_MATCH), 1016 PINMUX_IPSR_GPSR(IP0SR5_11_8, Ether_GPTP_MATCH), 1017 1018 PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB2_LINK), 1019 1020 PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB2_PHY_INT), 1021 1022 PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB2_MAGIC), 1023 PINMUX_IPSR_GPSR(IP0SR5_23_20, Ether_GPTP_PPS1), 1024 1025 PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB2_MDC), 1026 1027 PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB2_TXCREFCLK), 1028 1029 /* IP1SR5 */ 1030 PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB2_TD3), 1031 1032 PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB2_RD3), 1033 1034 PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB2_MDIO), 1035 1036 PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB2_TD2), 1037 1038 PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB2_TD1), 1039 1040 PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB2_RD2), 1041 1042 PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB2_RD1), 1043 1044 PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB2_TD0), 1045 1046 /* IP2SR5 */ 1047 PINMUX_IPSR_GPSR(IP2SR5_3_0, AVB2_TXC), 1048 1049 PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB2_RD0), 1050 1051 PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB2_RXC), 1052 1053 PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB2_TX_CTL), 1054 1055 PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB2_RX_CTL), 1056 1057 /* IP0SR6 */ 1058 PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO), 1059 1060 PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC), 1061 1062 PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC), 1063 1064 PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT), 1065 1066 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK), 1067 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER), 1068 1069 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH), 1070 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER), 1071 1072 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC), 1073 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC), 1074 1075 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL), 1076 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN), 1077 1078 /* IP1SR6 */ 1079 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC), 1080 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC), 1081 1082 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL), 1083 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV), 1084 1085 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS), 1086 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL), 1087 1088 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE), 1089 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS), 1090 1091 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1), 1092 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1), 1093 1094 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0), 1095 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0), 1096 1097 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1), 1098 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1), 1099 1100 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0), 1101 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0), 1102 1103 /* IP2SR6 */ 1104 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2), 1105 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2), 1106 1107 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2), 1108 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2), 1109 1110 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3), 1111 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3), 1112 1113 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3), 1114 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3), 1115 1116 PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK), 1117 1118 /* IP0SR7 */ 1119 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS), 1120 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL), 1121 1122 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE), 1123 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS), 1124 1125 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH), 1126 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER), 1127 PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT), 1128 1129 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3), 1130 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3), 1131 1132 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK), 1133 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER), 1134 1135 PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT), 1136 1137 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2), 1138 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2), 1139 1140 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1), 1141 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1), 1142 1143 /* IP1SR7 */ 1144 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3), 1145 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3), 1146 1147 PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK), 1148 1149 PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC), 1150 1151 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0), 1152 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0), 1153 1154 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2), 1155 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2), 1156 1157 PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC), 1158 1159 PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO), 1160 1161 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC), 1162 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC), 1163 1164 /* IP2SR7 */ 1165 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL), 1166 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN), 1167 1168 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1), 1169 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1), 1170 1171 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0), 1172 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0), 1173 1174 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC), 1175 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC), 1176 1177 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL), 1178 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV), 1179 }; 1180 1181 /* 1182 * Pins not associated with a GPIO port. 1183 */ 1184 enum { 1185 GP_ASSIGN_LAST(), 1186 NOGP_ALL(), 1187 }; 1188 1189 static const struct sh_pfc_pin pinmux_pins[] = { 1190 PINMUX_GPIO_GP_ALL(), 1191 PINMUX_NOGP_ALL(), 1192 }; 1193 1194 /* - AUDIO CLOCK ----------------------------------------- */ 1195 static const unsigned int audio_clkin_pins[] = { 1196 /* CLK IN */ 1197 RCAR_GP_PIN(1, 22), 1198 }; 1199 static const unsigned int audio_clkin_mux[] = { 1200 AUDIO_CLKIN_MARK, 1201 }; 1202 static const unsigned int audio_clkout_pins[] = { 1203 /* CLK OUT */ 1204 RCAR_GP_PIN(1, 21), 1205 }; 1206 static const unsigned int audio_clkout_mux[] = { 1207 AUDIO_CLKOUT_MARK, 1208 }; 1209 1210 /* - AVB0 ------------------------------------------------ */ 1211 static const unsigned int avb0_link_pins[] = { 1212 /* AVB0_LINK */ 1213 RCAR_GP_PIN(7, 4), 1214 }; 1215 static const unsigned int avb0_link_mux[] = { 1216 AVB0_LINK_MARK, 1217 }; 1218 static const unsigned int avb0_magic_pins[] = { 1219 /* AVB0_MAGIC */ 1220 RCAR_GP_PIN(7, 10), 1221 }; 1222 static const unsigned int avb0_magic_mux[] = { 1223 AVB0_MAGIC_MARK, 1224 }; 1225 static const unsigned int avb0_phy_int_pins[] = { 1226 /* AVB0_PHY_INT */ 1227 RCAR_GP_PIN(7, 5), 1228 }; 1229 static const unsigned int avb0_phy_int_mux[] = { 1230 AVB0_PHY_INT_MARK, 1231 }; 1232 static const unsigned int avb0_mdio_pins[] = { 1233 /* AVB0_MDC, AVB0_MDIO */ 1234 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14), 1235 }; 1236 static const unsigned int avb0_mdio_mux[] = { 1237 AVB0_MDC_MARK, AVB0_MDIO_MARK, 1238 }; 1239 static const unsigned int avb0_rgmii_pins[] = { 1240 /* 1241 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3, 1242 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3, 1243 */ 1244 RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15), 1245 RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7), 1246 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3), 1247 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19), 1248 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17), 1249 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8), 1250 }; 1251 static const unsigned int avb0_rgmii_mux[] = { 1252 AVB0_TX_CTL_MARK, AVB0_TXC_MARK, 1253 AVB0_TD0_MARK, AVB0_TD1_MARK, 1254 AVB0_TD2_MARK, AVB0_TD3_MARK, 1255 AVB0_RX_CTL_MARK, AVB0_RXC_MARK, 1256 AVB0_RD0_MARK, AVB0_RD1_MARK, 1257 AVB0_RD2_MARK, AVB0_RD3_MARK, 1258 }; 1259 static const unsigned int avb0_txcrefclk_pins[] = { 1260 /* AVB0_TXCREFCLK */ 1261 RCAR_GP_PIN(7, 9), 1262 }; 1263 static const unsigned int avb0_txcrefclk_mux[] = { 1264 AVB0_TXCREFCLK_MARK, 1265 }; 1266 static const unsigned int avb0_avtp_pps_pins[] = { 1267 /* AVB0_AVTP_PPS */ 1268 RCAR_GP_PIN(7, 0), 1269 }; 1270 static const unsigned int avb0_avtp_pps_mux[] = { 1271 AVB0_AVTP_PPS_MARK, 1272 }; 1273 static const unsigned int avb0_avtp_capture_pins[] = { 1274 /* AVB0_AVTP_CAPTURE */ 1275 RCAR_GP_PIN(7, 1), 1276 }; 1277 static const unsigned int avb0_avtp_capture_mux[] = { 1278 AVB0_AVTP_CAPTURE_MARK, 1279 }; 1280 static const unsigned int avb0_avtp_match_pins[] = { 1281 /* AVB0_AVTP_MATCH */ 1282 RCAR_GP_PIN(7, 2), 1283 }; 1284 static const unsigned int avb0_avtp_match_mux[] = { 1285 AVB0_AVTP_MATCH_MARK, 1286 }; 1287 1288 /* - AVB1 ------------------------------------------------ */ 1289 static const unsigned int avb1_link_pins[] = { 1290 /* AVB1_LINK */ 1291 RCAR_GP_PIN(6, 4), 1292 }; 1293 static const unsigned int avb1_link_mux[] = { 1294 AVB1_LINK_MARK, 1295 }; 1296 static const unsigned int avb1_magic_pins[] = { 1297 /* AVB1_MAGIC */ 1298 RCAR_GP_PIN(6, 1), 1299 }; 1300 static const unsigned int avb1_magic_mux[] = { 1301 AVB1_MAGIC_MARK, 1302 }; 1303 static const unsigned int avb1_phy_int_pins[] = { 1304 /* AVB1_PHY_INT */ 1305 RCAR_GP_PIN(6, 3), 1306 }; 1307 static const unsigned int avb1_phy_int_mux[] = { 1308 AVB1_PHY_INT_MARK, 1309 }; 1310 static const unsigned int avb1_mdio_pins[] = { 1311 /* AVB1_MDC, AVB1_MDIO */ 1312 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0), 1313 }; 1314 static const unsigned int avb1_mdio_mux[] = { 1315 AVB1_MDC_MARK, AVB1_MDIO_MARK, 1316 }; 1317 static const unsigned int avb1_rgmii_pins[] = { 1318 /* 1319 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3, 1320 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3, 1321 */ 1322 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 1323 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12), 1324 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18), 1325 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8), 1326 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14), 1327 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19), 1328 }; 1329 static const unsigned int avb1_rgmii_mux[] = { 1330 AVB1_TX_CTL_MARK, AVB1_TXC_MARK, 1331 AVB1_TD0_MARK, AVB1_TD1_MARK, 1332 AVB1_TD2_MARK, AVB1_TD3_MARK, 1333 AVB1_RX_CTL_MARK, AVB1_RXC_MARK, 1334 AVB1_RD0_MARK, AVB1_RD1_MARK, 1335 AVB1_RD2_MARK, AVB1_RD3_MARK, 1336 }; 1337 static const unsigned int avb1_txcrefclk_pins[] = { 1338 /* AVB1_TXCREFCLK */ 1339 RCAR_GP_PIN(6, 20), 1340 }; 1341 static const unsigned int avb1_txcrefclk_mux[] = { 1342 AVB1_TXCREFCLK_MARK, 1343 }; 1344 static const unsigned int avb1_avtp_pps_pins[] = { 1345 /* AVB1_AVTP_PPS */ 1346 RCAR_GP_PIN(6, 10), 1347 }; 1348 static const unsigned int avb1_avtp_pps_mux[] = { 1349 AVB1_AVTP_PPS_MARK, 1350 }; 1351 static const unsigned int avb1_avtp_capture_pins[] = { 1352 /* AVB1_AVTP_CAPTURE */ 1353 RCAR_GP_PIN(6, 11), 1354 }; 1355 static const unsigned int avb1_avtp_capture_mux[] = { 1356 AVB1_AVTP_CAPTURE_MARK, 1357 }; 1358 static const unsigned int avb1_avtp_match_pins[] = { 1359 /* AVB1_AVTP_MATCH */ 1360 RCAR_GP_PIN(6, 5), 1361 }; 1362 static const unsigned int avb1_avtp_match_mux[] = { 1363 AVB1_AVTP_MATCH_MARK, 1364 }; 1365 1366 /* - AVB2 ------------------------------------------------ */ 1367 static const unsigned int avb2_link_pins[] = { 1368 /* AVB2_LINK */ 1369 RCAR_GP_PIN(5, 3), 1370 }; 1371 static const unsigned int avb2_link_mux[] = { 1372 AVB2_LINK_MARK, 1373 }; 1374 static const unsigned int avb2_magic_pins[] = { 1375 /* AVB2_MAGIC */ 1376 RCAR_GP_PIN(5, 5), 1377 }; 1378 static const unsigned int avb2_magic_mux[] = { 1379 AVB2_MAGIC_MARK, 1380 }; 1381 static const unsigned int avb2_phy_int_pins[] = { 1382 /* AVB2_PHY_INT */ 1383 RCAR_GP_PIN(5, 4), 1384 }; 1385 static const unsigned int avb2_phy_int_mux[] = { 1386 AVB2_PHY_INT_MARK, 1387 }; 1388 static const unsigned int avb2_mdio_pins[] = { 1389 /* AVB2_MDC, AVB2_MDIO */ 1390 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10), 1391 }; 1392 static const unsigned int avb2_mdio_mux[] = { 1393 AVB2_MDC_MARK, AVB2_MDIO_MARK, 1394 }; 1395 static const unsigned int avb2_rgmii_pins[] = { 1396 /* 1397 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3, 1398 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3, 1399 */ 1400 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16), 1401 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12), 1402 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8), 1403 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18), 1404 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14), 1405 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9), 1406 }; 1407 static const unsigned int avb2_rgmii_mux[] = { 1408 AVB2_TX_CTL_MARK, AVB2_TXC_MARK, 1409 AVB2_TD0_MARK, AVB2_TD1_MARK, 1410 AVB2_TD2_MARK, AVB2_TD3_MARK, 1411 AVB2_RX_CTL_MARK, AVB2_RXC_MARK, 1412 AVB2_RD0_MARK, AVB2_RD1_MARK, 1413 AVB2_RD2_MARK, AVB2_RD3_MARK, 1414 }; 1415 static const unsigned int avb2_txcrefclk_pins[] = { 1416 /* AVB2_TXCREFCLK */ 1417 RCAR_GP_PIN(5, 7), 1418 }; 1419 static const unsigned int avb2_txcrefclk_mux[] = { 1420 AVB2_TXCREFCLK_MARK, 1421 }; 1422 static const unsigned int avb2_avtp_pps_pins[] = { 1423 /* AVB2_AVTP_PPS */ 1424 RCAR_GP_PIN(5, 0), 1425 }; 1426 static const unsigned int avb2_avtp_pps_mux[] = { 1427 AVB2_AVTP_PPS_MARK, 1428 }; 1429 static const unsigned int avb2_avtp_capture_pins[] = { 1430 /* AVB2_AVTP_CAPTURE */ 1431 RCAR_GP_PIN(5, 1), 1432 }; 1433 static const unsigned int avb2_avtp_capture_mux[] = { 1434 AVB2_AVTP_CAPTURE_MARK, 1435 }; 1436 static const unsigned int avb2_avtp_match_pins[] = { 1437 /* AVB2_AVTP_MATCH */ 1438 RCAR_GP_PIN(5, 2), 1439 }; 1440 static const unsigned int avb2_avtp_match_mux[] = { 1441 AVB2_AVTP_MATCH_MARK, 1442 }; 1443 1444 /* - CANFD0 ----------------------------------------------------------------- */ 1445 static const unsigned int canfd0_data_pins[] = { 1446 /* CANFD0_TX, CANFD0_RX */ 1447 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 1448 }; 1449 static const unsigned int canfd0_data_mux[] = { 1450 CANFD0_TX_MARK, CANFD0_RX_MARK, 1451 }; 1452 1453 /* - CANFD1 ----------------------------------------------------------------- */ 1454 static const unsigned int canfd1_data_pins[] = { 1455 /* CANFD1_TX, CANFD1_RX */ 1456 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 19), 1457 }; 1458 static const unsigned int canfd1_data_mux[] = { 1459 CANFD1_TX_MARK, CANFD1_RX_MARK, 1460 }; 1461 1462 /* - CANFD2 ----------------------------------------------------------------- */ 1463 static const unsigned int canfd2_data_pins[] = { 1464 /* CANFD2_TX, CANFD2_RX */ 1465 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 1466 }; 1467 static const unsigned int canfd2_data_mux[] = { 1468 CANFD2_TX_MARK, CANFD2_RX_MARK, 1469 }; 1470 1471 /* - CANFD3 ----------------------------------------------------------------- */ 1472 static const unsigned int canfd3_data_pins[] = { 1473 /* CANFD3_TX, CANFD3_RX */ 1474 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 1475 }; 1476 static const unsigned int canfd3_data_mux[] = { 1477 CANFD3_TX_MARK, CANFD3_RX_MARK, 1478 }; 1479 1480 /* - CANFD Clock ------------------------------------------------------------ */ 1481 static const unsigned int can_clk_pins[] = { 1482 /* CAN_CLK */ 1483 RCAR_GP_PIN(2, 9), 1484 }; 1485 static const unsigned int can_clk_mux[] = { 1486 CAN_CLK_MARK, 1487 }; 1488 1489 /* - HSCIF0 ----------------------------------------------------------------- */ 1490 static const unsigned int hscif0_data_pins[] = { 1491 /* HRX0, HTX0 */ 1492 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12), 1493 }; 1494 static const unsigned int hscif0_data_mux[] = { 1495 HRX0_MARK, HTX0_MARK, 1496 }; 1497 static const unsigned int hscif0_clk_pins[] = { 1498 /* HSCK0 */ 1499 RCAR_GP_PIN(1, 15), 1500 }; 1501 static const unsigned int hscif0_clk_mux[] = { 1502 HSCK0_MARK, 1503 }; 1504 static const unsigned int hscif0_ctrl_pins[] = { 1505 /* HRTS0_N, HCTS0_N */ 1506 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 1507 }; 1508 static const unsigned int hscif0_ctrl_mux[] = { 1509 HRTS0_N_MARK, HCTS0_N_MARK, 1510 }; 1511 1512 /* - HSCIF1_A ----------------------------------------------------------------- */ 1513 static const unsigned int hscif1_data_a_pins[] = { 1514 /* HRX1_A, HTX1_A */ 1515 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 1516 }; 1517 static const unsigned int hscif1_data_a_mux[] = { 1518 HRX1_A_MARK, HTX1_A_MARK, 1519 }; 1520 static const unsigned int hscif1_clk_a_pins[] = { 1521 /* HSCK1_A */ 1522 RCAR_GP_PIN(0, 18), 1523 }; 1524 static const unsigned int hscif1_clk_a_mux[] = { 1525 HSCK1_A_MARK, 1526 }; 1527 static const unsigned int hscif1_ctrl_a_pins[] = { 1528 /* HRTS1_N_A, HCTS1_N_A */ 1529 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), 1530 }; 1531 static const unsigned int hscif1_ctrl_a_mux[] = { 1532 HRTS1_N_A_MARK, HCTS1_N_A_MARK, 1533 }; 1534 1535 /* - HSCIF1_B ---------------------------------------------------------------- */ 1536 static const unsigned int hscif1_data_b_pins[] = { 1537 /* HRX1_B, HTX1_B */ 1538 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), 1539 }; 1540 static const unsigned int hscif1_data_b_mux[] = { 1541 HRX1_B_MARK, HTX1_B_MARK, 1542 }; 1543 static const unsigned int hscif1_clk_b_pins[] = { 1544 /* HSCK1_B */ 1545 RCAR_GP_PIN(1, 10), 1546 }; 1547 static const unsigned int hscif1_clk_b_mux[] = { 1548 HSCK1_B_MARK, 1549 }; 1550 static const unsigned int hscif1_ctrl_b_pins[] = { 1551 /* HRTS1_N_B, HCTS1_N_B */ 1552 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), 1553 }; 1554 static const unsigned int hscif1_ctrl_b_mux[] = { 1555 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 1556 }; 1557 1558 /* - HSCIF2 ----------------------------------------------------------------- */ 1559 static const unsigned int hscif2_data_pins[] = { 1560 /* HRX2, HTX2 */ 1561 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 1562 }; 1563 static const unsigned int hscif2_data_mux[] = { 1564 HRX2_MARK, HTX2_MARK, 1565 }; 1566 static const unsigned int hscif2_clk_pins[] = { 1567 /* HSCK2 */ 1568 RCAR_GP_PIN(4, 13), 1569 }; 1570 static const unsigned int hscif2_clk_mux[] = { 1571 HSCK2_MARK, 1572 }; 1573 static const unsigned int hscif2_ctrl_pins[] = { 1574 /* HRTS2_N, HCTS2_N */ 1575 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 12), 1576 }; 1577 static const unsigned int hscif2_ctrl_mux[] = { 1578 HRTS2_N_MARK, HCTS2_N_MARK, 1579 }; 1580 1581 /* - HSCIF3_A ----------------------------------------------------------------- */ 1582 static const unsigned int hscif3_data_a_pins[] = { 1583 /* HRX3_A, HTX3_A */ 1584 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28), 1585 }; 1586 static const unsigned int hscif3_data_a_mux[] = { 1587 HRX3_A_MARK, HTX3_A_MARK, 1588 }; 1589 static const unsigned int hscif3_clk_a_pins[] = { 1590 /* HSCK3_A */ 1591 RCAR_GP_PIN(1, 25), 1592 }; 1593 static const unsigned int hscif3_clk_a_mux[] = { 1594 HSCK3_A_MARK, 1595 }; 1596 static const unsigned int hscif3_ctrl_a_pins[] = { 1597 /* HRTS3_N_A, HCTS3_N_A */ 1598 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27), 1599 }; 1600 static const unsigned int hscif3_ctrl_a_mux[] = { 1601 HRTS3_N_A_MARK, HCTS3_N_A_MARK, 1602 }; 1603 1604 /* - HSCIF3_B ----------------------------------------------------------------- */ 1605 static const unsigned int hscif3_data_b_pins[] = { 1606 /* HRX3_B, HTX3_B */ 1607 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), 1608 }; 1609 static const unsigned int hscif3_data_b_mux[] = { 1610 HRX3_B_MARK, HTX3_B_MARK, 1611 }; 1612 static const unsigned int hscif3_clk_b_pins[] = { 1613 /* HSCK3_B */ 1614 RCAR_GP_PIN(1, 3), 1615 }; 1616 static const unsigned int hscif3_clk_b_mux[] = { 1617 HSCK3_B_MARK, 1618 }; 1619 static const unsigned int hscif3_ctrl_b_pins[] = { 1620 /* HRTS3_N_B, HCTS3_N_B */ 1621 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), 1622 }; 1623 static const unsigned int hscif3_ctrl_b_mux[] = { 1624 HRTS3_N_B_MARK, HCTS3_N_B_MARK, 1625 }; 1626 1627 /* - I2C0 ------------------------------------------------------------------- */ 1628 static const unsigned int i2c0_pins[] = { 1629 /* SDA0, SCL0 */ 1630 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0), 1631 }; 1632 static const unsigned int i2c0_mux[] = { 1633 SDA0_MARK, SCL0_MARK, 1634 }; 1635 1636 /* - I2C1 ------------------------------------------------------------------- */ 1637 static const unsigned int i2c1_pins[] = { 1638 /* SDA1, SCL1 */ 1639 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1640 }; 1641 static const unsigned int i2c1_mux[] = { 1642 SDA1_MARK, SCL1_MARK, 1643 }; 1644 1645 /* - I2C2 ------------------------------------------------------------------- */ 1646 static const unsigned int i2c2_pins[] = { 1647 /* SDA2, SCL2 */ 1648 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4), 1649 }; 1650 static const unsigned int i2c2_mux[] = { 1651 SDA2_MARK, SCL2_MARK, 1652 }; 1653 1654 /* - I2C3 ------------------------------------------------------------------- */ 1655 static const unsigned int i2c3_pins[] = { 1656 /* SDA3, SCL3 */ 1657 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), 1658 }; 1659 static const unsigned int i2c3_mux[] = { 1660 SDA3_MARK, SCL3_MARK, 1661 }; 1662 1663 /* - INTC-EX ---------------------------------------------------------------- */ 1664 static const unsigned int intc_ex_irq0_a_pins[] = { 1665 /* IRQ0_A */ 1666 RCAR_GP_PIN(0, 6), 1667 }; 1668 static const unsigned int intc_ex_irq0_a_mux[] = { 1669 IRQ0_A_MARK, 1670 }; 1671 static const unsigned int intc_ex_irq0_b_pins[] = { 1672 /* IRQ0_B */ 1673 RCAR_GP_PIN(1, 20), 1674 }; 1675 static const unsigned int intc_ex_irq0_b_mux[] = { 1676 IRQ0_B_MARK, 1677 }; 1678 1679 static const unsigned int intc_ex_irq1_a_pins[] = { 1680 /* IRQ1_A */ 1681 RCAR_GP_PIN(0, 5), 1682 }; 1683 static const unsigned int intc_ex_irq1_a_mux[] = { 1684 IRQ1_A_MARK, 1685 }; 1686 static const unsigned int intc_ex_irq1_b_pins[] = { 1687 /* IRQ1_B */ 1688 RCAR_GP_PIN(1, 21), 1689 }; 1690 static const unsigned int intc_ex_irq1_b_mux[] = { 1691 IRQ1_B_MARK, 1692 }; 1693 1694 static const unsigned int intc_ex_irq2_a_pins[] = { 1695 /* IRQ2_A */ 1696 RCAR_GP_PIN(0, 4), 1697 }; 1698 static const unsigned int intc_ex_irq2_a_mux[] = { 1699 IRQ2_A_MARK, 1700 }; 1701 static const unsigned int intc_ex_irq2_b_pins[] = { 1702 /* IRQ2_B */ 1703 RCAR_GP_PIN(0, 13), 1704 }; 1705 static const unsigned int intc_ex_irq2_b_mux[] = { 1706 IRQ2_B_MARK, 1707 }; 1708 1709 static const unsigned int intc_ex_irq3_a_pins[] = { 1710 /* IRQ3_A */ 1711 RCAR_GP_PIN(0, 3), 1712 }; 1713 static const unsigned int intc_ex_irq3_a_mux[] = { 1714 IRQ3_A_MARK, 1715 }; 1716 static const unsigned int intc_ex_irq3_b_pins[] = { 1717 /* IRQ3_B */ 1718 RCAR_GP_PIN(1, 23), 1719 }; 1720 static const unsigned int intc_ex_irq3_b_mux[] = { 1721 IRQ3_B_MARK, 1722 }; 1723 1724 static const unsigned int intc_ex_irq4_a_pins[] = { 1725 /* IRQ4_A */ 1726 RCAR_GP_PIN(1, 17), 1727 }; 1728 static const unsigned int intc_ex_irq4_a_mux[] = { 1729 IRQ4_A_MARK, 1730 }; 1731 static const unsigned int intc_ex_irq4_b_pins[] = { 1732 /* IRQ4_B */ 1733 RCAR_GP_PIN(2, 3), 1734 }; 1735 static const unsigned int intc_ex_irq4_b_mux[] = { 1736 IRQ4_B_MARK, 1737 }; 1738 1739 static const unsigned int intc_ex_irq5_pins[] = { 1740 /* IRQ5 */ 1741 RCAR_GP_PIN(2, 2), 1742 }; 1743 static const unsigned int intc_ex_irq5_mux[] = { 1744 IRQ5_MARK, 1745 }; 1746 1747 /* - MMC -------------------------------------------------------------------- */ 1748 static const unsigned int mmc_data_pins[] = { 1749 /* MMC_SD_D[0:3], MMC_D[4:7] */ 1750 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 1751 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5), 1752 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), 1753 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), 1754 }; 1755 static const unsigned int mmc_data_mux[] = { 1756 MMC_SD_D0_MARK, MMC_SD_D1_MARK, 1757 MMC_SD_D2_MARK, MMC_SD_D3_MARK, 1758 MMC_D4_MARK, MMC_D5_MARK, 1759 MMC_D6_MARK, MMC_D7_MARK, 1760 }; 1761 static const unsigned int mmc_ctrl_pins[] = { 1762 /* MMC_SD_CLK, MMC_SD_CMD */ 1763 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10), 1764 }; 1765 static const unsigned int mmc_ctrl_mux[] = { 1766 MMC_SD_CLK_MARK, MMC_SD_CMD_MARK, 1767 }; 1768 static const unsigned int mmc_cd_pins[] = { 1769 /* SD_CD */ 1770 RCAR_GP_PIN(3, 11), 1771 }; 1772 static const unsigned int mmc_cd_mux[] = { 1773 SD_CD_MARK, 1774 }; 1775 static const unsigned int mmc_wp_pins[] = { 1776 /* SD_WP */ 1777 RCAR_GP_PIN(3, 12), 1778 }; 1779 static const unsigned int mmc_wp_mux[] = { 1780 SD_WP_MARK, 1781 }; 1782 static const unsigned int mmc_ds_pins[] = { 1783 /* MMC_DS */ 1784 RCAR_GP_PIN(3, 4), 1785 }; 1786 static const unsigned int mmc_ds_mux[] = { 1787 MMC_DS_MARK, 1788 }; 1789 1790 /* - MSIOF0 ----------------------------------------------------------------- */ 1791 static const unsigned int msiof0_clk_pins[] = { 1792 /* MSIOF0_SCK */ 1793 RCAR_GP_PIN(1, 10), 1794 }; 1795 static const unsigned int msiof0_clk_mux[] = { 1796 MSIOF0_SCK_MARK, 1797 }; 1798 static const unsigned int msiof0_sync_pins[] = { 1799 /* MSIOF0_SYNC */ 1800 RCAR_GP_PIN(1, 8), 1801 }; 1802 static const unsigned int msiof0_sync_mux[] = { 1803 MSIOF0_SYNC_MARK, 1804 }; 1805 static const unsigned int msiof0_ss1_pins[] = { 1806 /* MSIOF0_SS1 */ 1807 RCAR_GP_PIN(1, 7), 1808 }; 1809 static const unsigned int msiof0_ss1_mux[] = { 1810 MSIOF0_SS1_MARK, 1811 }; 1812 static const unsigned int msiof0_ss2_pins[] = { 1813 /* MSIOF0_SS2 */ 1814 RCAR_GP_PIN(1, 6), 1815 }; 1816 static const unsigned int msiof0_ss2_mux[] = { 1817 MSIOF0_SS2_MARK, 1818 }; 1819 static const unsigned int msiof0_txd_pins[] = { 1820 /* MSIOF0_TXD */ 1821 RCAR_GP_PIN(1, 9), 1822 }; 1823 static const unsigned int msiof0_txd_mux[] = { 1824 MSIOF0_TXD_MARK, 1825 }; 1826 static const unsigned int msiof0_rxd_pins[] = { 1827 /* MSIOF0_RXD */ 1828 RCAR_GP_PIN(1, 11), 1829 }; 1830 static const unsigned int msiof0_rxd_mux[] = { 1831 MSIOF0_RXD_MARK, 1832 }; 1833 1834 /* - MSIOF1 ----------------------------------------------------------------- */ 1835 static const unsigned int msiof1_clk_pins[] = { 1836 /* MSIOF1_SCK */ 1837 RCAR_GP_PIN(1, 3), 1838 }; 1839 static const unsigned int msiof1_clk_mux[] = { 1840 MSIOF1_SCK_MARK, 1841 }; 1842 static const unsigned int msiof1_sync_pins[] = { 1843 /* MSIOF1_SYNC */ 1844 RCAR_GP_PIN(1, 2), 1845 }; 1846 static const unsigned int msiof1_sync_mux[] = { 1847 MSIOF1_SYNC_MARK, 1848 }; 1849 static const unsigned int msiof1_ss1_pins[] = { 1850 /* MSIOF1_SS1 */ 1851 RCAR_GP_PIN(1, 1), 1852 }; 1853 static const unsigned int msiof1_ss1_mux[] = { 1854 MSIOF1_SS1_MARK, 1855 }; 1856 static const unsigned int msiof1_ss2_pins[] = { 1857 /* MSIOF1_SS2 */ 1858 RCAR_GP_PIN(1, 0), 1859 }; 1860 static const unsigned int msiof1_ss2_mux[] = { 1861 MSIOF1_SS2_MARK, 1862 }; 1863 static const unsigned int msiof1_txd_pins[] = { 1864 /* MSIOF1_TXD */ 1865 RCAR_GP_PIN(1, 4), 1866 }; 1867 static const unsigned int msiof1_txd_mux[] = { 1868 MSIOF1_TXD_MARK, 1869 }; 1870 static const unsigned int msiof1_rxd_pins[] = { 1871 /* MSIOF1_RXD */ 1872 RCAR_GP_PIN(1, 5), 1873 }; 1874 static const unsigned int msiof1_rxd_mux[] = { 1875 MSIOF1_RXD_MARK, 1876 }; 1877 1878 /* - MSIOF2 ----------------------------------------------------------------- */ 1879 static const unsigned int msiof2_clk_pins[] = { 1880 /* MSIOF2_SCK */ 1881 RCAR_GP_PIN(0, 17), 1882 }; 1883 static const unsigned int msiof2_clk_mux[] = { 1884 MSIOF2_SCK_MARK, 1885 }; 1886 static const unsigned int msiof2_sync_pins[] = { 1887 /* MSIOF2_SYNC */ 1888 RCAR_GP_PIN(0, 15), 1889 }; 1890 static const unsigned int msiof2_sync_mux[] = { 1891 MSIOF2_SYNC_MARK, 1892 }; 1893 static const unsigned int msiof2_ss1_pins[] = { 1894 /* MSIOF2_SS1 */ 1895 RCAR_GP_PIN(0, 14), 1896 }; 1897 static const unsigned int msiof2_ss1_mux[] = { 1898 MSIOF2_SS1_MARK, 1899 }; 1900 static const unsigned int msiof2_ss2_pins[] = { 1901 /* MSIOF2_SS2 */ 1902 RCAR_GP_PIN(0, 13), 1903 }; 1904 static const unsigned int msiof2_ss2_mux[] = { 1905 MSIOF2_SS2_MARK, 1906 }; 1907 static const unsigned int msiof2_txd_pins[] = { 1908 /* MSIOF2_TXD */ 1909 RCAR_GP_PIN(0, 16), 1910 }; 1911 static const unsigned int msiof2_txd_mux[] = { 1912 MSIOF2_TXD_MARK, 1913 }; 1914 static const unsigned int msiof2_rxd_pins[] = { 1915 /* MSIOF2_RXD */ 1916 RCAR_GP_PIN(0, 18), 1917 }; 1918 static const unsigned int msiof2_rxd_mux[] = { 1919 MSIOF2_RXD_MARK, 1920 }; 1921 1922 /* - MSIOF3 ----------------------------------------------------------------- */ 1923 static const unsigned int msiof3_clk_pins[] = { 1924 /* MSIOF3_SCK */ 1925 RCAR_GP_PIN(0, 3), 1926 }; 1927 static const unsigned int msiof3_clk_mux[] = { 1928 MSIOF3_SCK_MARK, 1929 }; 1930 static const unsigned int msiof3_sync_pins[] = { 1931 /* MSIOF3_SYNC */ 1932 RCAR_GP_PIN(0, 6), 1933 }; 1934 static const unsigned int msiof3_sync_mux[] = { 1935 MSIOF3_SYNC_MARK, 1936 }; 1937 static const unsigned int msiof3_ss1_pins[] = { 1938 /* MSIOF3_SS1 */ 1939 RCAR_GP_PIN(0, 1), 1940 }; 1941 static const unsigned int msiof3_ss1_mux[] = { 1942 MSIOF3_SS1_MARK, 1943 }; 1944 static const unsigned int msiof3_ss2_pins[] = { 1945 /* MSIOF3_SS2 */ 1946 RCAR_GP_PIN(0, 2), 1947 }; 1948 static const unsigned int msiof3_ss2_mux[] = { 1949 MSIOF3_SS2_MARK, 1950 }; 1951 static const unsigned int msiof3_txd_pins[] = { 1952 /* MSIOF3_TXD */ 1953 RCAR_GP_PIN(0, 4), 1954 }; 1955 static const unsigned int msiof3_txd_mux[] = { 1956 MSIOF3_TXD_MARK, 1957 }; 1958 static const unsigned int msiof3_rxd_pins[] = { 1959 /* MSIOF3_RXD */ 1960 RCAR_GP_PIN(0, 5), 1961 }; 1962 static const unsigned int msiof3_rxd_mux[] = { 1963 MSIOF3_RXD_MARK, 1964 }; 1965 1966 /* - MSIOF4 ----------------------------------------------------------------- */ 1967 static const unsigned int msiof4_clk_pins[] = { 1968 /* MSIOF4_SCK */ 1969 RCAR_GP_PIN(1, 25), 1970 }; 1971 static const unsigned int msiof4_clk_mux[] = { 1972 MSIOF4_SCK_MARK, 1973 }; 1974 static const unsigned int msiof4_sync_pins[] = { 1975 /* MSIOF4_SYNC */ 1976 RCAR_GP_PIN(1, 28), 1977 }; 1978 static const unsigned int msiof4_sync_mux[] = { 1979 MSIOF4_SYNC_MARK, 1980 }; 1981 static const unsigned int msiof4_ss1_pins[] = { 1982 /* MSIOF4_SS1 */ 1983 RCAR_GP_PIN(1, 23), 1984 }; 1985 static const unsigned int msiof4_ss1_mux[] = { 1986 MSIOF4_SS1_MARK, 1987 }; 1988 static const unsigned int msiof4_ss2_pins[] = { 1989 /* MSIOF4_SS2 */ 1990 RCAR_GP_PIN(1, 24), 1991 }; 1992 static const unsigned int msiof4_ss2_mux[] = { 1993 MSIOF4_SS2_MARK, 1994 }; 1995 static const unsigned int msiof4_txd_pins[] = { 1996 /* MSIOF4_TXD */ 1997 RCAR_GP_PIN(1, 26), 1998 }; 1999 static const unsigned int msiof4_txd_mux[] = { 2000 MSIOF4_TXD_MARK, 2001 }; 2002 static const unsigned int msiof4_rxd_pins[] = { 2003 /* MSIOF4_RXD */ 2004 RCAR_GP_PIN(1, 27), 2005 }; 2006 static const unsigned int msiof4_rxd_mux[] = { 2007 MSIOF4_RXD_MARK, 2008 }; 2009 2010 /* - MSIOF5 ----------------------------------------------------------------- */ 2011 static const unsigned int msiof5_clk_pins[] = { 2012 /* MSIOF5_SCK */ 2013 RCAR_GP_PIN(0, 11), 2014 }; 2015 static const unsigned int msiof5_clk_mux[] = { 2016 MSIOF5_SCK_MARK, 2017 }; 2018 static const unsigned int msiof5_sync_pins[] = { 2019 /* MSIOF5_SYNC */ 2020 RCAR_GP_PIN(0, 9), 2021 }; 2022 static const unsigned int msiof5_sync_mux[] = { 2023 MSIOF5_SYNC_MARK, 2024 }; 2025 static const unsigned int msiof5_ss1_pins[] = { 2026 /* MSIOF5_SS1 */ 2027 RCAR_GP_PIN(0, 8), 2028 }; 2029 static const unsigned int msiof5_ss1_mux[] = { 2030 MSIOF5_SS1_MARK, 2031 }; 2032 static const unsigned int msiof5_ss2_pins[] = { 2033 /* MSIOF5_SS2 */ 2034 RCAR_GP_PIN(0, 7), 2035 }; 2036 static const unsigned int msiof5_ss2_mux[] = { 2037 MSIOF5_SS2_MARK, 2038 }; 2039 static const unsigned int msiof5_txd_pins[] = { 2040 /* MSIOF5_TXD */ 2041 RCAR_GP_PIN(0, 10), 2042 }; 2043 static const unsigned int msiof5_txd_mux[] = { 2044 MSIOF5_TXD_MARK, 2045 }; 2046 static const unsigned int msiof5_rxd_pins[] = { 2047 /* MSIOF5_RXD */ 2048 RCAR_GP_PIN(0, 12), 2049 }; 2050 static const unsigned int msiof5_rxd_mux[] = { 2051 MSIOF5_RXD_MARK, 2052 }; 2053 2054 /* - PCIE ------------------------------------------------------------------- */ 2055 static const unsigned int pcie0_clkreq_n_pins[] = { 2056 /* PCIE0_CLKREQ_N */ 2057 RCAR_GP_PIN(4, 21), 2058 }; 2059 2060 static const unsigned int pcie0_clkreq_n_mux[] = { 2061 PCIE0_CLKREQ_N_MARK, 2062 }; 2063 2064 /* - PWM0_A ------------------------------------------------------------------- */ 2065 static const unsigned int pwm0_a_pins[] = { 2066 /* PWM0_A */ 2067 RCAR_GP_PIN(1, 15), 2068 }; 2069 static const unsigned int pwm0_a_mux[] = { 2070 PWM0_A_MARK, 2071 }; 2072 2073 /* - PWM0_B ------------------------------------------------------------------- */ 2074 static const unsigned int pwm0_b_pins[] = { 2075 /* PWM0_B */ 2076 RCAR_GP_PIN(1, 14), 2077 }; 2078 static const unsigned int pwm0_b_mux[] = { 2079 PWM0_B_MARK, 2080 }; 2081 2082 /* - PWM1_A ------------------------------------------------------------------- */ 2083 static const unsigned int pwm1_a_pins[] = { 2084 /* PWM1_A */ 2085 RCAR_GP_PIN(3, 13), 2086 }; 2087 static const unsigned int pwm1_a_mux[] = { 2088 PWM1_A_MARK, 2089 }; 2090 2091 /* - PWM1_B ------------------------------------------------------------------- */ 2092 static const unsigned int pwm1_b_pins[] = { 2093 /* PWM1_B */ 2094 RCAR_GP_PIN(2, 13), 2095 }; 2096 static const unsigned int pwm1_b_mux[] = { 2097 PWM1_B_MARK, 2098 }; 2099 2100 /* - PWM1_C ------------------------------------------------------------------- */ 2101 static const unsigned int pwm1_c_pins[] = { 2102 /* PWM1_C */ 2103 RCAR_GP_PIN(2, 17), 2104 }; 2105 static const unsigned int pwm1_c_mux[] = { 2106 PWM1_C_MARK, 2107 }; 2108 2109 /* - PWM2_A ------------------------------------------------------------------- */ 2110 static const unsigned int pwm2_a_pins[] = { 2111 /* PWM2_A */ 2112 RCAR_GP_PIN(3, 14), 2113 }; 2114 static const unsigned int pwm2_a_mux[] = { 2115 PWM2_A_MARK, 2116 }; 2117 2118 /* - PWM2_B ------------------------------------------------------------------- */ 2119 static const unsigned int pwm2_b_pins[] = { 2120 /* PWM2_B */ 2121 RCAR_GP_PIN(2, 14), 2122 }; 2123 static const unsigned int pwm2_b_mux[] = { 2124 PWM2_B_MARK, 2125 }; 2126 2127 /* - PWM2_C ------------------------------------------------------------------- */ 2128 static const unsigned int pwm2_c_pins[] = { 2129 /* PWM2_C */ 2130 RCAR_GP_PIN(2, 19), 2131 }; 2132 static const unsigned int pwm2_c_mux[] = { 2133 PWM2_C_MARK, 2134 }; 2135 2136 /* - PWM3_A ------------------------------------------------------------------- */ 2137 static const unsigned int pwm3_a_pins[] = { 2138 /* PWM3_A */ 2139 RCAR_GP_PIN(4, 14), 2140 }; 2141 static const unsigned int pwm3_a_mux[] = { 2142 PWM3_A_MARK, 2143 }; 2144 2145 /* - PWM3_B ------------------------------------------------------------------- */ 2146 static const unsigned int pwm3_b_pins[] = { 2147 /* PWM3_B */ 2148 RCAR_GP_PIN(2, 15), 2149 }; 2150 static const unsigned int pwm3_b_mux[] = { 2151 PWM3_B_MARK, 2152 }; 2153 2154 /* - PWM3_C ------------------------------------------------------------------- */ 2155 static const unsigned int pwm3_c_pins[] = { 2156 /* PWM3_C */ 2157 RCAR_GP_PIN(1, 22), 2158 }; 2159 static const unsigned int pwm3_c_mux[] = { 2160 PWM3_C_MARK, 2161 }; 2162 2163 /* - PWM4 ------------------------------------------------------------------- */ 2164 static const unsigned int pwm4_pins[] = { 2165 /* PWM4 */ 2166 RCAR_GP_PIN(4, 15), 2167 }; 2168 static const unsigned int pwm4_mux[] = { 2169 PWM4_MARK, 2170 }; 2171 2172 /* - QSPI0 ------------------------------------------------------------------ */ 2173 static const unsigned int qspi0_ctrl_pins[] = { 2174 /* SPCLK, SSL */ 2175 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15), 2176 }; 2177 static const unsigned int qspi0_ctrl_mux[] = { 2178 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 2179 }; 2180 static const unsigned int qspi0_data_pins[] = { 2181 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 2182 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18), 2183 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), 2184 }; 2185 static const unsigned int qspi0_data_mux[] = { 2186 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 2187 QSPI0_IO2_MARK, QSPI0_IO3_MARK 2188 }; 2189 2190 /* - QSPI1 ------------------------------------------------------------------ */ 2191 static const unsigned int qspi1_ctrl_pins[] = { 2192 /* SPCLK, SSL */ 2193 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25), 2194 }; 2195 static const unsigned int qspi1_ctrl_mux[] = { 2196 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 2197 }; 2198 static const unsigned int qspi1_data_pins[] = { 2199 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 2200 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23), 2201 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26), 2202 }; 2203 static const unsigned int qspi1_data_mux[] = { 2204 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 2205 QSPI1_IO2_MARK, QSPI1_IO3_MARK 2206 }; 2207 2208 /* - SCIF0 ------------------------------------------------------------------ */ 2209 static const unsigned int scif0_data_pins[] = { 2210 /* RX0, TX0 */ 2211 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12), 2212 }; 2213 static const unsigned int scif0_data_mux[] = { 2214 RX0_MARK, TX0_MARK, 2215 }; 2216 static const unsigned int scif0_clk_pins[] = { 2217 /* SCK0 */ 2218 RCAR_GP_PIN(1, 15), 2219 }; 2220 static const unsigned int scif0_clk_mux[] = { 2221 SCK0_MARK, 2222 }; 2223 static const unsigned int scif0_ctrl_pins[] = { 2224 /* RTS0_N, CTS0_N */ 2225 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2226 }; 2227 static const unsigned int scif0_ctrl_mux[] = { 2228 RTS0_N_MARK, CTS0_N_MARK, 2229 }; 2230 2231 /* - SCIF1_A ------------------------------------------------------------------ */ 2232 static const unsigned int scif1_data_a_pins[] = { 2233 /* RX1_A, TX1_A */ 2234 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 2235 }; 2236 static const unsigned int scif1_data_a_mux[] = { 2237 RX1_A_MARK, TX1_A_MARK, 2238 }; 2239 static const unsigned int scif1_clk_a_pins[] = { 2240 /* SCK1_A */ 2241 RCAR_GP_PIN(0, 18), 2242 }; 2243 static const unsigned int scif1_clk_a_mux[] = { 2244 SCK1_A_MARK, 2245 }; 2246 static const unsigned int scif1_ctrl_a_pins[] = { 2247 /* RTS1_N_A, CTS1_N_A */ 2248 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), 2249 }; 2250 static const unsigned int scif1_ctrl_a_mux[] = { 2251 RTS1_N_A_MARK, CTS1_N_A_MARK, 2252 }; 2253 2254 /* - SCIF1_B ------------------------------------------------------------------ */ 2255 static const unsigned int scif1_data_b_pins[] = { 2256 /* RX1_B, TX1_B */ 2257 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), 2258 }; 2259 static const unsigned int scif1_data_b_mux[] = { 2260 RX1_B_MARK, TX1_B_MARK, 2261 }; 2262 static const unsigned int scif1_clk_b_pins[] = { 2263 /* SCK1_B */ 2264 RCAR_GP_PIN(1, 10), 2265 }; 2266 static const unsigned int scif1_clk_b_mux[] = { 2267 SCK1_B_MARK, 2268 }; 2269 static const unsigned int scif1_ctrl_b_pins[] = { 2270 /* RTS1_N_B, CTS1_N_B */ 2271 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), 2272 }; 2273 static const unsigned int scif1_ctrl_b_mux[] = { 2274 RTS1_N_B_MARK, CTS1_N_B_MARK, 2275 }; 2276 2277 /* - SCIF3_A ------------------------------------------------------------------ */ 2278 static const unsigned int scif3_data_a_pins[] = { 2279 /* RX3_A, TX3_A */ 2280 RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28), 2281 }; 2282 static const unsigned int scif3_data_a_mux[] = { 2283 RX3_A_MARK, TX3_A_MARK, 2284 }; 2285 static const unsigned int scif3_clk_a_pins[] = { 2286 /* SCK3_A */ 2287 RCAR_GP_PIN(1, 24), 2288 }; 2289 static const unsigned int scif3_clk_a_mux[] = { 2290 SCK3_A_MARK, 2291 }; 2292 static const unsigned int scif3_ctrl_a_pins[] = { 2293 /* RTS3_N_A, CTS3_N_A */ 2294 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2295 }; 2296 static const unsigned int scif3_ctrl_a_mux[] = { 2297 RTS3_N_A_MARK, CTS3_N_A_MARK, 2298 }; 2299 2300 /* - SCIF3_B ------------------------------------------------------------------ */ 2301 static const unsigned int scif3_data_b_pins[] = { 2302 /* RX3_B, TX3_B */ 2303 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 2304 }; 2305 static const unsigned int scif3_data_b_mux[] = { 2306 RX3_B_MARK, TX3_B_MARK, 2307 }; 2308 static const unsigned int scif3_clk_b_pins[] = { 2309 /* SCK3_B */ 2310 RCAR_GP_PIN(1, 4), 2311 }; 2312 static const unsigned int scif3_clk_b_mux[] = { 2313 SCK3_B_MARK, 2314 }; 2315 static const unsigned int scif3_ctrl_b_pins[] = { 2316 /* RTS3_N_B, CTS3_N_B */ 2317 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 2318 }; 2319 static const unsigned int scif3_ctrl_b_mux[] = { 2320 RTS3_N_B_MARK, CTS3_N_B_MARK, 2321 }; 2322 2323 /* - SCIF4 ------------------------------------------------------------------ */ 2324 static const unsigned int scif4_data_pins[] = { 2325 /* RX4, TX4 */ 2326 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12), 2327 }; 2328 static const unsigned int scif4_data_mux[] = { 2329 RX4_MARK, TX4_MARK, 2330 }; 2331 static const unsigned int scif4_clk_pins[] = { 2332 /* SCK4 */ 2333 RCAR_GP_PIN(4, 8), 2334 }; 2335 static const unsigned int scif4_clk_mux[] = { 2336 SCK4_MARK, 2337 }; 2338 static const unsigned int scif4_ctrl_pins[] = { 2339 /* RTS4_N, CTS4_N */ 2340 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 9), 2341 }; 2342 static const unsigned int scif4_ctrl_mux[] = { 2343 RTS4_N_MARK, CTS4_N_MARK, 2344 }; 2345 2346 /* - SCIF Clock ------------------------------------------------------------- */ 2347 static const unsigned int scif_clk_pins[] = { 2348 /* SCIF_CLK */ 2349 RCAR_GP_PIN(1, 17), 2350 }; 2351 static const unsigned int scif_clk_mux[] = { 2352 SCIF_CLK_MARK, 2353 }; 2354 2355 static const unsigned int scif_clk2_pins[] = { 2356 /* SCIF_CLK2 */ 2357 RCAR_GP_PIN(4, 11), 2358 }; 2359 static const unsigned int scif_clk2_mux[] = { 2360 SCIF_CLK2_MARK, 2361 }; 2362 2363 /* - SSI ------------------------------------------------- */ 2364 static const unsigned int ssi_data_pins[] = { 2365 /* SSI_SD */ 2366 RCAR_GP_PIN(1, 20), 2367 }; 2368 static const unsigned int ssi_data_mux[] = { 2369 SSI_SD_MARK, 2370 }; 2371 static const unsigned int ssi_ctrl_pins[] = { 2372 /* SSI_SCK, SSI_WS */ 2373 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), 2374 }; 2375 static const unsigned int ssi_ctrl_mux[] = { 2376 SSI_SCK_MARK, SSI_WS_MARK, 2377 }; 2378 2379 /* - TPU_A ------------------------------------------------------------------- */ 2380 static const unsigned int tpu_to0_a_pins[] = { 2381 /* TPU0TO0_A */ 2382 RCAR_GP_PIN(2, 8), 2383 }; 2384 static const unsigned int tpu_to0_a_mux[] = { 2385 TPU0TO0_A_MARK, 2386 }; 2387 static const unsigned int tpu_to1_a_pins[] = { 2388 /* TPU0TO1_A */ 2389 RCAR_GP_PIN(2, 7), 2390 }; 2391 static const unsigned int tpu_to1_a_mux[] = { 2392 TPU0TO1_A_MARK, 2393 }; 2394 static const unsigned int tpu_to2_a_pins[] = { 2395 /* TPU0TO2_A */ 2396 RCAR_GP_PIN(2, 12), 2397 }; 2398 static const unsigned int tpu_to2_a_mux[] = { 2399 TPU0TO2_A_MARK, 2400 }; 2401 static const unsigned int tpu_to3_a_pins[] = { 2402 /* TPU0TO3_A */ 2403 RCAR_GP_PIN(2, 13), 2404 }; 2405 static const unsigned int tpu_to3_a_mux[] = { 2406 TPU0TO3_A_MARK, 2407 }; 2408 2409 /* - TPU_B ------------------------------------------------------------------- */ 2410 static const unsigned int tpu_to0_b_pins[] = { 2411 /* TPU0TO0_B */ 2412 RCAR_GP_PIN(1, 25), 2413 }; 2414 static const unsigned int tpu_to0_b_mux[] = { 2415 TPU0TO0_B_MARK, 2416 }; 2417 static const unsigned int tpu_to1_b_pins[] = { 2418 /* TPU0TO1_B */ 2419 RCAR_GP_PIN(1, 26), 2420 }; 2421 static const unsigned int tpu_to1_b_mux[] = { 2422 TPU0TO1_B_MARK, 2423 }; 2424 static const unsigned int tpu_to2_b_pins[] = { 2425 /* TPU0TO2_B */ 2426 RCAR_GP_PIN(2, 0), 2427 }; 2428 static const unsigned int tpu_to2_b_mux[] = { 2429 TPU0TO2_B_MARK, 2430 }; 2431 static const unsigned int tpu_to3_b_pins[] = { 2432 /* TPU0TO3_B */ 2433 RCAR_GP_PIN(2, 1), 2434 }; 2435 static const unsigned int tpu_to3_b_mux[] = { 2436 TPU0TO3_B_MARK, 2437 }; 2438 2439 static const struct sh_pfc_pin_group pinmux_groups[] = { 2440 SH_PFC_PIN_GROUP(audio_clkin), 2441 SH_PFC_PIN_GROUP(audio_clkout), 2442 2443 SH_PFC_PIN_GROUP(avb0_link), 2444 SH_PFC_PIN_GROUP(avb0_magic), 2445 SH_PFC_PIN_GROUP(avb0_phy_int), 2446 SH_PFC_PIN_GROUP(avb0_mdio), 2447 SH_PFC_PIN_GROUP(avb0_rgmii), 2448 SH_PFC_PIN_GROUP(avb0_txcrefclk), 2449 SH_PFC_PIN_GROUP(avb0_avtp_pps), 2450 SH_PFC_PIN_GROUP(avb0_avtp_capture), 2451 SH_PFC_PIN_GROUP(avb0_avtp_match), 2452 2453 SH_PFC_PIN_GROUP(avb1_link), 2454 SH_PFC_PIN_GROUP(avb1_magic), 2455 SH_PFC_PIN_GROUP(avb1_phy_int), 2456 SH_PFC_PIN_GROUP(avb1_mdio), 2457 SH_PFC_PIN_GROUP(avb1_rgmii), 2458 SH_PFC_PIN_GROUP(avb1_txcrefclk), 2459 SH_PFC_PIN_GROUP(avb1_avtp_pps), 2460 SH_PFC_PIN_GROUP(avb1_avtp_capture), 2461 SH_PFC_PIN_GROUP(avb1_avtp_match), 2462 2463 SH_PFC_PIN_GROUP(avb2_link), 2464 SH_PFC_PIN_GROUP(avb2_magic), 2465 SH_PFC_PIN_GROUP(avb2_phy_int), 2466 SH_PFC_PIN_GROUP(avb2_mdio), 2467 SH_PFC_PIN_GROUP(avb2_rgmii), 2468 SH_PFC_PIN_GROUP(avb2_txcrefclk), 2469 SH_PFC_PIN_GROUP(avb2_avtp_pps), 2470 SH_PFC_PIN_GROUP(avb2_avtp_capture), 2471 SH_PFC_PIN_GROUP(avb2_avtp_match), 2472 2473 SH_PFC_PIN_GROUP(canfd0_data), 2474 SH_PFC_PIN_GROUP(canfd1_data), 2475 SH_PFC_PIN_GROUP(canfd2_data), 2476 SH_PFC_PIN_GROUP(canfd3_data), 2477 SH_PFC_PIN_GROUP(can_clk), 2478 2479 SH_PFC_PIN_GROUP(hscif0_data), 2480 SH_PFC_PIN_GROUP(hscif0_clk), 2481 SH_PFC_PIN_GROUP(hscif0_ctrl), 2482 SH_PFC_PIN_GROUP(hscif1_data_a), 2483 SH_PFC_PIN_GROUP(hscif1_clk_a), 2484 SH_PFC_PIN_GROUP(hscif1_ctrl_a), 2485 SH_PFC_PIN_GROUP(hscif1_data_b), 2486 SH_PFC_PIN_GROUP(hscif1_clk_b), 2487 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 2488 SH_PFC_PIN_GROUP(hscif2_data), 2489 SH_PFC_PIN_GROUP(hscif2_clk), 2490 SH_PFC_PIN_GROUP(hscif2_ctrl), 2491 SH_PFC_PIN_GROUP(hscif3_data_a), 2492 SH_PFC_PIN_GROUP(hscif3_clk_a), 2493 SH_PFC_PIN_GROUP(hscif3_ctrl_a), 2494 SH_PFC_PIN_GROUP(hscif3_data_b), 2495 SH_PFC_PIN_GROUP(hscif3_clk_b), 2496 SH_PFC_PIN_GROUP(hscif3_ctrl_b), 2497 2498 SH_PFC_PIN_GROUP(i2c0), 2499 SH_PFC_PIN_GROUP(i2c1), 2500 SH_PFC_PIN_GROUP(i2c2), 2501 SH_PFC_PIN_GROUP(i2c3), 2502 2503 SH_PFC_PIN_GROUP(intc_ex_irq0_a), 2504 SH_PFC_PIN_GROUP(intc_ex_irq0_b), 2505 SH_PFC_PIN_GROUP(intc_ex_irq1_a), 2506 SH_PFC_PIN_GROUP(intc_ex_irq1_b), 2507 SH_PFC_PIN_GROUP(intc_ex_irq2_a), 2508 SH_PFC_PIN_GROUP(intc_ex_irq2_b), 2509 SH_PFC_PIN_GROUP(intc_ex_irq3_a), 2510 SH_PFC_PIN_GROUP(intc_ex_irq3_b), 2511 SH_PFC_PIN_GROUP(intc_ex_irq4_a), 2512 SH_PFC_PIN_GROUP(intc_ex_irq4_b), 2513 SH_PFC_PIN_GROUP(intc_ex_irq5), 2514 2515 BUS_DATA_PIN_GROUP(mmc_data, 1), 2516 BUS_DATA_PIN_GROUP(mmc_data, 4), 2517 BUS_DATA_PIN_GROUP(mmc_data, 8), 2518 SH_PFC_PIN_GROUP(mmc_ctrl), 2519 SH_PFC_PIN_GROUP(mmc_cd), 2520 SH_PFC_PIN_GROUP(mmc_wp), 2521 SH_PFC_PIN_GROUP(mmc_ds), 2522 2523 SH_PFC_PIN_GROUP(msiof0_clk), 2524 SH_PFC_PIN_GROUP(msiof0_sync), 2525 SH_PFC_PIN_GROUP(msiof0_ss1), 2526 SH_PFC_PIN_GROUP(msiof0_ss2), 2527 SH_PFC_PIN_GROUP(msiof0_txd), 2528 SH_PFC_PIN_GROUP(msiof0_rxd), 2529 2530 SH_PFC_PIN_GROUP(msiof1_clk), 2531 SH_PFC_PIN_GROUP(msiof1_sync), 2532 SH_PFC_PIN_GROUP(msiof1_ss1), 2533 SH_PFC_PIN_GROUP(msiof1_ss2), 2534 SH_PFC_PIN_GROUP(msiof1_txd), 2535 SH_PFC_PIN_GROUP(msiof1_rxd), 2536 2537 SH_PFC_PIN_GROUP(msiof2_clk), 2538 SH_PFC_PIN_GROUP(msiof2_sync), 2539 SH_PFC_PIN_GROUP(msiof2_ss1), 2540 SH_PFC_PIN_GROUP(msiof2_ss2), 2541 SH_PFC_PIN_GROUP(msiof2_txd), 2542 SH_PFC_PIN_GROUP(msiof2_rxd), 2543 2544 SH_PFC_PIN_GROUP(msiof3_clk), 2545 SH_PFC_PIN_GROUP(msiof3_sync), 2546 SH_PFC_PIN_GROUP(msiof3_ss1), 2547 SH_PFC_PIN_GROUP(msiof3_ss2), 2548 SH_PFC_PIN_GROUP(msiof3_txd), 2549 SH_PFC_PIN_GROUP(msiof3_rxd), 2550 2551 SH_PFC_PIN_GROUP(msiof4_clk), 2552 SH_PFC_PIN_GROUP(msiof4_sync), 2553 SH_PFC_PIN_GROUP(msiof4_ss1), 2554 SH_PFC_PIN_GROUP(msiof4_ss2), 2555 SH_PFC_PIN_GROUP(msiof4_txd), 2556 SH_PFC_PIN_GROUP(msiof4_rxd), 2557 2558 SH_PFC_PIN_GROUP(msiof5_clk), 2559 SH_PFC_PIN_GROUP(msiof5_sync), 2560 SH_PFC_PIN_GROUP(msiof5_ss1), 2561 SH_PFC_PIN_GROUP(msiof5_ss2), 2562 SH_PFC_PIN_GROUP(msiof5_txd), 2563 SH_PFC_PIN_GROUP(msiof5_rxd), 2564 2565 SH_PFC_PIN_GROUP(pcie0_clkreq_n), 2566 2567 SH_PFC_PIN_GROUP(pwm0_a), 2568 SH_PFC_PIN_GROUP(pwm0_b), 2569 SH_PFC_PIN_GROUP(pwm1_a), 2570 SH_PFC_PIN_GROUP(pwm1_b), 2571 SH_PFC_PIN_GROUP(pwm1_c), 2572 SH_PFC_PIN_GROUP(pwm2_a), 2573 SH_PFC_PIN_GROUP(pwm2_b), 2574 SH_PFC_PIN_GROUP(pwm2_c), 2575 SH_PFC_PIN_GROUP(pwm3_a), 2576 SH_PFC_PIN_GROUP(pwm3_b), 2577 SH_PFC_PIN_GROUP(pwm3_c), 2578 SH_PFC_PIN_GROUP(pwm4), 2579 2580 SH_PFC_PIN_GROUP(qspi0_ctrl), 2581 BUS_DATA_PIN_GROUP(qspi0_data, 2), 2582 BUS_DATA_PIN_GROUP(qspi0_data, 4), 2583 SH_PFC_PIN_GROUP(qspi1_ctrl), 2584 BUS_DATA_PIN_GROUP(qspi1_data, 2), 2585 BUS_DATA_PIN_GROUP(qspi1_data, 4), 2586 2587 SH_PFC_PIN_GROUP(scif0_data), 2588 SH_PFC_PIN_GROUP(scif0_clk), 2589 SH_PFC_PIN_GROUP(scif0_ctrl), 2590 SH_PFC_PIN_GROUP(scif1_data_a), 2591 SH_PFC_PIN_GROUP(scif1_clk_a), 2592 SH_PFC_PIN_GROUP(scif1_ctrl_a), 2593 SH_PFC_PIN_GROUP(scif1_data_b), 2594 SH_PFC_PIN_GROUP(scif1_clk_b), 2595 SH_PFC_PIN_GROUP(scif1_ctrl_b), 2596 SH_PFC_PIN_GROUP(scif3_data_a), 2597 SH_PFC_PIN_GROUP(scif3_clk_a), 2598 SH_PFC_PIN_GROUP(scif3_ctrl_a), 2599 SH_PFC_PIN_GROUP(scif3_data_b), 2600 SH_PFC_PIN_GROUP(scif3_clk_b), 2601 SH_PFC_PIN_GROUP(scif3_ctrl_b), 2602 SH_PFC_PIN_GROUP(scif4_data), 2603 SH_PFC_PIN_GROUP(scif4_clk), 2604 SH_PFC_PIN_GROUP(scif4_ctrl), 2605 SH_PFC_PIN_GROUP(scif_clk), 2606 SH_PFC_PIN_GROUP(scif_clk2), 2607 2608 SH_PFC_PIN_GROUP(ssi_data), 2609 SH_PFC_PIN_GROUP(ssi_ctrl), 2610 2611 SH_PFC_PIN_GROUP(tpu_to0_a), 2612 SH_PFC_PIN_GROUP(tpu_to0_b), 2613 SH_PFC_PIN_GROUP(tpu_to1_a), 2614 SH_PFC_PIN_GROUP(tpu_to1_b), 2615 SH_PFC_PIN_GROUP(tpu_to2_a), 2616 SH_PFC_PIN_GROUP(tpu_to2_b), 2617 SH_PFC_PIN_GROUP(tpu_to3_a), 2618 SH_PFC_PIN_GROUP(tpu_to3_b), 2619 }; 2620 2621 static const char * const audio_clk_groups[] = { 2622 "audio_clkin", 2623 "audio_clkout", 2624 }; 2625 2626 static const char * const avb0_groups[] = { 2627 "avb0_link", 2628 "avb0_magic", 2629 "avb0_phy_int", 2630 "avb0_mdio", 2631 "avb0_rgmii", 2632 "avb0_txcrefclk", 2633 "avb0_avtp_pps", 2634 "avb0_avtp_capture", 2635 "avb0_avtp_match", 2636 }; 2637 2638 static const char * const avb1_groups[] = { 2639 "avb1_link", 2640 "avb1_magic", 2641 "avb1_phy_int", 2642 "avb1_mdio", 2643 "avb1_rgmii", 2644 "avb1_txcrefclk", 2645 "avb1_avtp_pps", 2646 "avb1_avtp_capture", 2647 "avb1_avtp_match", 2648 }; 2649 2650 static const char * const avb2_groups[] = { 2651 "avb2_link", 2652 "avb2_magic", 2653 "avb2_phy_int", 2654 "avb2_mdio", 2655 "avb2_rgmii", 2656 "avb2_txcrefclk", 2657 "avb2_avtp_pps", 2658 "avb2_avtp_capture", 2659 "avb2_avtp_match", 2660 }; 2661 2662 static const char * const canfd0_groups[] = { 2663 "canfd0_data", 2664 }; 2665 2666 static const char * const canfd1_groups[] = { 2667 "canfd1_data", 2668 }; 2669 2670 static const char * const canfd2_groups[] = { 2671 "canfd2_data", 2672 }; 2673 2674 static const char * const canfd3_groups[] = { 2675 "canfd3_data", 2676 }; 2677 2678 static const char * const can_clk_groups[] = { 2679 "can_clk", 2680 }; 2681 2682 static const char * const hscif0_groups[] = { 2683 "hscif0_data", 2684 "hscif0_clk", 2685 "hscif0_ctrl", 2686 }; 2687 2688 static const char * const hscif1_groups[] = { 2689 "hscif1_data_a", 2690 "hscif1_clk_a", 2691 "hscif1_ctrl_a", 2692 "hscif1_data_b", 2693 "hscif1_clk_b", 2694 "hscif1_ctrl_b", 2695 }; 2696 2697 static const char * const hscif2_groups[] = { 2698 "hscif2_data", 2699 "hscif2_clk", 2700 "hscif2_ctrl", 2701 }; 2702 2703 static const char * const hscif3_groups[] = { 2704 "hscif3_data_a", 2705 "hscif3_clk_a", 2706 "hscif3_ctrl_a", 2707 "hscif3_data_b", 2708 "hscif3_clk_b", 2709 "hscif3_ctrl_b", 2710 }; 2711 2712 static const char * const i2c0_groups[] = { 2713 "i2c0", 2714 }; 2715 2716 static const char * const i2c1_groups[] = { 2717 "i2c1", 2718 }; 2719 2720 static const char * const i2c2_groups[] = { 2721 "i2c2", 2722 }; 2723 2724 static const char * const i2c3_groups[] = { 2725 "i2c3", 2726 }; 2727 2728 static const char * const intc_ex_groups[] = { 2729 "intc_ex_irq0_a", 2730 "intc_ex_irq0_b", 2731 "intc_ex_irq1_a", 2732 "intc_ex_irq1_b", 2733 "intc_ex_irq2_a", 2734 "intc_ex_irq2_b", 2735 "intc_ex_irq3_a", 2736 "intc_ex_irq3_b", 2737 "intc_ex_irq4_a", 2738 "intc_ex_irq4_b", 2739 "intc_ex_irq5", 2740 }; 2741 2742 static const char * const mmc_groups[] = { 2743 "mmc_data1", 2744 "mmc_data4", 2745 "mmc_data8", 2746 "mmc_ctrl", 2747 "mmc_cd", 2748 "mmc_wp", 2749 "mmc_ds", 2750 }; 2751 2752 static const char * const msiof0_groups[] = { 2753 "msiof0_clk", 2754 "msiof0_sync", 2755 "msiof0_ss1", 2756 "msiof0_ss2", 2757 "msiof0_txd", 2758 "msiof0_rxd", 2759 }; 2760 2761 static const char * const msiof1_groups[] = { 2762 "msiof1_clk", 2763 "msiof1_sync", 2764 "msiof1_ss1", 2765 "msiof1_ss2", 2766 "msiof1_txd", 2767 "msiof1_rxd", 2768 }; 2769 2770 static const char * const msiof2_groups[] = { 2771 "msiof2_clk", 2772 "msiof2_sync", 2773 "msiof2_ss1", 2774 "msiof2_ss2", 2775 "msiof2_txd", 2776 "msiof2_rxd", 2777 }; 2778 2779 static const char * const msiof3_groups[] = { 2780 "msiof3_clk", 2781 "msiof3_sync", 2782 "msiof3_ss1", 2783 "msiof3_ss2", 2784 "msiof3_txd", 2785 "msiof3_rxd", 2786 }; 2787 2788 static const char * const msiof4_groups[] = { 2789 "msiof4_clk", 2790 "msiof4_sync", 2791 "msiof4_ss1", 2792 "msiof4_ss2", 2793 "msiof4_txd", 2794 "msiof4_rxd", 2795 }; 2796 2797 static const char * const msiof5_groups[] = { 2798 "msiof5_clk", 2799 "msiof5_sync", 2800 "msiof5_ss1", 2801 "msiof5_ss2", 2802 "msiof5_txd", 2803 "msiof5_rxd", 2804 }; 2805 2806 static const char * const pcie_groups[] = { 2807 "pcie0_clkreq_n", 2808 }; 2809 2810 static const char * const pwm0_groups[] = { 2811 "pwm0_a", 2812 "pwm0_b", 2813 }; 2814 2815 static const char * const pwm1_groups[] = { 2816 "pwm1_a", 2817 "pwm1_b", 2818 "pwm1_c", 2819 }; 2820 2821 static const char * const pwm2_groups[] = { 2822 "pwm2_a", 2823 "pwm2_b", 2824 "pwm2_c", 2825 }; 2826 2827 static const char * const pwm3_groups[] = { 2828 "pwm3_a", 2829 "pwm3_b", 2830 "pwm3_c", 2831 }; 2832 2833 static const char * const pwm4_groups[] = { 2834 "pwm4", 2835 }; 2836 2837 static const char * const qspi0_groups[] = { 2838 "qspi0_ctrl", 2839 "qspi0_data2", 2840 "qspi0_data4", 2841 }; 2842 2843 static const char * const qspi1_groups[] = { 2844 "qspi1_ctrl", 2845 "qspi1_data2", 2846 "qspi1_data4", 2847 }; 2848 2849 static const char * const scif0_groups[] = { 2850 "scif0_data", 2851 "scif0_clk", 2852 "scif0_ctrl", 2853 }; 2854 2855 static const char * const scif1_groups[] = { 2856 "scif1_data_a", 2857 "scif1_clk_a", 2858 "scif1_ctrl_a", 2859 "scif1_data_b", 2860 "scif1_clk_b", 2861 "scif1_ctrl_b", 2862 }; 2863 2864 static const char * const scif3_groups[] = { 2865 "scif3_data_a", 2866 "scif3_clk_a", 2867 "scif3_ctrl_a", 2868 "scif3_data_b", 2869 "scif3_clk_b", 2870 "scif3_ctrl_b", 2871 }; 2872 2873 static const char * const scif4_groups[] = { 2874 "scif4_data", 2875 "scif4_clk", 2876 "scif4_ctrl", 2877 }; 2878 2879 static const char * const scif_clk_groups[] = { 2880 "scif_clk", 2881 }; 2882 2883 static const char * const scif_clk2_groups[] = { 2884 "scif_clk2", 2885 }; 2886 2887 static const char * const ssi_groups[] = { 2888 "ssi_data", 2889 "ssi_ctrl", 2890 }; 2891 2892 static const char * const tpu_groups[] = { 2893 "tpu_to0_a", 2894 "tpu_to0_b", 2895 "tpu_to1_a", 2896 "tpu_to1_b", 2897 "tpu_to2_a", 2898 "tpu_to2_b", 2899 "tpu_to3_a", 2900 "tpu_to3_b", 2901 }; 2902 2903 static const struct sh_pfc_function pinmux_functions[] = { 2904 SH_PFC_FUNCTION(audio_clk), 2905 2906 SH_PFC_FUNCTION(avb0), 2907 SH_PFC_FUNCTION(avb1), 2908 SH_PFC_FUNCTION(avb2), 2909 2910 SH_PFC_FUNCTION(canfd0), 2911 SH_PFC_FUNCTION(canfd1), 2912 SH_PFC_FUNCTION(canfd2), 2913 SH_PFC_FUNCTION(canfd3), 2914 SH_PFC_FUNCTION(can_clk), 2915 2916 SH_PFC_FUNCTION(hscif0), 2917 SH_PFC_FUNCTION(hscif1), 2918 SH_PFC_FUNCTION(hscif2), 2919 SH_PFC_FUNCTION(hscif3), 2920 2921 SH_PFC_FUNCTION(i2c0), 2922 SH_PFC_FUNCTION(i2c1), 2923 SH_PFC_FUNCTION(i2c2), 2924 SH_PFC_FUNCTION(i2c3), 2925 2926 SH_PFC_FUNCTION(intc_ex), 2927 2928 SH_PFC_FUNCTION(mmc), 2929 2930 SH_PFC_FUNCTION(msiof0), 2931 SH_PFC_FUNCTION(msiof1), 2932 SH_PFC_FUNCTION(msiof2), 2933 SH_PFC_FUNCTION(msiof3), 2934 SH_PFC_FUNCTION(msiof4), 2935 SH_PFC_FUNCTION(msiof5), 2936 2937 SH_PFC_FUNCTION(pcie), 2938 2939 SH_PFC_FUNCTION(pwm0), 2940 SH_PFC_FUNCTION(pwm1), 2941 SH_PFC_FUNCTION(pwm2), 2942 SH_PFC_FUNCTION(pwm3), 2943 SH_PFC_FUNCTION(pwm4), 2944 2945 SH_PFC_FUNCTION(qspi0), 2946 SH_PFC_FUNCTION(qspi1), 2947 2948 SH_PFC_FUNCTION(scif0), 2949 SH_PFC_FUNCTION(scif1), 2950 SH_PFC_FUNCTION(scif3), 2951 SH_PFC_FUNCTION(scif4), 2952 SH_PFC_FUNCTION(scif_clk), 2953 SH_PFC_FUNCTION(scif_clk2), 2954 2955 SH_PFC_FUNCTION(ssi), 2956 2957 SH_PFC_FUNCTION(tpu), 2958 }; 2959 2960 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2961 #define F_(x, y) FN_##y 2962 #define FM(x) FN_##x 2963 { PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32, 2964 GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2965 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 2966 GROUP( 2967 /* GP0_31_19 RESERVED */ 2968 GP_0_18_FN, GPSR0_18, 2969 GP_0_17_FN, GPSR0_17, 2970 GP_0_16_FN, GPSR0_16, 2971 GP_0_15_FN, GPSR0_15, 2972 GP_0_14_FN, GPSR0_14, 2973 GP_0_13_FN, GPSR0_13, 2974 GP_0_12_FN, GPSR0_12, 2975 GP_0_11_FN, GPSR0_11, 2976 GP_0_10_FN, GPSR0_10, 2977 GP_0_9_FN, GPSR0_9, 2978 GP_0_8_FN, GPSR0_8, 2979 GP_0_7_FN, GPSR0_7, 2980 GP_0_6_FN, GPSR0_6, 2981 GP_0_5_FN, GPSR0_5, 2982 GP_0_4_FN, GPSR0_4, 2983 GP_0_3_FN, GPSR0_3, 2984 GP_0_2_FN, GPSR0_2, 2985 GP_0_1_FN, GPSR0_1, 2986 GP_0_0_FN, GPSR0_0, )) 2987 }, 2988 { PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP( 2989 0, 0, 2990 0, 0, 2991 GP_1_29_FN, GPSR1_29, 2992 GP_1_28_FN, GPSR1_28, 2993 GP_1_27_FN, GPSR1_27, 2994 GP_1_26_FN, GPSR1_26, 2995 GP_1_25_FN, GPSR1_25, 2996 GP_1_24_FN, GPSR1_24, 2997 GP_1_23_FN, GPSR1_23, 2998 GP_1_22_FN, GPSR1_22, 2999 GP_1_21_FN, GPSR1_21, 3000 GP_1_20_FN, GPSR1_20, 3001 GP_1_19_FN, GPSR1_19, 3002 GP_1_18_FN, GPSR1_18, 3003 GP_1_17_FN, GPSR1_17, 3004 GP_1_16_FN, GPSR1_16, 3005 GP_1_15_FN, GPSR1_15, 3006 GP_1_14_FN, GPSR1_14, 3007 GP_1_13_FN, GPSR1_13, 3008 GP_1_12_FN, GPSR1_12, 3009 GP_1_11_FN, GPSR1_11, 3010 GP_1_10_FN, GPSR1_10, 3011 GP_1_9_FN, GPSR1_9, 3012 GP_1_8_FN, GPSR1_8, 3013 GP_1_7_FN, GPSR1_7, 3014 GP_1_6_FN, GPSR1_6, 3015 GP_1_5_FN, GPSR1_5, 3016 GP_1_4_FN, GPSR1_4, 3017 GP_1_3_FN, GPSR1_3, 3018 GP_1_2_FN, GPSR1_2, 3019 GP_1_1_FN, GPSR1_1, 3020 GP_1_0_FN, GPSR1_0, )) 3021 }, 3022 { PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32, 3023 GROUP(-12, 1, -1, 1, -1, 1, 1, 1, 1, 1, 1, 3024 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3025 GROUP( 3026 /* GP2_31_20 RESERVED */ 3027 GP_2_19_FN, GPSR2_19, 3028 /* GP2_18 RESERVED */ 3029 GP_2_17_FN, GPSR2_17, 3030 /* GP2_16 RESERVED */ 3031 GP_2_15_FN, GPSR2_15, 3032 GP_2_14_FN, GPSR2_14, 3033 GP_2_13_FN, GPSR2_13, 3034 GP_2_12_FN, GPSR2_12, 3035 GP_2_11_FN, GPSR2_11, 3036 GP_2_10_FN, GPSR2_10, 3037 GP_2_9_FN, GPSR2_9, 3038 GP_2_8_FN, GPSR2_8, 3039 GP_2_7_FN, GPSR2_7, 3040 GP_2_6_FN, GPSR2_6, 3041 GP_2_5_FN, GPSR2_5, 3042 GP_2_4_FN, GPSR2_4, 3043 GP_2_3_FN, GPSR2_3, 3044 GP_2_2_FN, GPSR2_2, 3045 GP_2_1_FN, GPSR2_1, 3046 GP_2_0_FN, GPSR2_0, )) 3047 }, 3048 { PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP( 3049 GP_3_31_FN, GPSR3_31, 3050 GP_3_30_FN, GPSR3_30, 3051 GP_3_29_FN, GPSR3_29, 3052 GP_3_28_FN, GPSR3_28, 3053 GP_3_27_FN, GPSR3_27, 3054 GP_3_26_FN, GPSR3_26, 3055 GP_3_25_FN, GPSR3_25, 3056 GP_3_24_FN, GPSR3_24, 3057 GP_3_23_FN, GPSR3_23, 3058 GP_3_22_FN, GPSR3_22, 3059 GP_3_21_FN, GPSR3_21, 3060 GP_3_20_FN, GPSR3_20, 3061 GP_3_19_FN, GPSR3_19, 3062 GP_3_18_FN, GPSR3_18, 3063 GP_3_17_FN, GPSR3_17, 3064 GP_3_16_FN, GPSR3_16, 3065 GP_3_15_FN, GPSR3_15, 3066 GP_3_14_FN, GPSR3_14, 3067 GP_3_13_FN, GPSR3_13, 3068 GP_3_12_FN, GPSR3_12, 3069 GP_3_11_FN, GPSR3_11, 3070 GP_3_10_FN, GPSR3_10, 3071 GP_3_9_FN, GPSR3_9, 3072 GP_3_8_FN, GPSR3_8, 3073 GP_3_7_FN, GPSR3_7, 3074 GP_3_6_FN, GPSR3_6, 3075 GP_3_5_FN, GPSR3_5, 3076 GP_3_4_FN, GPSR3_4, 3077 GP_3_3_FN, GPSR3_3, 3078 GP_3_2_FN, GPSR3_2, 3079 GP_3_1_FN, GPSR3_1, 3080 GP_3_0_FN, GPSR3_0, )) 3081 }, 3082 { PINMUX_CFG_REG_VAR("GPSR4", 0xE6060040, 32, 3083 GROUP(-7, 1, 1, -1, 1, -5, 1, 1, 1, 1, 1, 3084 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3085 GROUP( 3086 /* GP4_31_25 RESERVED */ 3087 GP_4_24_FN, GPSR4_24, 3088 GP_4_23_FN, GPSR4_23, 3089 /* GP4_22 RESERVED */ 3090 GP_4_21_FN, GPSR4_21, 3091 /* GP4_20_16 RESERVED */ 3092 GP_4_15_FN, GPSR4_15, 3093 GP_4_14_FN, GPSR4_14, 3094 GP_4_13_FN, GPSR4_13, 3095 GP_4_12_FN, GPSR4_12, 3096 GP_4_11_FN, GPSR4_11, 3097 GP_4_10_FN, GPSR4_10, 3098 GP_4_9_FN, GPSR4_9, 3099 GP_4_8_FN, GPSR4_8, 3100 GP_4_7_FN, GPSR4_7, 3101 GP_4_6_FN, GPSR4_6, 3102 GP_4_5_FN, GPSR4_5, 3103 GP_4_4_FN, GPSR4_4, 3104 GP_4_3_FN, GPSR4_3, 3105 GP_4_2_FN, GPSR4_2, 3106 GP_4_1_FN, GPSR4_1, 3107 GP_4_0_FN, GPSR4_0, )) 3108 }, 3109 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32, 3110 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3111 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3112 GROUP( 3113 /* GP5_31_21 RESERVED */ 3114 GP_5_20_FN, GPSR5_20, 3115 GP_5_19_FN, GPSR5_19, 3116 GP_5_18_FN, GPSR5_18, 3117 GP_5_17_FN, GPSR5_17, 3118 GP_5_16_FN, GPSR5_16, 3119 GP_5_15_FN, GPSR5_15, 3120 GP_5_14_FN, GPSR5_14, 3121 GP_5_13_FN, GPSR5_13, 3122 GP_5_12_FN, GPSR5_12, 3123 GP_5_11_FN, GPSR5_11, 3124 GP_5_10_FN, GPSR5_10, 3125 GP_5_9_FN, GPSR5_9, 3126 GP_5_8_FN, GPSR5_8, 3127 GP_5_7_FN, GPSR5_7, 3128 GP_5_6_FN, GPSR5_6, 3129 GP_5_5_FN, GPSR5_5, 3130 GP_5_4_FN, GPSR5_4, 3131 GP_5_3_FN, GPSR5_3, 3132 GP_5_2_FN, GPSR5_2, 3133 GP_5_1_FN, GPSR5_1, 3134 GP_5_0_FN, GPSR5_0, )) 3135 }, 3136 { PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32, 3137 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3138 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3139 GROUP( 3140 /* GP6_31_21 RESERVED */ 3141 GP_6_20_FN, GPSR6_20, 3142 GP_6_19_FN, GPSR6_19, 3143 GP_6_18_FN, GPSR6_18, 3144 GP_6_17_FN, GPSR6_17, 3145 GP_6_16_FN, GPSR6_16, 3146 GP_6_15_FN, GPSR6_15, 3147 GP_6_14_FN, GPSR6_14, 3148 GP_6_13_FN, GPSR6_13, 3149 GP_6_12_FN, GPSR6_12, 3150 GP_6_11_FN, GPSR6_11, 3151 GP_6_10_FN, GPSR6_10, 3152 GP_6_9_FN, GPSR6_9, 3153 GP_6_8_FN, GPSR6_8, 3154 GP_6_7_FN, GPSR6_7, 3155 GP_6_6_FN, GPSR6_6, 3156 GP_6_5_FN, GPSR6_5, 3157 GP_6_4_FN, GPSR6_4, 3158 GP_6_3_FN, GPSR6_3, 3159 GP_6_2_FN, GPSR6_2, 3160 GP_6_1_FN, GPSR6_1, 3161 GP_6_0_FN, GPSR6_0, )) 3162 }, 3163 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32, 3164 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3165 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), 3166 GROUP( 3167 /* GP7_31_21 RESERVED */ 3168 GP_7_20_FN, GPSR7_20, 3169 GP_7_19_FN, GPSR7_19, 3170 GP_7_18_FN, GPSR7_18, 3171 GP_7_17_FN, GPSR7_17, 3172 GP_7_16_FN, GPSR7_16, 3173 GP_7_15_FN, GPSR7_15, 3174 GP_7_14_FN, GPSR7_14, 3175 GP_7_13_FN, GPSR7_13, 3176 GP_7_12_FN, GPSR7_12, 3177 GP_7_11_FN, GPSR7_11, 3178 GP_7_10_FN, GPSR7_10, 3179 GP_7_9_FN, GPSR7_9, 3180 GP_7_8_FN, GPSR7_8, 3181 GP_7_7_FN, GPSR7_7, 3182 GP_7_6_FN, GPSR7_6, 3183 GP_7_5_FN, GPSR7_5, 3184 GP_7_4_FN, GPSR7_4, 3185 GP_7_3_FN, GPSR7_3, 3186 GP_7_2_FN, GPSR7_2, 3187 GP_7_1_FN, GPSR7_1, 3188 GP_7_0_FN, GPSR7_0, )) 3189 }, 3190 #undef F_ 3191 #undef FM 3192 3193 #define F_(x, y) x, 3194 #define FM(x) FN_##x, 3195 { PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP( 3196 IP0SR0_31_28 3197 IP0SR0_27_24 3198 IP0SR0_23_20 3199 IP0SR0_19_16 3200 IP0SR0_15_12 3201 IP0SR0_11_8 3202 IP0SR0_7_4 3203 IP0SR0_3_0)) 3204 }, 3205 { PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP( 3206 IP1SR0_31_28 3207 IP1SR0_27_24 3208 IP1SR0_23_20 3209 IP1SR0_19_16 3210 IP1SR0_15_12 3211 IP1SR0_11_8 3212 IP1SR0_7_4 3213 IP1SR0_3_0)) 3214 }, 3215 { PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32, 3216 GROUP(-20, 4, 4, 4), 3217 GROUP( 3218 /* IP2SR0_31_12 RESERVED */ 3219 IP2SR0_11_8 3220 IP2SR0_7_4 3221 IP2SR0_3_0)) 3222 }, 3223 { PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP( 3224 IP0SR1_31_28 3225 IP0SR1_27_24 3226 IP0SR1_23_20 3227 IP0SR1_19_16 3228 IP0SR1_15_12 3229 IP0SR1_11_8 3230 IP0SR1_7_4 3231 IP0SR1_3_0)) 3232 }, 3233 { PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP( 3234 IP1SR1_31_28 3235 IP1SR1_27_24 3236 IP1SR1_23_20 3237 IP1SR1_19_16 3238 IP1SR1_15_12 3239 IP1SR1_11_8 3240 IP1SR1_7_4 3241 IP1SR1_3_0)) 3242 }, 3243 { PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP( 3244 IP2SR1_31_28 3245 IP2SR1_27_24 3246 IP2SR1_23_20 3247 IP2SR1_19_16 3248 IP2SR1_15_12 3249 IP2SR1_11_8 3250 IP2SR1_7_4 3251 IP2SR1_3_0)) 3252 }, 3253 { PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32, 3254 GROUP(-8, 4, 4, 4, 4, 4, 4), 3255 GROUP( 3256 /* IP3SR1_31_24 RESERVED */ 3257 IP3SR1_23_20 3258 IP3SR1_19_16 3259 IP3SR1_15_12 3260 IP3SR1_11_8 3261 IP3SR1_7_4 3262 IP3SR1_3_0)) 3263 }, 3264 { PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP( 3265 IP0SR2_31_28 3266 IP0SR2_27_24 3267 IP0SR2_23_20 3268 IP0SR2_19_16 3269 IP0SR2_15_12 3270 IP0SR2_11_8 3271 IP0SR2_7_4 3272 IP0SR2_3_0)) 3273 }, 3274 { PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP( 3275 IP1SR2_31_28 3276 IP1SR2_27_24 3277 IP1SR2_23_20 3278 IP1SR2_19_16 3279 IP1SR2_15_12 3280 IP1SR2_11_8 3281 IP1SR2_7_4 3282 IP1SR2_3_0)) 3283 }, 3284 { PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32, 3285 GROUP(-16, 4, -4, 4, -4), 3286 GROUP( 3287 /* IP2SR2_31_16 RESERVED */ 3288 IP2SR2_15_12 3289 /* IP2SR2_11_8 RESERVED */ 3290 IP2SR2_7_4 3291 /* IP2SR2_3_0 RESERVED */)) 3292 }, 3293 { PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP( 3294 IP0SR3_31_28 3295 IP0SR3_27_24 3296 IP0SR3_23_20 3297 IP0SR3_19_16 3298 IP0SR3_15_12 3299 IP0SR3_11_8 3300 IP0SR3_7_4 3301 IP0SR3_3_0)) 3302 }, 3303 { PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP( 3304 IP1SR3_31_28 3305 IP1SR3_27_24 3306 IP1SR3_23_20 3307 IP1SR3_19_16 3308 IP1SR3_15_12 3309 IP1SR3_11_8 3310 IP1SR3_7_4 3311 IP1SR3_3_0)) 3312 }, 3313 { PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP( 3314 IP2SR3_31_28 3315 IP2SR3_27_24 3316 IP2SR3_23_20 3317 IP2SR3_19_16 3318 IP2SR3_15_12 3319 IP2SR3_11_8 3320 IP2SR3_7_4 3321 IP2SR3_3_0)) 3322 }, 3323 { PINMUX_CFG_REG("IP3SR3", 0xE605886C, 32, 4, GROUP( 3324 IP3SR3_31_28 3325 IP3SR3_27_24 3326 IP3SR3_23_20 3327 IP3SR3_19_16 3328 IP3SR3_15_12 3329 IP3SR3_11_8 3330 IP3SR3_7_4 3331 IP3SR3_3_0)) 3332 }, 3333 { PINMUX_CFG_REG("IP0SR4", 0xE6060060, 32, 4, GROUP( 3334 IP0SR4_31_28 3335 IP0SR4_27_24 3336 IP0SR4_23_20 3337 IP0SR4_19_16 3338 IP0SR4_15_12 3339 IP0SR4_11_8 3340 IP0SR4_7_4 3341 IP0SR4_3_0)) 3342 }, 3343 { PINMUX_CFG_REG("IP1SR4", 0xE6060064, 32, 4, GROUP( 3344 IP1SR4_31_28 3345 IP1SR4_27_24 3346 IP1SR4_23_20 3347 IP1SR4_19_16 3348 IP1SR4_15_12 3349 IP1SR4_11_8 3350 IP1SR4_7_4 3351 IP1SR4_3_0)) 3352 }, 3353 { PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32, 3354 GROUP(4, -4, 4, -20), 3355 GROUP( 3356 IP2SR4_31_28 3357 /* IP2SR4_27_24 RESERVED */ 3358 IP2SR4_23_20 3359 /* IP2SR4_19_0 RESERVED */)) 3360 }, 3361 { PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32, 3362 GROUP(-28, 4), 3363 GROUP( 3364 /* IP3SR4_31_4 RESERVED */ 3365 IP3SR4_3_0)) 3366 }, 3367 { PINMUX_CFG_REG("IP0SR5", 0xE6060860, 32, 4, GROUP( 3368 IP0SR5_31_28 3369 IP0SR5_27_24 3370 IP0SR5_23_20 3371 IP0SR5_19_16 3372 IP0SR5_15_12 3373 IP0SR5_11_8 3374 IP0SR5_7_4 3375 IP0SR5_3_0)) 3376 }, 3377 { PINMUX_CFG_REG("IP1SR5", 0xE6060864, 32, 4, GROUP( 3378 IP1SR5_31_28 3379 IP1SR5_27_24 3380 IP1SR5_23_20 3381 IP1SR5_19_16 3382 IP1SR5_15_12 3383 IP1SR5_11_8 3384 IP1SR5_7_4 3385 IP1SR5_3_0)) 3386 }, 3387 { PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32, 3388 GROUP(-12, 4, 4, 4, 4, 4), 3389 GROUP( 3390 /* IP2SR5_31_20 RESERVED */ 3391 IP2SR5_19_16 3392 IP2SR5_15_12 3393 IP2SR5_11_8 3394 IP2SR5_7_4 3395 IP2SR5_3_0)) 3396 }, 3397 { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP( 3398 IP0SR6_31_28 3399 IP0SR6_27_24 3400 IP0SR6_23_20 3401 IP0SR6_19_16 3402 IP0SR6_15_12 3403 IP0SR6_11_8 3404 IP0SR6_7_4 3405 IP0SR6_3_0)) 3406 }, 3407 { PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP( 3408 IP1SR6_31_28 3409 IP1SR6_27_24 3410 IP1SR6_23_20 3411 IP1SR6_19_16 3412 IP1SR6_15_12 3413 IP1SR6_11_8 3414 IP1SR6_7_4 3415 IP1SR6_3_0)) 3416 }, 3417 { PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32, 3418 GROUP(-12, 4, 4, 4, 4, 4), 3419 GROUP( 3420 /* IP2SR6_31_20 RESERVED */ 3421 IP2SR6_19_16 3422 IP2SR6_15_12 3423 IP2SR6_11_8 3424 IP2SR6_7_4 3425 IP2SR6_3_0)) 3426 }, 3427 { PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP( 3428 IP0SR7_31_28 3429 IP0SR7_27_24 3430 IP0SR7_23_20 3431 IP0SR7_19_16 3432 IP0SR7_15_12 3433 IP0SR7_11_8 3434 IP0SR7_7_4 3435 IP0SR7_3_0)) 3436 }, 3437 { PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP( 3438 IP1SR7_31_28 3439 IP1SR7_27_24 3440 IP1SR7_23_20 3441 IP1SR7_19_16 3442 IP1SR7_15_12 3443 IP1SR7_11_8 3444 IP1SR7_7_4 3445 IP1SR7_3_0)) 3446 }, 3447 { PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32, 3448 GROUP(-12, 4, 4, 4, 4, 4), 3449 GROUP( 3450 /* IP2SR7_31_20 RESERVED */ 3451 IP2SR7_19_16 3452 IP2SR7_15_12 3453 IP2SR7_11_8 3454 IP2SR7_7_4 3455 IP2SR7_3_0)) 3456 }, 3457 #undef F_ 3458 #undef FM 3459 3460 #define F_(x, y) x, 3461 #define FM(x) FN_##x, 3462 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE6060100, 32, 3463 GROUP(-24, 1, 1, 1, 1, 1, 1, 1, 1), 3464 GROUP( 3465 /* RESERVED 31-8 */ 3466 MOD_SEL4_7 3467 MOD_SEL4_6 3468 MOD_SEL4_5 3469 MOD_SEL4_4 3470 MOD_SEL4_3 3471 MOD_SEL4_2 3472 MOD_SEL4_1 3473 MOD_SEL4_0)) 3474 }, 3475 { }, 3476 }; 3477 3478 static const struct pinmux_drive_reg pinmux_drive_regs[] = { 3479 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) { 3480 { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */ 3481 { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */ 3482 { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */ 3483 { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */ 3484 { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */ 3485 { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */ 3486 { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */ 3487 { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */ 3488 } }, 3489 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) { 3490 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */ 3491 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */ 3492 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */ 3493 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */ 3494 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */ 3495 { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */ 3496 { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */ 3497 { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */ 3498 } }, 3499 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) { 3500 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */ 3501 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */ 3502 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */ 3503 } }, 3504 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) { 3505 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */ 3506 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */ 3507 { RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */ 3508 { RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */ 3509 { RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */ 3510 { RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */ 3511 { RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */ 3512 { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */ 3513 } }, 3514 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) { 3515 { RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */ 3516 { RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */ 3517 { RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */ 3518 { RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */ 3519 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */ 3520 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */ 3521 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */ 3522 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */ 3523 } }, 3524 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) { 3525 { RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */ 3526 { RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */ 3527 { RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */ 3528 { RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */ 3529 { RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */ 3530 { RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */ 3531 { RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */ 3532 { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */ 3533 } }, 3534 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) { 3535 { RCAR_GP_PIN(1, 29), 20, 2 }, /* ERROROUTC_N */ 3536 { RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */ 3537 { RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */ 3538 { RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */ 3539 { RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */ 3540 { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */ 3541 } }, 3542 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) { 3543 { RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */ 3544 { RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */ 3545 { RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */ 3546 { RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */ 3547 { RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */ 3548 { RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */ 3549 { RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */ 3550 { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */ 3551 } }, 3552 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) { 3553 { RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */ 3554 { RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */ 3555 { RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */ 3556 { RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */ 3557 { RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */ 3558 { RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */ 3559 { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */ 3560 { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */ 3561 } }, 3562 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) { 3563 { RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD1_RX */ 3564 { RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD1_TX */ 3565 } }, 3566 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) { 3567 { RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */ 3568 { RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */ 3569 { RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */ 3570 { RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */ 3571 { RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */ 3572 { RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */ 3573 { RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */ 3574 { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */ 3575 } }, 3576 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) { 3577 { RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */ 3578 { RCAR_GP_PIN(3, 14), 24, 2 }, /* PWM2 */ 3579 { RCAR_GP_PIN(3, 13), 20, 2 }, /* PWM1 */ 3580 { RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */ 3581 { RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */ 3582 { RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */ 3583 { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/ 3584 { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */ 3585 } }, 3586 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) { 3587 { RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */ 3588 { RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */ 3589 { RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */ 3590 { RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */ 3591 { RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */ 3592 { RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */ 3593 { RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */ 3594 { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */ 3595 } }, 3596 { PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) { 3597 { RCAR_GP_PIN(3, 31), 28, 2 }, /* TCLK4 */ 3598 { RCAR_GP_PIN(3, 30), 24, 2 }, /* TCLK3 */ 3599 { RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */ 3600 { RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */ 3601 { RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */ 3602 { RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */ 3603 { RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */ 3604 { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */ 3605 } }, 3606 { PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) { 3607 { RCAR_GP_PIN(4, 7), 28, 3 }, /* SDA3 */ 3608 { RCAR_GP_PIN(4, 6), 24, 3 }, /* SCL3 */ 3609 { RCAR_GP_PIN(4, 5), 20, 3 }, /* SDA2 */ 3610 { RCAR_GP_PIN(4, 4), 16, 3 }, /* SCL2 */ 3611 { RCAR_GP_PIN(4, 3), 12, 3 }, /* SDA1 */ 3612 { RCAR_GP_PIN(4, 2), 8, 3 }, /* SCL1 */ 3613 { RCAR_GP_PIN(4, 1), 4, 3 }, /* SDA0 */ 3614 { RCAR_GP_PIN(4, 0), 0, 3 }, /* SCL0 */ 3615 } }, 3616 { PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) { 3617 { RCAR_GP_PIN(4, 15), 28, 3 }, /* PWM4 */ 3618 { RCAR_GP_PIN(4, 14), 24, 3 }, /* PWM3 */ 3619 { RCAR_GP_PIN(4, 13), 20, 3 }, /* HSCK2 */ 3620 { RCAR_GP_PIN(4, 12), 16, 3 }, /* HCTS2_N */ 3621 { RCAR_GP_PIN(4, 11), 12, 3 }, /* SCIF_CLK2 */ 3622 { RCAR_GP_PIN(4, 10), 8, 3 }, /* HRTS2_N */ 3623 { RCAR_GP_PIN(4, 9), 4, 3 }, /* HTX2 */ 3624 { RCAR_GP_PIN(4, 8), 0, 3 }, /* HRX2 */ 3625 } }, 3626 { PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) { 3627 { RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */ 3628 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */ 3629 } }, 3630 { PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) { 3631 { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */ 3632 } }, 3633 { PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) { 3634 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */ 3635 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */ 3636 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */ 3637 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */ 3638 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */ 3639 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */ 3640 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */ 3641 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */ 3642 } }, 3643 { PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) { 3644 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */ 3645 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */ 3646 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */ 3647 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */ 3648 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */ 3649 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */ 3650 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */ 3651 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */ 3652 } }, 3653 { PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) { 3654 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */ 3655 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */ 3656 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */ 3657 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */ 3658 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */ 3659 } }, 3660 { PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) { 3661 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */ 3662 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */ 3663 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */ 3664 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */ 3665 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */ 3666 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */ 3667 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */ 3668 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */ 3669 } }, 3670 { PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) { 3671 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */ 3672 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */ 3673 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */ 3674 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */ 3675 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */ 3676 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */ 3677 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */ 3678 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */ 3679 } }, 3680 { PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) { 3681 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */ 3682 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */ 3683 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */ 3684 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */ 3685 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */ 3686 } }, 3687 { PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) { 3688 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */ 3689 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */ 3690 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */ 3691 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */ 3692 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */ 3693 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */ 3694 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */ 3695 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */ 3696 } }, 3697 { PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) { 3698 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */ 3699 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */ 3700 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */ 3701 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */ 3702 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */ 3703 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */ 3704 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */ 3705 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */ 3706 } }, 3707 { PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) { 3708 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */ 3709 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */ 3710 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */ 3711 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */ 3712 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */ 3713 } }, 3714 { }, 3715 }; 3716 3717 enum ioctrl_regs { 3718 POC0, 3719 POC1, 3720 POC3, 3721 POC4, 3722 POC5, 3723 POC6, 3724 POC7, 3725 }; 3726 3727 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 3728 [POC0] = { 0xE60500A0, }, 3729 [POC1] = { 0xE60508A0, }, 3730 [POC3] = { 0xE60588A0, }, 3731 [POC4] = { 0xE60600A0, }, 3732 [POC5] = { 0xE60608A0, }, 3733 [POC6] = { 0xE60610A0, }, 3734 [POC7] = { 0xE60618A0, }, 3735 { /* sentinel */ }, 3736 }; 3737 3738 static int r8a779h0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) 3739 { 3740 int bit = pin & 0x1f; 3741 3742 switch (pin) { 3743 case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18): 3744 *pocctrl = pinmux_ioctrl_regs[POC0].reg; 3745 return bit; 3746 3747 case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 28): 3748 *pocctrl = pinmux_ioctrl_regs[POC1].reg; 3749 return bit; 3750 3751 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12): 3752 *pocctrl = pinmux_ioctrl_regs[POC3].reg; 3753 return bit; 3754 3755 case RCAR_GP_PIN(4, 0) ... RCAR_GP_PIN(4, 13): 3756 *pocctrl = pinmux_ioctrl_regs[POC4].reg; 3757 return bit; 3758 3759 case PIN_VDDQ_AVB2: 3760 *pocctrl = pinmux_ioctrl_regs[POC5].reg; 3761 return 0; 3762 3763 case PIN_VDDQ_AVB1: 3764 *pocctrl = pinmux_ioctrl_regs[POC6].reg; 3765 return 0; 3766 3767 case PIN_VDDQ_AVB0: 3768 *pocctrl = pinmux_ioctrl_regs[POC7].reg; 3769 return 0; 3770 3771 default: 3772 return -EINVAL; 3773 } 3774 } 3775 3776 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 3777 { PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) { 3778 [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */ 3779 [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */ 3780 [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */ 3781 [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */ 3782 [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */ 3783 [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */ 3784 [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */ 3785 [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */ 3786 [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */ 3787 [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */ 3788 [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */ 3789 [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */ 3790 [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */ 3791 [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */ 3792 [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */ 3793 [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */ 3794 [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */ 3795 [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */ 3796 [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */ 3797 [19] = SH_PFC_PIN_NONE, 3798 [20] = SH_PFC_PIN_NONE, 3799 [21] = SH_PFC_PIN_NONE, 3800 [22] = SH_PFC_PIN_NONE, 3801 [23] = SH_PFC_PIN_NONE, 3802 [24] = SH_PFC_PIN_NONE, 3803 [25] = SH_PFC_PIN_NONE, 3804 [26] = SH_PFC_PIN_NONE, 3805 [27] = SH_PFC_PIN_NONE, 3806 [28] = SH_PFC_PIN_NONE, 3807 [29] = SH_PFC_PIN_NONE, 3808 [30] = SH_PFC_PIN_NONE, 3809 [31] = SH_PFC_PIN_NONE, 3810 } }, 3811 { PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) { 3812 [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */ 3813 [ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */ 3814 [ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */ 3815 [ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */ 3816 [ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */ 3817 [ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */ 3818 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */ 3819 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */ 3820 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */ 3821 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */ 3822 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */ 3823 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */ 3824 [12] = RCAR_GP_PIN(1, 12), /* HTX0 */ 3825 [13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */ 3826 [14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */ 3827 [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */ 3828 [16] = RCAR_GP_PIN(1, 16), /* HRX0 */ 3829 [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */ 3830 [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */ 3831 [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */ 3832 [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */ 3833 [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */ 3834 [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */ 3835 [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */ 3836 [24] = RCAR_GP_PIN(1, 24), /* HRX3 */ 3837 [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */ 3838 [26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */ 3839 [27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */ 3840 [28] = RCAR_GP_PIN(1, 28), /* HTX3 */ 3841 [29] = RCAR_GP_PIN(1, 29), /* ERROROUTC_N */ 3842 [30] = SH_PFC_PIN_NONE, 3843 [31] = SH_PFC_PIN_NONE, 3844 } }, 3845 { PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) { 3846 [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */ 3847 [ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */ 3848 [ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */ 3849 [ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */ 3850 [ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */ 3851 [ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */ 3852 [ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */ 3853 [ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */ 3854 [ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */ 3855 [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */ 3856 [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */ 3857 [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */ 3858 [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */ 3859 [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */ 3860 [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */ 3861 [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */ 3862 [16] = SH_PFC_PIN_NONE, 3863 [17] = RCAR_GP_PIN(2, 17), /* CANFD1_TX */ 3864 [18] = SH_PFC_PIN_NONE, 3865 [19] = RCAR_GP_PIN(2, 19), /* CANFD1_RX */ 3866 [20] = SH_PFC_PIN_NONE, 3867 [21] = SH_PFC_PIN_NONE, 3868 [22] = SH_PFC_PIN_NONE, 3869 [23] = SH_PFC_PIN_NONE, 3870 [24] = SH_PFC_PIN_NONE, 3871 [25] = SH_PFC_PIN_NONE, 3872 [26] = SH_PFC_PIN_NONE, 3873 [27] = SH_PFC_PIN_NONE, 3874 [28] = SH_PFC_PIN_NONE, 3875 [29] = SH_PFC_PIN_NONE, 3876 [30] = SH_PFC_PIN_NONE, 3877 [31] = SH_PFC_PIN_NONE, 3878 } }, 3879 { PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) { 3880 [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */ 3881 [ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */ 3882 [ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */ 3883 [ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */ 3884 [ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */ 3885 [ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */ 3886 [ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */ 3887 [ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */ 3888 [ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */ 3889 [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */ 3890 [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */ 3891 [11] = RCAR_GP_PIN(3, 11), /* SD_CD */ 3892 [12] = RCAR_GP_PIN(3, 12), /* SD_WP */ 3893 [13] = RCAR_GP_PIN(3, 13), /* PWM1 */ 3894 [14] = RCAR_GP_PIN(3, 14), /* PWM2 */ 3895 [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */ 3896 [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */ 3897 [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */ 3898 [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */ 3899 [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */ 3900 [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */ 3901 [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */ 3902 [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */ 3903 [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */ 3904 [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */ 3905 [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */ 3906 [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */ 3907 [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */ 3908 [28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */ 3909 [29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */ 3910 [30] = RCAR_GP_PIN(3, 30), /* TCLK3 */ 3911 [31] = RCAR_GP_PIN(3, 31), /* TCLK4 */ 3912 } }, 3913 { PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) { 3914 [ 0] = RCAR_GP_PIN(4, 0), /* SCL0 */ 3915 [ 1] = RCAR_GP_PIN(4, 1), /* SDA0 */ 3916 [ 2] = RCAR_GP_PIN(4, 2), /* SCL1 */ 3917 [ 3] = RCAR_GP_PIN(4, 3), /* SDA1 */ 3918 [ 4] = RCAR_GP_PIN(4, 4), /* SCL2 */ 3919 [ 5] = RCAR_GP_PIN(4, 5), /* SDA2 */ 3920 [ 6] = RCAR_GP_PIN(4, 6), /* SCL3 */ 3921 [ 7] = RCAR_GP_PIN(4, 7), /* SDA3 */ 3922 [ 8] = RCAR_GP_PIN(4, 8), /* HRX2 */ 3923 [ 9] = RCAR_GP_PIN(4, 9), /* HTX2 */ 3924 [10] = RCAR_GP_PIN(4, 10), /* HRTS2_N */ 3925 [11] = RCAR_GP_PIN(4, 11), /* SCIF_CLK2 */ 3926 [12] = RCAR_GP_PIN(4, 12), /* HCTS2_N */ 3927 [13] = RCAR_GP_PIN(4, 13), /* HSCK2 */ 3928 [14] = RCAR_GP_PIN(4, 14), /* PWM3 */ 3929 [15] = RCAR_GP_PIN(4, 15), /* PWM4 */ 3930 [16] = SH_PFC_PIN_NONE, 3931 [17] = SH_PFC_PIN_NONE, 3932 [18] = SH_PFC_PIN_NONE, 3933 [19] = SH_PFC_PIN_NONE, 3934 [20] = SH_PFC_PIN_NONE, 3935 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */ 3936 [22] = SH_PFC_PIN_NONE, 3937 [23] = RCAR_GP_PIN(4, 23), /* AVS0 */ 3938 [24] = RCAR_GP_PIN(4, 24), /* AVS1 */ 3939 [25] = SH_PFC_PIN_NONE, 3940 [26] = SH_PFC_PIN_NONE, 3941 [27] = SH_PFC_PIN_NONE, 3942 [28] = SH_PFC_PIN_NONE, 3943 [29] = SH_PFC_PIN_NONE, 3944 [30] = SH_PFC_PIN_NONE, 3945 [31] = SH_PFC_PIN_NONE, 3946 } }, 3947 { PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) { 3948 [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */ 3949 [ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */ 3950 [ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */ 3951 [ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */ 3952 [ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */ 3953 [ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */ 3954 [ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */ 3955 [ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */ 3956 [ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */ 3957 [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */ 3958 [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */ 3959 [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */ 3960 [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */ 3961 [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */ 3962 [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */ 3963 [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */ 3964 [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */ 3965 [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */ 3966 [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */ 3967 [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */ 3968 [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */ 3969 [21] = SH_PFC_PIN_NONE, 3970 [22] = SH_PFC_PIN_NONE, 3971 [23] = SH_PFC_PIN_NONE, 3972 [24] = SH_PFC_PIN_NONE, 3973 [25] = SH_PFC_PIN_NONE, 3974 [26] = SH_PFC_PIN_NONE, 3975 [27] = SH_PFC_PIN_NONE, 3976 [28] = SH_PFC_PIN_NONE, 3977 [29] = SH_PFC_PIN_NONE, 3978 [30] = SH_PFC_PIN_NONE, 3979 [31] = SH_PFC_PIN_NONE, 3980 } }, 3981 { PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) { 3982 [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */ 3983 [ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */ 3984 [ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */ 3985 [ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */ 3986 [ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */ 3987 [ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */ 3988 [ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */ 3989 [ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */ 3990 [ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */ 3991 [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */ 3992 [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */ 3993 [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */ 3994 [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */ 3995 [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */ 3996 [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/ 3997 [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */ 3998 [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */ 3999 [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */ 4000 [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */ 4001 [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */ 4002 [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */ 4003 [21] = SH_PFC_PIN_NONE, 4004 [22] = SH_PFC_PIN_NONE, 4005 [23] = SH_PFC_PIN_NONE, 4006 [24] = SH_PFC_PIN_NONE, 4007 [25] = SH_PFC_PIN_NONE, 4008 [26] = SH_PFC_PIN_NONE, 4009 [27] = SH_PFC_PIN_NONE, 4010 [28] = SH_PFC_PIN_NONE, 4011 [29] = SH_PFC_PIN_NONE, 4012 [30] = SH_PFC_PIN_NONE, 4013 [31] = SH_PFC_PIN_NONE, 4014 } }, 4015 { PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) { 4016 [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */ 4017 [ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */ 4018 [ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */ 4019 [ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */ 4020 [ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */ 4021 [ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */ 4022 [ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */ 4023 [ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */ 4024 [ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */ 4025 [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */ 4026 [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */ 4027 [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */ 4028 [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */ 4029 [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */ 4030 [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */ 4031 [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */ 4032 [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */ 4033 [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */ 4034 [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */ 4035 [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */ 4036 [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */ 4037 [21] = SH_PFC_PIN_NONE, 4038 [22] = SH_PFC_PIN_NONE, 4039 [23] = SH_PFC_PIN_NONE, 4040 [24] = SH_PFC_PIN_NONE, 4041 [25] = SH_PFC_PIN_NONE, 4042 [26] = SH_PFC_PIN_NONE, 4043 [27] = SH_PFC_PIN_NONE, 4044 [28] = SH_PFC_PIN_NONE, 4045 [29] = SH_PFC_PIN_NONE, 4046 [30] = SH_PFC_PIN_NONE, 4047 [31] = SH_PFC_PIN_NONE, 4048 } }, 4049 { /* sentinel */ }, 4050 }; 4051 4052 static const struct sh_pfc_soc_operations r8a779h0_pin_ops = { 4053 .pin_to_pocctrl = r8a779h0_pin_to_pocctrl, 4054 .get_bias = rcar_pinmux_get_bias, 4055 .set_bias = rcar_pinmux_set_bias, 4056 }; 4057 4058 const struct sh_pfc_soc_info r8a779h0_pinmux_info = { 4059 .name = "r8a779h0_pfc", 4060 .ops = &r8a779h0_pin_ops, 4061 .unlock_reg = 0x1ff, /* PMMRn mask */ 4062 4063 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 4064 4065 .pins = pinmux_pins, 4066 .nr_pins = ARRAY_SIZE(pinmux_pins), 4067 .groups = pinmux_groups, 4068 .nr_groups = ARRAY_SIZE(pinmux_groups), 4069 .functions = pinmux_functions, 4070 .nr_functions = ARRAY_SIZE(pinmux_functions), 4071 4072 .cfg_regs = pinmux_config_regs, 4073 .drive_regs = pinmux_drive_regs, 4074 .bias_regs = pinmux_bias_regs, 4075 .ioctrl_regs = pinmux_ioctrl_regs, 4076 4077 .pinmux_data = pinmux_data, 4078 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 4079 }; 4080