1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77995 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2017 Renesas Electronics Corp. 6 * 7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c 8 * 9 * R-Car Gen3 processor support - PFC hardware block. 10 * 11 * Copyright (C) 2015 Renesas Electronics Corporation 12 */ 13 14 #include <linux/errno.h> 15 #include <linux/kernel.h> 16 17 #include "sh_pfc.h" 18 19 #define CPU_ALL_GP(fn, sfx) \ 20 PORT_GP_9(0, fn, sfx), \ 21 PORT_GP_32(1, fn, sfx), \ 22 PORT_GP_32(2, fn, sfx), \ 23 PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ 24 PORT_GP_32(4, fn, sfx), \ 25 PORT_GP_21(5, fn, sfx), \ 26 PORT_GP_14(6, fn, sfx) 27 28 /* 29 * F_() : just information 30 * FM() : macro for FN_xxx / xxx_MARK 31 */ 32 33 /* GPSR0 */ 34 #define GPSR0_8 F_(MLB_SIG, IP0_27_24) 35 #define GPSR0_7 F_(MLB_DAT, IP0_23_20) 36 #define GPSR0_6 F_(MLB_CLK, IP0_19_16) 37 #define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12) 38 #define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8) 39 #define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4) 40 #define GPSR0_2 F_(IRQ0_A, IP0_3_0) 41 #define GPSR0_1 FM(USB0_OVC) 42 #define GPSR0_0 FM(USB0_PWEN) 43 44 /* GPSR1 */ 45 #define GPSR1_31 F_(QPOLB, IP4_27_24) 46 #define GPSR1_30 F_(QPOLA, IP4_23_20) 47 #define GPSR1_29 F_(DU_CDE, IP4_19_16) 48 #define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12) 49 #define GPSR1_27 F_(DU_DISP, IP4_11_8) 50 #define GPSR1_26 F_(DU_VSYNC, IP4_7_4) 51 #define GPSR1_25 F_(DU_HSYNC, IP4_3_0) 52 #define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28) 53 #define GPSR1_23 F_(DU_DR7, IP3_27_24) 54 #define GPSR1_22 F_(DU_DR6, IP3_23_20) 55 #define GPSR1_21 F_(DU_DR5, IP3_19_16) 56 #define GPSR1_20 F_(DU_DR4, IP3_15_12) 57 #define GPSR1_19 F_(DU_DR3, IP3_11_8) 58 #define GPSR1_18 F_(DU_DR2, IP3_7_4) 59 #define GPSR1_17 F_(DU_DR1, IP3_3_0) 60 #define GPSR1_16 F_(DU_DR0, IP2_31_28) 61 #define GPSR1_15 F_(DU_DG7, IP2_27_24) 62 #define GPSR1_14 F_(DU_DG6, IP2_23_20) 63 #define GPSR1_13 F_(DU_DG5, IP2_19_16) 64 #define GPSR1_12 F_(DU_DG4, IP2_15_12) 65 #define GPSR1_11 F_(DU_DG3, IP2_11_8) 66 #define GPSR1_10 F_(DU_DG2, IP2_7_4) 67 #define GPSR1_9 F_(DU_DG1, IP2_3_0) 68 #define GPSR1_8 F_(DU_DG0, IP1_31_28) 69 #define GPSR1_7 F_(DU_DB7, IP1_27_24) 70 #define GPSR1_6 F_(DU_DB6, IP1_23_20) 71 #define GPSR1_5 F_(DU_DB5, IP1_19_16) 72 #define GPSR1_4 F_(DU_DB4, IP1_15_12) 73 #define GPSR1_3 F_(DU_DB3, IP1_11_8) 74 #define GPSR1_2 F_(DU_DB2, IP1_7_4) 75 #define GPSR1_1 F_(DU_DB1, IP1_3_0) 76 #define GPSR1_0 F_(DU_DB0, IP0_31_28) 77 78 /* GPSR2 */ 79 #define GPSR2_31 F_(NFCE_N, IP8_19_16) 80 #define GPSR2_30 F_(NFCLE, IP8_15_12) 81 #define GPSR2_29 F_(NFALE, IP8_11_8) 82 #define GPSR2_28 F_(VI4_CLKENB, IP8_7_4) 83 #define GPSR2_27 F_(VI4_FIELD, IP8_3_0) 84 #define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28) 85 #define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24) 86 #define GPSR2_24 F_(VI4_DATA23, IP7_23_20) 87 #define GPSR2_23 F_(VI4_DATA22, IP7_19_16) 88 #define GPSR2_22 F_(VI4_DATA21, IP7_15_12) 89 #define GPSR2_21 F_(VI4_DATA20, IP7_11_8) 90 #define GPSR2_20 F_(VI4_DATA19, IP7_7_4) 91 #define GPSR2_19 F_(VI4_DATA18, IP7_3_0) 92 #define GPSR2_18 F_(VI4_DATA17, IP6_31_28) 93 #define GPSR2_17 F_(VI4_DATA16, IP6_27_24) 94 #define GPSR2_16 F_(VI4_DATA15, IP6_23_20) 95 #define GPSR2_15 F_(VI4_DATA14, IP6_19_16) 96 #define GPSR2_14 F_(VI4_DATA13, IP6_15_12) 97 #define GPSR2_13 F_(VI4_DATA12, IP6_11_8) 98 #define GPSR2_12 F_(VI4_DATA11, IP6_7_4) 99 #define GPSR2_11 F_(VI4_DATA10, IP6_3_0) 100 #define GPSR2_10 F_(VI4_DATA9, IP5_31_28) 101 #define GPSR2_9 F_(VI4_DATA8, IP5_27_24) 102 #define GPSR2_8 F_(VI4_DATA7, IP5_23_20) 103 #define GPSR2_7 F_(VI4_DATA6, IP5_19_16) 104 #define GPSR2_6 F_(VI4_DATA5, IP5_15_12) 105 #define GPSR2_5 FM(VI4_DATA4) 106 #define GPSR2_4 F_(VI4_DATA3, IP5_11_8) 107 #define GPSR2_3 F_(VI4_DATA2, IP5_7_4) 108 #define GPSR2_2 F_(VI4_DATA1, IP5_3_0) 109 #define GPSR2_1 F_(VI4_DATA0, IP4_31_28) 110 #define GPSR2_0 FM(VI4_CLK) 111 112 /* GPSR3 */ 113 #define GPSR3_9 F_(NFDATA7, IP9_31_28) 114 #define GPSR3_8 F_(NFDATA6, IP9_27_24) 115 #define GPSR3_7 F_(NFDATA5, IP9_23_20) 116 #define GPSR3_6 F_(NFDATA4, IP9_19_16) 117 #define GPSR3_5 F_(NFDATA3, IP9_15_12) 118 #define GPSR3_4 F_(NFDATA2, IP9_11_8) 119 #define GPSR3_3 F_(NFDATA1, IP9_7_4) 120 #define GPSR3_2 F_(NFDATA0, IP9_3_0) 121 #define GPSR3_1 F_(NFWE_N, IP8_31_28) 122 #define GPSR3_0 F_(NFRE_N, IP8_27_24) 123 124 /* GPSR4 */ 125 #define GPSR4_31 F_(CAN0_RX_A, IP12_27_24) 126 #define GPSR4_30 F_(CAN1_TX_A, IP13_7_4) 127 #define GPSR4_29 F_(CAN1_RX_A, IP13_3_0) 128 #define GPSR4_28 F_(CAN0_TX_A, IP12_31_28) 129 #define GPSR4_27 FM(TX2) 130 #define GPSR4_26 FM(RX2) 131 #define GPSR4_25 F_(SCK2, IP12_11_8) 132 #define GPSR4_24 F_(TX1_A, IP12_7_4) 133 #define GPSR4_23 F_(RX1_A, IP12_3_0) 134 #define GPSR4_22 F_(SCK1_A, IP11_31_28) 135 #define GPSR4_21 F_(TX0_A, IP11_27_24) 136 #define GPSR4_20 F_(RX0_A, IP11_23_20) 137 #define GPSR4_19 F_(SCK0_A, IP11_19_16) 138 #define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12) 139 #define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8) 140 #define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4) 141 #define GPSR4_15 FM(MSIOF0_RXD) 142 #define GPSR4_14 FM(MSIOF0_TXD) 143 #define GPSR4_13 FM(MSIOF0_SYNC) 144 #define GPSR4_12 FM(MSIOF0_SCK) 145 #define GPSR4_11 F_(SDA1, IP11_3_0) 146 #define GPSR4_10 F_(SCL1, IP10_31_28) 147 #define GPSR4_9 FM(SDA0) 148 #define GPSR4_8 FM(SCL0) 149 #define GPSR4_7 F_(SSI_WS4_A, IP10_27_24) 150 #define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20) 151 #define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16) 152 #define GPSR4_4 F_(SSI_WS34, IP10_15_12) 153 #define GPSR4_3 F_(SSI_SDATA3, IP10_11_8) 154 #define GPSR4_2 F_(SSI_SCK34, IP10_7_4) 155 #define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0) 156 #define GPSR4_0 F_(NFRB_N, IP8_23_20) 157 158 /* GPSR5 */ 159 #define GPSR5_20 FM(AVB0_LINK) 160 #define GPSR5_19 FM(AVB0_PHY_INT) 161 #define GPSR5_18 FM(AVB0_MAGIC) 162 #define GPSR5_17 FM(AVB0_MDC) 163 #define GPSR5_16 FM(AVB0_MDIO) 164 #define GPSR5_15 FM(AVB0_TXCREFCLK) 165 #define GPSR5_14 FM(AVB0_TD3) 166 #define GPSR5_13 FM(AVB0_TD2) 167 #define GPSR5_12 FM(AVB0_TD1) 168 #define GPSR5_11 FM(AVB0_TD0) 169 #define GPSR5_10 FM(AVB0_TXC) 170 #define GPSR5_9 FM(AVB0_TX_CTL) 171 #define GPSR5_8 FM(AVB0_RD3) 172 #define GPSR5_7 FM(AVB0_RD2) 173 #define GPSR5_6 FM(AVB0_RD1) 174 #define GPSR5_5 FM(AVB0_RD0) 175 #define GPSR5_4 FM(AVB0_RXC) 176 #define GPSR5_3 FM(AVB0_RX_CTL) 177 #define GPSR5_2 F_(CAN_CLK, IP12_23_20) 178 #define GPSR5_1 F_(TPU0TO1_A, IP12_19_16) 179 #define GPSR5_0 F_(TPU0TO0_A, IP12_15_12) 180 181 /* GPSR6 */ 182 #define GPSR6_13 FM(RPC_INT_N) 183 #define GPSR6_12 FM(RPC_RESET_N) 184 #define GPSR6_11 FM(QSPI1_SSL) 185 #define GPSR6_10 FM(QSPI1_IO3) 186 #define GPSR6_9 FM(QSPI1_IO2) 187 #define GPSR6_8 FM(QSPI1_MISO_IO1) 188 #define GPSR6_7 FM(QSPI1_MOSI_IO0) 189 #define GPSR6_6 FM(QSPI1_SPCLK) 190 #define GPSR6_5 FM(QSPI0_SSL) 191 #define GPSR6_4 FM(QSPI0_IO3) 192 #define GPSR6_3 FM(QSPI0_IO2) 193 #define GPSR6_2 FM(QSPI0_MISO_IO1) 194 #define GPSR6_1 FM(QSPI0_MOSI_IO0) 195 #define GPSR6_0 FM(QSPI0_SPCLK) 196 197 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 198 #define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 199 #define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 200 #define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 201 #define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 202 #define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 203 #define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 204 #define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 205 #define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 206 #define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 207 #define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 208 #define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 209 #define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 210 #define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 211 #define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 212 #define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 213 #define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 214 #define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215 #define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216 #define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 217 #define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 218 #define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 219 #define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220 #define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221 #define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222 #define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223 #define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224 #define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 225 #define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 226 #define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 227 #define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 228 #define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 229 #define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 230 231 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 232 #define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 233 #define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 234 #define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 235 #define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 236 #define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 237 #define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 238 #define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 239 #define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 240 #define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 241 #define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 242 #define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 243 #define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 244 #define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 245 #define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 246 #define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 247 #define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 248 #define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 249 #define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 250 #define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 251 #define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 252 #define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 253 #define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 254 #define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 255 #define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 256 #define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 257 #define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258 #define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259 #define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260 #define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 265 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 266 #define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 #define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274 #define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275 #define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276 #define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 #define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 #define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 #define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284 #define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285 #define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286 #define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287 #define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 288 #define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 289 #define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290 #define IP11_3_0 FM(SDA1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291 #define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 299 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 300 #define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301 #define IP12_7_4 FM(TX1_A) FM(RTS0_N) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302 #define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303 #define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 #define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306 #define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307 #define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 #define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309 #define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310 311 #define PINMUX_GPSR \ 312 \ 313 GPSR1_31 GPSR2_31 GPSR4_31 \ 314 GPSR1_30 GPSR2_30 GPSR4_30 \ 315 GPSR1_29 GPSR2_29 GPSR4_29 \ 316 GPSR1_28 GPSR2_28 GPSR4_28 \ 317 GPSR1_27 GPSR2_27 GPSR4_27 \ 318 GPSR1_26 GPSR2_26 GPSR4_26 \ 319 GPSR1_25 GPSR2_25 GPSR4_25 \ 320 GPSR1_24 GPSR2_24 GPSR4_24 \ 321 GPSR1_23 GPSR2_23 GPSR4_23 \ 322 GPSR1_22 GPSR2_22 GPSR4_22 \ 323 GPSR1_21 GPSR2_21 GPSR4_21 \ 324 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \ 325 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \ 326 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \ 327 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \ 328 GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \ 329 GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \ 330 GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \ 331 GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \ 332 GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \ 333 GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \ 334 GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 335 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 336 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 337 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 338 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 339 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 340 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 341 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \ 342 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \ 343 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \ 344 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 345 346 #define PINMUX_IPSR \ 347 \ 348 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 349 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 350 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 351 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 352 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 353 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 354 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 355 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 356 \ 357 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 358 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 359 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 360 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ 361 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 362 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 363 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 364 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 365 \ 366 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 367 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 368 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 369 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 370 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 371 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 372 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 373 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 374 \ 375 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \ 376 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \ 377 FM(IP12_11_8) IP12_11_8 \ 378 FM(IP12_15_12) IP12_15_12 \ 379 FM(IP12_19_16) IP12_19_16 \ 380 FM(IP12_23_20) IP12_23_20 \ 381 FM(IP12_27_24) IP12_27_24 \ 382 FM(IP12_31_28) IP12_31_28 \ 383 384 /* The bit numbering in MOD_SEL fields is reversed */ 385 #define REV4(f0, f1, f2, f3) f0 f2 f1 f3 386 387 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ 388 #define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) 389 #define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1) 390 #define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 391 #define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) 392 #define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) 393 #define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) 394 #define MOD_SEL0_24_23 REV4(FM(SEL_PWM0_0), FM(SEL_PWM0_1), FM(SEL_PWM0_2), F_(0, 0)) 395 #define MOD_SEL0_22_21 REV4(FM(SEL_PWM1_0), FM(SEL_PWM1_1), FM(SEL_PWM1_2), F_(0, 0)) 396 #define MOD_SEL0_20_19 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0)) 397 #define MOD_SEL0_18_17 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0)) 398 #define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1) 399 #define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1) 400 #define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1) 401 #define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1) 402 #define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1) 403 #define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1) 404 #define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1) 405 #define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1) 406 #define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 407 #define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 408 #define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1) 409 #define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1) 410 411 #define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1) 412 #define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1) 413 #define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1) 414 #define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 415 #define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) 416 #define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1) 417 418 419 #define PINMUX_MOD_SELS \ 420 \ 421 MOD_SEL1_31 \ 422 MOD_SEL0_30 MOD_SEL1_30 \ 423 MOD_SEL0_29 MOD_SEL1_29 \ 424 MOD_SEL0_28 MOD_SEL1_28 \ 425 MOD_SEL0_27 MOD_SEL1_27 \ 426 MOD_SEL0_26 MOD_SEL1_26 \ 427 MOD_SEL0_25 \ 428 MOD_SEL0_24_23 \ 429 MOD_SEL0_22_21 \ 430 MOD_SEL0_20_19 \ 431 MOD_SEL0_18_17 \ 432 MOD_SEL0_15 \ 433 MOD_SEL0_14 \ 434 MOD_SEL0_13 \ 435 MOD_SEL0_12 \ 436 MOD_SEL0_11 \ 437 MOD_SEL0_10 \ 438 MOD_SEL0_5 \ 439 MOD_SEL0_4 \ 440 MOD_SEL0_3 \ 441 MOD_SEL0_2 \ 442 MOD_SEL0_1 \ 443 MOD_SEL0_0 444 445 enum { 446 PINMUX_RESERVED = 0, 447 448 PINMUX_DATA_BEGIN, 449 GP_ALL(DATA), 450 PINMUX_DATA_END, 451 452 #define F_(x, y) 453 #define FM(x) FN_##x, 454 PINMUX_FUNCTION_BEGIN, 455 GP_ALL(FN), 456 PINMUX_GPSR 457 PINMUX_IPSR 458 PINMUX_MOD_SELS 459 PINMUX_FUNCTION_END, 460 #undef F_ 461 #undef FM 462 463 #define F_(x, y) 464 #define FM(x) x##_MARK, 465 PINMUX_MARK_BEGIN, 466 PINMUX_GPSR 467 PINMUX_IPSR 468 PINMUX_MOD_SELS 469 PINMUX_MARK_END, 470 #undef F_ 471 #undef FM 472 }; 473 474 static const u16 pinmux_data[] = { 475 PINMUX_DATA_GP_ALL(), 476 477 PINMUX_SINGLE(USB0_OVC), 478 PINMUX_SINGLE(USB0_PWEN), 479 PINMUX_SINGLE(VI4_DATA4), 480 PINMUX_SINGLE(VI4_CLK), 481 PINMUX_SINGLE(TX2), 482 PINMUX_SINGLE(RX2), 483 PINMUX_SINGLE(AVB0_LINK), 484 PINMUX_SINGLE(AVB0_PHY_INT), 485 PINMUX_SINGLE(AVB0_MAGIC), 486 PINMUX_SINGLE(AVB0_MDC), 487 PINMUX_SINGLE(AVB0_MDIO), 488 PINMUX_SINGLE(AVB0_TXCREFCLK), 489 PINMUX_SINGLE(AVB0_TD3), 490 PINMUX_SINGLE(AVB0_TD2), 491 PINMUX_SINGLE(AVB0_TD1), 492 PINMUX_SINGLE(AVB0_TD0), 493 PINMUX_SINGLE(AVB0_TXC), 494 PINMUX_SINGLE(AVB0_TX_CTL), 495 PINMUX_SINGLE(AVB0_RD3), 496 PINMUX_SINGLE(AVB0_RD2), 497 PINMUX_SINGLE(AVB0_RD1), 498 PINMUX_SINGLE(AVB0_RD0), 499 PINMUX_SINGLE(AVB0_RXC), 500 PINMUX_SINGLE(AVB0_RX_CTL), 501 PINMUX_SINGLE(RPC_INT_N), 502 PINMUX_SINGLE(RPC_RESET_N), 503 PINMUX_SINGLE(QSPI1_SSL), 504 PINMUX_SINGLE(QSPI1_IO3), 505 PINMUX_SINGLE(QSPI1_IO2), 506 PINMUX_SINGLE(QSPI1_MISO_IO1), 507 PINMUX_SINGLE(QSPI1_MOSI_IO0), 508 PINMUX_SINGLE(QSPI1_SPCLK), 509 PINMUX_SINGLE(QSPI0_SSL), 510 PINMUX_SINGLE(QSPI0_IO3), 511 PINMUX_SINGLE(QSPI0_IO2), 512 PINMUX_SINGLE(QSPI0_MISO_IO1), 513 PINMUX_SINGLE(QSPI0_MOSI_IO0), 514 PINMUX_SINGLE(QSPI0_SPCLK), 515 PINMUX_SINGLE(SCL0), 516 PINMUX_SINGLE(SDA0), 517 PINMUX_SINGLE(MSIOF0_RXD), 518 PINMUX_SINGLE(MSIOF0_TXD), 519 PINMUX_SINGLE(MSIOF0_SYNC), 520 PINMUX_SINGLE(MSIOF0_SCK), 521 522 /* IPSR0 */ 523 PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0), 524 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 525 526 PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK), 527 528 PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD), 529 PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0), 530 531 PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD), 532 PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0), 533 534 PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK), 535 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0), 536 PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0), 537 538 PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT), 539 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1), 540 PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0), 541 PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1), 542 543 PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG), 544 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2), 545 PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0), 546 PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1), 547 548 PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0), 549 PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0), 550 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1), 551 552 /* IPSR1 */ 553 PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1), 554 PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1), 555 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1), 556 557 PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2), 558 PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2), 559 PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1), 560 561 PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3), 562 PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3), 563 PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1), 564 565 PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4), 566 PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4), 567 PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1), 568 569 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5), 570 PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5), 571 PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1), 572 573 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6), 574 PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6), 575 PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1), 576 577 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7), 578 PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7), 579 PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1), 580 581 PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0), 582 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8), 583 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1), 584 585 /* IPSR2 */ 586 PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1), 587 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9), 588 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1), 589 590 PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2), 591 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10), 592 593 PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3), 594 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11), 595 PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0), 596 597 PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4), 598 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12), 599 PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1), 600 601 PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5), 602 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13), 603 PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1), 604 605 PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6), 606 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14), 607 PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1), 608 609 PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7), 610 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15), 611 PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1), 612 613 PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0), 614 PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16), 615 PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1), 616 617 /* IPSR3 */ 618 PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1), 619 PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17), 620 PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1), 621 622 PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2), 623 PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18), 624 PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2), 625 626 PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3), 627 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19), 628 PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2), 629 630 PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4), 631 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20), 632 PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1), 633 634 PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5), 635 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21), 636 PINMUX_IPSR_GPSR(IP3_19_16, NMI), 637 638 PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6), 639 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22), 640 PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2), 641 642 PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7), 643 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23), 644 PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1), 645 646 PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0), 647 PINMUX_IPSR_GPSR(IP3_31_28, QCLK), 648 649 /* IPSR4 */ 650 PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC), 651 PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS), 652 PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0), 653 654 PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC), 655 PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS), 656 PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0), 657 658 PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP), 659 PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE), 660 PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2), 661 662 PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE), 663 PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE), 664 PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1), 665 PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1), 666 667 PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE), 668 PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE), 669 PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1), 670 671 PINMUX_IPSR_GPSR(IP4_23_20, QPOLA), 672 PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1), 673 674 PINMUX_IPSR_GPSR(IP4_27_24, QPOLB), 675 PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1), 676 677 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0), 678 PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0), 679 680 /* IPSR5 */ 681 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1), 682 PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0), 683 684 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2), 685 PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0), 686 687 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3), 688 PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0), 689 690 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5), 691 PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0), 692 693 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6), 694 PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0), 695 696 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7), 697 PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0), 698 699 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8), 700 701 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9), 702 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0), 703 PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1), 704 705 /* IPSR6 */ 706 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10), 707 PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0), 708 709 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11), 710 PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0), 711 712 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12), 713 PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0), 714 715 PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13), 716 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0), 717 PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N), 718 719 PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14), 720 PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1), 721 PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N), 722 723 PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15), 724 PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1), 725 726 PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16), 727 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0), 728 729 PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17), 730 PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0), 731 732 /* IPSR7 */ 733 PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18), 734 PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0), 735 736 PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19), 737 PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1), 738 PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15), 739 740 PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20), 741 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0), 742 PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14), 743 744 PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21), 745 PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0), 746 747 PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13), 748 PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22), 749 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0), 750 751 PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12), 752 PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23), 753 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0), 754 755 PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11), 756 757 PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N), 758 PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1), 759 PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10), 760 761 PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N), 762 PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1), 763 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9), 764 765 /* IPSR8 */ 766 PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD), 767 PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB), 768 PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0), 769 PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK), 770 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8), 771 772 PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB), 773 PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1), 774 PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N), 775 PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0), 776 777 PINMUX_IPSR_GPSR(IP8_11_8, NFALE), 778 PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1), 779 PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1), 780 PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1), 781 782 PINMUX_IPSR_GPSR(IP8_15_12, NFCLE), 783 PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1), 784 PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0), 785 PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1), 786 787 PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N), 788 PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0), 789 PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1), 790 791 PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N), 792 PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0), 793 PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1), 794 795 PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N), 796 PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD), 797 798 PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N), 799 PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK), 800 801 /* IPSR9 */ 802 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0), 803 PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0), 804 805 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1), 806 PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1), 807 808 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2), 809 PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2), 810 811 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3), 812 PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3), 813 814 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4), 815 PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4), 816 817 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5), 818 PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5), 819 820 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6), 821 PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6), 822 823 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7), 824 PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7), 825 826 /* IPSR10 */ 827 PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA), 828 PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1), 829 830 PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34), 831 PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0), 832 833 PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3), 834 PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0), 835 836 PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34), 837 PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0), 838 839 PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0), 840 PINMUX_IPSR_GPSR(IP10_19_16, HSCK0), 841 PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT), 842 PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1), 843 PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1), 844 845 PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0), 846 PINMUX_IPSR_GPSR(IP10_23_20, HTX0), 847 PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0), 848 PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1), 849 850 PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0), 851 PINMUX_IPSR_GPSR(IP10_27_24, HRX0), 852 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0), 853 PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1), 854 855 PINMUX_IPSR_GPSR(IP10_31_28, SCL1), 856 PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N), 857 858 /* IPSR11 */ 859 PINMUX_IPSR_GPSR(IP11_3_0, SDA1), 860 PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N), 861 862 PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK), 863 PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1), 864 865 PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD), 866 PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1), 867 868 PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD), 869 PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1), 870 871 PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0), 872 PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC), 873 PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1), 874 875 PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0), 876 PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1), 877 PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1), 878 879 PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0), 880 PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2), 881 PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1), 882 883 PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0), 884 PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2), 885 PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B), 886 PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1), 887 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1), 888 889 /* IPSR12 */ 890 PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0), 891 PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N), 892 PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B), 893 894 PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0), 895 PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N), 896 PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B), 897 898 PINMUX_IPSR_GPSR(IP12_11_8, SCK2), 899 PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1), 900 PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B), 901 902 PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A), 903 PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0), 904 PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N), 905 906 PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A), 907 PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0), 908 PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N), 909 910 PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK), 911 PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0), 912 PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1), 913 PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1), 914 915 PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0), 916 PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX), 917 PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1), 918 919 PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0), 920 PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX), 921 PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1), 922 923 /* IPSR13 */ 924 PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0), 925 PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX), 926 PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A), 927 928 PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0), 929 PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX), 930 PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A), 931 }; 932 933 static const struct sh_pfc_pin pinmux_pins[] = { 934 PINMUX_GPIO_GP_ALL(), 935 }; 936 937 /* - AUDIO CLOCK ------------------------------------------------------------- */ 938 static const unsigned int audio_clk_a_pins[] = { 939 /* CLK A */ 940 RCAR_GP_PIN(4, 1), 941 }; 942 static const unsigned int audio_clk_a_mux[] = { 943 AUDIO_CLKA_MARK, 944 }; 945 static const unsigned int audio_clk_b_pins[] = { 946 /* CLK B */ 947 RCAR_GP_PIN(2, 27), 948 }; 949 static const unsigned int audio_clk_b_mux[] = { 950 AUDIO_CLKB_MARK, 951 }; 952 static const unsigned int audio_clkout_pins[] = { 953 /* CLKOUT */ 954 RCAR_GP_PIN(4, 5), 955 }; 956 static const unsigned int audio_clkout_mux[] = { 957 AUDIO_CLKOUT_MARK, 958 }; 959 static const unsigned int audio_clkout1_pins[] = { 960 /* CLKOUT1 */ 961 RCAR_GP_PIN(4, 22), 962 }; 963 static const unsigned int audio_clkout1_mux[] = { 964 AUDIO_CLKOUT1_MARK, 965 }; 966 967 /* - EtherAVB --------------------------------------------------------------- */ 968 static const unsigned int avb0_link_pins[] = { 969 /* AVB0_LINK */ 970 RCAR_GP_PIN(5, 20), 971 }; 972 static const unsigned int avb0_link_mux[] = { 973 AVB0_LINK_MARK, 974 }; 975 static const unsigned int avb0_magic_pins[] = { 976 /* AVB0_MAGIC */ 977 RCAR_GP_PIN(5, 18), 978 }; 979 static const unsigned int avb0_magic_mux[] = { 980 AVB0_MAGIC_MARK, 981 }; 982 static const unsigned int avb0_phy_int_pins[] = { 983 /* AVB0_PHY_INT */ 984 RCAR_GP_PIN(5, 19), 985 }; 986 static const unsigned int avb0_phy_int_mux[] = { 987 AVB0_PHY_INT_MARK, 988 }; 989 static const unsigned int avb0_mdio_pins[] = { 990 /* AVB0_MDC, AVB0_MDIO */ 991 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16), 992 }; 993 static const unsigned int avb0_mdio_mux[] = { 994 AVB0_MDC_MARK, AVB0_MDIO_MARK, 995 }; 996 static const unsigned int avb0_mii_pins[] = { 997 /* 998 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, 999 * AVB0_TD1, AVB0_TD2, AVB0_TD3, 1000 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, 1001 * AVB0_RD1, AVB0_RD2, AVB0_RD3, 1002 * AVB0_TXCREFCLK 1003 */ 1004 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), 1005 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 1006 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), 1007 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), 1008 RCAR_GP_PIN(5, 15), 1009 }; 1010 static const unsigned int avb0_mii_mux[] = { 1011 AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK, 1012 AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK, 1013 AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK, 1014 AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK, 1015 AVB0_TXCREFCLK_MARK, 1016 }; 1017 static const unsigned int avb0_avtp_pps_a_pins[] = { 1018 /* AVB0_AVTP_PPS_A */ 1019 RCAR_GP_PIN(5, 2), 1020 }; 1021 static const unsigned int avb0_avtp_pps_a_mux[] = { 1022 AVB0_AVTP_PPS_A_MARK, 1023 }; 1024 static const unsigned int avb0_avtp_match_a_pins[] = { 1025 /* AVB0_AVTP_MATCH_A */ 1026 RCAR_GP_PIN(5, 1), 1027 }; 1028 static const unsigned int avb0_avtp_match_a_mux[] = { 1029 AVB0_AVTP_MATCH_A_MARK, 1030 }; 1031 static const unsigned int avb0_avtp_capture_a_pins[] = { 1032 /* AVB0_AVTP_CAPTURE_A */ 1033 RCAR_GP_PIN(5, 0), 1034 }; 1035 static const unsigned int avb0_avtp_capture_a_mux[] = { 1036 AVB0_AVTP_CAPTURE_A_MARK, 1037 }; 1038 static const unsigned int avb0_avtp_pps_b_pins[] = { 1039 /* AVB0_AVTP_PPS_B */ 1040 RCAR_GP_PIN(4, 16), 1041 }; 1042 static const unsigned int avb0_avtp_pps_b_mux[] = { 1043 AVB0_AVTP_PPS_B_MARK, 1044 }; 1045 static const unsigned int avb0_avtp_match_b_pins[] = { 1046 /* AVB0_AVTP_MATCH_B */ 1047 RCAR_GP_PIN(4, 18), 1048 }; 1049 static const unsigned int avb0_avtp_match_b_mux[] = { 1050 AVB0_AVTP_MATCH_B_MARK, 1051 }; 1052 static const unsigned int avb0_avtp_capture_b_pins[] = { 1053 /* AVB0_AVTP_CAPTURE_B */ 1054 RCAR_GP_PIN(4, 17), 1055 }; 1056 static const unsigned int avb0_avtp_capture_b_mux[] = { 1057 AVB0_AVTP_CAPTURE_B_MARK, 1058 }; 1059 1060 /* - CAN ------------------------------------------------------------------ */ 1061 static const unsigned int can0_data_a_pins[] = { 1062 /* TX, RX */ 1063 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31), 1064 }; 1065 static const unsigned int can0_data_a_mux[] = { 1066 CAN0_TX_A_MARK, CAN0_RX_A_MARK, 1067 }; 1068 static const unsigned int can0_data_b_pins[] = { 1069 /* TX, RX */ 1070 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5), 1071 }; 1072 static const unsigned int can0_data_b_mux[] = { 1073 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1074 }; 1075 static const unsigned int can1_data_a_pins[] = { 1076 /* TX, RX */ 1077 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29), 1078 }; 1079 static const unsigned int can1_data_a_mux[] = { 1080 CAN1_TX_A_MARK, CAN1_RX_A_MARK, 1081 }; 1082 static const unsigned int can1_data_b_pins[] = { 1083 /* TX, RX */ 1084 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), 1085 }; 1086 static const unsigned int can1_data_b_mux[] = { 1087 CAN1_TX_B_MARK, CAN1_RX_B_MARK, 1088 }; 1089 1090 /* - CAN Clock -------------------------------------------------------------- */ 1091 static const unsigned int can_clk_pins[] = { 1092 /* CLK */ 1093 RCAR_GP_PIN(5, 2), 1094 }; 1095 static const unsigned int can_clk_mux[] = { 1096 CAN_CLK_MARK, 1097 }; 1098 1099 /* - CAN FD ----------------------------------------------------------------- */ 1100 static const unsigned int canfd0_data_pins[] = { 1101 /* TX, RX */ 1102 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31), 1103 }; 1104 static const unsigned int canfd0_data_mux[] = { 1105 CANFD0_TX_MARK, CANFD0_RX_MARK, 1106 }; 1107 static const unsigned int canfd1_data_pins[] = { 1108 /* TX, RX */ 1109 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29), 1110 }; 1111 static const unsigned int canfd1_data_mux[] = { 1112 CANFD1_TX_MARK, CANFD1_RX_MARK, 1113 }; 1114 1115 /* - DU --------------------------------------------------------------------- */ 1116 static const unsigned int du_rgb666_pins[] = { 1117 /* R[7:2], G[7:2], B[7:2] */ 1118 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), 1119 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 1120 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 1121 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), 1122 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 1123 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 1124 }; 1125 static const unsigned int du_rgb666_mux[] = { 1126 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 1127 DU_DR3_MARK, DU_DR2_MARK, 1128 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 1129 DU_DG3_MARK, DU_DG2_MARK, 1130 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 1131 DU_DB3_MARK, DU_DB2_MARK, 1132 }; 1133 static const unsigned int du_rgb888_pins[] = { 1134 /* R[7:0], G[7:0], B[7:0] */ 1135 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), 1136 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 1137 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 1138 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 1139 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), 1140 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), 1141 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 1142 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 1143 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 1144 }; 1145 static const unsigned int du_rgb888_mux[] = { 1146 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 1147 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 1148 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 1149 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 1150 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 1151 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 1152 }; 1153 static const unsigned int du_clk_in_1_pins[] = { 1154 /* CLKIN */ 1155 RCAR_GP_PIN(1, 28), 1156 }; 1157 static const unsigned int du_clk_in_1_mux[] = { 1158 DU_DOTCLKIN1_MARK 1159 }; 1160 static const unsigned int du_clk_out_0_pins[] = { 1161 /* CLKOUT */ 1162 RCAR_GP_PIN(1, 24), 1163 }; 1164 static const unsigned int du_clk_out_0_mux[] = { 1165 DU_DOTCLKOUT0_MARK 1166 }; 1167 static const unsigned int du_sync_pins[] = { 1168 /* VSYNC, HSYNC */ 1169 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 1170 }; 1171 static const unsigned int du_sync_mux[] = { 1172 DU_VSYNC_MARK, DU_HSYNC_MARK 1173 }; 1174 static const unsigned int du_disp_cde_pins[] = { 1175 /* DISP_CDE */ 1176 RCAR_GP_PIN(1, 28), 1177 }; 1178 static const unsigned int du_disp_cde_mux[] = { 1179 DU_DISP_CDE_MARK, 1180 }; 1181 static const unsigned int du_cde_pins[] = { 1182 /* CDE */ 1183 RCAR_GP_PIN(1, 29), 1184 }; 1185 static const unsigned int du_cde_mux[] = { 1186 DU_CDE_MARK, 1187 }; 1188 static const unsigned int du_disp_pins[] = { 1189 /* DISP */ 1190 RCAR_GP_PIN(1, 27), 1191 }; 1192 static const unsigned int du_disp_mux[] = { 1193 DU_DISP_MARK, 1194 }; 1195 1196 /* - I2C -------------------------------------------------------------------- */ 1197 static const unsigned int i2c0_pins[] = { 1198 /* SCL, SDA */ 1199 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 1200 }; 1201 static const unsigned int i2c0_mux[] = { 1202 SCL0_MARK, SDA0_MARK, 1203 }; 1204 static const unsigned int i2c1_pins[] = { 1205 /* SCL, SDA */ 1206 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), 1207 }; 1208 static const unsigned int i2c1_mux[] = { 1209 SCL1_MARK, SDA1_MARK, 1210 }; 1211 static const unsigned int i2c2_a_pins[] = { 1212 /* SCL, SDA */ 1213 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), 1214 }; 1215 static const unsigned int i2c2_a_mux[] = { 1216 SCL2_A_MARK, SDA2_A_MARK, 1217 }; 1218 static const unsigned int i2c2_b_pins[] = { 1219 /* SCL, SDA */ 1220 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30), 1221 }; 1222 static const unsigned int i2c2_b_mux[] = { 1223 SCL2_B_MARK, SDA2_B_MARK, 1224 }; 1225 static const unsigned int i2c3_a_pins[] = { 1226 /* SCL, SDA */ 1227 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 1228 }; 1229 static const unsigned int i2c3_a_mux[] = { 1230 SCL3_A_MARK, SDA3_A_MARK, 1231 }; 1232 static const unsigned int i2c3_b_pins[] = { 1233 /* SCL, SDA */ 1234 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), 1235 }; 1236 static const unsigned int i2c3_b_mux[] = { 1237 SCL3_B_MARK, SDA3_B_MARK, 1238 }; 1239 1240 /* - MMC ------------------------------------------------------------------- */ 1241 static const unsigned int mmc_data1_pins[] = { 1242 /* D0 */ 1243 RCAR_GP_PIN(3, 2), 1244 }; 1245 static const unsigned int mmc_data1_mux[] = { 1246 MMC_D0_MARK, 1247 }; 1248 static const unsigned int mmc_data4_pins[] = { 1249 /* D[0:3] */ 1250 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 1251 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 1252 }; 1253 static const unsigned int mmc_data4_mux[] = { 1254 MMC_D0_MARK, MMC_D1_MARK, 1255 MMC_D2_MARK, MMC_D3_MARK, 1256 }; 1257 static const unsigned int mmc_data8_pins[] = { 1258 /* D[0:7] */ 1259 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 1260 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 1261 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 1262 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1263 }; 1264 static const unsigned int mmc_data8_mux[] = { 1265 MMC_D0_MARK, MMC_D1_MARK, 1266 MMC_D2_MARK, MMC_D3_MARK, 1267 MMC_D4_MARK, MMC_D5_MARK, 1268 MMC_D6_MARK, MMC_D7_MARK, 1269 }; 1270 static const unsigned int mmc_ctrl_pins[] = { 1271 /* CLK, CMD */ 1272 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), 1273 }; 1274 static const unsigned int mmc_ctrl_mux[] = { 1275 MMC_CLK_MARK, MMC_CMD_MARK, 1276 }; 1277 1278 /* - MSIOF0 ----------------------------------------------------------------- */ 1279 static const unsigned int msiof0_clk_pins[] = { 1280 /* SCK */ 1281 RCAR_GP_PIN(4, 12), 1282 }; 1283 1284 static const unsigned int msiof0_clk_mux[] = { 1285 MSIOF0_SCK_MARK, 1286 }; 1287 1288 static const unsigned int msiof0_sync_pins[] = { 1289 /* SYNC */ 1290 RCAR_GP_PIN(4, 13), 1291 }; 1292 1293 static const unsigned int msiof0_sync_mux[] = { 1294 MSIOF0_SYNC_MARK, 1295 }; 1296 1297 static const unsigned int msiof0_ss1_pins[] = { 1298 /* SS1 */ 1299 RCAR_GP_PIN(4, 20), 1300 }; 1301 1302 static const unsigned int msiof0_ss1_mux[] = { 1303 MSIOF0_SS1_MARK, 1304 }; 1305 1306 static const unsigned int msiof0_ss2_pins[] = { 1307 /* SS2 */ 1308 RCAR_GP_PIN(4, 21), 1309 }; 1310 1311 static const unsigned int msiof0_ss2_mux[] = { 1312 MSIOF0_SS2_MARK, 1313 }; 1314 1315 static const unsigned int msiof0_txd_pins[] = { 1316 /* TXD */ 1317 RCAR_GP_PIN(4, 14), 1318 }; 1319 1320 static const unsigned int msiof0_txd_mux[] = { 1321 MSIOF0_TXD_MARK, 1322 }; 1323 1324 static const unsigned int msiof0_rxd_pins[] = { 1325 /* RXD */ 1326 RCAR_GP_PIN(4, 15), 1327 }; 1328 1329 static const unsigned int msiof0_rxd_mux[] = { 1330 MSIOF0_RXD_MARK, 1331 }; 1332 1333 /* - MSIOF1 ----------------------------------------------------------------- */ 1334 static const unsigned int msiof1_clk_pins[] = { 1335 /* SCK */ 1336 RCAR_GP_PIN(4, 16), 1337 }; 1338 1339 static const unsigned int msiof1_clk_mux[] = { 1340 MSIOF1_SCK_MARK, 1341 }; 1342 1343 static const unsigned int msiof1_sync_pins[] = { 1344 /* SYNC */ 1345 RCAR_GP_PIN(4, 19), 1346 }; 1347 1348 static const unsigned int msiof1_sync_mux[] = { 1349 MSIOF1_SYNC_MARK, 1350 }; 1351 1352 static const unsigned int msiof1_ss1_pins[] = { 1353 /* SS1 */ 1354 RCAR_GP_PIN(4, 25), 1355 }; 1356 1357 static const unsigned int msiof1_ss1_mux[] = { 1358 MSIOF1_SS1_MARK, 1359 }; 1360 1361 static const unsigned int msiof1_ss2_pins[] = { 1362 /* SS2 */ 1363 RCAR_GP_PIN(4, 22), 1364 }; 1365 1366 static const unsigned int msiof1_ss2_mux[] = { 1367 MSIOF1_SS2_MARK, 1368 }; 1369 1370 static const unsigned int msiof1_txd_pins[] = { 1371 /* TXD */ 1372 RCAR_GP_PIN(4, 17), 1373 }; 1374 1375 static const unsigned int msiof1_txd_mux[] = { 1376 MSIOF1_TXD_MARK, 1377 }; 1378 1379 static const unsigned int msiof1_rxd_pins[] = { 1380 /* RXD */ 1381 RCAR_GP_PIN(4, 18), 1382 }; 1383 1384 static const unsigned int msiof1_rxd_mux[] = { 1385 MSIOF1_RXD_MARK, 1386 }; 1387 1388 /* - MSIOF2 ----------------------------------------------------------------- */ 1389 static const unsigned int msiof2_clk_pins[] = { 1390 /* SCK */ 1391 RCAR_GP_PIN(0, 3), 1392 }; 1393 1394 static const unsigned int msiof2_clk_mux[] = { 1395 MSIOF2_SCK_MARK, 1396 }; 1397 1398 static const unsigned int msiof2_sync_a_pins[] = { 1399 /* SYNC */ 1400 RCAR_GP_PIN(0, 6), 1401 }; 1402 1403 static const unsigned int msiof2_sync_a_mux[] = { 1404 MSIOF2_SYNC_A_MARK, 1405 }; 1406 1407 static const unsigned int msiof2_sync_b_pins[] = { 1408 /* SYNC */ 1409 RCAR_GP_PIN(0, 2), 1410 }; 1411 1412 static const unsigned int msiof2_sync_b_mux[] = { 1413 MSIOF2_SYNC_B_MARK, 1414 }; 1415 1416 static const unsigned int msiof2_ss1_pins[] = { 1417 /* SS1 */ 1418 RCAR_GP_PIN(0, 7), 1419 }; 1420 1421 static const unsigned int msiof2_ss1_mux[] = { 1422 MSIOF2_SS1_MARK, 1423 }; 1424 1425 static const unsigned int msiof2_ss2_pins[] = { 1426 /* SS2 */ 1427 RCAR_GP_PIN(0, 8), 1428 }; 1429 1430 static const unsigned int msiof2_ss2_mux[] = { 1431 MSIOF2_SS2_MARK, 1432 }; 1433 1434 static const unsigned int msiof2_txd_pins[] = { 1435 /* TXD */ 1436 RCAR_GP_PIN(0, 4), 1437 }; 1438 1439 static const unsigned int msiof2_txd_mux[] = { 1440 MSIOF2_TXD_MARK, 1441 }; 1442 1443 static const unsigned int msiof2_rxd_pins[] = { 1444 /* RXD */ 1445 RCAR_GP_PIN(0, 5), 1446 }; 1447 1448 static const unsigned int msiof2_rxd_mux[] = { 1449 MSIOF2_RXD_MARK, 1450 }; 1451 1452 /* - MSIOF3 ----------------------------------------------------------------- */ 1453 static const unsigned int msiof3_clk_a_pins[] = { 1454 /* SCK */ 1455 RCAR_GP_PIN(2, 24), 1456 }; 1457 1458 static const unsigned int msiof3_clk_a_mux[] = { 1459 MSIOF3_SCK_A_MARK, 1460 }; 1461 1462 static const unsigned int msiof3_sync_a_pins[] = { 1463 /* SYNC */ 1464 RCAR_GP_PIN(2, 21), 1465 }; 1466 1467 static const unsigned int msiof3_sync_a_mux[] = { 1468 MSIOF3_SYNC_A_MARK, 1469 }; 1470 1471 static const unsigned int msiof3_ss1_a_pins[] = { 1472 /* SS1 */ 1473 RCAR_GP_PIN(2, 14), 1474 }; 1475 1476 static const unsigned int msiof3_ss1_a_mux[] = { 1477 MSIOF3_SS1_A_MARK, 1478 }; 1479 1480 static const unsigned int msiof3_ss2_a_pins[] = { 1481 /* SS2 */ 1482 RCAR_GP_PIN(2, 10), 1483 }; 1484 1485 static const unsigned int msiof3_ss2_a_mux[] = { 1486 MSIOF3_SS2_A_MARK, 1487 }; 1488 1489 static const unsigned int msiof3_txd_a_pins[] = { 1490 /* TXD */ 1491 RCAR_GP_PIN(2, 22), 1492 }; 1493 1494 static const unsigned int msiof3_txd_a_mux[] = { 1495 MSIOF3_TXD_A_MARK, 1496 }; 1497 1498 static const unsigned int msiof3_rxd_a_pins[] = { 1499 /* RXD */ 1500 RCAR_GP_PIN(2, 23), 1501 }; 1502 1503 static const unsigned int msiof3_rxd_a_mux[] = { 1504 MSIOF3_RXD_A_MARK, 1505 }; 1506 1507 static const unsigned int msiof3_clk_b_pins[] = { 1508 /* SCK */ 1509 RCAR_GP_PIN(1, 8), 1510 }; 1511 1512 static const unsigned int msiof3_clk_b_mux[] = { 1513 MSIOF3_SCK_B_MARK, 1514 }; 1515 1516 static const unsigned int msiof3_sync_b_pins[] = { 1517 /* SYNC */ 1518 RCAR_GP_PIN(1, 9), 1519 }; 1520 1521 static const unsigned int msiof3_sync_b_mux[] = { 1522 MSIOF3_SYNC_B_MARK, 1523 }; 1524 1525 static const unsigned int msiof3_ss1_b_pins[] = { 1526 /* SS1 */ 1527 RCAR_GP_PIN(1, 6), 1528 }; 1529 1530 static const unsigned int msiof3_ss1_b_mux[] = { 1531 MSIOF3_SS1_B_MARK, 1532 }; 1533 1534 static const unsigned int msiof3_ss2_b_pins[] = { 1535 /* SS2 */ 1536 RCAR_GP_PIN(1, 7), 1537 }; 1538 1539 static const unsigned int msiof3_ss2_b_mux[] = { 1540 MSIOF3_SS2_B_MARK, 1541 }; 1542 1543 static const unsigned int msiof3_txd_b_pins[] = { 1544 /* TXD */ 1545 RCAR_GP_PIN(1, 0), 1546 }; 1547 1548 static const unsigned int msiof3_txd_b_mux[] = { 1549 MSIOF3_TXD_B_MARK, 1550 }; 1551 1552 static const unsigned int msiof3_rxd_b_pins[] = { 1553 /* RXD */ 1554 RCAR_GP_PIN(1, 1), 1555 }; 1556 1557 static const unsigned int msiof3_rxd_b_mux[] = { 1558 MSIOF3_RXD_B_MARK, 1559 }; 1560 1561 /* - PWM0 ------------------------------------------------------------------ */ 1562 static const unsigned int pwm0_a_pins[] = { 1563 /* PWM */ 1564 RCAR_GP_PIN(2, 1), 1565 }; 1566 1567 static const unsigned int pwm0_a_mux[] = { 1568 PWM0_A_MARK, 1569 }; 1570 1571 static const unsigned int pwm0_b_pins[] = { 1572 /* PWM */ 1573 RCAR_GP_PIN(1, 18), 1574 }; 1575 1576 static const unsigned int pwm0_b_mux[] = { 1577 PWM0_B_MARK, 1578 }; 1579 1580 static const unsigned int pwm0_c_pins[] = { 1581 /* PWM */ 1582 RCAR_GP_PIN(2, 29), 1583 }; 1584 1585 static const unsigned int pwm0_c_mux[] = { 1586 PWM0_C_MARK, 1587 }; 1588 1589 /* - PWM1 ------------------------------------------------------------------ */ 1590 static const unsigned int pwm1_a_pins[] = { 1591 /* PWM */ 1592 RCAR_GP_PIN(2, 2), 1593 }; 1594 1595 static const unsigned int pwm1_a_mux[] = { 1596 PWM1_A_MARK, 1597 }; 1598 1599 static const unsigned int pwm1_b_pins[] = { 1600 /* PWM */ 1601 RCAR_GP_PIN(1, 19), 1602 }; 1603 1604 static const unsigned int pwm1_b_mux[] = { 1605 PWM1_B_MARK, 1606 }; 1607 1608 static const unsigned int pwm1_c_pins[] = { 1609 /* PWM */ 1610 RCAR_GP_PIN(2, 30), 1611 }; 1612 1613 static const unsigned int pwm1_c_mux[] = { 1614 PWM1_C_MARK, 1615 }; 1616 1617 /* - PWM2 ------------------------------------------------------------------ */ 1618 static const unsigned int pwm2_a_pins[] = { 1619 /* PWM */ 1620 RCAR_GP_PIN(2, 3), 1621 }; 1622 1623 static const unsigned int pwm2_a_mux[] = { 1624 PWM2_A_MARK, 1625 }; 1626 1627 static const unsigned int pwm2_b_pins[] = { 1628 /* PWM */ 1629 RCAR_GP_PIN(1, 22), 1630 }; 1631 1632 static const unsigned int pwm2_b_mux[] = { 1633 PWM2_B_MARK, 1634 }; 1635 1636 static const unsigned int pwm2_c_pins[] = { 1637 /* PWM */ 1638 RCAR_GP_PIN(2, 31), 1639 }; 1640 1641 static const unsigned int pwm2_c_mux[] = { 1642 PWM2_C_MARK, 1643 }; 1644 1645 /* - PWM3 ------------------------------------------------------------------ */ 1646 static const unsigned int pwm3_a_pins[] = { 1647 /* PWM */ 1648 RCAR_GP_PIN(2, 4), 1649 }; 1650 1651 static const unsigned int pwm3_a_mux[] = { 1652 PWM3_A_MARK, 1653 }; 1654 1655 static const unsigned int pwm3_b_pins[] = { 1656 /* PWM */ 1657 RCAR_GP_PIN(1, 27), 1658 }; 1659 1660 static const unsigned int pwm3_b_mux[] = { 1661 PWM3_B_MARK, 1662 }; 1663 1664 static const unsigned int pwm3_c_pins[] = { 1665 /* PWM */ 1666 RCAR_GP_PIN(4, 0), 1667 }; 1668 1669 static const unsigned int pwm3_c_mux[] = { 1670 PWM3_C_MARK, 1671 }; 1672 1673 /* - SCIF0 ------------------------------------------------------------------ */ 1674 static const unsigned int scif0_data_a_pins[] = { 1675 /* RX, TX */ 1676 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), 1677 }; 1678 static const unsigned int scif0_data_a_mux[] = { 1679 RX0_A_MARK, TX0_A_MARK, 1680 }; 1681 static const unsigned int scif0_clk_a_pins[] = { 1682 /* SCK */ 1683 RCAR_GP_PIN(4, 19), 1684 }; 1685 static const unsigned int scif0_clk_a_mux[] = { 1686 SCK0_A_MARK, 1687 }; 1688 static const unsigned int scif0_data_b_pins[] = { 1689 /* RX, TX */ 1690 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28), 1691 }; 1692 static const unsigned int scif0_data_b_mux[] = { 1693 RX0_B_MARK, TX0_B_MARK, 1694 }; 1695 static const unsigned int scif0_clk_b_pins[] = { 1696 /* SCK */ 1697 RCAR_GP_PIN(5, 2), 1698 }; 1699 static const unsigned int scif0_clk_b_mux[] = { 1700 SCK0_B_MARK, 1701 }; 1702 static const unsigned int scif0_ctrl_pins[] = { 1703 /* RTS, CTS */ 1704 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23), 1705 }; 1706 static const unsigned int scif0_ctrl_mux[] = { 1707 RTS0_N_MARK, CTS0_N_MARK, 1708 }; 1709 /* - SCIF1 ------------------------------------------------------------------ */ 1710 static const unsigned int scif1_data_a_pins[] = { 1711 /* RX, TX */ 1712 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), 1713 }; 1714 static const unsigned int scif1_data_a_mux[] = { 1715 RX1_A_MARK, TX1_A_MARK, 1716 }; 1717 static const unsigned int scif1_clk_a_pins[] = { 1718 /* SCK */ 1719 RCAR_GP_PIN(4, 22), 1720 }; 1721 static const unsigned int scif1_clk_a_mux[] = { 1722 SCK1_A_MARK, 1723 }; 1724 static const unsigned int scif1_data_b_pins[] = { 1725 /* RX, TX */ 1726 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28), 1727 }; 1728 static const unsigned int scif1_data_b_mux[] = { 1729 RX1_B_MARK, TX1_B_MARK, 1730 }; 1731 static const unsigned int scif1_clk_b_pins[] = { 1732 /* SCK */ 1733 RCAR_GP_PIN(2, 25), 1734 }; 1735 static const unsigned int scif1_clk_b_mux[] = { 1736 SCK1_B_MARK, 1737 }; 1738 static const unsigned int scif1_ctrl_pins[] = { 1739 /* RTS, CTS */ 1740 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), 1741 }; 1742 static const unsigned int scif1_ctrl_mux[] = { 1743 RTS1_N_MARK, CTS1_N_MARK, 1744 }; 1745 1746 /* - SCIF2 ------------------------------------------------------------------ */ 1747 static const unsigned int scif2_data_pins[] = { 1748 /* RX, TX */ 1749 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27), 1750 }; 1751 static const unsigned int scif2_data_mux[] = { 1752 RX2_MARK, TX2_MARK, 1753 }; 1754 static const unsigned int scif2_clk_pins[] = { 1755 /* SCK */ 1756 RCAR_GP_PIN(4, 25), 1757 }; 1758 static const unsigned int scif2_clk_mux[] = { 1759 SCK2_MARK, 1760 }; 1761 /* - SCIF3 ------------------------------------------------------------------ */ 1762 static const unsigned int scif3_data_a_pins[] = { 1763 /* RX, TX */ 1764 RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00), 1765 }; 1766 static const unsigned int scif3_data_a_mux[] = { 1767 RX3_A_MARK, TX3_A_MARK, 1768 }; 1769 static const unsigned int scif3_clk_a_pins[] = { 1770 /* SCK */ 1771 RCAR_GP_PIN(2, 30), 1772 }; 1773 static const unsigned int scif3_clk_a_mux[] = { 1774 SCK3_A_MARK, 1775 }; 1776 static const unsigned int scif3_data_b_pins[] = { 1777 /* RX, TX */ 1778 RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31), 1779 }; 1780 static const unsigned int scif3_data_b_mux[] = { 1781 RX3_B_MARK, TX3_B_MARK, 1782 }; 1783 static const unsigned int scif3_clk_b_pins[] = { 1784 /* SCK */ 1785 RCAR_GP_PIN(1, 29), 1786 }; 1787 static const unsigned int scif3_clk_b_mux[] = { 1788 SCK3_B_MARK, 1789 }; 1790 /* - SCIF4 ------------------------------------------------------------------ */ 1791 static const unsigned int scif4_data_a_pins[] = { 1792 /* RX, TX */ 1793 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 1794 }; 1795 static const unsigned int scif4_data_a_mux[] = { 1796 RX4_A_MARK, TX4_A_MARK, 1797 }; 1798 static const unsigned int scif4_clk_a_pins[] = { 1799 /* SCK */ 1800 RCAR_GP_PIN(2, 6), 1801 }; 1802 static const unsigned int scif4_clk_a_mux[] = { 1803 SCK4_A_MARK, 1804 }; 1805 static const unsigned int scif4_data_b_pins[] = { 1806 /* RX, TX */ 1807 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), 1808 }; 1809 static const unsigned int scif4_data_b_mux[] = { 1810 RX4_B_MARK, TX4_B_MARK, 1811 }; 1812 static const unsigned int scif4_clk_b_pins[] = { 1813 /* SCK */ 1814 RCAR_GP_PIN(1, 15), 1815 }; 1816 static const unsigned int scif4_clk_b_mux[] = { 1817 SCK4_B_MARK, 1818 }; 1819 /* - SCIF5 ------------------------------------------------------------------ */ 1820 static const unsigned int scif5_data_a_pins[] = { 1821 /* RX, TX */ 1822 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), 1823 }; 1824 static const unsigned int scif5_data_a_mux[] = { 1825 RX5_A_MARK, TX5_A_MARK, 1826 }; 1827 static const unsigned int scif5_clk_a_pins[] = { 1828 /* SCK */ 1829 RCAR_GP_PIN(0, 6), 1830 }; 1831 static const unsigned int scif5_clk_a_mux[] = { 1832 SCK5_A_MARK, 1833 }; 1834 static const unsigned int scif5_data_b_pins[] = { 1835 /* RX, TX */ 1836 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 1837 }; 1838 static const unsigned int scif5_data_b_mux[] = { 1839 RX5_B_MARK, TX5_B_MARK, 1840 }; 1841 static const unsigned int scif5_clk_b_pins[] = { 1842 /* SCK */ 1843 RCAR_GP_PIN(1, 3), 1844 }; 1845 static const unsigned int scif5_clk_b_mux[] = { 1846 SCK5_B_MARK, 1847 }; 1848 /* - SCIF Clock ------------------------------------------------------------- */ 1849 static const unsigned int scif_clk_pins[] = { 1850 /* SCIF_CLK */ 1851 RCAR_GP_PIN(2, 27), 1852 }; 1853 static const unsigned int scif_clk_mux[] = { 1854 SCIF_CLK_MARK, 1855 }; 1856 1857 /* - SSI ---------------------------------------------------------------*/ 1858 static const unsigned int ssi3_data_pins[] = { 1859 /* SDATA */ 1860 RCAR_GP_PIN(4, 3), 1861 }; 1862 static const unsigned int ssi3_data_mux[] = { 1863 SSI_SDATA3_MARK, 1864 }; 1865 static const unsigned int ssi34_ctrl_pins[] = { 1866 /* SCK, WS */ 1867 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4), 1868 }; 1869 static const unsigned int ssi34_ctrl_mux[] = { 1870 SSI_SCK34_MARK, SSI_WS34_MARK, 1871 }; 1872 static const unsigned int ssi4_ctrl_a_pins[] = { 1873 /* SCK, WS */ 1874 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7), 1875 }; 1876 static const unsigned int ssi4_ctrl_a_mux[] = { 1877 SSI_SCK4_A_MARK, SSI_WS4_A_MARK, 1878 }; 1879 static const unsigned int ssi4_data_a_pins[] = { 1880 /* SDATA */ 1881 RCAR_GP_PIN(4, 6), 1882 }; 1883 static const unsigned int ssi4_data_a_mux[] = { 1884 SSI_SDATA4_A_MARK, 1885 }; 1886 static const unsigned int ssi4_ctrl_b_pins[] = { 1887 /* SCK, WS */ 1888 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20), 1889 }; 1890 static const unsigned int ssi4_ctrl_b_mux[] = { 1891 SSI_SCK4_B_MARK, SSI_WS4_B_MARK, 1892 }; 1893 static const unsigned int ssi4_data_b_pins[] = { 1894 /* SDATA */ 1895 RCAR_GP_PIN(2, 16), 1896 }; 1897 static const unsigned int ssi4_data_b_mux[] = { 1898 SSI_SDATA4_B_MARK, 1899 }; 1900 1901 /* - USB0 ------------------------------------------------------------------- */ 1902 static const unsigned int usb0_pins[] = { 1903 /* PWEN, OVC */ 1904 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 1905 }; 1906 static const unsigned int usb0_mux[] = { 1907 USB0_PWEN_MARK, USB0_OVC_MARK, 1908 }; 1909 1910 /* - VIN4 ------------------------------------------------------------------- */ 1911 static const unsigned int vin4_data18_pins[] = { 1912 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 1913 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 1914 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 1915 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 1916 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), 1917 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 1918 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 1919 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 1920 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), 1921 }; 1922 static const unsigned int vin4_data18_mux[] = { 1923 VI4_DATA2_MARK, VI4_DATA3_MARK, 1924 VI4_DATA4_MARK, VI4_DATA5_MARK, 1925 VI4_DATA6_MARK, VI4_DATA7_MARK, 1926 VI4_DATA10_MARK, VI4_DATA11_MARK, 1927 VI4_DATA12_MARK, VI4_DATA13_MARK, 1928 VI4_DATA14_MARK, VI4_DATA15_MARK, 1929 VI4_DATA18_MARK, VI4_DATA19_MARK, 1930 VI4_DATA20_MARK, VI4_DATA21_MARK, 1931 VI4_DATA22_MARK, VI4_DATA23_MARK, 1932 }; 1933 static const union vin_data vin4_data_pins = { 1934 .data24 = { 1935 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 1936 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 1937 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 1938 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 1939 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), 1940 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 1941 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), 1942 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 1943 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 1944 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 1945 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), 1946 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), 1947 }, 1948 }; 1949 static const union vin_data vin4_data_mux = { 1950 .data24 = { 1951 VI4_DATA0_MARK, VI4_DATA1_MARK, 1952 VI4_DATA2_MARK, VI4_DATA3_MARK, 1953 VI4_DATA4_MARK, VI4_DATA5_MARK, 1954 VI4_DATA6_MARK, VI4_DATA7_MARK, 1955 VI4_DATA8_MARK, VI4_DATA9_MARK, 1956 VI4_DATA10_MARK, VI4_DATA11_MARK, 1957 VI4_DATA12_MARK, VI4_DATA13_MARK, 1958 VI4_DATA14_MARK, VI4_DATA15_MARK, 1959 VI4_DATA16_MARK, VI4_DATA17_MARK, 1960 VI4_DATA18_MARK, VI4_DATA19_MARK, 1961 VI4_DATA20_MARK, VI4_DATA21_MARK, 1962 VI4_DATA22_MARK, VI4_DATA23_MARK, 1963 }, 1964 }; 1965 static const unsigned int vin4_sync_pins[] = { 1966 /* HSYNC#, VSYNC# */ 1967 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25), 1968 }; 1969 static const unsigned int vin4_sync_mux[] = { 1970 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 1971 }; 1972 static const unsigned int vin4_field_pins[] = { 1973 /* FIELD */ 1974 RCAR_GP_PIN(2, 27), 1975 }; 1976 static const unsigned int vin4_field_mux[] = { 1977 VI4_FIELD_MARK, 1978 }; 1979 static const unsigned int vin4_clkenb_pins[] = { 1980 /* CLKENB */ 1981 RCAR_GP_PIN(2, 28), 1982 }; 1983 static const unsigned int vin4_clkenb_mux[] = { 1984 VI4_CLKENB_MARK, 1985 }; 1986 static const unsigned int vin4_clk_pins[] = { 1987 /* CLK */ 1988 RCAR_GP_PIN(2, 0), 1989 }; 1990 static const unsigned int vin4_clk_mux[] = { 1991 VI4_CLK_MARK, 1992 }; 1993 1994 static const struct sh_pfc_pin_group pinmux_groups[] = { 1995 SH_PFC_PIN_GROUP(audio_clk_a), 1996 SH_PFC_PIN_GROUP(audio_clk_b), 1997 SH_PFC_PIN_GROUP(audio_clkout), 1998 SH_PFC_PIN_GROUP(audio_clkout1), 1999 SH_PFC_PIN_GROUP(avb0_link), 2000 SH_PFC_PIN_GROUP(avb0_magic), 2001 SH_PFC_PIN_GROUP(avb0_phy_int), 2002 SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio), /* Deprecated */ 2003 SH_PFC_PIN_GROUP(avb0_mdio), 2004 SH_PFC_PIN_GROUP(avb0_mii), 2005 SH_PFC_PIN_GROUP(avb0_avtp_pps_a), 2006 SH_PFC_PIN_GROUP(avb0_avtp_match_a), 2007 SH_PFC_PIN_GROUP(avb0_avtp_capture_a), 2008 SH_PFC_PIN_GROUP(avb0_avtp_pps_b), 2009 SH_PFC_PIN_GROUP(avb0_avtp_match_b), 2010 SH_PFC_PIN_GROUP(avb0_avtp_capture_b), 2011 SH_PFC_PIN_GROUP(can0_data_a), 2012 SH_PFC_PIN_GROUP(can0_data_b), 2013 SH_PFC_PIN_GROUP(can1_data_a), 2014 SH_PFC_PIN_GROUP(can1_data_b), 2015 SH_PFC_PIN_GROUP(can_clk), 2016 SH_PFC_PIN_GROUP(canfd0_data), 2017 SH_PFC_PIN_GROUP(canfd1_data), 2018 SH_PFC_PIN_GROUP(du_rgb666), 2019 SH_PFC_PIN_GROUP(du_rgb888), 2020 SH_PFC_PIN_GROUP(du_clk_in_1), 2021 SH_PFC_PIN_GROUP(du_clk_out_0), 2022 SH_PFC_PIN_GROUP(du_sync), 2023 SH_PFC_PIN_GROUP(du_disp_cde), 2024 SH_PFC_PIN_GROUP(du_cde), 2025 SH_PFC_PIN_GROUP(du_disp), 2026 SH_PFC_PIN_GROUP(i2c0), 2027 SH_PFC_PIN_GROUP(i2c1), 2028 SH_PFC_PIN_GROUP(i2c2_a), 2029 SH_PFC_PIN_GROUP(i2c2_b), 2030 SH_PFC_PIN_GROUP(i2c3_a), 2031 SH_PFC_PIN_GROUP(i2c3_b), 2032 SH_PFC_PIN_GROUP(mmc_data1), 2033 SH_PFC_PIN_GROUP(mmc_data4), 2034 SH_PFC_PIN_GROUP(mmc_data8), 2035 SH_PFC_PIN_GROUP(mmc_ctrl), 2036 SH_PFC_PIN_GROUP(msiof0_clk), 2037 SH_PFC_PIN_GROUP(msiof0_sync), 2038 SH_PFC_PIN_GROUP(msiof0_ss1), 2039 SH_PFC_PIN_GROUP(msiof0_ss2), 2040 SH_PFC_PIN_GROUP(msiof0_txd), 2041 SH_PFC_PIN_GROUP(msiof0_rxd), 2042 SH_PFC_PIN_GROUP(msiof1_clk), 2043 SH_PFC_PIN_GROUP(msiof1_sync), 2044 SH_PFC_PIN_GROUP(msiof1_ss1), 2045 SH_PFC_PIN_GROUP(msiof1_ss2), 2046 SH_PFC_PIN_GROUP(msiof1_txd), 2047 SH_PFC_PIN_GROUP(msiof1_rxd), 2048 SH_PFC_PIN_GROUP(msiof2_clk), 2049 SH_PFC_PIN_GROUP(msiof2_sync_a), 2050 SH_PFC_PIN_GROUP(msiof2_sync_b), 2051 SH_PFC_PIN_GROUP(msiof2_ss1), 2052 SH_PFC_PIN_GROUP(msiof2_ss2), 2053 SH_PFC_PIN_GROUP(msiof2_txd), 2054 SH_PFC_PIN_GROUP(msiof2_rxd), 2055 SH_PFC_PIN_GROUP(msiof3_clk_a), 2056 SH_PFC_PIN_GROUP(msiof3_sync_a), 2057 SH_PFC_PIN_GROUP(msiof3_ss1_a), 2058 SH_PFC_PIN_GROUP(msiof3_ss2_a), 2059 SH_PFC_PIN_GROUP(msiof3_txd_a), 2060 SH_PFC_PIN_GROUP(msiof3_rxd_a), 2061 SH_PFC_PIN_GROUP(msiof3_clk_b), 2062 SH_PFC_PIN_GROUP(msiof3_sync_b), 2063 SH_PFC_PIN_GROUP(msiof3_ss1_b), 2064 SH_PFC_PIN_GROUP(msiof3_ss2_b), 2065 SH_PFC_PIN_GROUP(msiof3_txd_b), 2066 SH_PFC_PIN_GROUP(msiof3_rxd_b), 2067 SH_PFC_PIN_GROUP(pwm0_a), 2068 SH_PFC_PIN_GROUP(pwm0_b), 2069 SH_PFC_PIN_GROUP(pwm0_c), 2070 SH_PFC_PIN_GROUP(pwm1_a), 2071 SH_PFC_PIN_GROUP(pwm1_b), 2072 SH_PFC_PIN_GROUP(pwm1_c), 2073 SH_PFC_PIN_GROUP(pwm2_a), 2074 SH_PFC_PIN_GROUP(pwm2_b), 2075 SH_PFC_PIN_GROUP(pwm2_c), 2076 SH_PFC_PIN_GROUP(pwm3_a), 2077 SH_PFC_PIN_GROUP(pwm3_b), 2078 SH_PFC_PIN_GROUP(pwm3_c), 2079 SH_PFC_PIN_GROUP(scif0_data_a), 2080 SH_PFC_PIN_GROUP(scif0_clk_a), 2081 SH_PFC_PIN_GROUP(scif0_data_b), 2082 SH_PFC_PIN_GROUP(scif0_clk_b), 2083 SH_PFC_PIN_GROUP(scif0_ctrl), 2084 SH_PFC_PIN_GROUP(scif1_data_a), 2085 SH_PFC_PIN_GROUP(scif1_clk_a), 2086 SH_PFC_PIN_GROUP(scif1_data_b), 2087 SH_PFC_PIN_GROUP(scif1_clk_b), 2088 SH_PFC_PIN_GROUP(scif1_ctrl), 2089 SH_PFC_PIN_GROUP(scif2_data), 2090 SH_PFC_PIN_GROUP(scif2_clk), 2091 SH_PFC_PIN_GROUP(scif3_data_a), 2092 SH_PFC_PIN_GROUP(scif3_clk_a), 2093 SH_PFC_PIN_GROUP(scif3_data_b), 2094 SH_PFC_PIN_GROUP(scif3_clk_b), 2095 SH_PFC_PIN_GROUP(scif4_data_a), 2096 SH_PFC_PIN_GROUP(scif4_clk_a), 2097 SH_PFC_PIN_GROUP(scif4_data_b), 2098 SH_PFC_PIN_GROUP(scif4_clk_b), 2099 SH_PFC_PIN_GROUP(scif5_data_a), 2100 SH_PFC_PIN_GROUP(scif5_clk_a), 2101 SH_PFC_PIN_GROUP(scif5_data_b), 2102 SH_PFC_PIN_GROUP(scif5_clk_b), 2103 SH_PFC_PIN_GROUP(scif_clk), 2104 SH_PFC_PIN_GROUP(ssi3_data), 2105 SH_PFC_PIN_GROUP(ssi34_ctrl), 2106 SH_PFC_PIN_GROUP(ssi4_ctrl_a), 2107 SH_PFC_PIN_GROUP(ssi4_data_a), 2108 SH_PFC_PIN_GROUP(ssi4_ctrl_b), 2109 SH_PFC_PIN_GROUP(ssi4_data_b), 2110 SH_PFC_PIN_GROUP(usb0), 2111 VIN_DATA_PIN_GROUP(vin4_data, 8), 2112 VIN_DATA_PIN_GROUP(vin4_data, 10), 2113 VIN_DATA_PIN_GROUP(vin4_data, 12), 2114 VIN_DATA_PIN_GROUP(vin4_data, 16), 2115 SH_PFC_PIN_GROUP(vin4_data18), 2116 VIN_DATA_PIN_GROUP(vin4_data, 20), 2117 VIN_DATA_PIN_GROUP(vin4_data, 24), 2118 SH_PFC_PIN_GROUP(vin4_sync), 2119 SH_PFC_PIN_GROUP(vin4_field), 2120 SH_PFC_PIN_GROUP(vin4_clkenb), 2121 SH_PFC_PIN_GROUP(vin4_clk), 2122 }; 2123 2124 static const char * const audio_clk_groups[] = { 2125 "audio_clk_a", 2126 "audio_clk_b", 2127 "audio_clkout", 2128 "audio_clkout1", 2129 }; 2130 2131 static const char * const avb0_groups[] = { 2132 "avb0_link", 2133 "avb0_magic", 2134 "avb0_phy_int", 2135 "avb0_mdc", /* Deprecated, please use "avb0_mdio" instead */ 2136 "avb0_mdio", 2137 "avb0_mii", 2138 "avb0_avtp_pps_a", 2139 "avb0_avtp_match_a", 2140 "avb0_avtp_capture_a", 2141 "avb0_avtp_pps_b", 2142 "avb0_avtp_match_b", 2143 "avb0_avtp_capture_b", 2144 }; 2145 2146 static const char * const can0_groups[] = { 2147 "can0_data_a", 2148 "can0_data_b", 2149 }; 2150 static const char * const can1_groups[] = { 2151 "can1_data_a", 2152 "can1_data_b", 2153 }; 2154 static const char * const can_clk_groups[] = { 2155 "can_clk", 2156 }; 2157 2158 static const char * const canfd0_groups[] = { 2159 "canfd0_data", 2160 }; 2161 static const char * const canfd1_groups[] = { 2162 "canfd1_data", 2163 }; 2164 2165 static const char * const du_groups[] = { 2166 "du_rgb666", 2167 "du_rgb888", 2168 "du_clk_in_1", 2169 "du_clk_out_0", 2170 "du_sync", 2171 "du_disp_cde", 2172 "du_cde", 2173 "du_disp", 2174 }; 2175 2176 static const char * const i2c0_groups[] = { 2177 "i2c0", 2178 }; 2179 static const char * const i2c1_groups[] = { 2180 "i2c1", 2181 }; 2182 2183 static const char * const i2c2_groups[] = { 2184 "i2c2_a", 2185 "i2c2_b", 2186 }; 2187 2188 static const char * const i2c3_groups[] = { 2189 "i2c3_a", 2190 "i2c3_b", 2191 }; 2192 2193 static const char * const mmc_groups[] = { 2194 "mmc_data1", 2195 "mmc_data4", 2196 "mmc_data8", 2197 "mmc_ctrl", 2198 }; 2199 2200 static const char * const pwm0_groups[] = { 2201 "pwm0_a", 2202 "pwm0_b", 2203 "pwm0_c", 2204 }; 2205 2206 static const char * const pwm1_groups[] = { 2207 "pwm1_a", 2208 "pwm1_b", 2209 "pwm1_c", 2210 }; 2211 2212 static const char * const pwm2_groups[] = { 2213 "pwm2_a", 2214 "pwm2_b", 2215 "pwm2_c", 2216 }; 2217 2218 static const char * const pwm3_groups[] = { 2219 "pwm3_a", 2220 "pwm3_b", 2221 "pwm3_c", 2222 }; 2223 2224 static const char * const scif0_groups[] = { 2225 "scif0_data_a", 2226 "scif0_clk_a", 2227 "scif0_data_b", 2228 "scif0_clk_b", 2229 "scif0_ctrl", 2230 }; 2231 2232 static const char * const scif1_groups[] = { 2233 "scif1_data_a", 2234 "scif1_clk_a", 2235 "scif1_data_b", 2236 "scif1_clk_b", 2237 "scif1_ctrl", 2238 }; 2239 2240 static const char * const scif2_groups[] = { 2241 "scif2_data", 2242 "scif2_clk", 2243 }; 2244 2245 static const char * const scif3_groups[] = { 2246 "scif3_data_a", 2247 "scif3_clk_a", 2248 "scif3_data_b", 2249 "scif3_clk_b", 2250 }; 2251 2252 static const char * const scif4_groups[] = { 2253 "scif4_data_a", 2254 "scif4_clk_a", 2255 "scif4_data_b", 2256 "scif4_clk_b", 2257 }; 2258 2259 static const char * const scif5_groups[] = { 2260 "scif5_data_a", 2261 "scif5_clk_a", 2262 "scif5_data_b", 2263 "scif5_clk_b", 2264 }; 2265 2266 static const char * const scif_clk_groups[] = { 2267 "scif_clk", 2268 }; 2269 2270 static const char * const ssi_groups[] = { 2271 "ssi3_data", 2272 "ssi34_ctrl", 2273 "ssi4_ctrl_a", 2274 "ssi4_data_a", 2275 "ssi4_ctrl_b", 2276 "ssi4_data_b", 2277 }; 2278 2279 static const char * const usb0_groups[] = { 2280 "usb0", 2281 }; 2282 2283 static const char * const vin4_groups[] = { 2284 "vin4_data8", 2285 "vin4_data10", 2286 "vin4_data12", 2287 "vin4_data16", 2288 "vin4_data18", 2289 "vin4_data20", 2290 "vin4_data24", 2291 "vin4_sync", 2292 "vin4_field", 2293 "vin4_clkenb", 2294 "vin4_clk", 2295 }; 2296 2297 static const char * const msiof0_groups[] = { 2298 "msiof0_clk", 2299 "msiof0_sync", 2300 "msiof0_ss1", 2301 "msiof0_ss2", 2302 "msiof0_txd", 2303 "msiof0_rxd", 2304 }; 2305 2306 static const char * const msiof1_groups[] = { 2307 "msiof1_clk", 2308 "msiof1_sync", 2309 "msiof1_ss1", 2310 "msiof1_ss2", 2311 "msiof1_txd", 2312 "msiof1_rxd", 2313 }; 2314 2315 static const char * const msiof2_groups[] = { 2316 "msiof2_clk", 2317 "msiof2_sync_a", 2318 "msiof2_sync_b", 2319 "msiof2_ss1", 2320 "msiof2_ss2", 2321 "msiof2_txd", 2322 "msiof2_rxd", 2323 }; 2324 2325 static const char * const msiof3_groups[] = { 2326 "msiof3_clk_a", 2327 "msiof3_sync_a", 2328 "msiof3_ss1_a", 2329 "msiof3_ss2_a", 2330 "msiof3_txd_a", 2331 "msiof3_rxd_a", 2332 "msiof3_clk_b", 2333 "msiof3_sync_b", 2334 "msiof3_ss1_b", 2335 "msiof3_ss2_b", 2336 "msiof3_txd_b", 2337 "msiof3_rxd_b", 2338 }; 2339 2340 static const struct sh_pfc_function pinmux_functions[] = { 2341 SH_PFC_FUNCTION(audio_clk), 2342 SH_PFC_FUNCTION(avb0), 2343 SH_PFC_FUNCTION(can0), 2344 SH_PFC_FUNCTION(can1), 2345 SH_PFC_FUNCTION(can_clk), 2346 SH_PFC_FUNCTION(canfd0), 2347 SH_PFC_FUNCTION(canfd1), 2348 SH_PFC_FUNCTION(du), 2349 SH_PFC_FUNCTION(i2c0), 2350 SH_PFC_FUNCTION(i2c1), 2351 SH_PFC_FUNCTION(i2c2), 2352 SH_PFC_FUNCTION(i2c3), 2353 SH_PFC_FUNCTION(mmc), 2354 SH_PFC_FUNCTION(msiof0), 2355 SH_PFC_FUNCTION(msiof1), 2356 SH_PFC_FUNCTION(msiof2), 2357 SH_PFC_FUNCTION(msiof3), 2358 SH_PFC_FUNCTION(pwm0), 2359 SH_PFC_FUNCTION(pwm1), 2360 SH_PFC_FUNCTION(pwm2), 2361 SH_PFC_FUNCTION(pwm3), 2362 SH_PFC_FUNCTION(scif0), 2363 SH_PFC_FUNCTION(scif1), 2364 SH_PFC_FUNCTION(scif2), 2365 SH_PFC_FUNCTION(scif3), 2366 SH_PFC_FUNCTION(scif4), 2367 SH_PFC_FUNCTION(scif5), 2368 SH_PFC_FUNCTION(scif_clk), 2369 SH_PFC_FUNCTION(ssi), 2370 SH_PFC_FUNCTION(usb0), 2371 SH_PFC_FUNCTION(vin4), 2372 }; 2373 2374 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2375 #define F_(x, y) FN_##y 2376 #define FM(x) FN_##x 2377 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 2378 0, 0, 2379 0, 0, 2380 0, 0, 2381 0, 0, 2382 0, 0, 2383 0, 0, 2384 0, 0, 2385 0, 0, 2386 0, 0, 2387 0, 0, 2388 0, 0, 2389 0, 0, 2390 0, 0, 2391 0, 0, 2392 0, 0, 2393 0, 0, 2394 0, 0, 2395 0, 0, 2396 0, 0, 2397 0, 0, 2398 0, 0, 2399 0, 0, 2400 0, 0, 2401 GP_0_8_FN, GPSR0_8, 2402 GP_0_7_FN, GPSR0_7, 2403 GP_0_6_FN, GPSR0_6, 2404 GP_0_5_FN, GPSR0_5, 2405 GP_0_4_FN, GPSR0_4, 2406 GP_0_3_FN, GPSR0_3, 2407 GP_0_2_FN, GPSR0_2, 2408 GP_0_1_FN, GPSR0_1, 2409 GP_0_0_FN, GPSR0_0, )) 2410 }, 2411 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 2412 GP_1_31_FN, GPSR1_31, 2413 GP_1_30_FN, GPSR1_30, 2414 GP_1_29_FN, GPSR1_29, 2415 GP_1_28_FN, GPSR1_28, 2416 GP_1_27_FN, GPSR1_27, 2417 GP_1_26_FN, GPSR1_26, 2418 GP_1_25_FN, GPSR1_25, 2419 GP_1_24_FN, GPSR1_24, 2420 GP_1_23_FN, GPSR1_23, 2421 GP_1_22_FN, GPSR1_22, 2422 GP_1_21_FN, GPSR1_21, 2423 GP_1_20_FN, GPSR1_20, 2424 GP_1_19_FN, GPSR1_19, 2425 GP_1_18_FN, GPSR1_18, 2426 GP_1_17_FN, GPSR1_17, 2427 GP_1_16_FN, GPSR1_16, 2428 GP_1_15_FN, GPSR1_15, 2429 GP_1_14_FN, GPSR1_14, 2430 GP_1_13_FN, GPSR1_13, 2431 GP_1_12_FN, GPSR1_12, 2432 GP_1_11_FN, GPSR1_11, 2433 GP_1_10_FN, GPSR1_10, 2434 GP_1_9_FN, GPSR1_9, 2435 GP_1_8_FN, GPSR1_8, 2436 GP_1_7_FN, GPSR1_7, 2437 GP_1_6_FN, GPSR1_6, 2438 GP_1_5_FN, GPSR1_5, 2439 GP_1_4_FN, GPSR1_4, 2440 GP_1_3_FN, GPSR1_3, 2441 GP_1_2_FN, GPSR1_2, 2442 GP_1_1_FN, GPSR1_1, 2443 GP_1_0_FN, GPSR1_0, )) 2444 }, 2445 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 2446 GP_2_31_FN, GPSR2_31, 2447 GP_2_30_FN, GPSR2_30, 2448 GP_2_29_FN, GPSR2_29, 2449 GP_2_28_FN, GPSR2_28, 2450 GP_2_27_FN, GPSR2_27, 2451 GP_2_26_FN, GPSR2_26, 2452 GP_2_25_FN, GPSR2_25, 2453 GP_2_24_FN, GPSR2_24, 2454 GP_2_23_FN, GPSR2_23, 2455 GP_2_22_FN, GPSR2_22, 2456 GP_2_21_FN, GPSR2_21, 2457 GP_2_20_FN, GPSR2_20, 2458 GP_2_19_FN, GPSR2_19, 2459 GP_2_18_FN, GPSR2_18, 2460 GP_2_17_FN, GPSR2_17, 2461 GP_2_16_FN, GPSR2_16, 2462 GP_2_15_FN, GPSR2_15, 2463 GP_2_14_FN, GPSR2_14, 2464 GP_2_13_FN, GPSR2_13, 2465 GP_2_12_FN, GPSR2_12, 2466 GP_2_11_FN, GPSR2_11, 2467 GP_2_10_FN, GPSR2_10, 2468 GP_2_9_FN, GPSR2_9, 2469 GP_2_8_FN, GPSR2_8, 2470 GP_2_7_FN, GPSR2_7, 2471 GP_2_6_FN, GPSR2_6, 2472 GP_2_5_FN, GPSR2_5, 2473 GP_2_4_FN, GPSR2_4, 2474 GP_2_3_FN, GPSR2_3, 2475 GP_2_2_FN, GPSR2_2, 2476 GP_2_1_FN, GPSR2_1, 2477 GP_2_0_FN, GPSR2_0, )) 2478 }, 2479 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 2480 0, 0, 2481 0, 0, 2482 0, 0, 2483 0, 0, 2484 0, 0, 2485 0, 0, 2486 0, 0, 2487 0, 0, 2488 0, 0, 2489 0, 0, 2490 0, 0, 2491 0, 0, 2492 0, 0, 2493 0, 0, 2494 0, 0, 2495 0, 0, 2496 0, 0, 2497 0, 0, 2498 0, 0, 2499 0, 0, 2500 0, 0, 2501 0, 0, 2502 GP_3_9_FN, GPSR3_9, 2503 GP_3_8_FN, GPSR3_8, 2504 GP_3_7_FN, GPSR3_7, 2505 GP_3_6_FN, GPSR3_6, 2506 GP_3_5_FN, GPSR3_5, 2507 GP_3_4_FN, GPSR3_4, 2508 GP_3_3_FN, GPSR3_3, 2509 GP_3_2_FN, GPSR3_2, 2510 GP_3_1_FN, GPSR3_1, 2511 GP_3_0_FN, GPSR3_0, )) 2512 }, 2513 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 2514 GP_4_31_FN, GPSR4_31, 2515 GP_4_30_FN, GPSR4_30, 2516 GP_4_29_FN, GPSR4_29, 2517 GP_4_28_FN, GPSR4_28, 2518 GP_4_27_FN, GPSR4_27, 2519 GP_4_26_FN, GPSR4_26, 2520 GP_4_25_FN, GPSR4_25, 2521 GP_4_24_FN, GPSR4_24, 2522 GP_4_23_FN, GPSR4_23, 2523 GP_4_22_FN, GPSR4_22, 2524 GP_4_21_FN, GPSR4_21, 2525 GP_4_20_FN, GPSR4_20, 2526 GP_4_19_FN, GPSR4_19, 2527 GP_4_18_FN, GPSR4_18, 2528 GP_4_17_FN, GPSR4_17, 2529 GP_4_16_FN, GPSR4_16, 2530 GP_4_15_FN, GPSR4_15, 2531 GP_4_14_FN, GPSR4_14, 2532 GP_4_13_FN, GPSR4_13, 2533 GP_4_12_FN, GPSR4_12, 2534 GP_4_11_FN, GPSR4_11, 2535 GP_4_10_FN, GPSR4_10, 2536 GP_4_9_FN, GPSR4_9, 2537 GP_4_8_FN, GPSR4_8, 2538 GP_4_7_FN, GPSR4_7, 2539 GP_4_6_FN, GPSR4_6, 2540 GP_4_5_FN, GPSR4_5, 2541 GP_4_4_FN, GPSR4_4, 2542 GP_4_3_FN, GPSR4_3, 2543 GP_4_2_FN, GPSR4_2, 2544 GP_4_1_FN, GPSR4_1, 2545 GP_4_0_FN, GPSR4_0, )) 2546 }, 2547 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 2548 0, 0, 2549 0, 0, 2550 0, 0, 2551 0, 0, 2552 0, 0, 2553 0, 0, 2554 0, 0, 2555 0, 0, 2556 0, 0, 2557 0, 0, 2558 0, 0, 2559 GP_5_20_FN, GPSR5_20, 2560 GP_5_19_FN, GPSR5_19, 2561 GP_5_18_FN, GPSR5_18, 2562 GP_5_17_FN, GPSR5_17, 2563 GP_5_16_FN, GPSR5_16, 2564 GP_5_15_FN, GPSR5_15, 2565 GP_5_14_FN, GPSR5_14, 2566 GP_5_13_FN, GPSR5_13, 2567 GP_5_12_FN, GPSR5_12, 2568 GP_5_11_FN, GPSR5_11, 2569 GP_5_10_FN, GPSR5_10, 2570 GP_5_9_FN, GPSR5_9, 2571 GP_5_8_FN, GPSR5_8, 2572 GP_5_7_FN, GPSR5_7, 2573 GP_5_6_FN, GPSR5_6, 2574 GP_5_5_FN, GPSR5_5, 2575 GP_5_4_FN, GPSR5_4, 2576 GP_5_3_FN, GPSR5_3, 2577 GP_5_2_FN, GPSR5_2, 2578 GP_5_1_FN, GPSR5_1, 2579 GP_5_0_FN, GPSR5_0, )) 2580 }, 2581 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 2582 0, 0, 2583 0, 0, 2584 0, 0, 2585 0, 0, 2586 0, 0, 2587 0, 0, 2588 0, 0, 2589 0, 0, 2590 0, 0, 2591 0, 0, 2592 0, 0, 2593 0, 0, 2594 0, 0, 2595 0, 0, 2596 0, 0, 2597 0, 0, 2598 0, 0, 2599 0, 0, 2600 GP_6_13_FN, GPSR6_13, 2601 GP_6_12_FN, GPSR6_12, 2602 GP_6_11_FN, GPSR6_11, 2603 GP_6_10_FN, GPSR6_10, 2604 GP_6_9_FN, GPSR6_9, 2605 GP_6_8_FN, GPSR6_8, 2606 GP_6_7_FN, GPSR6_7, 2607 GP_6_6_FN, GPSR6_6, 2608 GP_6_5_FN, GPSR6_5, 2609 GP_6_4_FN, GPSR6_4, 2610 GP_6_3_FN, GPSR6_3, 2611 GP_6_2_FN, GPSR6_2, 2612 GP_6_1_FN, GPSR6_1, 2613 GP_6_0_FN, GPSR6_0, )) 2614 }, 2615 #undef F_ 2616 #undef FM 2617 2618 #define F_(x, y) x, 2619 #define FM(x) FN_##x, 2620 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 2621 IP0_31_28 2622 IP0_27_24 2623 IP0_23_20 2624 IP0_19_16 2625 IP0_15_12 2626 IP0_11_8 2627 IP0_7_4 2628 IP0_3_0 )) 2629 }, 2630 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 2631 IP1_31_28 2632 IP1_27_24 2633 IP1_23_20 2634 IP1_19_16 2635 IP1_15_12 2636 IP1_11_8 2637 IP1_7_4 2638 IP1_3_0 )) 2639 }, 2640 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 2641 IP2_31_28 2642 IP2_27_24 2643 IP2_23_20 2644 IP2_19_16 2645 IP2_15_12 2646 IP2_11_8 2647 IP2_7_4 2648 IP2_3_0 )) 2649 }, 2650 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 2651 IP3_31_28 2652 IP3_27_24 2653 IP3_23_20 2654 IP3_19_16 2655 IP3_15_12 2656 IP3_11_8 2657 IP3_7_4 2658 IP3_3_0 )) 2659 }, 2660 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 2661 IP4_31_28 2662 IP4_27_24 2663 IP4_23_20 2664 IP4_19_16 2665 IP4_15_12 2666 IP4_11_8 2667 IP4_7_4 2668 IP4_3_0 )) 2669 }, 2670 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 2671 IP5_31_28 2672 IP5_27_24 2673 IP5_23_20 2674 IP5_19_16 2675 IP5_15_12 2676 IP5_11_8 2677 IP5_7_4 2678 IP5_3_0 )) 2679 }, 2680 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 2681 IP6_31_28 2682 IP6_27_24 2683 IP6_23_20 2684 IP6_19_16 2685 IP6_15_12 2686 IP6_11_8 2687 IP6_7_4 2688 IP6_3_0 )) 2689 }, 2690 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 2691 IP7_31_28 2692 IP7_27_24 2693 IP7_23_20 2694 IP7_19_16 2695 IP7_15_12 2696 IP7_11_8 2697 IP7_7_4 2698 IP7_3_0 )) 2699 }, 2700 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 2701 IP8_31_28 2702 IP8_27_24 2703 IP8_23_20 2704 IP8_19_16 2705 IP8_15_12 2706 IP8_11_8 2707 IP8_7_4 2708 IP8_3_0 )) 2709 }, 2710 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 2711 IP9_31_28 2712 IP9_27_24 2713 IP9_23_20 2714 IP9_19_16 2715 IP9_15_12 2716 IP9_11_8 2717 IP9_7_4 2718 IP9_3_0 )) 2719 }, 2720 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 2721 IP10_31_28 2722 IP10_27_24 2723 IP10_23_20 2724 IP10_19_16 2725 IP10_15_12 2726 IP10_11_8 2727 IP10_7_4 2728 IP10_3_0 )) 2729 }, 2730 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 2731 IP11_31_28 2732 IP11_27_24 2733 IP11_23_20 2734 IP11_19_16 2735 IP11_15_12 2736 IP11_11_8 2737 IP11_7_4 2738 IP11_3_0 )) 2739 }, 2740 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 2741 IP12_31_28 2742 IP12_27_24 2743 IP12_23_20 2744 IP12_19_16 2745 IP12_15_12 2746 IP12_11_8 2747 IP12_7_4 2748 IP12_3_0 )) 2749 }, 2750 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 2751 /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2752 /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2753 /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2754 /* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2755 /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2756 /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2757 IP13_7_4 2758 IP13_3_0 )) 2759 }, 2760 #undef F_ 2761 #undef FM 2762 2763 #define F_(x, y) x, 2764 #define FM(x) FN_##x, 2765 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 2766 GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1, 2767 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1), 2768 GROUP( 2769 /* RESERVED 31 */ 2770 0, 0, 2771 MOD_SEL0_30 2772 MOD_SEL0_29 2773 MOD_SEL0_28 2774 MOD_SEL0_27 2775 MOD_SEL0_26 2776 MOD_SEL0_25 2777 MOD_SEL0_24_23 2778 MOD_SEL0_22_21 2779 MOD_SEL0_20_19 2780 MOD_SEL0_18_17 2781 /* RESERVED 16 */ 2782 0, 0, 2783 MOD_SEL0_15 2784 MOD_SEL0_14 2785 MOD_SEL0_13 2786 MOD_SEL0_12 2787 MOD_SEL0_11 2788 MOD_SEL0_10 2789 /* RESERVED 9, 8, 7, 6 */ 2790 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2791 MOD_SEL0_5 2792 MOD_SEL0_4 2793 MOD_SEL0_3 2794 MOD_SEL0_2 2795 MOD_SEL0_1 2796 MOD_SEL0_0 )) 2797 }, 2798 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 2799 GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4), 2800 GROUP( 2801 MOD_SEL1_31 2802 MOD_SEL1_30 2803 MOD_SEL1_29 2804 MOD_SEL1_28 2805 MOD_SEL1_27 2806 MOD_SEL1_26 2807 /* RESERVED 25, 24 */ 2808 0, 0, 0, 0, 2809 /* RESERVED 23, 22, 21, 20 */ 2810 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2811 /* RESERVED 19, 18, 17, 16 */ 2812 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2813 /* RESERVED 15, 14, 13, 12 */ 2814 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2815 /* RESERVED 11, 10, 9, 8 */ 2816 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2817 /* RESERVED 7, 6, 5, 4 */ 2818 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2819 /* RESERVED 3, 2, 1, 0 */ 2820 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 )) 2821 }, 2822 { }, 2823 }; 2824 2825 static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 2826 { 2827 int bit = -EINVAL; 2828 2829 *pocctrl = 0xe6060380; 2830 2831 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9)) 2832 bit = 29 - (pin - RCAR_GP_PIN(3, 0)); 2833 2834 return bit; 2835 } 2836 2837 enum ioctrl_regs { 2838 TDSELCTRL, 2839 }; 2840 2841 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 2842 [TDSELCTRL] = { 0xe60603c0, }, 2843 { /* sentinel */ }, 2844 }; 2845 2846 static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { 2847 .pin_to_pocctrl = r8a77995_pin_to_pocctrl, 2848 }; 2849 2850 const struct sh_pfc_soc_info r8a77995_pinmux_info = { 2851 .name = "r8a77995_pfc", 2852 .ops = &r8a77995_pinmux_ops, 2853 .unlock_reg = 0xe6060000, /* PMMR */ 2854 2855 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2856 2857 .pins = pinmux_pins, 2858 .nr_pins = ARRAY_SIZE(pinmux_pins), 2859 .groups = pinmux_groups, 2860 .nr_groups = ARRAY_SIZE(pinmux_groups), 2861 .functions = pinmux_functions, 2862 .nr_functions = ARRAY_SIZE(pinmux_functions), 2863 2864 .cfg_regs = pinmux_config_regs, 2865 .ioctrl_regs = pinmux_ioctrl_regs, 2866 2867 .pinmux_data = pinmux_data, 2868 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 2869 }; 2870