1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77990 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2018-2019 Renesas Electronics Corp. 6 * 7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c 8 * 9 * R8A7796 processor support - PFC hardware block. 10 * 11 * Copyright (C) 2016-2017 Renesas Electronics Corp. 12 */ 13 14 #include <linux/errno.h> 15 #include <linux/kernel.h> 16 17 #include "sh_pfc.h" 18 19 #define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN) 20 21 #define CPU_ALL_GP(fn, sfx) \ 22 PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ 23 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \ 24 PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \ 25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 30 PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 31 PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \ 32 PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \ 33 PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ 34 PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \ 35 PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \ 36 PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \ 37 PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \ 38 PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \ 39 PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \ 40 PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \ 41 PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS) 42 43 #define CPU_ALL_NOGP(fn) \ 44 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ 45 PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \ 46 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ 47 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ 48 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ 49 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ 50 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ 51 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ 52 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ 53 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \ 54 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ 55 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \ 56 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ 57 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ 58 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ 59 PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP) 60 61 /* 62 * F_() : just information 63 * FM() : macro for FN_xxx / xxx_MARK 64 */ 65 66 /* GPSR0 */ 67 #define GPSR0_17 F_(SDA4, IP7_27_24) 68 #define GPSR0_16 F_(SCL4, IP7_23_20) 69 #define GPSR0_15 F_(D15, IP7_19_16) 70 #define GPSR0_14 F_(D14, IP7_15_12) 71 #define GPSR0_13 F_(D13, IP7_11_8) 72 #define GPSR0_12 F_(D12, IP7_7_4) 73 #define GPSR0_11 F_(D11, IP7_3_0) 74 #define GPSR0_10 F_(D10, IP6_31_28) 75 #define GPSR0_9 F_(D9, IP6_27_24) 76 #define GPSR0_8 F_(D8, IP6_23_20) 77 #define GPSR0_7 F_(D7, IP6_19_16) 78 #define GPSR0_6 F_(D6, IP6_15_12) 79 #define GPSR0_5 F_(D5, IP6_11_8) 80 #define GPSR0_4 F_(D4, IP6_7_4) 81 #define GPSR0_3 F_(D3, IP6_3_0) 82 #define GPSR0_2 F_(D2, IP5_31_28) 83 #define GPSR0_1 F_(D1, IP5_27_24) 84 #define GPSR0_0 F_(D0, IP5_23_20) 85 86 /* GPSR1 */ 87 #define GPSR1_22 F_(WE0_N, IP5_19_16) 88 #define GPSR1_21 F_(CS0_N, IP5_15_12) 89 #define GPSR1_20 FM(CLKOUT) 90 #define GPSR1_19 F_(A19, IP5_11_8) 91 #define GPSR1_18 F_(A18, IP5_7_4) 92 #define GPSR1_17 F_(A17, IP5_3_0) 93 #define GPSR1_16 F_(A16, IP4_31_28) 94 #define GPSR1_15 F_(A15, IP4_27_24) 95 #define GPSR1_14 F_(A14, IP4_23_20) 96 #define GPSR1_13 F_(A13, IP4_19_16) 97 #define GPSR1_12 F_(A12, IP4_15_12) 98 #define GPSR1_11 F_(A11, IP4_11_8) 99 #define GPSR1_10 F_(A10, IP4_7_4) 100 #define GPSR1_9 F_(A9, IP4_3_0) 101 #define GPSR1_8 F_(A8, IP3_31_28) 102 #define GPSR1_7 F_(A7, IP3_27_24) 103 #define GPSR1_6 F_(A6, IP3_23_20) 104 #define GPSR1_5 F_(A5, IP3_19_16) 105 #define GPSR1_4 F_(A4, IP3_15_12) 106 #define GPSR1_3 F_(A3, IP3_11_8) 107 #define GPSR1_2 F_(A2, IP3_7_4) 108 #define GPSR1_1 F_(A1, IP3_3_0) 109 #define GPSR1_0 F_(A0, IP2_31_28) 110 111 /* GPSR2 */ 112 #define GPSR2_25 F_(EX_WAIT0, IP2_27_24) 113 #define GPSR2_24 F_(RD_WR_N, IP2_23_20) 114 #define GPSR2_23 F_(RD_N, IP2_19_16) 115 #define GPSR2_22 F_(BS_N, IP2_15_12) 116 #define GPSR2_21 FM(AVB_PHY_INT) 117 #define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0) 118 #define GPSR2_19 FM(AVB_RD3) 119 #define GPSR2_18 F_(AVB_RD2, IP1_31_28) 120 #define GPSR2_17 F_(AVB_RD1, IP1_27_24) 121 #define GPSR2_16 F_(AVB_RD0, IP1_23_20) 122 #define GPSR2_15 FM(AVB_RXC) 123 #define GPSR2_14 FM(AVB_RX_CTL) 124 #define GPSR2_13 F_(RPC_RESET_N, IP1_19_16) 125 #define GPSR2_12 F_(RPC_INT_N, IP1_15_12) 126 #define GPSR2_11 F_(QSPI1_SSL, IP1_11_8) 127 #define GPSR2_10 F_(QSPI1_IO3, IP1_7_4) 128 #define GPSR2_9 F_(QSPI1_IO2, IP1_3_0) 129 #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28) 130 #define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24) 131 #define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20) 132 #define GPSR2_5 FM(QSPI0_SSL) 133 #define GPSR2_4 F_(QSPI0_IO3, IP0_19_16) 134 #define GPSR2_3 F_(QSPI0_IO2, IP0_15_12) 135 #define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8) 136 #define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4) 137 #define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0) 138 139 /* GPSR3 */ 140 #define GPSR3_15 F_(SD1_WP, IP11_7_4) 141 #define GPSR3_14 F_(SD1_CD, IP11_3_0) 142 #define GPSR3_13 F_(SD0_WP, IP10_31_28) 143 #define GPSR3_12 F_(SD0_CD, IP10_27_24) 144 #define GPSR3_11 F_(SD1_DAT3, IP9_11_8) 145 #define GPSR3_10 F_(SD1_DAT2, IP9_7_4) 146 #define GPSR3_9 F_(SD1_DAT1, IP9_3_0) 147 #define GPSR3_8 F_(SD1_DAT0, IP8_31_28) 148 #define GPSR3_7 F_(SD1_CMD, IP8_27_24) 149 #define GPSR3_6 F_(SD1_CLK, IP8_23_20) 150 #define GPSR3_5 F_(SD0_DAT3, IP8_19_16) 151 #define GPSR3_4 F_(SD0_DAT2, IP8_15_12) 152 #define GPSR3_3 F_(SD0_DAT1, IP8_11_8) 153 #define GPSR3_2 F_(SD0_DAT0, IP8_7_4) 154 #define GPSR3_1 F_(SD0_CMD, IP8_3_0) 155 #define GPSR3_0 F_(SD0_CLK, IP7_31_28) 156 157 /* GPSR4 */ 158 #define GPSR4_10 F_(SD3_DS, IP10_23_20) 159 #define GPSR4_9 F_(SD3_DAT7, IP10_19_16) 160 #define GPSR4_8 F_(SD3_DAT6, IP10_15_12) 161 #define GPSR4_7 F_(SD3_DAT5, IP10_11_8) 162 #define GPSR4_6 F_(SD3_DAT4, IP10_7_4) 163 #define GPSR4_5 F_(SD3_DAT3, IP10_3_0) 164 #define GPSR4_4 F_(SD3_DAT2, IP9_31_28) 165 #define GPSR4_3 F_(SD3_DAT1, IP9_27_24) 166 #define GPSR4_2 F_(SD3_DAT0, IP9_23_20) 167 #define GPSR4_1 F_(SD3_CMD, IP9_19_16) 168 #define GPSR4_0 F_(SD3_CLK, IP9_15_12) 169 170 /* GPSR5 */ 171 #define GPSR5_19 F_(MLB_DAT, IP13_23_20) 172 #define GPSR5_18 F_(MLB_SIG, IP13_19_16) 173 #define GPSR5_17 F_(MLB_CLK, IP13_15_12) 174 #define GPSR5_16 F_(SSI_SDATA9, IP13_11_8) 175 #define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4) 176 #define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0) 177 #define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28) 178 #define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24) 179 #define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20) 180 #define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16) 181 #define GPSR5_9 F_(RX2_A, IP12_15_12) 182 #define GPSR5_8 F_(TX2_A, IP12_11_8) 183 #define GPSR5_7 F_(SCK2_A, IP12_7_4) 184 #define GPSR5_6 F_(TX1, IP12_3_0) 185 #define GPSR5_5 F_(RX1, IP11_31_28) 186 #define GPSR5_4 F_(RTS0_N_A, IP11_23_20) 187 #define GPSR5_3 F_(CTS0_N_A, IP11_19_16) 188 #define GPSR5_2 F_(TX0_A, IP11_15_12) 189 #define GPSR5_1 F_(RX0_A, IP11_11_8) 190 #define GPSR5_0 F_(SCK0_A, IP11_27_24) 191 192 /* GPSR6 */ 193 #define GPSR6_17 F_(USB30_PWEN, IP15_27_24) 194 #define GPSR6_16 F_(SSI_SDATA6, IP15_19_16) 195 #define GPSR6_15 F_(SSI_WS6, IP15_15_12) 196 #define GPSR6_14 F_(SSI_SCK6, IP15_11_8) 197 #define GPSR6_13 F_(SSI_SDATA5, IP15_7_4) 198 #define GPSR6_12 F_(SSI_WS5, IP15_3_0) 199 #define GPSR6_11 F_(SSI_SCK5, IP14_31_28) 200 #define GPSR6_10 F_(SSI_SDATA4, IP14_27_24) 201 #define GPSR6_9 F_(USB30_OVC, IP15_31_28) 202 #define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20) 203 #define GPSR6_7 F_(SSI_SDATA3, IP14_23_20) 204 #define GPSR6_6 F_(SSI_WS349, IP14_19_16) 205 #define GPSR6_5 F_(SSI_SCK349, IP14_15_12) 206 #define GPSR6_4 F_(SSI_SDATA2, IP14_11_8) 207 #define GPSR6_3 F_(SSI_SDATA1, IP14_7_4) 208 #define GPSR6_2 F_(SSI_SDATA0, IP14_3_0) 209 #define GPSR6_1 F_(SSI_WS01239, IP13_31_28) 210 #define GPSR6_0 F_(SSI_SCK01239, IP13_27_24) 211 212 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ 213 #define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 214 #define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215 #define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216 #define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 217 #define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 218 #define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 219 #define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220 #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221 #define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222 #define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223 #define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224 #define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 225 #define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 226 #define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 227 #define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 228 #define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 229 #define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 230 #define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 231 #define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 232 #define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 233 #define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 234 #define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 235 #define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 236 #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 237 #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 238 #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 239 #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 240 #define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 241 #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 242 #define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 243 #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 244 #define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 245 246 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ 247 #define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 248 #define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 249 #define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 250 #define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 251 #define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 252 #define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 253 #define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 254 #define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 255 #define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 256 #define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 257 #define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258 #define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259 #define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 260 #define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 #define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274 #define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275 #define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276 #define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 280 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ 281 #define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 #define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 #define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284 #define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285 #define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286 #define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287 #define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 288 #define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 289 #define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290 #define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291 #define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 #define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299 #define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300 #define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301 #define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302 #define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303 #define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 #define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306 #define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307 #define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309 #define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310 #define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311 #define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312 #define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313 314 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ 315 #define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316 #define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317 #define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318 #define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 319 #define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 320 #define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321 #define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322 #define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323 #define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324 #define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325 #define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326 #define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327 #define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328 #define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329 #define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330 #define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331 #define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332 #define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333 #define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334 #define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335 #define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336 #define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337 #define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338 #define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339 #define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340 #define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341 #define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 #define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343 #define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344 #define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345 #define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346 #define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347 348 #define PINMUX_GPSR \ 349 \ 350 \ 351 \ 352 \ 353 \ 354 \ 355 \ 356 GPSR2_25 \ 357 GPSR2_24 \ 358 GPSR2_23 \ 359 GPSR1_22 GPSR2_22 \ 360 GPSR1_21 GPSR2_21 \ 361 GPSR1_20 GPSR2_20 \ 362 GPSR1_19 GPSR2_19 GPSR5_19 \ 363 GPSR1_18 GPSR2_18 GPSR5_18 \ 364 GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \ 365 GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \ 366 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \ 367 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \ 368 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \ 369 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \ 370 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \ 371 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 372 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 373 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 374 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 375 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 376 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 377 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 378 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \ 379 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \ 380 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \ 381 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 382 383 #define PINMUX_IPSR \ 384 \ 385 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 386 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 387 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 388 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 389 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 390 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 391 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 392 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 393 \ 394 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 395 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 396 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 397 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ 398 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 399 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 400 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 401 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 402 \ 403 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 404 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 405 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 406 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 407 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 408 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 409 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 410 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 411 \ 412 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 413 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 414 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 415 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 416 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 417 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 418 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 419 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 420 421 /* The bit numbering in MOD_SEL fields is reversed */ 422 #define REV4(f0, f1, f2, f3) f0 f2 f1 f3 423 #define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7 424 425 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 426 #define MOD_SEL0_30_29 REV4(FM(SEL_ADGB_0), FM(SEL_ADGB_1), FM(SEL_ADGB_2), F_(0, 0)) 427 #define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) 428 #define MOD_SEL0_27_26 REV4(FM(SEL_FM_0), FM(SEL_FM_1), FM(SEL_FM_2), F_(0, 0)) 429 #define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1) 430 #define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1) 431 #define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 432 #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) 433 #define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3)) 434 #define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0)) 435 #define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1) 436 #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1) 437 #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 438 #define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0)) 439 #define MOD_SEL0_11_10 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0)) 440 #define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 441 #define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 442 #define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 443 #define MOD_SEL0_6_5 REV4(FM(SEL_REMOCON_0), FM(SEL_REMOCON_1), FM(SEL_REMOCON_2), F_(0, 0)) 444 #define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 445 #define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) 446 #define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 447 #define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0)) 448 449 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 450 #define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) 451 #define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 452 #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) 453 #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1) 454 #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 455 #define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 456 #define MOD_SEL1_24_23_22 REV8(FM(SEL_HSCIF3_0), FM(SEL_HSCIF3_1), FM(SEL_HSCIF3_2), FM(SEL_HSCIF3_3), FM(SEL_HSCIF3_4), F_(0, 0), F_(0, 0), F_(0, 0)) 457 #define MOD_SEL1_21_20_19 REV8(FM(SEL_HSCIF4_0), FM(SEL_HSCIF4_1), FM(SEL_HSCIF4_2), FM(SEL_HSCIF4_3), FM(SEL_HSCIF4_4), F_(0, 0), F_(0, 0), F_(0, 0)) 458 #define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1) 459 #define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1) 460 #define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) 461 #define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) 462 #define MOD_SEL1_14_13 REV4(FM(SEL_SCIF3_0), FM(SEL_SCIF3_1), FM(SEL_SCIF3_2), F_(0, 0)) 463 #define MOD_SEL1_12_11 REV4(FM(SEL_SCIF4_0), FM(SEL_SCIF4_1), FM(SEL_SCIF4_2), F_(0, 0)) 464 #define MOD_SEL1_10_9 REV4(FM(SEL_SCIF5_0), FM(SEL_SCIF5_1), FM(SEL_SCIF5_2), F_(0, 0)) 465 #define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 466 #define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1) 467 #define MOD_SEL1_6_5 REV4(FM(SEL_ADGC_0), FM(SEL_ADGC_1), FM(SEL_ADGC_2), F_(0, 0)) 468 #define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 469 470 #define PINMUX_MOD_SELS \ 471 \ 472 MOD_SEL1_31 \ 473 MOD_SEL0_30_29 MOD_SEL1_30 \ 474 MOD_SEL1_29 \ 475 MOD_SEL0_28 MOD_SEL1_28 \ 476 MOD_SEL0_27_26 \ 477 MOD_SEL1_26 \ 478 MOD_SEL0_25 MOD_SEL1_25 \ 479 MOD_SEL0_24 MOD_SEL1_24_23_22 \ 480 MOD_SEL0_23 \ 481 MOD_SEL0_22 \ 482 MOD_SEL0_21_20 MOD_SEL1_21_20_19 \ 483 MOD_SEL0_19_18_17 MOD_SEL1_18 \ 484 MOD_SEL1_17 \ 485 MOD_SEL0_16 MOD_SEL1_16 \ 486 MOD_SEL0_15 MOD_SEL1_15 \ 487 MOD_SEL0_14 MOD_SEL1_14_13 \ 488 MOD_SEL0_13_12 \ 489 MOD_SEL1_12_11 \ 490 MOD_SEL0_11_10 \ 491 MOD_SEL1_10_9 \ 492 MOD_SEL0_9 \ 493 MOD_SEL0_8 MOD_SEL1_8 \ 494 MOD_SEL0_7 MOD_SEL1_7 \ 495 MOD_SEL0_6_5 MOD_SEL1_6_5 \ 496 MOD_SEL0_4 MOD_SEL1_4 \ 497 MOD_SEL0_3 \ 498 MOD_SEL0_2 \ 499 MOD_SEL0_1_0 500 501 /* 502 * These pins are not able to be muxed but have other properties 503 * that can be set, such as pull-up/pull-down enable. 504 */ 505 #define PINMUX_STATIC \ 506 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \ 507 FM(AVB_TD3) \ 508 FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \ 509 FM(ASEBRK) \ 510 FM(MLB_REF) 511 512 enum { 513 PINMUX_RESERVED = 0, 514 515 PINMUX_DATA_BEGIN, 516 GP_ALL(DATA), 517 PINMUX_DATA_END, 518 519 #define F_(x, y) 520 #define FM(x) FN_##x, 521 PINMUX_FUNCTION_BEGIN, 522 GP_ALL(FN), 523 PINMUX_GPSR 524 PINMUX_IPSR 525 PINMUX_MOD_SELS 526 PINMUX_FUNCTION_END, 527 #undef F_ 528 #undef FM 529 530 #define F_(x, y) 531 #define FM(x) x##_MARK, 532 PINMUX_MARK_BEGIN, 533 PINMUX_GPSR 534 PINMUX_IPSR 535 PINMUX_MOD_SELS 536 PINMUX_STATIC 537 PINMUX_MARK_END, 538 #undef F_ 539 #undef FM 540 }; 541 542 static const u16 pinmux_data[] = { 543 PINMUX_DATA_GP_ALL(), 544 545 PINMUX_SINGLE(CLKOUT), 546 PINMUX_SINGLE(AVB_PHY_INT), 547 PINMUX_SINGLE(AVB_RD3), 548 PINMUX_SINGLE(AVB_RXC), 549 PINMUX_SINGLE(AVB_RX_CTL), 550 PINMUX_SINGLE(QSPI0_SSL), 551 552 /* IPSR0 */ 553 PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK), 554 PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0), 555 556 PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0), 557 PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0), 558 559 PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1), 560 PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0), 561 562 PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2), 563 PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A), 564 565 PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3), 566 PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0), 567 568 PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK), 569 PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0), 570 PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1), 571 PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0), 572 573 PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0), 574 PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 575 PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B), 576 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0), 577 578 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1), 579 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0), 580 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1), 581 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0), 582 583 /* IPSR1 */ 584 PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2), 585 PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0), 586 PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C), 587 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0), 588 589 PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3), 590 PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0), 591 PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2), 592 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0), 593 594 PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL), 595 PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0), 596 PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2), 597 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0), 598 599 PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N), 600 PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0), 601 PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2), 602 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0), 603 604 PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N), 605 PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0), 606 PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2), 607 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0), 608 609 PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0), 610 611 PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1), 612 613 PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2), 614 615 /* IPSR2 */ 616 PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK), 617 618 PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO), 619 620 PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC), 621 622 PINMUX_IPSR_GPSR(IP2_15_12, BS_N), 623 PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0), 624 PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC), 625 PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK), 626 PINMUX_IPSR_GPSR(IP2_15_12, TX3_C), 627 PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1), 628 629 PINMUX_IPSR_GPSR(IP2_19_16, RD_N), 630 PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0), 631 PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK), 632 PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD), 633 PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2), 634 PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A), 635 PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1), 636 637 PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N), 638 PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0), 639 PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH), 640 PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N), 641 PINMUX_IPSR_GPSR(IP2_23_20, TX5_B), 642 PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2), 643 PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0), 644 645 PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0), 646 PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0), 647 PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE), 648 PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N), 649 PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1), 650 PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0), 651 652 PINMUX_IPSR_GPSR(IP2_31_28, A0), 653 PINMUX_IPSR_GPSR(IP2_31_28, IRQ0), 654 PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0), 655 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1), 656 PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0), 657 PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE), 658 PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3), 659 PINMUX_IPSR_GPSR(IP2_31_28, IERX), 660 PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE), 661 662 /* IPSR3 */ 663 PINMUX_IPSR_GPSR(IP3_3_0, A1), 664 PINMUX_IPSR_GPSR(IP3_3_0, IRQ1), 665 PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0), 666 PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1), 667 PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0), 668 PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE), 669 PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1), 670 PINMUX_IPSR_GPSR(IP3_3_0, IETX), 671 PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE), 672 673 PINMUX_IPSR_GPSR(IP3_7_4, A2), 674 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2), 675 PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS), 676 PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB), 677 PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0), 678 PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP), 679 PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1), 680 PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE), 681 682 PINMUX_IPSR_GPSR(IP3_11_8, A3), 683 PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0), 684 PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0), 685 PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12), 686 PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0), 687 PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D), 688 PINMUX_IPSR_GPSR(IP3_11_8, IECLK), 689 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12), 690 691 PINMUX_IPSR_GPSR(IP3_15_12, A4), 692 PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0), 693 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1), 694 PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8), 695 PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1), 696 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 697 PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1), 698 699 PINMUX_IPSR_GPSR(IP3_19_16, A5), 700 PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0), 701 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1), 702 PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9), 703 PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1), 704 PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1), 705 PINMUX_IPSR_GPSR(IP3_19_16, QPOLA), 706 707 PINMUX_IPSR_GPSR(IP3_23_20, A6), 708 PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0), 709 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1), 710 PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10), 711 PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1), 712 713 PINMUX_IPSR_GPSR(IP3_27_24, A7), 714 PINMUX_IPSR_GPSR(IP3_27_24, TX4_A), 715 PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B), 716 PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11), 717 PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1), 718 719 PINMUX_IPSR_GPSR(IP3_31_28, A8), 720 PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0), 721 PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1), 722 PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2), 723 PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0), 724 PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC), 725 PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1), 726 PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS), 727 728 /* IPSR4 */ 729 PINMUX_IPSR_GPSR(IP4_3_0, A9), 730 PINMUX_IPSR_GPSR(IP4_3_0, TX5_A), 731 PINMUX_IPSR_GPSR(IP4_3_0, IRQ3), 732 PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16), 733 PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0), 734 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7), 735 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15), 736 737 PINMUX_IPSR_GPSR(IP4_7_4, A10), 738 PINMUX_IPSR_GPSR(IP4_7_4, IRQ4), 739 PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1), 740 PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13), 741 PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0), 742 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5), 743 PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B), 744 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13), 745 746 PINMUX_IPSR_GPSR(IP4_11_8, A11), 747 PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0), 748 PINMUX_IPSR_GPSR(IP4_11_8, TX3_B), 749 PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C), 750 PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC), 751 PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1), 752 PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS), 753 754 PINMUX_IPSR_GPSR(IP4_15_12, A12), 755 PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0), 756 PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B), 757 PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17), 758 PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0), 759 PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6), 760 PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14), 761 762 PINMUX_IPSR_GPSR(IP4_19_16, A13), 763 PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0), 764 PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1), 765 PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14), 766 PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3), 767 PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2), 768 PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2), 769 770 PINMUX_IPSR_GPSR(IP4_23_20, A14), 771 PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1), 772 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1), 773 PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15), 774 PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D), 775 PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3), 776 PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3), 777 778 PINMUX_IPSR_GPSR(IP4_27_24, A15), 779 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2), 780 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B), 781 PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18), 782 PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0), 783 PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4), 784 PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4), 785 786 PINMUX_IPSR_GPSR(IP4_31_28, A16), 787 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC), 788 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B), 789 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19), 790 PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0), 791 PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5), 792 PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5), 793 794 /* IPSR5 */ 795 PINMUX_IPSR_GPSR(IP5_3_0, A17), 796 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD), 797 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20), 798 PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0), 799 PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6), 800 PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6), 801 802 PINMUX_IPSR_GPSR(IP5_7_4, A18), 803 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD), 804 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21), 805 PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0), 806 PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0), 807 PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4), 808 PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0), 809 810 PINMUX_IPSR_GPSR(IP5_11_8, A19), 811 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK), 812 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22), 813 PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0), 814 PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1), 815 PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E), 816 PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1), 817 818 PINMUX_IPSR_GPSR(IP5_15_12, CS0_N), 819 PINMUX_IPSR_GPSR(IP5_15_12, SCL5), 820 PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0), 821 PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1), 822 PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16), 823 824 PINMUX_IPSR_GPSR(IP5_19_16, WE0_N), 825 PINMUX_IPSR_GPSR(IP5_19_16, SDA5), 826 PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1), 827 PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1), 828 PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17), 829 830 PINMUX_IPSR_GPSR(IP5_23_20, D0), 831 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0), 832 PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2), 833 PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2), 834 PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18), 835 836 PINMUX_IPSR_GPSR(IP5_27_24, D1), 837 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0), 838 PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0), 839 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23), 840 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0), 841 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7), 842 PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2), 843 PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7), 844 845 PINMUX_IPSR_GPSR(IP5_31_28, D2), 846 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0), 847 PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2), 848 PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0), 849 PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3), 850 PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2), 851 PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19), 852 853 /* IPSR6 */ 854 PINMUX_IPSR_GPSR(IP6_3_0, D3), 855 PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A), 856 PINMUX_IPSR_GPSR(IP6_3_0, TX5_C), 857 PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0), 858 PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4), 859 PINMUX_IPSR_GPSR(IP6_3_0, TX4_C), 860 PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20), 861 862 PINMUX_IPSR_GPSR(IP6_7_4, D4), 863 PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX), 864 PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1), 865 PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX), 866 PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0), 867 PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A), 868 PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1), 869 870 PINMUX_IPSR_GPSR(IP6_11_8, D5), 871 PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0), 872 PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1), 873 PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5), 874 PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1), 875 PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21), 876 877 PINMUX_IPSR_GPSR(IP6_15_12, D6), 878 PINMUX_IPSR_GPSR(IP6_15_12, TX3_A), 879 PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B), 880 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6), 881 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1), 882 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22), 883 884 PINMUX_IPSR_GPSR(IP6_19_16, D7), 885 PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX), 886 PINMUX_IPSR_GPSR(IP6_19_16, IRQ5), 887 PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX), 888 PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0), 889 PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1), 890 891 PINMUX_IPSR_GPSR(IP6_23_20, D8), 892 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0), 893 PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1), 894 PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0), 895 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7), 896 PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1), 897 PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4), 898 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23), 899 900 PINMUX_IPSR_GPSR(IP6_27_24, D9), 901 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0), 902 PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0), 903 PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0), 904 PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1), 905 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4), 906 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8), 907 908 PINMUX_IPSR_GPSR(IP6_31_28, D10), 909 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0), 910 PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0), 911 PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1), 912 PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1), 913 PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E), 914 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9), 915 916 /* IPSR7 */ 917 PINMUX_IPSR_GPSR(IP7_3_0, D11), 918 PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A), 919 PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0), 920 PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2), 921 PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1), 922 PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4), 923 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10), 924 925 PINMUX_IPSR_GPSR(IP7_7_4, D12), 926 PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX), 927 PINMUX_IPSR_GPSR(IP7_7_4, TX4_B), 928 PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX), 929 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0), 930 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1), 931 932 PINMUX_IPSR_GPSR(IP7_11_8, D13), 933 PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX), 934 PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1), 935 PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX), 936 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0), 937 PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1), 938 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1), 939 940 PINMUX_IPSR_GPSR(IP7_15_12, D14), 941 PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK), 942 PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0), 943 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A), 944 PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1), 945 PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1), 946 947 PINMUX_IPSR_GPSR(IP7_19_16, D15), 948 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A), 949 PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A), 950 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A), 951 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3), 952 PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11), 953 954 PINMUX_IPSR_GPSR(IP7_23_20, SCL4), 955 PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26), 956 PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0), 957 PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1), 958 PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1), 959 PINMUX_IPSR_GPSR(IP7_23_20, QCLK), 960 961 PINMUX_IPSR_GPSR(IP7_27_24, SDA4), 962 PINMUX_IPSR_GPSR(IP7_27_24, WE1_N), 963 PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1), 964 PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1), 965 PINMUX_IPSR_GPSR(IP7_27_24, QPOLB), 966 967 PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK), 968 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8), 969 PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2), 970 PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1), 971 PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4), 972 PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1), 973 974 /* IPSR8 */ 975 PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD), 976 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9), 977 PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1), 978 PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1), 979 980 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0), 981 PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10), 982 PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B), 983 PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1), 984 985 PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1), 986 PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11), 987 PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2), 988 PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1), 989 PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1), 990 991 PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2), 992 PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12), 993 PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2), 994 PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1), 995 PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B), 996 997 PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3), 998 PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13), 999 PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2), 1000 PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4), 1001 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2), 1002 PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2), 1003 1004 PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK), 1005 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), 1006 1007 PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD), 1008 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), 1009 1010 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0), 1011 PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1), 1012 1013 /* IPSR9 */ 1014 PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1), 1015 PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1), 1016 1017 PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2), 1018 PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1), 1019 1020 PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3), 1021 PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1), 1022 1023 PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK), 1024 PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N), 1025 1026 PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD), 1027 PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N), 1028 1029 PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0), 1030 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0), 1031 1032 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1), 1033 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1), 1034 1035 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2), 1036 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2), 1037 1038 /* IPSR10 */ 1039 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3), 1040 PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3), 1041 1042 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4), 1043 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4), 1044 1045 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5), 1046 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5), 1047 1048 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6), 1049 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6), 1050 1051 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7), 1052 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7), 1053 1054 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS), 1055 PINMUX_IPSR_GPSR(IP10_23_20, NFCLE), 1056 1057 PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD), 1058 PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0), 1059 PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD), 1060 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1061 PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1), 1062 PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0), 1063 PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1), 1064 PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0), 1065 1066 PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP), 1067 PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0), 1068 PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP), 1069 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), 1070 PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1), 1071 PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0), 1072 PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1), 1073 PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0), 1074 1075 /* IPSR11 */ 1076 PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD), 1077 PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0), 1078 PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1), 1079 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), 1080 PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0), 1081 1082 PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP), 1083 PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0), 1084 PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1), 1085 PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1), 1086 PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0), 1087 1088 PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0), 1089 PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0), 1090 PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0), 1091 PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC), 1092 PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1), 1093 1094 PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0), 1095 PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A), 1096 PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0), 1097 PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0), 1098 PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1), 1099 1100 PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0), 1101 PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0), 1102 PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A), 1103 PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1), 1104 PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0), 1105 PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0), 1106 1107 PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0), 1108 PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0), 1109 PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A), 1110 PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK), 1111 PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0), 1112 PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0), 1113 1114 PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0), 1115 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0), 1116 PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID), 1117 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N), 1118 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1119 PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2), 1120 PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID), 1121 1122 PINMUX_IPSR_GPSR(IP11_31_28, RX1), 1123 PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1), 1124 PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1), 1125 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B), 1126 1127 /* IPSR12 */ 1128 PINMUX_IPSR_GPSR(IP12_3_0, TX1), 1129 PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B), 1130 PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1), 1131 PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B), 1132 1133 PINMUX_IPSR_MSEL(IP12_7_4, SCK2_A, SEL_SCIF2_0), 1134 PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0), 1135 PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0), 1136 PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N), 1137 PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0), 1138 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0), 1139 PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1), 1140 1141 PINMUX_IPSR_MSEL(IP12_11_8, TX2_A, SEL_SCIF2_0), 1142 PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0), 1143 PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A), 1144 PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0), 1145 PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0), 1146 PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1), 1147 1148 PINMUX_IPSR_MSEL(IP12_15_12, RX2_A, SEL_SCIF2_0), 1149 PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A), 1150 PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A), 1151 PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0), 1152 PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0), 1153 PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1), 1154 1155 PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK), 1156 PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78), 1157 1158 PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD), 1159 PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78), 1160 PINMUX_IPSR_MSEL(IP12_23_20, TX2_B, SEL_SCIF2_1), 1161 1162 PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD), 1163 PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7), 1164 PINMUX_IPSR_MSEL(IP12_27_24, RX2_B, SEL_SCIF2_1), 1165 1166 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC), 1167 PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B), 1168 PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8), 1169 1170 /* IPSR13 */ 1171 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1), 1172 PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0), 1173 PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4), 1174 PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0), 1175 PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C), 1176 PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0), 1177 1178 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2), 1179 PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A), 1180 PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4), 1181 PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0), 1182 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2), 1183 PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A), 1184 1185 PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9), 1186 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0), 1187 PINMUX_IPSR_GPSR(IP13_11_8, SCK1), 1188 1189 PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK), 1190 PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1), 1191 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0), 1192 PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1), 1193 PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1), 1194 PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A), 1195 1196 PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG), 1197 PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1), 1198 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0), 1199 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1), 1200 PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1), 1201 PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0), 1202 1203 PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT), 1204 PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1), 1205 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0), 1206 PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A), 1207 1208 PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239), 1209 1210 PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239), 1211 1212 /* IPSR14 */ 1213 PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0), 1214 1215 PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1), 1216 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1), 1217 PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1), 1218 1219 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2), 1220 PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B), 1221 PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0), 1222 PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1), 1223 1224 PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349), 1225 PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2), 1226 1227 PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349), 1228 PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2), 1229 1230 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3), 1231 PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C), 1232 PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1), 1233 PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1), 1234 1235 PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4), 1236 PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0), 1237 PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1), 1238 1239 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5), 1240 PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1), 1241 PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B), 1242 PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3), 1243 PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1), 1244 1245 /* IPSR15 */ 1246 PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5), 1247 PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B), 1248 PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1), 1249 PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3), 1250 1251 PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5), 1252 PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1), 1253 PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2), 1254 PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0), 1255 1256 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6), 1257 PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0), 1258 PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2), 1259 PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1), 1260 PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1), 1261 PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B), 1262 1263 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6), 1264 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1265 PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C), 1266 PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2), 1267 PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3), 1268 PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1), 1269 PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1), 1270 1271 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6), 1272 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1273 PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C), 1274 PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3), 1275 PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3), 1276 PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1), 1277 PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B), 1278 1279 PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA), 1280 1281 PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN), 1282 PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A), 1283 1284 PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC), 1285 PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0), 1286 1287 /* 1288 * Static pins can not be muxed between different functions but 1289 * still need mark entries in the pinmux list. Add each static 1290 * pin to the list without an associated function. The sh-pfc 1291 * core will do the right thing and skip trying to mux the pin 1292 * while still applying configuration to it. 1293 */ 1294 #define FM(x) PINMUX_DATA(x##_MARK, 0), 1295 PINMUX_STATIC 1296 #undef FM 1297 }; 1298 1299 /* 1300 * Pins not associated with a GPIO port. 1301 */ 1302 enum { 1303 GP_ASSIGN_LAST(), 1304 NOGP_ALL(), 1305 }; 1306 1307 static const struct sh_pfc_pin pinmux_pins[] = { 1308 PINMUX_GPIO_GP_ALL(), 1309 PINMUX_NOGP_ALL(), 1310 }; 1311 1312 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1313 static const unsigned int audio_clk_a_pins[] = { 1314 /* CLK A */ 1315 RCAR_GP_PIN(6, 8), 1316 }; 1317 1318 static const unsigned int audio_clk_a_mux[] = { 1319 AUDIO_CLKA_MARK, 1320 }; 1321 1322 static const unsigned int audio_clk_b_a_pins[] = { 1323 /* CLK B_A */ 1324 RCAR_GP_PIN(5, 7), 1325 }; 1326 1327 static const unsigned int audio_clk_b_a_mux[] = { 1328 AUDIO_CLKB_A_MARK, 1329 }; 1330 1331 static const unsigned int audio_clk_b_b_pins[] = { 1332 /* CLK B_B */ 1333 RCAR_GP_PIN(6, 7), 1334 }; 1335 1336 static const unsigned int audio_clk_b_b_mux[] = { 1337 AUDIO_CLKB_B_MARK, 1338 }; 1339 1340 static const unsigned int audio_clk_b_c_pins[] = { 1341 /* CLK B_C */ 1342 RCAR_GP_PIN(6, 13), 1343 }; 1344 1345 static const unsigned int audio_clk_b_c_mux[] = { 1346 AUDIO_CLKB_C_MARK, 1347 }; 1348 1349 static const unsigned int audio_clk_c_a_pins[] = { 1350 /* CLK C_A */ 1351 RCAR_GP_PIN(5, 16), 1352 }; 1353 1354 static const unsigned int audio_clk_c_a_mux[] = { 1355 AUDIO_CLKC_A_MARK, 1356 }; 1357 1358 static const unsigned int audio_clk_c_b_pins[] = { 1359 /* CLK C_B */ 1360 RCAR_GP_PIN(6, 3), 1361 }; 1362 1363 static const unsigned int audio_clk_c_b_mux[] = { 1364 AUDIO_CLKC_B_MARK, 1365 }; 1366 1367 static const unsigned int audio_clk_c_c_pins[] = { 1368 /* CLK C_C */ 1369 RCAR_GP_PIN(6, 14), 1370 }; 1371 1372 static const unsigned int audio_clk_c_c_mux[] = { 1373 AUDIO_CLKC_C_MARK, 1374 }; 1375 1376 static const unsigned int audio_clkout_a_pins[] = { 1377 /* CLKOUT_A */ 1378 RCAR_GP_PIN(5, 3), 1379 }; 1380 1381 static const unsigned int audio_clkout_a_mux[] = { 1382 AUDIO_CLKOUT_A_MARK, 1383 }; 1384 1385 static const unsigned int audio_clkout_b_pins[] = { 1386 /* CLKOUT_B */ 1387 RCAR_GP_PIN(5, 13), 1388 }; 1389 1390 static const unsigned int audio_clkout_b_mux[] = { 1391 AUDIO_CLKOUT_B_MARK, 1392 }; 1393 1394 static const unsigned int audio_clkout1_a_pins[] = { 1395 /* CLKOUT1_A */ 1396 RCAR_GP_PIN(5, 4), 1397 }; 1398 1399 static const unsigned int audio_clkout1_a_mux[] = { 1400 AUDIO_CLKOUT1_A_MARK, 1401 }; 1402 1403 static const unsigned int audio_clkout1_b_pins[] = { 1404 /* CLKOUT1_B */ 1405 RCAR_GP_PIN(5, 5), 1406 }; 1407 1408 static const unsigned int audio_clkout1_b_mux[] = { 1409 AUDIO_CLKOUT1_B_MARK, 1410 }; 1411 1412 static const unsigned int audio_clkout1_c_pins[] = { 1413 /* CLKOUT1_C */ 1414 RCAR_GP_PIN(6, 7), 1415 }; 1416 1417 static const unsigned int audio_clkout1_c_mux[] = { 1418 AUDIO_CLKOUT1_C_MARK, 1419 }; 1420 1421 static const unsigned int audio_clkout2_a_pins[] = { 1422 /* CLKOUT2_A */ 1423 RCAR_GP_PIN(5, 8), 1424 }; 1425 1426 static const unsigned int audio_clkout2_a_mux[] = { 1427 AUDIO_CLKOUT2_A_MARK, 1428 }; 1429 1430 static const unsigned int audio_clkout2_b_pins[] = { 1431 /* CLKOUT2_B */ 1432 RCAR_GP_PIN(6, 4), 1433 }; 1434 1435 static const unsigned int audio_clkout2_b_mux[] = { 1436 AUDIO_CLKOUT2_B_MARK, 1437 }; 1438 1439 static const unsigned int audio_clkout2_c_pins[] = { 1440 /* CLKOUT2_C */ 1441 RCAR_GP_PIN(6, 15), 1442 }; 1443 1444 static const unsigned int audio_clkout2_c_mux[] = { 1445 AUDIO_CLKOUT2_C_MARK, 1446 }; 1447 1448 static const unsigned int audio_clkout3_a_pins[] = { 1449 /* CLKOUT3_A */ 1450 RCAR_GP_PIN(5, 9), 1451 }; 1452 1453 static const unsigned int audio_clkout3_a_mux[] = { 1454 AUDIO_CLKOUT3_A_MARK, 1455 }; 1456 1457 static const unsigned int audio_clkout3_b_pins[] = { 1458 /* CLKOUT3_B */ 1459 RCAR_GP_PIN(5, 6), 1460 }; 1461 1462 static const unsigned int audio_clkout3_b_mux[] = { 1463 AUDIO_CLKOUT3_B_MARK, 1464 }; 1465 1466 static const unsigned int audio_clkout3_c_pins[] = { 1467 /* CLKOUT3_C */ 1468 RCAR_GP_PIN(6, 16), 1469 }; 1470 1471 static const unsigned int audio_clkout3_c_mux[] = { 1472 AUDIO_CLKOUT3_C_MARK, 1473 }; 1474 1475 /* - EtherAVB --------------------------------------------------------------- */ 1476 static const unsigned int avb_link_pins[] = { 1477 /* AVB_LINK */ 1478 RCAR_GP_PIN(2, 23), 1479 }; 1480 1481 static const unsigned int avb_link_mux[] = { 1482 AVB_LINK_MARK, 1483 }; 1484 1485 static const unsigned int avb_magic_pins[] = { 1486 /* AVB_MAGIC */ 1487 RCAR_GP_PIN(2, 22), 1488 }; 1489 1490 static const unsigned int avb_magic_mux[] = { 1491 AVB_MAGIC_MARK, 1492 }; 1493 1494 static const unsigned int avb_phy_int_pins[] = { 1495 /* AVB_PHY_INT */ 1496 RCAR_GP_PIN(2, 21), 1497 }; 1498 1499 static const unsigned int avb_phy_int_mux[] = { 1500 AVB_PHY_INT_MARK, 1501 }; 1502 1503 static const unsigned int avb_mii_pins[] = { 1504 /* 1505 * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1506 * AVB_RD1, AVB_RD2, AVB_RD3, 1507 * AVB_TXCREFCLK 1508 */ 1509 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), 1510 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), 1511 RCAR_GP_PIN(2, 20), 1512 }; 1513 1514 static const unsigned int avb_mii_mux[] = { 1515 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1516 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1517 AVB_TXCREFCLK_MARK, 1518 }; 1519 1520 static const unsigned int avb_avtp_pps_pins[] = { 1521 /* AVB_AVTP_PPS */ 1522 RCAR_GP_PIN(1, 2), 1523 }; 1524 1525 static const unsigned int avb_avtp_pps_mux[] = { 1526 AVB_AVTP_PPS_MARK, 1527 }; 1528 1529 static const unsigned int avb_avtp_match_pins[] = { 1530 /* AVB_AVTP_MATCH */ 1531 RCAR_GP_PIN(2, 24), 1532 }; 1533 1534 static const unsigned int avb_avtp_match_mux[] = { 1535 AVB_AVTP_MATCH_MARK, 1536 }; 1537 1538 static const unsigned int avb_avtp_capture_pins[] = { 1539 /* AVB_AVTP_CAPTURE */ 1540 RCAR_GP_PIN(2, 25), 1541 }; 1542 1543 static const unsigned int avb_avtp_capture_mux[] = { 1544 AVB_AVTP_CAPTURE_MARK, 1545 }; 1546 1547 /* - CAN ------------------------------------------------------------------ */ 1548 static const unsigned int can0_data_pins[] = { 1549 /* TX, RX */ 1550 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 1551 }; 1552 1553 static const unsigned int can0_data_mux[] = { 1554 CAN0_TX_MARK, CAN0_RX_MARK, 1555 }; 1556 1557 static const unsigned int can1_data_pins[] = { 1558 /* TX, RX */ 1559 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), 1560 }; 1561 1562 static const unsigned int can1_data_mux[] = { 1563 CAN1_TX_MARK, CAN1_RX_MARK, 1564 }; 1565 1566 /* - CAN Clock -------------------------------------------------------------- */ 1567 static const unsigned int can_clk_pins[] = { 1568 /* CLK */ 1569 RCAR_GP_PIN(0, 14), 1570 }; 1571 1572 static const unsigned int can_clk_mux[] = { 1573 CAN_CLK_MARK, 1574 }; 1575 1576 /* - CAN FD --------------------------------------------------------------- */ 1577 static const unsigned int canfd0_data_pins[] = { 1578 /* TX, RX */ 1579 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 1580 }; 1581 1582 static const unsigned int canfd0_data_mux[] = { 1583 CANFD0_TX_MARK, CANFD0_RX_MARK, 1584 }; 1585 1586 static const unsigned int canfd1_data_pins[] = { 1587 /* TX, RX */ 1588 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), 1589 }; 1590 1591 static const unsigned int canfd1_data_mux[] = { 1592 CANFD1_TX_MARK, CANFD1_RX_MARK, 1593 }; 1594 1595 #ifdef CONFIG_PINCTRL_PFC_R8A77990 1596 /* - DRIF0 --------------------------------------------------------------- */ 1597 static const unsigned int drif0_ctrl_a_pins[] = { 1598 /* CLK, SYNC */ 1599 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19), 1600 }; 1601 1602 static const unsigned int drif0_ctrl_a_mux[] = { 1603 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1604 }; 1605 1606 static const unsigned int drif0_data0_a_pins[] = { 1607 /* D0 */ 1608 RCAR_GP_PIN(5, 17), 1609 }; 1610 1611 static const unsigned int drif0_data0_a_mux[] = { 1612 RIF0_D0_A_MARK, 1613 }; 1614 1615 static const unsigned int drif0_data1_a_pins[] = { 1616 /* D1 */ 1617 RCAR_GP_PIN(5, 18), 1618 }; 1619 1620 static const unsigned int drif0_data1_a_mux[] = { 1621 RIF0_D1_A_MARK, 1622 }; 1623 1624 static const unsigned int drif0_ctrl_b_pins[] = { 1625 /* CLK, SYNC */ 1626 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15), 1627 }; 1628 1629 static const unsigned int drif0_ctrl_b_mux[] = { 1630 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1631 }; 1632 1633 static const unsigned int drif0_data0_b_pins[] = { 1634 /* D0 */ 1635 RCAR_GP_PIN(3, 13), 1636 }; 1637 1638 static const unsigned int drif0_data0_b_mux[] = { 1639 RIF0_D0_B_MARK, 1640 }; 1641 1642 static const unsigned int drif0_data1_b_pins[] = { 1643 /* D1 */ 1644 RCAR_GP_PIN(3, 14), 1645 }; 1646 1647 static const unsigned int drif0_data1_b_mux[] = { 1648 RIF0_D1_B_MARK, 1649 }; 1650 1651 /* - DRIF1 --------------------------------------------------------------- */ 1652 static const unsigned int drif1_ctrl_pins[] = { 1653 /* CLK, SYNC */ 1654 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1), 1655 }; 1656 1657 static const unsigned int drif1_ctrl_mux[] = { 1658 RIF1_CLK_MARK, RIF1_SYNC_MARK, 1659 }; 1660 1661 static const unsigned int drif1_data0_pins[] = { 1662 /* D0 */ 1663 RCAR_GP_PIN(5, 2), 1664 }; 1665 1666 static const unsigned int drif1_data0_mux[] = { 1667 RIF1_D0_MARK, 1668 }; 1669 1670 static const unsigned int drif1_data1_pins[] = { 1671 /* D1 */ 1672 RCAR_GP_PIN(5, 3), 1673 }; 1674 1675 static const unsigned int drif1_data1_mux[] = { 1676 RIF1_D1_MARK, 1677 }; 1678 1679 /* - DRIF2 --------------------------------------------------------------- */ 1680 static const unsigned int drif2_ctrl_a_pins[] = { 1681 /* CLK, SYNC */ 1682 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 1683 }; 1684 1685 static const unsigned int drif2_ctrl_a_mux[] = { 1686 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 1687 }; 1688 1689 static const unsigned int drif2_data0_a_pins[] = { 1690 /* D0 */ 1691 RCAR_GP_PIN(2, 8), 1692 }; 1693 1694 static const unsigned int drif2_data0_a_mux[] = { 1695 RIF2_D0_A_MARK, 1696 }; 1697 1698 static const unsigned int drif2_data1_a_pins[] = { 1699 /* D1 */ 1700 RCAR_GP_PIN(2, 9), 1701 }; 1702 1703 static const unsigned int drif2_data1_a_mux[] = { 1704 RIF2_D1_A_MARK, 1705 }; 1706 1707 static const unsigned int drif2_ctrl_b_pins[] = { 1708 /* CLK, SYNC */ 1709 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 1710 }; 1711 1712 static const unsigned int drif2_ctrl_b_mux[] = { 1713 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 1714 }; 1715 1716 static const unsigned int drif2_data0_b_pins[] = { 1717 /* D0 */ 1718 RCAR_GP_PIN(1, 6), 1719 }; 1720 1721 static const unsigned int drif2_data0_b_mux[] = { 1722 RIF2_D0_B_MARK, 1723 }; 1724 1725 static const unsigned int drif2_data1_b_pins[] = { 1726 /* D1 */ 1727 RCAR_GP_PIN(1, 7), 1728 }; 1729 1730 static const unsigned int drif2_data1_b_mux[] = { 1731 RIF2_D1_B_MARK, 1732 }; 1733 1734 /* - DRIF3 --------------------------------------------------------------- */ 1735 static const unsigned int drif3_ctrl_a_pins[] = { 1736 /* CLK, SYNC */ 1737 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 1738 }; 1739 1740 static const unsigned int drif3_ctrl_a_mux[] = { 1741 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 1742 }; 1743 1744 static const unsigned int drif3_data0_a_pins[] = { 1745 /* D0 */ 1746 RCAR_GP_PIN(2, 12), 1747 }; 1748 1749 static const unsigned int drif3_data0_a_mux[] = { 1750 RIF3_D0_A_MARK, 1751 }; 1752 1753 static const unsigned int drif3_data1_a_pins[] = { 1754 /* D1 */ 1755 RCAR_GP_PIN(2, 13), 1756 }; 1757 1758 static const unsigned int drif3_data1_a_mux[] = { 1759 RIF3_D1_A_MARK, 1760 }; 1761 1762 static const unsigned int drif3_ctrl_b_pins[] = { 1763 /* CLK, SYNC */ 1764 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 1765 }; 1766 1767 static const unsigned int drif3_ctrl_b_mux[] = { 1768 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 1769 }; 1770 1771 static const unsigned int drif3_data0_b_pins[] = { 1772 /* D0 */ 1773 RCAR_GP_PIN(0, 10), 1774 }; 1775 1776 static const unsigned int drif3_data0_b_mux[] = { 1777 RIF3_D0_B_MARK, 1778 }; 1779 1780 static const unsigned int drif3_data1_b_pins[] = { 1781 /* D1 */ 1782 RCAR_GP_PIN(0, 11), 1783 }; 1784 1785 static const unsigned int drif3_data1_b_mux[] = { 1786 RIF3_D1_B_MARK, 1787 }; 1788 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ 1789 1790 /* - DU --------------------------------------------------------------------- */ 1791 static const unsigned int du_rgb666_pins[] = { 1792 /* R[7:2], G[7:2], B[7:2] */ 1793 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5), 1794 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0), 1795 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10), 1796 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), 1797 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 1798 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 1799 }; 1800 static const unsigned int du_rgb666_mux[] = { 1801 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 1802 DU_DR3_MARK, DU_DR2_MARK, 1803 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 1804 DU_DG3_MARK, DU_DG2_MARK, 1805 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 1806 DU_DB3_MARK, DU_DB2_MARK, 1807 }; 1808 static const unsigned int du_rgb888_pins[] = { 1809 /* R[7:0], G[7:0], B[7:0] */ 1810 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5), 1811 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0), 1812 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), 1813 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10), 1814 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), 1815 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), 1816 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 1817 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 1818 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 1819 }; 1820 static const unsigned int du_rgb888_mux[] = { 1821 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 1822 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 1823 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 1824 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 1825 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 1826 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 1827 }; 1828 static const unsigned int du_clk_in_0_pins[] = { 1829 /* CLKIN0 */ 1830 RCAR_GP_PIN(0, 16), 1831 }; 1832 static const unsigned int du_clk_in_0_mux[] = { 1833 DU_DOTCLKIN0_MARK 1834 }; 1835 static const unsigned int du_clk_in_1_pins[] = { 1836 /* CLKIN1 */ 1837 RCAR_GP_PIN(1, 1), 1838 }; 1839 static const unsigned int du_clk_in_1_mux[] = { 1840 DU_DOTCLKIN1_MARK 1841 }; 1842 static const unsigned int du_clk_out_0_pins[] = { 1843 /* CLKOUT */ 1844 RCAR_GP_PIN(1, 3), 1845 }; 1846 static const unsigned int du_clk_out_0_mux[] = { 1847 DU_DOTCLKOUT0_MARK 1848 }; 1849 static const unsigned int du_sync_pins[] = { 1850 /* VSYNC, HSYNC */ 1851 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8), 1852 }; 1853 static const unsigned int du_sync_mux[] = { 1854 DU_VSYNC_MARK, DU_HSYNC_MARK 1855 }; 1856 static const unsigned int du_disp_cde_pins[] = { 1857 /* DISP_CDE */ 1858 RCAR_GP_PIN(1, 1), 1859 }; 1860 static const unsigned int du_disp_cde_mux[] = { 1861 DU_DISP_CDE_MARK, 1862 }; 1863 static const unsigned int du_cde_pins[] = { 1864 /* CDE */ 1865 RCAR_GP_PIN(1, 0), 1866 }; 1867 static const unsigned int du_cde_mux[] = { 1868 DU_CDE_MARK, 1869 }; 1870 static const unsigned int du_disp_pins[] = { 1871 /* DISP */ 1872 RCAR_GP_PIN(1, 2), 1873 }; 1874 static const unsigned int du_disp_mux[] = { 1875 DU_DISP_MARK, 1876 }; 1877 1878 /* - HSCIF0 --------------------------------------------------*/ 1879 static const unsigned int hscif0_data_a_pins[] = { 1880 /* RX, TX */ 1881 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), 1882 }; 1883 1884 static const unsigned int hscif0_data_a_mux[] = { 1885 HRX0_A_MARK, HTX0_A_MARK, 1886 }; 1887 1888 static const unsigned int hscif0_clk_a_pins[] = { 1889 /* SCK */ 1890 RCAR_GP_PIN(5, 7), 1891 }; 1892 1893 static const unsigned int hscif0_clk_a_mux[] = { 1894 HSCK0_A_MARK, 1895 }; 1896 1897 static const unsigned int hscif0_ctrl_a_pins[] = { 1898 /* RTS, CTS */ 1899 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), 1900 }; 1901 1902 static const unsigned int hscif0_ctrl_a_mux[] = { 1903 HRTS0_N_A_MARK, HCTS0_N_A_MARK, 1904 }; 1905 1906 static const unsigned int hscif0_data_b_pins[] = { 1907 /* RX, TX */ 1908 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 1909 }; 1910 1911 static const unsigned int hscif0_data_b_mux[] = { 1912 HRX0_B_MARK, HTX0_B_MARK, 1913 }; 1914 1915 static const unsigned int hscif0_clk_b_pins[] = { 1916 /* SCK */ 1917 RCAR_GP_PIN(6, 13), 1918 }; 1919 1920 static const unsigned int hscif0_clk_b_mux[] = { 1921 HSCK0_B_MARK, 1922 }; 1923 1924 /* - HSCIF1 ------------------------------------------------- */ 1925 static const unsigned int hscif1_data_a_pins[] = { 1926 /* RX, TX */ 1927 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 1928 }; 1929 1930 static const unsigned int hscif1_data_a_mux[] = { 1931 HRX1_A_MARK, HTX1_A_MARK, 1932 }; 1933 1934 static const unsigned int hscif1_clk_a_pins[] = { 1935 /* SCK */ 1936 RCAR_GP_PIN(5, 0), 1937 }; 1938 1939 static const unsigned int hscif1_clk_a_mux[] = { 1940 HSCK1_A_MARK, 1941 }; 1942 1943 static const unsigned int hscif1_data_b_pins[] = { 1944 /* RX, TX */ 1945 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), 1946 }; 1947 1948 static const unsigned int hscif1_data_b_mux[] = { 1949 HRX1_B_MARK, HTX1_B_MARK, 1950 }; 1951 1952 static const unsigned int hscif1_clk_b_pins[] = { 1953 /* SCK */ 1954 RCAR_GP_PIN(3, 0), 1955 }; 1956 1957 static const unsigned int hscif1_clk_b_mux[] = { 1958 HSCK1_B_MARK, 1959 }; 1960 1961 static const unsigned int hscif1_ctrl_b_pins[] = { 1962 /* RTS, CTS */ 1963 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), 1964 }; 1965 1966 static const unsigned int hscif1_ctrl_b_mux[] = { 1967 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 1968 }; 1969 1970 /* - HSCIF2 ------------------------------------------------- */ 1971 static const unsigned int hscif2_data_a_pins[] = { 1972 /* RX, TX */ 1973 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), 1974 }; 1975 1976 static const unsigned int hscif2_data_a_mux[] = { 1977 HRX2_A_MARK, HTX2_A_MARK, 1978 }; 1979 1980 static const unsigned int hscif2_clk_a_pins[] = { 1981 /* SCK */ 1982 RCAR_GP_PIN(6, 14), 1983 }; 1984 1985 static const unsigned int hscif2_clk_a_mux[] = { 1986 HSCK2_A_MARK, 1987 }; 1988 1989 static const unsigned int hscif2_ctrl_a_pins[] = { 1990 /* RTS, CTS */ 1991 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15), 1992 }; 1993 1994 static const unsigned int hscif2_ctrl_a_mux[] = { 1995 HRTS2_N_A_MARK, HCTS2_N_A_MARK, 1996 }; 1997 1998 static const unsigned int hscif2_data_b_pins[] = { 1999 /* RX, TX */ 2000 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2001 }; 2002 2003 static const unsigned int hscif2_data_b_mux[] = { 2004 HRX2_B_MARK, HTX2_B_MARK, 2005 }; 2006 2007 /* - HSCIF3 ------------------------------------------------*/ 2008 static const unsigned int hscif3_data_a_pins[] = { 2009 /* RX, TX */ 2010 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2011 }; 2012 2013 static const unsigned int hscif3_data_a_mux[] = { 2014 HRX3_A_MARK, HTX3_A_MARK, 2015 }; 2016 2017 static const unsigned int hscif3_data_b_pins[] = { 2018 /* RX, TX */ 2019 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 2020 }; 2021 2022 static const unsigned int hscif3_data_b_mux[] = { 2023 HRX3_B_MARK, HTX3_B_MARK, 2024 }; 2025 2026 static const unsigned int hscif3_clk_b_pins[] = { 2027 /* SCK */ 2028 RCAR_GP_PIN(0, 4), 2029 }; 2030 2031 static const unsigned int hscif3_clk_b_mux[] = { 2032 HSCK3_B_MARK, 2033 }; 2034 2035 static const unsigned int hscif3_data_c_pins[] = { 2036 /* RX, TX */ 2037 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9), 2038 }; 2039 2040 static const unsigned int hscif3_data_c_mux[] = { 2041 HRX3_C_MARK, HTX3_C_MARK, 2042 }; 2043 2044 static const unsigned int hscif3_clk_c_pins[] = { 2045 /* SCK */ 2046 RCAR_GP_PIN(2, 11), 2047 }; 2048 2049 static const unsigned int hscif3_clk_c_mux[] = { 2050 HSCK3_C_MARK, 2051 }; 2052 2053 static const unsigned int hscif3_ctrl_c_pins[] = { 2054 /* RTS, CTS */ 2055 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12), 2056 }; 2057 2058 static const unsigned int hscif3_ctrl_c_mux[] = { 2059 HRTS3_N_C_MARK, HCTS3_N_C_MARK, 2060 }; 2061 2062 static const unsigned int hscif3_data_d_pins[] = { 2063 /* RX, TX */ 2064 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3), 2065 }; 2066 2067 static const unsigned int hscif3_data_d_mux[] = { 2068 HRX3_D_MARK, HTX3_D_MARK, 2069 }; 2070 2071 static const unsigned int hscif3_data_e_pins[] = { 2072 /* RX, TX */ 2073 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 2074 }; 2075 2076 static const unsigned int hscif3_data_e_mux[] = { 2077 HRX3_E_MARK, HTX3_E_MARK, 2078 }; 2079 2080 static const unsigned int hscif3_ctrl_e_pins[] = { 2081 /* RTS, CTS */ 2082 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8), 2083 }; 2084 2085 static const unsigned int hscif3_ctrl_e_mux[] = { 2086 HRTS3_N_E_MARK, HCTS3_N_E_MARK, 2087 }; 2088 2089 /* - HSCIF4 -------------------------------------------------- */ 2090 static const unsigned int hscif4_data_a_pins[] = { 2091 /* RX, TX */ 2092 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), 2093 }; 2094 2095 static const unsigned int hscif4_data_a_mux[] = { 2096 HRX4_A_MARK, HTX4_A_MARK, 2097 }; 2098 2099 static const unsigned int hscif4_clk_a_pins[] = { 2100 /* SCK */ 2101 RCAR_GP_PIN(2, 0), 2102 }; 2103 2104 static const unsigned int hscif4_clk_a_mux[] = { 2105 HSCK4_A_MARK, 2106 }; 2107 2108 static const unsigned int hscif4_ctrl_a_pins[] = { 2109 /* RTS, CTS */ 2110 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1), 2111 }; 2112 2113 static const unsigned int hscif4_ctrl_a_mux[] = { 2114 HRTS4_N_A_MARK, HCTS4_N_A_MARK, 2115 }; 2116 2117 static const unsigned int hscif4_data_b_pins[] = { 2118 /* RX, TX */ 2119 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7), 2120 }; 2121 2122 static const unsigned int hscif4_data_b_mux[] = { 2123 HRX4_B_MARK, HTX4_B_MARK, 2124 }; 2125 2126 static const unsigned int hscif4_clk_b_pins[] = { 2127 /* SCK */ 2128 RCAR_GP_PIN(2, 6), 2129 }; 2130 2131 static const unsigned int hscif4_clk_b_mux[] = { 2132 HSCK4_B_MARK, 2133 }; 2134 2135 static const unsigned int hscif4_data_c_pins[] = { 2136 /* RX, TX */ 2137 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2138 }; 2139 2140 static const unsigned int hscif4_data_c_mux[] = { 2141 HRX4_C_MARK, HTX4_C_MARK, 2142 }; 2143 2144 static const unsigned int hscif4_data_d_pins[] = { 2145 /* RX, TX */ 2146 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 2147 }; 2148 2149 static const unsigned int hscif4_data_d_mux[] = { 2150 HRX4_D_MARK, HTX4_D_MARK, 2151 }; 2152 2153 static const unsigned int hscif4_data_e_pins[] = { 2154 /* RX, TX */ 2155 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), 2156 }; 2157 2158 static const unsigned int hscif4_data_e_mux[] = { 2159 HRX4_E_MARK, HTX4_E_MARK, 2160 }; 2161 2162 /* - I2C -------------------------------------------------------------------- */ 2163 static const unsigned int i2c1_a_pins[] = { 2164 /* SCL, SDA */ 2165 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), 2166 }; 2167 2168 static const unsigned int i2c1_a_mux[] = { 2169 SCL1_A_MARK, SDA1_A_MARK, 2170 }; 2171 2172 static const unsigned int i2c1_b_pins[] = { 2173 /* SCL, SDA */ 2174 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), 2175 }; 2176 2177 static const unsigned int i2c1_b_mux[] = { 2178 SCL1_B_MARK, SDA1_B_MARK, 2179 }; 2180 2181 static const unsigned int i2c1_c_pins[] = { 2182 /* SCL, SDA */ 2183 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5), 2184 }; 2185 2186 static const unsigned int i2c1_c_mux[] = { 2187 SCL1_C_MARK, SDA1_C_MARK, 2188 }; 2189 2190 static const unsigned int i2c1_d_pins[] = { 2191 /* SCL, SDA */ 2192 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15), 2193 }; 2194 2195 static const unsigned int i2c1_d_mux[] = { 2196 SCL1_D_MARK, SDA1_D_MARK, 2197 }; 2198 2199 static const unsigned int i2c2_a_pins[] = { 2200 /* SCL, SDA */ 2201 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0), 2202 }; 2203 2204 static const unsigned int i2c2_a_mux[] = { 2205 SCL2_A_MARK, SDA2_A_MARK, 2206 }; 2207 2208 static const unsigned int i2c2_b_pins[] = { 2209 /* SCL, SDA */ 2210 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 2211 }; 2212 2213 static const unsigned int i2c2_b_mux[] = { 2214 SCL2_B_MARK, SDA2_B_MARK, 2215 }; 2216 2217 static const unsigned int i2c2_c_pins[] = { 2218 /* SCL, SDA */ 2219 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), 2220 }; 2221 2222 static const unsigned int i2c2_c_mux[] = { 2223 SCL2_C_MARK, SDA2_C_MARK, 2224 }; 2225 2226 static const unsigned int i2c2_d_pins[] = { 2227 /* SCL, SDA */ 2228 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 2229 }; 2230 2231 static const unsigned int i2c2_d_mux[] = { 2232 SCL2_D_MARK, SDA2_D_MARK, 2233 }; 2234 2235 static const unsigned int i2c2_e_pins[] = { 2236 /* SCL, SDA */ 2237 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0), 2238 }; 2239 2240 static const unsigned int i2c2_e_mux[] = { 2241 SCL2_E_MARK, SDA2_E_MARK, 2242 }; 2243 2244 static const unsigned int i2c4_pins[] = { 2245 /* SCL, SDA */ 2246 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), 2247 }; 2248 2249 static const unsigned int i2c4_mux[] = { 2250 SCL4_MARK, SDA4_MARK, 2251 }; 2252 2253 static const unsigned int i2c5_pins[] = { 2254 /* SCL, SDA */ 2255 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 2256 }; 2257 2258 static const unsigned int i2c5_mux[] = { 2259 SCL5_MARK, SDA5_MARK, 2260 }; 2261 2262 static const unsigned int i2c6_a_pins[] = { 2263 /* SCL, SDA */ 2264 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8), 2265 }; 2266 2267 static const unsigned int i2c6_a_mux[] = { 2268 SCL6_A_MARK, SDA6_A_MARK, 2269 }; 2270 2271 static const unsigned int i2c6_b_pins[] = { 2272 /* SCL, SDA */ 2273 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), 2274 }; 2275 2276 static const unsigned int i2c6_b_mux[] = { 2277 SCL6_B_MARK, SDA6_B_MARK, 2278 }; 2279 2280 static const unsigned int i2c7_a_pins[] = { 2281 /* SCL, SDA */ 2282 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25), 2283 }; 2284 2285 static const unsigned int i2c7_a_mux[] = { 2286 SCL7_A_MARK, SDA7_A_MARK, 2287 }; 2288 2289 static const unsigned int i2c7_b_pins[] = { 2290 /* SCL, SDA */ 2291 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), 2292 }; 2293 2294 static const unsigned int i2c7_b_mux[] = { 2295 SCL7_B_MARK, SDA7_B_MARK, 2296 }; 2297 2298 /* - INTC-EX ---------------------------------------------------------------- */ 2299 static const unsigned int intc_ex_irq0_pins[] = { 2300 /* IRQ0 */ 2301 RCAR_GP_PIN(1, 0), 2302 }; 2303 static const unsigned int intc_ex_irq0_mux[] = { 2304 IRQ0_MARK, 2305 }; 2306 static const unsigned int intc_ex_irq1_pins[] = { 2307 /* IRQ1 */ 2308 RCAR_GP_PIN(1, 1), 2309 }; 2310 static const unsigned int intc_ex_irq1_mux[] = { 2311 IRQ1_MARK, 2312 }; 2313 static const unsigned int intc_ex_irq2_pins[] = { 2314 /* IRQ2 */ 2315 RCAR_GP_PIN(1, 2), 2316 }; 2317 static const unsigned int intc_ex_irq2_mux[] = { 2318 IRQ2_MARK, 2319 }; 2320 static const unsigned int intc_ex_irq3_pins[] = { 2321 /* IRQ3 */ 2322 RCAR_GP_PIN(1, 9), 2323 }; 2324 static const unsigned int intc_ex_irq3_mux[] = { 2325 IRQ3_MARK, 2326 }; 2327 static const unsigned int intc_ex_irq4_pins[] = { 2328 /* IRQ4 */ 2329 RCAR_GP_PIN(1, 10), 2330 }; 2331 static const unsigned int intc_ex_irq4_mux[] = { 2332 IRQ4_MARK, 2333 }; 2334 static const unsigned int intc_ex_irq5_pins[] = { 2335 /* IRQ5 */ 2336 RCAR_GP_PIN(0, 7), 2337 }; 2338 static const unsigned int intc_ex_irq5_mux[] = { 2339 IRQ5_MARK, 2340 }; 2341 2342 /* - MSIOF0 ----------------------------------------------------------------- */ 2343 static const unsigned int msiof0_clk_pins[] = { 2344 /* SCK */ 2345 RCAR_GP_PIN(5, 10), 2346 }; 2347 2348 static const unsigned int msiof0_clk_mux[] = { 2349 MSIOF0_SCK_MARK, 2350 }; 2351 2352 static const unsigned int msiof0_sync_pins[] = { 2353 /* SYNC */ 2354 RCAR_GP_PIN(5, 13), 2355 }; 2356 2357 static const unsigned int msiof0_sync_mux[] = { 2358 MSIOF0_SYNC_MARK, 2359 }; 2360 2361 static const unsigned int msiof0_ss1_pins[] = { 2362 /* SS1 */ 2363 RCAR_GP_PIN(5, 14), 2364 }; 2365 2366 static const unsigned int msiof0_ss1_mux[] = { 2367 MSIOF0_SS1_MARK, 2368 }; 2369 2370 static const unsigned int msiof0_ss2_pins[] = { 2371 /* SS2 */ 2372 RCAR_GP_PIN(5, 15), 2373 }; 2374 2375 static const unsigned int msiof0_ss2_mux[] = { 2376 MSIOF0_SS2_MARK, 2377 }; 2378 2379 static const unsigned int msiof0_txd_pins[] = { 2380 /* TXD */ 2381 RCAR_GP_PIN(5, 12), 2382 }; 2383 2384 static const unsigned int msiof0_txd_mux[] = { 2385 MSIOF0_TXD_MARK, 2386 }; 2387 2388 static const unsigned int msiof0_rxd_pins[] = { 2389 /* RXD */ 2390 RCAR_GP_PIN(5, 11), 2391 }; 2392 2393 static const unsigned int msiof0_rxd_mux[] = { 2394 MSIOF0_RXD_MARK, 2395 }; 2396 2397 /* - MSIOF1 ----------------------------------------------------------------- */ 2398 static const unsigned int msiof1_clk_pins[] = { 2399 /* SCK */ 2400 RCAR_GP_PIN(1, 19), 2401 }; 2402 2403 static const unsigned int msiof1_clk_mux[] = { 2404 MSIOF1_SCK_MARK, 2405 }; 2406 2407 static const unsigned int msiof1_sync_pins[] = { 2408 /* SYNC */ 2409 RCAR_GP_PIN(1, 16), 2410 }; 2411 2412 static const unsigned int msiof1_sync_mux[] = { 2413 MSIOF1_SYNC_MARK, 2414 }; 2415 2416 static const unsigned int msiof1_ss1_pins[] = { 2417 /* SS1 */ 2418 RCAR_GP_PIN(1, 14), 2419 }; 2420 2421 static const unsigned int msiof1_ss1_mux[] = { 2422 MSIOF1_SS1_MARK, 2423 }; 2424 2425 static const unsigned int msiof1_ss2_pins[] = { 2426 /* SS2 */ 2427 RCAR_GP_PIN(1, 15), 2428 }; 2429 2430 static const unsigned int msiof1_ss2_mux[] = { 2431 MSIOF1_SS2_MARK, 2432 }; 2433 2434 static const unsigned int msiof1_txd_pins[] = { 2435 /* TXD */ 2436 RCAR_GP_PIN(1, 18), 2437 }; 2438 2439 static const unsigned int msiof1_txd_mux[] = { 2440 MSIOF1_TXD_MARK, 2441 }; 2442 2443 static const unsigned int msiof1_rxd_pins[] = { 2444 /* RXD */ 2445 RCAR_GP_PIN(1, 17), 2446 }; 2447 2448 static const unsigned int msiof1_rxd_mux[] = { 2449 MSIOF1_RXD_MARK, 2450 }; 2451 2452 /* - MSIOF2 ----------------------------------------------------------------- */ 2453 static const unsigned int msiof2_clk_a_pins[] = { 2454 /* SCK */ 2455 RCAR_GP_PIN(0, 8), 2456 }; 2457 2458 static const unsigned int msiof2_clk_a_mux[] = { 2459 MSIOF2_SCK_A_MARK, 2460 }; 2461 2462 static const unsigned int msiof2_sync_a_pins[] = { 2463 /* SYNC */ 2464 RCAR_GP_PIN(0, 9), 2465 }; 2466 2467 static const unsigned int msiof2_sync_a_mux[] = { 2468 MSIOF2_SYNC_A_MARK, 2469 }; 2470 2471 static const unsigned int msiof2_ss1_a_pins[] = { 2472 /* SS1 */ 2473 RCAR_GP_PIN(0, 15), 2474 }; 2475 2476 static const unsigned int msiof2_ss1_a_mux[] = { 2477 MSIOF2_SS1_A_MARK, 2478 }; 2479 2480 static const unsigned int msiof2_ss2_a_pins[] = { 2481 /* SS2 */ 2482 RCAR_GP_PIN(0, 14), 2483 }; 2484 2485 static const unsigned int msiof2_ss2_a_mux[] = { 2486 MSIOF2_SS2_A_MARK, 2487 }; 2488 2489 static const unsigned int msiof2_txd_a_pins[] = { 2490 /* TXD */ 2491 RCAR_GP_PIN(0, 11), 2492 }; 2493 2494 static const unsigned int msiof2_txd_a_mux[] = { 2495 MSIOF2_TXD_A_MARK, 2496 }; 2497 2498 static const unsigned int msiof2_rxd_a_pins[] = { 2499 /* RXD */ 2500 RCAR_GP_PIN(0, 10), 2501 }; 2502 2503 static const unsigned int msiof2_rxd_a_mux[] = { 2504 MSIOF2_RXD_A_MARK, 2505 }; 2506 2507 static const unsigned int msiof2_clk_b_pins[] = { 2508 /* SCK */ 2509 RCAR_GP_PIN(1, 13), 2510 }; 2511 2512 static const unsigned int msiof2_clk_b_mux[] = { 2513 MSIOF2_SCK_B_MARK, 2514 }; 2515 2516 static const unsigned int msiof2_sync_b_pins[] = { 2517 /* SYNC */ 2518 RCAR_GP_PIN(1, 10), 2519 }; 2520 2521 static const unsigned int msiof2_sync_b_mux[] = { 2522 MSIOF2_SYNC_B_MARK, 2523 }; 2524 2525 static const unsigned int msiof2_ss1_b_pins[] = { 2526 /* SS1 */ 2527 RCAR_GP_PIN(1, 16), 2528 }; 2529 2530 static const unsigned int msiof2_ss1_b_mux[] = { 2531 MSIOF2_SS1_B_MARK, 2532 }; 2533 2534 static const unsigned int msiof2_ss2_b_pins[] = { 2535 /* SS2 */ 2536 RCAR_GP_PIN(1, 12), 2537 }; 2538 2539 static const unsigned int msiof2_ss2_b_mux[] = { 2540 MSIOF2_SS2_B_MARK, 2541 }; 2542 2543 static const unsigned int msiof2_txd_b_pins[] = { 2544 /* TXD */ 2545 RCAR_GP_PIN(1, 15), 2546 }; 2547 2548 static const unsigned int msiof2_txd_b_mux[] = { 2549 MSIOF2_TXD_B_MARK, 2550 }; 2551 2552 static const unsigned int msiof2_rxd_b_pins[] = { 2553 /* RXD */ 2554 RCAR_GP_PIN(1, 14), 2555 }; 2556 2557 static const unsigned int msiof2_rxd_b_mux[] = { 2558 MSIOF2_RXD_B_MARK, 2559 }; 2560 2561 /* - MSIOF3 ----------------------------------------------------------------- */ 2562 static const unsigned int msiof3_clk_a_pins[] = { 2563 /* SCK */ 2564 RCAR_GP_PIN(0, 0), 2565 }; 2566 2567 static const unsigned int msiof3_clk_a_mux[] = { 2568 MSIOF3_SCK_A_MARK, 2569 }; 2570 2571 static const unsigned int msiof3_sync_a_pins[] = { 2572 /* SYNC */ 2573 RCAR_GP_PIN(0, 1), 2574 }; 2575 2576 static const unsigned int msiof3_sync_a_mux[] = { 2577 MSIOF3_SYNC_A_MARK, 2578 }; 2579 2580 static const unsigned int msiof3_ss1_a_pins[] = { 2581 /* SS1 */ 2582 RCAR_GP_PIN(0, 15), 2583 }; 2584 2585 static const unsigned int msiof3_ss1_a_mux[] = { 2586 MSIOF3_SS1_A_MARK, 2587 }; 2588 2589 static const unsigned int msiof3_ss2_a_pins[] = { 2590 /* SS2 */ 2591 RCAR_GP_PIN(0, 4), 2592 }; 2593 2594 static const unsigned int msiof3_ss2_a_mux[] = { 2595 MSIOF3_SS2_A_MARK, 2596 }; 2597 2598 static const unsigned int msiof3_txd_a_pins[] = { 2599 /* TXD */ 2600 RCAR_GP_PIN(0, 3), 2601 }; 2602 2603 static const unsigned int msiof3_txd_a_mux[] = { 2604 MSIOF3_TXD_A_MARK, 2605 }; 2606 2607 static const unsigned int msiof3_rxd_a_pins[] = { 2608 /* RXD */ 2609 RCAR_GP_PIN(0, 2), 2610 }; 2611 2612 static const unsigned int msiof3_rxd_a_mux[] = { 2613 MSIOF3_RXD_A_MARK, 2614 }; 2615 2616 static const unsigned int msiof3_clk_b_pins[] = { 2617 /* SCK */ 2618 RCAR_GP_PIN(1, 5), 2619 }; 2620 2621 static const unsigned int msiof3_clk_b_mux[] = { 2622 MSIOF3_SCK_B_MARK, 2623 }; 2624 2625 static const unsigned int msiof3_sync_b_pins[] = { 2626 /* SYNC */ 2627 RCAR_GP_PIN(1, 4), 2628 }; 2629 2630 static const unsigned int msiof3_sync_b_mux[] = { 2631 MSIOF3_SYNC_B_MARK, 2632 }; 2633 2634 static const unsigned int msiof3_ss1_b_pins[] = { 2635 /* SS1 */ 2636 RCAR_GP_PIN(1, 0), 2637 }; 2638 2639 static const unsigned int msiof3_ss1_b_mux[] = { 2640 MSIOF3_SS1_B_MARK, 2641 }; 2642 2643 static const unsigned int msiof3_txd_b_pins[] = { 2644 /* TXD */ 2645 RCAR_GP_PIN(1, 7), 2646 }; 2647 2648 static const unsigned int msiof3_txd_b_mux[] = { 2649 MSIOF3_TXD_B_MARK, 2650 }; 2651 2652 static const unsigned int msiof3_rxd_b_pins[] = { 2653 /* RXD */ 2654 RCAR_GP_PIN(1, 6), 2655 }; 2656 2657 static const unsigned int msiof3_rxd_b_mux[] = { 2658 MSIOF3_RXD_B_MARK, 2659 }; 2660 2661 /* - PWM0 --------------------------------------------------------------------*/ 2662 static const unsigned int pwm0_a_pins[] = { 2663 /* PWM */ 2664 RCAR_GP_PIN(2, 22), 2665 }; 2666 2667 static const unsigned int pwm0_a_mux[] = { 2668 PWM0_A_MARK, 2669 }; 2670 2671 static const unsigned int pwm0_b_pins[] = { 2672 /* PWM */ 2673 RCAR_GP_PIN(6, 3), 2674 }; 2675 2676 static const unsigned int pwm0_b_mux[] = { 2677 PWM0_B_MARK, 2678 }; 2679 2680 /* - PWM1 --------------------------------------------------------------------*/ 2681 static const unsigned int pwm1_a_pins[] = { 2682 /* PWM */ 2683 RCAR_GP_PIN(2, 23), 2684 }; 2685 2686 static const unsigned int pwm1_a_mux[] = { 2687 PWM1_A_MARK, 2688 }; 2689 2690 static const unsigned int pwm1_b_pins[] = { 2691 /* PWM */ 2692 RCAR_GP_PIN(6, 4), 2693 }; 2694 2695 static const unsigned int pwm1_b_mux[] = { 2696 PWM1_B_MARK, 2697 }; 2698 2699 /* - PWM2 --------------------------------------------------------------------*/ 2700 static const unsigned int pwm2_a_pins[] = { 2701 /* PWM */ 2702 RCAR_GP_PIN(1, 0), 2703 }; 2704 2705 static const unsigned int pwm2_a_mux[] = { 2706 PWM2_A_MARK, 2707 }; 2708 2709 static const unsigned int pwm2_b_pins[] = { 2710 /* PWM */ 2711 RCAR_GP_PIN(1, 4), 2712 }; 2713 2714 static const unsigned int pwm2_b_mux[] = { 2715 PWM2_B_MARK, 2716 }; 2717 2718 static const unsigned int pwm2_c_pins[] = { 2719 /* PWM */ 2720 RCAR_GP_PIN(6, 5), 2721 }; 2722 2723 static const unsigned int pwm2_c_mux[] = { 2724 PWM2_C_MARK, 2725 }; 2726 2727 /* - PWM3 --------------------------------------------------------------------*/ 2728 static const unsigned int pwm3_a_pins[] = { 2729 /* PWM */ 2730 RCAR_GP_PIN(1, 1), 2731 }; 2732 2733 static const unsigned int pwm3_a_mux[] = { 2734 PWM3_A_MARK, 2735 }; 2736 2737 static const unsigned int pwm3_b_pins[] = { 2738 /* PWM */ 2739 RCAR_GP_PIN(1, 5), 2740 }; 2741 2742 static const unsigned int pwm3_b_mux[] = { 2743 PWM3_B_MARK, 2744 }; 2745 2746 static const unsigned int pwm3_c_pins[] = { 2747 /* PWM */ 2748 RCAR_GP_PIN(6, 6), 2749 }; 2750 2751 static const unsigned int pwm3_c_mux[] = { 2752 PWM3_C_MARK, 2753 }; 2754 2755 /* - PWM4 --------------------------------------------------------------------*/ 2756 static const unsigned int pwm4_a_pins[] = { 2757 /* PWM */ 2758 RCAR_GP_PIN(1, 3), 2759 }; 2760 2761 static const unsigned int pwm4_a_mux[] = { 2762 PWM4_A_MARK, 2763 }; 2764 2765 static const unsigned int pwm4_b_pins[] = { 2766 /* PWM */ 2767 RCAR_GP_PIN(6, 7), 2768 }; 2769 2770 static const unsigned int pwm4_b_mux[] = { 2771 PWM4_B_MARK, 2772 }; 2773 2774 /* - PWM5 --------------------------------------------------------------------*/ 2775 static const unsigned int pwm5_a_pins[] = { 2776 /* PWM */ 2777 RCAR_GP_PIN(2, 24), 2778 }; 2779 2780 static const unsigned int pwm5_a_mux[] = { 2781 PWM5_A_MARK, 2782 }; 2783 2784 static const unsigned int pwm5_b_pins[] = { 2785 /* PWM */ 2786 RCAR_GP_PIN(6, 10), 2787 }; 2788 2789 static const unsigned int pwm5_b_mux[] = { 2790 PWM5_B_MARK, 2791 }; 2792 2793 /* - PWM6 --------------------------------------------------------------------*/ 2794 static const unsigned int pwm6_a_pins[] = { 2795 /* PWM */ 2796 RCAR_GP_PIN(2, 25), 2797 }; 2798 2799 static const unsigned int pwm6_a_mux[] = { 2800 PWM6_A_MARK, 2801 }; 2802 2803 static const unsigned int pwm6_b_pins[] = { 2804 /* PWM */ 2805 RCAR_GP_PIN(6, 11), 2806 }; 2807 2808 static const unsigned int pwm6_b_mux[] = { 2809 PWM6_B_MARK, 2810 }; 2811 2812 /* - QSPI0 ------------------------------------------------------------------ */ 2813 static const unsigned int qspi0_ctrl_pins[] = { 2814 /* QSPI0_SPCLK, QSPI0_SSL */ 2815 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5), 2816 }; 2817 static const unsigned int qspi0_ctrl_mux[] = { 2818 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 2819 }; 2820 static const unsigned int qspi0_data2_pins[] = { 2821 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ 2822 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 2823 }; 2824 static const unsigned int qspi0_data2_mux[] = { 2825 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 2826 }; 2827 static const unsigned int qspi0_data4_pins[] = { 2828 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ 2829 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), 2830 /* QSPI0_IO2, QSPI0_IO3 */ 2831 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), 2832 }; 2833 static const unsigned int qspi0_data4_mux[] = { 2834 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 2835 QSPI0_IO2_MARK, QSPI0_IO3_MARK, 2836 }; 2837 /* - QSPI1 ------------------------------------------------------------------ */ 2838 static const unsigned int qspi1_ctrl_pins[] = { 2839 /* QSPI1_SPCLK, QSPI1_SSL */ 2840 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11), 2841 }; 2842 static const unsigned int qspi1_ctrl_mux[] = { 2843 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 2844 }; 2845 static const unsigned int qspi1_data2_pins[] = { 2846 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ 2847 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2848 }; 2849 static const unsigned int qspi1_data2_mux[] = { 2850 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 2851 }; 2852 static const unsigned int qspi1_data4_pins[] = { 2853 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ 2854 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2855 /* QSPI1_IO2, QSPI1_IO3 */ 2856 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), 2857 }; 2858 static const unsigned int qspi1_data4_mux[] = { 2859 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 2860 QSPI1_IO2_MARK, QSPI1_IO3_MARK, 2861 }; 2862 2863 /* - SCIF0 ------------------------------------------------------------------ */ 2864 static const unsigned int scif0_data_a_pins[] = { 2865 /* RX, TX */ 2866 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2867 }; 2868 2869 static const unsigned int scif0_data_a_mux[] = { 2870 RX0_A_MARK, TX0_A_MARK, 2871 }; 2872 2873 static const unsigned int scif0_clk_a_pins[] = { 2874 /* SCK */ 2875 RCAR_GP_PIN(5, 0), 2876 }; 2877 2878 static const unsigned int scif0_clk_a_mux[] = { 2879 SCK0_A_MARK, 2880 }; 2881 2882 static const unsigned int scif0_ctrl_a_pins[] = { 2883 /* RTS, CTS */ 2884 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2885 }; 2886 2887 static const unsigned int scif0_ctrl_a_mux[] = { 2888 RTS0_N_A_MARK, CTS0_N_A_MARK, 2889 }; 2890 2891 static const unsigned int scif0_data_b_pins[] = { 2892 /* RX, TX */ 2893 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19), 2894 }; 2895 2896 static const unsigned int scif0_data_b_mux[] = { 2897 RX0_B_MARK, TX0_B_MARK, 2898 }; 2899 2900 static const unsigned int scif0_clk_b_pins[] = { 2901 /* SCK */ 2902 RCAR_GP_PIN(5, 18), 2903 }; 2904 2905 static const unsigned int scif0_clk_b_mux[] = { 2906 SCK0_B_MARK, 2907 }; 2908 2909 /* - SCIF1 ------------------------------------------------------------------ */ 2910 static const unsigned int scif1_data_pins[] = { 2911 /* RX, TX */ 2912 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2913 }; 2914 2915 static const unsigned int scif1_data_mux[] = { 2916 RX1_MARK, TX1_MARK, 2917 }; 2918 2919 static const unsigned int scif1_clk_pins[] = { 2920 /* SCK */ 2921 RCAR_GP_PIN(5, 16), 2922 }; 2923 2924 static const unsigned int scif1_clk_mux[] = { 2925 SCK1_MARK, 2926 }; 2927 2928 static const unsigned int scif1_ctrl_pins[] = { 2929 /* RTS, CTS */ 2930 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7), 2931 }; 2932 2933 static const unsigned int scif1_ctrl_mux[] = { 2934 RTS1_N_MARK, CTS1_N_MARK, 2935 }; 2936 2937 /* - SCIF2 ------------------------------------------------------------------ */ 2938 static const unsigned int scif2_data_a_pins[] = { 2939 /* RX, TX */ 2940 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8), 2941 }; 2942 2943 static const unsigned int scif2_data_a_mux[] = { 2944 RX2_A_MARK, TX2_A_MARK, 2945 }; 2946 2947 static const unsigned int scif2_clk_a_pins[] = { 2948 /* SCK */ 2949 RCAR_GP_PIN(5, 7), 2950 }; 2951 2952 static const unsigned int scif2_clk_a_mux[] = { 2953 SCK2_A_MARK, 2954 }; 2955 2956 static const unsigned int scif2_data_b_pins[] = { 2957 /* RX, TX */ 2958 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), 2959 }; 2960 2961 static const unsigned int scif2_data_b_mux[] = { 2962 RX2_B_MARK, TX2_B_MARK, 2963 }; 2964 2965 /* - SCIF3 ------------------------------------------------------------------ */ 2966 static const unsigned int scif3_data_a_pins[] = { 2967 /* RX, TX */ 2968 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 2969 }; 2970 2971 static const unsigned int scif3_data_a_mux[] = { 2972 RX3_A_MARK, TX3_A_MARK, 2973 }; 2974 2975 static const unsigned int scif3_clk_a_pins[] = { 2976 /* SCK */ 2977 RCAR_GP_PIN(0, 1), 2978 }; 2979 2980 static const unsigned int scif3_clk_a_mux[] = { 2981 SCK3_A_MARK, 2982 }; 2983 2984 static const unsigned int scif3_ctrl_a_pins[] = { 2985 /* RTS, CTS */ 2986 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), 2987 }; 2988 2989 static const unsigned int scif3_ctrl_a_mux[] = { 2990 RTS3_N_A_MARK, CTS3_N_A_MARK, 2991 }; 2992 2993 static const unsigned int scif3_data_b_pins[] = { 2994 /* RX, TX */ 2995 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2996 }; 2997 2998 static const unsigned int scif3_data_b_mux[] = { 2999 RX3_B_MARK, TX3_B_MARK, 3000 }; 3001 3002 static const unsigned int scif3_data_c_pins[] = { 3003 /* RX, TX */ 3004 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), 3005 }; 3006 3007 static const unsigned int scif3_data_c_mux[] = { 3008 RX3_C_MARK, TX3_C_MARK, 3009 }; 3010 3011 static const unsigned int scif3_clk_c_pins[] = { 3012 /* SCK */ 3013 RCAR_GP_PIN(2, 24), 3014 }; 3015 3016 static const unsigned int scif3_clk_c_mux[] = { 3017 SCK3_C_MARK, 3018 }; 3019 3020 /* - SCIF4 ------------------------------------------------------------------ */ 3021 static const unsigned int scif4_data_a_pins[] = { 3022 /* RX, TX */ 3023 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3024 }; 3025 3026 static const unsigned int scif4_data_a_mux[] = { 3027 RX4_A_MARK, TX4_A_MARK, 3028 }; 3029 3030 static const unsigned int scif4_clk_a_pins[] = { 3031 /* SCK */ 3032 RCAR_GP_PIN(1, 5), 3033 }; 3034 3035 static const unsigned int scif4_clk_a_mux[] = { 3036 SCK4_A_MARK, 3037 }; 3038 3039 static const unsigned int scif4_ctrl_a_pins[] = { 3040 /* RTS, CTS */ 3041 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), 3042 }; 3043 3044 static const unsigned int scif4_ctrl_a_mux[] = { 3045 RTS4_N_A_MARK, CTS4_N_A_MARK, 3046 }; 3047 3048 static const unsigned int scif4_data_b_pins[] = { 3049 /* RX, TX */ 3050 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), 3051 }; 3052 3053 static const unsigned int scif4_data_b_mux[] = { 3054 RX4_B_MARK, TX4_B_MARK, 3055 }; 3056 3057 static const unsigned int scif4_clk_b_pins[] = { 3058 /* SCK */ 3059 RCAR_GP_PIN(0, 8), 3060 }; 3061 3062 static const unsigned int scif4_clk_b_mux[] = { 3063 SCK4_B_MARK, 3064 }; 3065 3066 static const unsigned int scif4_data_c_pins[] = { 3067 /* RX, TX */ 3068 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3069 }; 3070 3071 static const unsigned int scif4_data_c_mux[] = { 3072 RX4_C_MARK, TX4_C_MARK, 3073 }; 3074 3075 static const unsigned int scif4_ctrl_c_pins[] = { 3076 /* RTS, CTS */ 3077 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), 3078 }; 3079 3080 static const unsigned int scif4_ctrl_c_mux[] = { 3081 RTS4_N_C_MARK, CTS4_N_C_MARK, 3082 }; 3083 3084 /* - SCIF5 ------------------------------------------------------------------ */ 3085 static const unsigned int scif5_data_a_pins[] = { 3086 /* RX, TX */ 3087 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9), 3088 }; 3089 3090 static const unsigned int scif5_data_a_mux[] = { 3091 RX5_A_MARK, TX5_A_MARK, 3092 }; 3093 3094 static const unsigned int scif5_clk_a_pins[] = { 3095 /* SCK */ 3096 RCAR_GP_PIN(1, 13), 3097 }; 3098 3099 static const unsigned int scif5_clk_a_mux[] = { 3100 SCK5_A_MARK, 3101 }; 3102 3103 static const unsigned int scif5_data_b_pins[] = { 3104 /* RX, TX */ 3105 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), 3106 }; 3107 3108 static const unsigned int scif5_data_b_mux[] = { 3109 RX5_B_MARK, TX5_B_MARK, 3110 }; 3111 3112 static const unsigned int scif5_data_c_pins[] = { 3113 /* RX, TX */ 3114 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3115 }; 3116 3117 static const unsigned int scif5_data_c_mux[] = { 3118 RX5_C_MARK, TX5_C_MARK, 3119 }; 3120 3121 /* - SCIF Clock ------------------------------------------------------------- */ 3122 static const unsigned int scif_clk_a_pins[] = { 3123 /* SCIF_CLK */ 3124 RCAR_GP_PIN(5, 3), 3125 }; 3126 3127 static const unsigned int scif_clk_a_mux[] = { 3128 SCIF_CLK_A_MARK, 3129 }; 3130 3131 static const unsigned int scif_clk_b_pins[] = { 3132 /* SCIF_CLK */ 3133 RCAR_GP_PIN(5, 7), 3134 }; 3135 3136 static const unsigned int scif_clk_b_mux[] = { 3137 SCIF_CLK_B_MARK, 3138 }; 3139 3140 /* - SDHI0 ------------------------------------------------------------------ */ 3141 static const unsigned int sdhi0_data1_pins[] = { 3142 /* D0 */ 3143 RCAR_GP_PIN(3, 2), 3144 }; 3145 3146 static const unsigned int sdhi0_data1_mux[] = { 3147 SD0_DAT0_MARK, 3148 }; 3149 3150 static const unsigned int sdhi0_data4_pins[] = { 3151 /* D[0:3] */ 3152 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3153 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3154 }; 3155 3156 static const unsigned int sdhi0_data4_mux[] = { 3157 SD0_DAT0_MARK, SD0_DAT1_MARK, 3158 SD0_DAT2_MARK, SD0_DAT3_MARK, 3159 }; 3160 3161 static const unsigned int sdhi0_ctrl_pins[] = { 3162 /* CLK, CMD */ 3163 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3164 }; 3165 3166 static const unsigned int sdhi0_ctrl_mux[] = { 3167 SD0_CLK_MARK, SD0_CMD_MARK, 3168 }; 3169 3170 static const unsigned int sdhi0_cd_pins[] = { 3171 /* CD */ 3172 RCAR_GP_PIN(3, 12), 3173 }; 3174 3175 static const unsigned int sdhi0_cd_mux[] = { 3176 SD0_CD_MARK, 3177 }; 3178 3179 static const unsigned int sdhi0_wp_pins[] = { 3180 /* WP */ 3181 RCAR_GP_PIN(3, 13), 3182 }; 3183 3184 static const unsigned int sdhi0_wp_mux[] = { 3185 SD0_WP_MARK, 3186 }; 3187 3188 /* - SDHI1 ------------------------------------------------------------------ */ 3189 static const unsigned int sdhi1_data1_pins[] = { 3190 /* D0 */ 3191 RCAR_GP_PIN(3, 8), 3192 }; 3193 3194 static const unsigned int sdhi1_data1_mux[] = { 3195 SD1_DAT0_MARK, 3196 }; 3197 3198 static const unsigned int sdhi1_data4_pins[] = { 3199 /* D[0:3] */ 3200 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3201 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3202 }; 3203 3204 static const unsigned int sdhi1_data4_mux[] = { 3205 SD1_DAT0_MARK, SD1_DAT1_MARK, 3206 SD1_DAT2_MARK, SD1_DAT3_MARK, 3207 }; 3208 3209 static const unsigned int sdhi1_ctrl_pins[] = { 3210 /* CLK, CMD */ 3211 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3212 }; 3213 3214 static const unsigned int sdhi1_ctrl_mux[] = { 3215 SD1_CLK_MARK, SD1_CMD_MARK, 3216 }; 3217 3218 static const unsigned int sdhi1_cd_pins[] = { 3219 /* CD */ 3220 RCAR_GP_PIN(3, 14), 3221 }; 3222 3223 static const unsigned int sdhi1_cd_mux[] = { 3224 SD1_CD_MARK, 3225 }; 3226 3227 static const unsigned int sdhi1_wp_pins[] = { 3228 /* WP */ 3229 RCAR_GP_PIN(3, 15), 3230 }; 3231 3232 static const unsigned int sdhi1_wp_mux[] = { 3233 SD1_WP_MARK, 3234 }; 3235 3236 /* - SDHI3 ------------------------------------------------------------------ */ 3237 static const unsigned int sdhi3_data1_pins[] = { 3238 /* D0 */ 3239 RCAR_GP_PIN(4, 2), 3240 }; 3241 3242 static const unsigned int sdhi3_data1_mux[] = { 3243 SD3_DAT0_MARK, 3244 }; 3245 3246 static const unsigned int sdhi3_data4_pins[] = { 3247 /* D[0:3] */ 3248 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3249 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3250 }; 3251 3252 static const unsigned int sdhi3_data4_mux[] = { 3253 SD3_DAT0_MARK, SD3_DAT1_MARK, 3254 SD3_DAT2_MARK, SD3_DAT3_MARK, 3255 }; 3256 3257 static const unsigned int sdhi3_data8_pins[] = { 3258 /* D[0:7] */ 3259 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3260 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3261 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), 3262 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), 3263 }; 3264 3265 static const unsigned int sdhi3_data8_mux[] = { 3266 SD3_DAT0_MARK, SD3_DAT1_MARK, 3267 SD3_DAT2_MARK, SD3_DAT3_MARK, 3268 SD3_DAT4_MARK, SD3_DAT5_MARK, 3269 SD3_DAT6_MARK, SD3_DAT7_MARK, 3270 }; 3271 3272 static const unsigned int sdhi3_ctrl_pins[] = { 3273 /* CLK, CMD */ 3274 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3275 }; 3276 3277 static const unsigned int sdhi3_ctrl_mux[] = { 3278 SD3_CLK_MARK, SD3_CMD_MARK, 3279 }; 3280 3281 static const unsigned int sdhi3_cd_pins[] = { 3282 /* CD */ 3283 RCAR_GP_PIN(3, 12), 3284 }; 3285 3286 static const unsigned int sdhi3_cd_mux[] = { 3287 SD3_CD_MARK, 3288 }; 3289 3290 static const unsigned int sdhi3_wp_pins[] = { 3291 /* WP */ 3292 RCAR_GP_PIN(3, 13), 3293 }; 3294 3295 static const unsigned int sdhi3_wp_mux[] = { 3296 SD3_WP_MARK, 3297 }; 3298 3299 static const unsigned int sdhi3_ds_pins[] = { 3300 /* DS */ 3301 RCAR_GP_PIN(4, 10), 3302 }; 3303 3304 static const unsigned int sdhi3_ds_mux[] = { 3305 SD3_DS_MARK, 3306 }; 3307 3308 /* - SSI -------------------------------------------------------------------- */ 3309 static const unsigned int ssi0_data_pins[] = { 3310 /* SDATA */ 3311 RCAR_GP_PIN(6, 2), 3312 }; 3313 3314 static const unsigned int ssi0_data_mux[] = { 3315 SSI_SDATA0_MARK, 3316 }; 3317 3318 static const unsigned int ssi01239_ctrl_pins[] = { 3319 /* SCK, WS */ 3320 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3321 }; 3322 3323 static const unsigned int ssi01239_ctrl_mux[] = { 3324 SSI_SCK01239_MARK, SSI_WS01239_MARK, 3325 }; 3326 3327 static const unsigned int ssi1_data_pins[] = { 3328 /* SDATA */ 3329 RCAR_GP_PIN(6, 3), 3330 }; 3331 3332 static const unsigned int ssi1_data_mux[] = { 3333 SSI_SDATA1_MARK, 3334 }; 3335 3336 static const unsigned int ssi1_ctrl_pins[] = { 3337 /* SCK, WS */ 3338 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 3339 }; 3340 3341 static const unsigned int ssi1_ctrl_mux[] = { 3342 SSI_SCK1_MARK, SSI_WS1_MARK, 3343 }; 3344 3345 static const unsigned int ssi2_data_pins[] = { 3346 /* SDATA */ 3347 RCAR_GP_PIN(6, 4), 3348 }; 3349 3350 static const unsigned int ssi2_data_mux[] = { 3351 SSI_SDATA2_MARK, 3352 }; 3353 3354 static const unsigned int ssi2_ctrl_a_pins[] = { 3355 /* SCK, WS */ 3356 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3357 }; 3358 3359 static const unsigned int ssi2_ctrl_a_mux[] = { 3360 SSI_SCK2_A_MARK, SSI_WS2_A_MARK, 3361 }; 3362 3363 static const unsigned int ssi2_ctrl_b_pins[] = { 3364 /* SCK, WS */ 3365 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), 3366 }; 3367 3368 static const unsigned int ssi2_ctrl_b_mux[] = { 3369 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 3370 }; 3371 3372 static const unsigned int ssi3_data_pins[] = { 3373 /* SDATA */ 3374 RCAR_GP_PIN(6, 7), 3375 }; 3376 3377 static const unsigned int ssi3_data_mux[] = { 3378 SSI_SDATA3_MARK, 3379 }; 3380 3381 static const unsigned int ssi349_ctrl_pins[] = { 3382 /* SCK, WS */ 3383 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), 3384 }; 3385 3386 static const unsigned int ssi349_ctrl_mux[] = { 3387 SSI_SCK349_MARK, SSI_WS349_MARK, 3388 }; 3389 3390 static const unsigned int ssi4_data_pins[] = { 3391 /* SDATA */ 3392 RCAR_GP_PIN(6, 10), 3393 }; 3394 3395 static const unsigned int ssi4_data_mux[] = { 3396 SSI_SDATA4_MARK, 3397 }; 3398 3399 static const unsigned int ssi4_ctrl_pins[] = { 3400 /* SCK, WS */ 3401 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), 3402 }; 3403 3404 static const unsigned int ssi4_ctrl_mux[] = { 3405 SSI_SCK4_MARK, SSI_WS4_MARK, 3406 }; 3407 3408 static const unsigned int ssi5_data_pins[] = { 3409 /* SDATA */ 3410 RCAR_GP_PIN(6, 13), 3411 }; 3412 3413 static const unsigned int ssi5_data_mux[] = { 3414 SSI_SDATA5_MARK, 3415 }; 3416 3417 static const unsigned int ssi5_ctrl_pins[] = { 3418 /* SCK, WS */ 3419 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 3420 }; 3421 3422 static const unsigned int ssi5_ctrl_mux[] = { 3423 SSI_SCK5_MARK, SSI_WS5_MARK, 3424 }; 3425 3426 static const unsigned int ssi6_data_pins[] = { 3427 /* SDATA */ 3428 RCAR_GP_PIN(6, 16), 3429 }; 3430 3431 static const unsigned int ssi6_data_mux[] = { 3432 SSI_SDATA6_MARK, 3433 }; 3434 3435 static const unsigned int ssi6_ctrl_pins[] = { 3436 /* SCK, WS */ 3437 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 3438 }; 3439 3440 static const unsigned int ssi6_ctrl_mux[] = { 3441 SSI_SCK6_MARK, SSI_WS6_MARK, 3442 }; 3443 3444 static const unsigned int ssi7_data_pins[] = { 3445 /* SDATA */ 3446 RCAR_GP_PIN(5, 12), 3447 }; 3448 3449 static const unsigned int ssi7_data_mux[] = { 3450 SSI_SDATA7_MARK, 3451 }; 3452 3453 static const unsigned int ssi78_ctrl_pins[] = { 3454 /* SCK, WS */ 3455 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), 3456 }; 3457 3458 static const unsigned int ssi78_ctrl_mux[] = { 3459 SSI_SCK78_MARK, SSI_WS78_MARK, 3460 }; 3461 3462 static const unsigned int ssi8_data_pins[] = { 3463 /* SDATA */ 3464 RCAR_GP_PIN(5, 13), 3465 }; 3466 3467 static const unsigned int ssi8_data_mux[] = { 3468 SSI_SDATA8_MARK, 3469 }; 3470 3471 static const unsigned int ssi9_data_pins[] = { 3472 /* SDATA */ 3473 RCAR_GP_PIN(5, 16), 3474 }; 3475 3476 static const unsigned int ssi9_data_mux[] = { 3477 SSI_SDATA9_MARK, 3478 }; 3479 3480 static const unsigned int ssi9_ctrl_a_pins[] = { 3481 /* SCK, WS */ 3482 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10), 3483 }; 3484 3485 static const unsigned int ssi9_ctrl_a_mux[] = { 3486 SSI_SCK9_A_MARK, SSI_WS9_A_MARK, 3487 }; 3488 3489 static const unsigned int ssi9_ctrl_b_pins[] = { 3490 /* SCK, WS */ 3491 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3492 }; 3493 3494 static const unsigned int ssi9_ctrl_b_mux[] = { 3495 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3496 }; 3497 3498 /* - TMU -------------------------------------------------------------------- */ 3499 static const unsigned int tmu_tclk1_a_pins[] = { 3500 /* TCLK */ 3501 RCAR_GP_PIN(3, 12), 3502 }; 3503 3504 static const unsigned int tmu_tclk1_a_mux[] = { 3505 TCLK1_A_MARK, 3506 }; 3507 3508 static const unsigned int tmu_tclk1_b_pins[] = { 3509 /* TCLK */ 3510 RCAR_GP_PIN(5, 17), 3511 }; 3512 3513 static const unsigned int tmu_tclk1_b_mux[] = { 3514 TCLK1_B_MARK, 3515 }; 3516 3517 static const unsigned int tmu_tclk2_a_pins[] = { 3518 /* TCLK */ 3519 RCAR_GP_PIN(3, 13), 3520 }; 3521 3522 static const unsigned int tmu_tclk2_a_mux[] = { 3523 TCLK2_A_MARK, 3524 }; 3525 3526 static const unsigned int tmu_tclk2_b_pins[] = { 3527 /* TCLK */ 3528 RCAR_GP_PIN(5, 18), 3529 }; 3530 3531 static const unsigned int tmu_tclk2_b_mux[] = { 3532 TCLK2_B_MARK, 3533 }; 3534 3535 /* - USB0 ------------------------------------------------------------------- */ 3536 static const unsigned int usb0_a_pins[] = { 3537 /* PWEN, OVC */ 3538 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9), 3539 }; 3540 3541 static const unsigned int usb0_a_mux[] = { 3542 USB0_PWEN_A_MARK, USB0_OVC_A_MARK, 3543 }; 3544 3545 static const unsigned int usb0_b_pins[] = { 3546 /* PWEN, OVC */ 3547 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 3548 }; 3549 3550 static const unsigned int usb0_b_mux[] = { 3551 USB0_PWEN_B_MARK, USB0_OVC_B_MARK, 3552 }; 3553 3554 static const unsigned int usb0_id_pins[] = { 3555 /* ID */ 3556 RCAR_GP_PIN(5, 0) 3557 }; 3558 3559 static const unsigned int usb0_id_mux[] = { 3560 USB0_ID_MARK, 3561 }; 3562 3563 /* - USB30 ------------------------------------------------------------------ */ 3564 static const unsigned int usb30_pins[] = { 3565 /* PWEN, OVC */ 3566 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9), 3567 }; 3568 3569 static const unsigned int usb30_mux[] = { 3570 USB30_PWEN_MARK, USB30_OVC_MARK, 3571 }; 3572 3573 static const unsigned int usb30_id_pins[] = { 3574 /* ID */ 3575 RCAR_GP_PIN(5, 0), 3576 }; 3577 3578 static const unsigned int usb30_id_mux[] = { 3579 USB3HS0_ID_MARK, 3580 }; 3581 3582 /* - VIN4 ------------------------------------------------------------------- */ 3583 static const unsigned int vin4_data18_a_pins[] = { 3584 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 3585 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 3586 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3587 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3588 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), 3589 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 3590 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 3591 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3592 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), 3593 }; 3594 3595 static const unsigned int vin4_data18_a_mux[] = { 3596 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 3597 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 3598 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 3599 VI4_DATA10_MARK, VI4_DATA11_MARK, 3600 VI4_DATA12_MARK, VI4_DATA13_MARK, 3601 VI4_DATA14_MARK, VI4_DATA15_MARK, 3602 VI4_DATA18_MARK, VI4_DATA19_MARK, 3603 VI4_DATA20_MARK, VI4_DATA21_MARK, 3604 VI4_DATA22_MARK, VI4_DATA23_MARK, 3605 }; 3606 3607 static const union vin_data vin4_data_a_pins = { 3608 .data24 = { 3609 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 3610 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 3611 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 3612 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 3613 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3614 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3615 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), 3616 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 3617 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), 3618 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 3619 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3620 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), 3621 }, 3622 }; 3623 3624 static const union vin_data vin4_data_a_mux = { 3625 .data24 = { 3626 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, 3627 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 3628 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 3629 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 3630 VI4_DATA8_MARK, VI4_DATA9_MARK, 3631 VI4_DATA10_MARK, VI4_DATA11_MARK, 3632 VI4_DATA12_MARK, VI4_DATA13_MARK, 3633 VI4_DATA14_MARK, VI4_DATA15_MARK, 3634 VI4_DATA16_MARK, VI4_DATA17_MARK, 3635 VI4_DATA18_MARK, VI4_DATA19_MARK, 3636 VI4_DATA20_MARK, VI4_DATA21_MARK, 3637 VI4_DATA22_MARK, VI4_DATA23_MARK, 3638 }, 3639 }; 3640 3641 static const unsigned int vin4_data18_b_pins[] = { 3642 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 3643 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 3644 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), 3645 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3646 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), 3647 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 3648 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 3649 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3650 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), 3651 }; 3652 3653 static const unsigned int vin4_data18_b_mux[] = { 3654 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 3655 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 3656 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 3657 VI4_DATA10_MARK, VI4_DATA11_MARK, 3658 VI4_DATA12_MARK, VI4_DATA13_MARK, 3659 VI4_DATA14_MARK, VI4_DATA15_MARK, 3660 VI4_DATA18_MARK, VI4_DATA19_MARK, 3661 VI4_DATA20_MARK, VI4_DATA21_MARK, 3662 VI4_DATA22_MARK, VI4_DATA23_MARK, 3663 }; 3664 3665 static const union vin_data vin4_data_b_pins = { 3666 .data24 = { 3667 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3668 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), 3669 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 3670 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), 3671 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3672 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3673 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), 3674 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 3675 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), 3676 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 3677 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3678 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), 3679 }, 3680 }; 3681 3682 static const union vin_data vin4_data_b_mux = { 3683 .data24 = { 3684 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, 3685 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 3686 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 3687 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 3688 VI4_DATA8_MARK, VI4_DATA9_MARK, 3689 VI4_DATA10_MARK, VI4_DATA11_MARK, 3690 VI4_DATA12_MARK, VI4_DATA13_MARK, 3691 VI4_DATA14_MARK, VI4_DATA15_MARK, 3692 VI4_DATA16_MARK, VI4_DATA17_MARK, 3693 VI4_DATA18_MARK, VI4_DATA19_MARK, 3694 VI4_DATA20_MARK, VI4_DATA21_MARK, 3695 VI4_DATA22_MARK, VI4_DATA23_MARK, 3696 }, 3697 }; 3698 3699 static const unsigned int vin4_g8_pins[] = { 3700 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 3701 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3702 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), 3703 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 3704 }; 3705 3706 static const unsigned int vin4_g8_mux[] = { 3707 VI4_DATA8_MARK, VI4_DATA9_MARK, 3708 VI4_DATA10_MARK, VI4_DATA11_MARK, 3709 VI4_DATA12_MARK, VI4_DATA13_MARK, 3710 VI4_DATA14_MARK, VI4_DATA15_MARK, 3711 }; 3712 3713 static const unsigned int vin4_sync_pins[] = { 3714 /* HSYNC, VSYNC */ 3715 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), 3716 }; 3717 3718 static const unsigned int vin4_sync_mux[] = { 3719 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 3720 }; 3721 3722 static const unsigned int vin4_field_pins[] = { 3723 RCAR_GP_PIN(2, 23), 3724 }; 3725 3726 static const unsigned int vin4_field_mux[] = { 3727 VI4_FIELD_MARK, 3728 }; 3729 3730 static const unsigned int vin4_clkenb_pins[] = { 3731 RCAR_GP_PIN(1, 2), 3732 }; 3733 3734 static const unsigned int vin4_clkenb_mux[] = { 3735 VI4_CLKENB_MARK, 3736 }; 3737 3738 static const unsigned int vin4_clk_pins[] = { 3739 RCAR_GP_PIN(2, 22), 3740 }; 3741 3742 static const unsigned int vin4_clk_mux[] = { 3743 VI4_CLK_MARK, 3744 }; 3745 3746 /* - VIN5 ------------------------------------------------------------------- */ 3747 static const union vin_data16 vin5_data_a_pins = { 3748 .data16 = { 3749 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), 3750 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12), 3751 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 3752 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 3753 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3754 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), 3755 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), 3756 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3757 }, 3758 }; 3759 3760 static const union vin_data16 vin5_data_a_mux = { 3761 .data16 = { 3762 VI5_DATA0_A_MARK, VI5_DATA1_A_MARK, 3763 VI5_DATA2_A_MARK, VI5_DATA3_A_MARK, 3764 VI5_DATA4_A_MARK, VI5_DATA5_A_MARK, 3765 VI5_DATA6_A_MARK, VI5_DATA7_A_MARK, 3766 VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, 3767 VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, 3768 VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, 3769 VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, 3770 }, 3771 }; 3772 3773 static const unsigned int vin5_data8_b_pins[] = { 3774 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4), 3775 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 12), 3776 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), 3777 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), 3778 }; 3779 3780 static const unsigned int vin5_data8_b_mux[] = { 3781 VI5_DATA0_B_MARK, VI5_DATA1_B_MARK, 3782 VI5_DATA2_B_MARK, VI5_DATA3_B_MARK, 3783 VI5_DATA4_B_MARK, VI5_DATA5_B_MARK, 3784 VI5_DATA6_B_MARK, VI5_DATA7_B_MARK, 3785 }; 3786 3787 static const unsigned int vin5_high8_pins[] = { 3788 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3789 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), 3790 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), 3791 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3792 }; 3793 3794 static const unsigned int vin5_high8_mux[] = { 3795 VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, 3796 VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, 3797 VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, 3798 VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, 3799 }; 3800 3801 static const unsigned int vin5_sync_a_pins[] = { 3802 /* HSYNC_N, VSYNC_N */ 3803 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9), 3804 }; 3805 3806 static const unsigned int vin5_sync_a_mux[] = { 3807 VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK, 3808 }; 3809 3810 static const unsigned int vin5_field_a_pins[] = { 3811 RCAR_GP_PIN(1, 10), 3812 }; 3813 3814 static const unsigned int vin5_field_a_mux[] = { 3815 VI5_FIELD_A_MARK, 3816 }; 3817 3818 static const unsigned int vin5_clkenb_a_pins[] = { 3819 RCAR_GP_PIN(0, 1), 3820 }; 3821 3822 static const unsigned int vin5_clkenb_a_mux[] = { 3823 VI5_CLKENB_A_MARK, 3824 }; 3825 3826 static const unsigned int vin5_clk_a_pins[] = { 3827 RCAR_GP_PIN(1, 0), 3828 }; 3829 3830 static const unsigned int vin5_clk_a_mux[] = { 3831 VI5_CLK_A_MARK, 3832 }; 3833 3834 static const unsigned int vin5_clk_b_pins[] = { 3835 RCAR_GP_PIN(2, 22), 3836 }; 3837 3838 static const unsigned int vin5_clk_b_mux[] = { 3839 VI5_CLK_B_MARK, 3840 }; 3841 3842 static const struct { 3843 struct sh_pfc_pin_group common[255]; 3844 #ifdef CONFIG_PINCTRL_PFC_R8A77990 3845 struct sh_pfc_pin_group automotive[21]; 3846 #endif 3847 } pinmux_groups = { 3848 .common = { 3849 SH_PFC_PIN_GROUP(audio_clk_a), 3850 SH_PFC_PIN_GROUP(audio_clk_b_a), 3851 SH_PFC_PIN_GROUP(audio_clk_b_b), 3852 SH_PFC_PIN_GROUP(audio_clk_b_c), 3853 SH_PFC_PIN_GROUP(audio_clk_c_a), 3854 SH_PFC_PIN_GROUP(audio_clk_c_b), 3855 SH_PFC_PIN_GROUP(audio_clk_c_c), 3856 SH_PFC_PIN_GROUP(audio_clkout_a), 3857 SH_PFC_PIN_GROUP(audio_clkout_b), 3858 SH_PFC_PIN_GROUP(audio_clkout1_a), 3859 SH_PFC_PIN_GROUP(audio_clkout1_b), 3860 SH_PFC_PIN_GROUP(audio_clkout1_c), 3861 SH_PFC_PIN_GROUP(audio_clkout2_a), 3862 SH_PFC_PIN_GROUP(audio_clkout2_b), 3863 SH_PFC_PIN_GROUP(audio_clkout2_c), 3864 SH_PFC_PIN_GROUP(audio_clkout3_a), 3865 SH_PFC_PIN_GROUP(audio_clkout3_b), 3866 SH_PFC_PIN_GROUP(audio_clkout3_c), 3867 SH_PFC_PIN_GROUP(avb_link), 3868 SH_PFC_PIN_GROUP(avb_magic), 3869 SH_PFC_PIN_GROUP(avb_phy_int), 3870 SH_PFC_PIN_GROUP(avb_mii), 3871 SH_PFC_PIN_GROUP(avb_avtp_pps), 3872 SH_PFC_PIN_GROUP(avb_avtp_match), 3873 SH_PFC_PIN_GROUP(avb_avtp_capture), 3874 SH_PFC_PIN_GROUP(can0_data), 3875 SH_PFC_PIN_GROUP(can1_data), 3876 SH_PFC_PIN_GROUP(can_clk), 3877 SH_PFC_PIN_GROUP(canfd0_data), 3878 SH_PFC_PIN_GROUP(canfd1_data), 3879 SH_PFC_PIN_GROUP(du_rgb666), 3880 SH_PFC_PIN_GROUP(du_rgb888), 3881 SH_PFC_PIN_GROUP(du_clk_in_0), 3882 SH_PFC_PIN_GROUP(du_clk_in_1), 3883 SH_PFC_PIN_GROUP(du_clk_out_0), 3884 SH_PFC_PIN_GROUP(du_sync), 3885 SH_PFC_PIN_GROUP(du_disp_cde), 3886 SH_PFC_PIN_GROUP(du_cde), 3887 SH_PFC_PIN_GROUP(du_disp), 3888 SH_PFC_PIN_GROUP(hscif0_data_a), 3889 SH_PFC_PIN_GROUP(hscif0_clk_a), 3890 SH_PFC_PIN_GROUP(hscif0_ctrl_a), 3891 SH_PFC_PIN_GROUP(hscif0_data_b), 3892 SH_PFC_PIN_GROUP(hscif0_clk_b), 3893 SH_PFC_PIN_GROUP(hscif1_data_a), 3894 SH_PFC_PIN_GROUP(hscif1_clk_a), 3895 SH_PFC_PIN_GROUP(hscif1_data_b), 3896 SH_PFC_PIN_GROUP(hscif1_clk_b), 3897 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 3898 SH_PFC_PIN_GROUP(hscif2_data_a), 3899 SH_PFC_PIN_GROUP(hscif2_clk_a), 3900 SH_PFC_PIN_GROUP(hscif2_ctrl_a), 3901 SH_PFC_PIN_GROUP(hscif2_data_b), 3902 SH_PFC_PIN_GROUP(hscif3_data_a), 3903 SH_PFC_PIN_GROUP(hscif3_data_b), 3904 SH_PFC_PIN_GROUP(hscif3_clk_b), 3905 SH_PFC_PIN_GROUP(hscif3_data_c), 3906 SH_PFC_PIN_GROUP(hscif3_clk_c), 3907 SH_PFC_PIN_GROUP(hscif3_ctrl_c), 3908 SH_PFC_PIN_GROUP(hscif3_data_d), 3909 SH_PFC_PIN_GROUP(hscif3_data_e), 3910 SH_PFC_PIN_GROUP(hscif3_ctrl_e), 3911 SH_PFC_PIN_GROUP(hscif4_data_a), 3912 SH_PFC_PIN_GROUP(hscif4_clk_a), 3913 SH_PFC_PIN_GROUP(hscif4_ctrl_a), 3914 SH_PFC_PIN_GROUP(hscif4_data_b), 3915 SH_PFC_PIN_GROUP(hscif4_clk_b), 3916 SH_PFC_PIN_GROUP(hscif4_data_c), 3917 SH_PFC_PIN_GROUP(hscif4_data_d), 3918 SH_PFC_PIN_GROUP(hscif4_data_e), 3919 SH_PFC_PIN_GROUP(i2c1_a), 3920 SH_PFC_PIN_GROUP(i2c1_b), 3921 SH_PFC_PIN_GROUP(i2c1_c), 3922 SH_PFC_PIN_GROUP(i2c1_d), 3923 SH_PFC_PIN_GROUP(i2c2_a), 3924 SH_PFC_PIN_GROUP(i2c2_b), 3925 SH_PFC_PIN_GROUP(i2c2_c), 3926 SH_PFC_PIN_GROUP(i2c2_d), 3927 SH_PFC_PIN_GROUP(i2c2_e), 3928 SH_PFC_PIN_GROUP(i2c4), 3929 SH_PFC_PIN_GROUP(i2c5), 3930 SH_PFC_PIN_GROUP(i2c6_a), 3931 SH_PFC_PIN_GROUP(i2c6_b), 3932 SH_PFC_PIN_GROUP(i2c7_a), 3933 SH_PFC_PIN_GROUP(i2c7_b), 3934 SH_PFC_PIN_GROUP(intc_ex_irq0), 3935 SH_PFC_PIN_GROUP(intc_ex_irq1), 3936 SH_PFC_PIN_GROUP(intc_ex_irq2), 3937 SH_PFC_PIN_GROUP(intc_ex_irq3), 3938 SH_PFC_PIN_GROUP(intc_ex_irq4), 3939 SH_PFC_PIN_GROUP(intc_ex_irq5), 3940 SH_PFC_PIN_GROUP(msiof0_clk), 3941 SH_PFC_PIN_GROUP(msiof0_sync), 3942 SH_PFC_PIN_GROUP(msiof0_ss1), 3943 SH_PFC_PIN_GROUP(msiof0_ss2), 3944 SH_PFC_PIN_GROUP(msiof0_txd), 3945 SH_PFC_PIN_GROUP(msiof0_rxd), 3946 SH_PFC_PIN_GROUP(msiof1_clk), 3947 SH_PFC_PIN_GROUP(msiof1_sync), 3948 SH_PFC_PIN_GROUP(msiof1_ss1), 3949 SH_PFC_PIN_GROUP(msiof1_ss2), 3950 SH_PFC_PIN_GROUP(msiof1_txd), 3951 SH_PFC_PIN_GROUP(msiof1_rxd), 3952 SH_PFC_PIN_GROUP(msiof2_clk_a), 3953 SH_PFC_PIN_GROUP(msiof2_sync_a), 3954 SH_PFC_PIN_GROUP(msiof2_ss1_a), 3955 SH_PFC_PIN_GROUP(msiof2_ss2_a), 3956 SH_PFC_PIN_GROUP(msiof2_txd_a), 3957 SH_PFC_PIN_GROUP(msiof2_rxd_a), 3958 SH_PFC_PIN_GROUP(msiof2_clk_b), 3959 SH_PFC_PIN_GROUP(msiof2_sync_b), 3960 SH_PFC_PIN_GROUP(msiof2_ss1_b), 3961 SH_PFC_PIN_GROUP(msiof2_ss2_b), 3962 SH_PFC_PIN_GROUP(msiof2_txd_b), 3963 SH_PFC_PIN_GROUP(msiof2_rxd_b), 3964 SH_PFC_PIN_GROUP(msiof3_clk_a), 3965 SH_PFC_PIN_GROUP(msiof3_sync_a), 3966 SH_PFC_PIN_GROUP(msiof3_ss1_a), 3967 SH_PFC_PIN_GROUP(msiof3_ss2_a), 3968 SH_PFC_PIN_GROUP(msiof3_txd_a), 3969 SH_PFC_PIN_GROUP(msiof3_rxd_a), 3970 SH_PFC_PIN_GROUP(msiof3_clk_b), 3971 SH_PFC_PIN_GROUP(msiof3_sync_b), 3972 SH_PFC_PIN_GROUP(msiof3_ss1_b), 3973 SH_PFC_PIN_GROUP(msiof3_txd_b), 3974 SH_PFC_PIN_GROUP(msiof3_rxd_b), 3975 SH_PFC_PIN_GROUP(pwm0_a), 3976 SH_PFC_PIN_GROUP(pwm0_b), 3977 SH_PFC_PIN_GROUP(pwm1_a), 3978 SH_PFC_PIN_GROUP(pwm1_b), 3979 SH_PFC_PIN_GROUP(pwm2_a), 3980 SH_PFC_PIN_GROUP(pwm2_b), 3981 SH_PFC_PIN_GROUP(pwm2_c), 3982 SH_PFC_PIN_GROUP(pwm3_a), 3983 SH_PFC_PIN_GROUP(pwm3_b), 3984 SH_PFC_PIN_GROUP(pwm3_c), 3985 SH_PFC_PIN_GROUP(pwm4_a), 3986 SH_PFC_PIN_GROUP(pwm4_b), 3987 SH_PFC_PIN_GROUP(pwm5_a), 3988 SH_PFC_PIN_GROUP(pwm5_b), 3989 SH_PFC_PIN_GROUP(pwm6_a), 3990 SH_PFC_PIN_GROUP(pwm6_b), 3991 SH_PFC_PIN_GROUP(qspi0_ctrl), 3992 SH_PFC_PIN_GROUP(qspi0_data2), 3993 SH_PFC_PIN_GROUP(qspi0_data4), 3994 SH_PFC_PIN_GROUP(qspi1_ctrl), 3995 SH_PFC_PIN_GROUP(qspi1_data2), 3996 SH_PFC_PIN_GROUP(qspi1_data4), 3997 SH_PFC_PIN_GROUP(scif0_data_a), 3998 SH_PFC_PIN_GROUP(scif0_clk_a), 3999 SH_PFC_PIN_GROUP(scif0_ctrl_a), 4000 SH_PFC_PIN_GROUP(scif0_data_b), 4001 SH_PFC_PIN_GROUP(scif0_clk_b), 4002 SH_PFC_PIN_GROUP(scif1_data), 4003 SH_PFC_PIN_GROUP(scif1_clk), 4004 SH_PFC_PIN_GROUP(scif1_ctrl), 4005 SH_PFC_PIN_GROUP(scif2_data_a), 4006 SH_PFC_PIN_GROUP(scif2_clk_a), 4007 SH_PFC_PIN_GROUP(scif2_data_b), 4008 SH_PFC_PIN_GROUP(scif3_data_a), 4009 SH_PFC_PIN_GROUP(scif3_clk_a), 4010 SH_PFC_PIN_GROUP(scif3_ctrl_a), 4011 SH_PFC_PIN_GROUP(scif3_data_b), 4012 SH_PFC_PIN_GROUP(scif3_data_c), 4013 SH_PFC_PIN_GROUP(scif3_clk_c), 4014 SH_PFC_PIN_GROUP(scif4_data_a), 4015 SH_PFC_PIN_GROUP(scif4_clk_a), 4016 SH_PFC_PIN_GROUP(scif4_ctrl_a), 4017 SH_PFC_PIN_GROUP(scif4_data_b), 4018 SH_PFC_PIN_GROUP(scif4_clk_b), 4019 SH_PFC_PIN_GROUP(scif4_data_c), 4020 SH_PFC_PIN_GROUP(scif4_ctrl_c), 4021 SH_PFC_PIN_GROUP(scif5_data_a), 4022 SH_PFC_PIN_GROUP(scif5_clk_a), 4023 SH_PFC_PIN_GROUP(scif5_data_b), 4024 SH_PFC_PIN_GROUP(scif5_data_c), 4025 SH_PFC_PIN_GROUP(scif_clk_a), 4026 SH_PFC_PIN_GROUP(scif_clk_b), 4027 SH_PFC_PIN_GROUP(sdhi0_data1), 4028 SH_PFC_PIN_GROUP(sdhi0_data4), 4029 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4030 SH_PFC_PIN_GROUP(sdhi0_cd), 4031 SH_PFC_PIN_GROUP(sdhi0_wp), 4032 SH_PFC_PIN_GROUP(sdhi1_data1), 4033 SH_PFC_PIN_GROUP(sdhi1_data4), 4034 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4035 SH_PFC_PIN_GROUP(sdhi1_cd), 4036 SH_PFC_PIN_GROUP(sdhi1_wp), 4037 SH_PFC_PIN_GROUP(sdhi3_data1), 4038 SH_PFC_PIN_GROUP(sdhi3_data4), 4039 SH_PFC_PIN_GROUP(sdhi3_data8), 4040 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4041 SH_PFC_PIN_GROUP(sdhi3_cd), 4042 SH_PFC_PIN_GROUP(sdhi3_wp), 4043 SH_PFC_PIN_GROUP(sdhi3_ds), 4044 SH_PFC_PIN_GROUP(ssi0_data), 4045 SH_PFC_PIN_GROUP(ssi01239_ctrl), 4046 SH_PFC_PIN_GROUP(ssi1_data), 4047 SH_PFC_PIN_GROUP(ssi1_ctrl), 4048 SH_PFC_PIN_GROUP(ssi2_data), 4049 SH_PFC_PIN_GROUP(ssi2_ctrl_a), 4050 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4051 SH_PFC_PIN_GROUP(ssi3_data), 4052 SH_PFC_PIN_GROUP(ssi349_ctrl), 4053 SH_PFC_PIN_GROUP(ssi4_data), 4054 SH_PFC_PIN_GROUP(ssi4_ctrl), 4055 SH_PFC_PIN_GROUP(ssi5_data), 4056 SH_PFC_PIN_GROUP(ssi5_ctrl), 4057 SH_PFC_PIN_GROUP(ssi6_data), 4058 SH_PFC_PIN_GROUP(ssi6_ctrl), 4059 SH_PFC_PIN_GROUP(ssi7_data), 4060 SH_PFC_PIN_GROUP(ssi78_ctrl), 4061 SH_PFC_PIN_GROUP(ssi8_data), 4062 SH_PFC_PIN_GROUP(ssi9_data), 4063 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4064 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4065 SH_PFC_PIN_GROUP(tmu_tclk1_a), 4066 SH_PFC_PIN_GROUP(tmu_tclk1_b), 4067 SH_PFC_PIN_GROUP(tmu_tclk2_a), 4068 SH_PFC_PIN_GROUP(tmu_tclk2_b), 4069 SH_PFC_PIN_GROUP(usb0_a), 4070 SH_PFC_PIN_GROUP(usb0_b), 4071 SH_PFC_PIN_GROUP(usb0_id), 4072 SH_PFC_PIN_GROUP(usb30), 4073 SH_PFC_PIN_GROUP(usb30_id), 4074 VIN_DATA_PIN_GROUP(vin4_data, 8, _a), 4075 VIN_DATA_PIN_GROUP(vin4_data, 10, _a), 4076 VIN_DATA_PIN_GROUP(vin4_data, 12, _a), 4077 VIN_DATA_PIN_GROUP(vin4_data, 16, _a), 4078 SH_PFC_PIN_GROUP(vin4_data18_a), 4079 VIN_DATA_PIN_GROUP(vin4_data, 20, _a), 4080 VIN_DATA_PIN_GROUP(vin4_data, 24, _a), 4081 VIN_DATA_PIN_GROUP(vin4_data, 8, _b), 4082 VIN_DATA_PIN_GROUP(vin4_data, 10, _b), 4083 VIN_DATA_PIN_GROUP(vin4_data, 12, _b), 4084 VIN_DATA_PIN_GROUP(vin4_data, 16, _b), 4085 SH_PFC_PIN_GROUP(vin4_data18_b), 4086 VIN_DATA_PIN_GROUP(vin4_data, 20, _b), 4087 VIN_DATA_PIN_GROUP(vin4_data, 24, _b), 4088 SH_PFC_PIN_GROUP(vin4_g8), 4089 SH_PFC_PIN_GROUP(vin4_sync), 4090 SH_PFC_PIN_GROUP(vin4_field), 4091 SH_PFC_PIN_GROUP(vin4_clkenb), 4092 SH_PFC_PIN_GROUP(vin4_clk), 4093 VIN_DATA_PIN_GROUP(vin5_data, 8, _a), 4094 VIN_DATA_PIN_GROUP(vin5_data, 10, _a), 4095 VIN_DATA_PIN_GROUP(vin5_data, 12, _a), 4096 VIN_DATA_PIN_GROUP(vin5_data, 16, _a), 4097 SH_PFC_PIN_GROUP(vin5_data8_b), 4098 SH_PFC_PIN_GROUP(vin5_high8), 4099 SH_PFC_PIN_GROUP(vin5_sync_a), 4100 SH_PFC_PIN_GROUP(vin5_field_a), 4101 SH_PFC_PIN_GROUP(vin5_clkenb_a), 4102 SH_PFC_PIN_GROUP(vin5_clk_a), 4103 SH_PFC_PIN_GROUP(vin5_clk_b), 4104 }, 4105 #ifdef CONFIG_PINCTRL_PFC_R8A77990 4106 .automotive = { 4107 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4108 SH_PFC_PIN_GROUP(drif0_data0_a), 4109 SH_PFC_PIN_GROUP(drif0_data1_a), 4110 SH_PFC_PIN_GROUP(drif0_ctrl_b), 4111 SH_PFC_PIN_GROUP(drif0_data0_b), 4112 SH_PFC_PIN_GROUP(drif0_data1_b), 4113 SH_PFC_PIN_GROUP(drif1_ctrl), 4114 SH_PFC_PIN_GROUP(drif1_data0), 4115 SH_PFC_PIN_GROUP(drif1_data1), 4116 SH_PFC_PIN_GROUP(drif2_ctrl_a), 4117 SH_PFC_PIN_GROUP(drif2_data0_a), 4118 SH_PFC_PIN_GROUP(drif2_data1_a), 4119 SH_PFC_PIN_GROUP(drif2_ctrl_b), 4120 SH_PFC_PIN_GROUP(drif2_data0_b), 4121 SH_PFC_PIN_GROUP(drif2_data1_b), 4122 SH_PFC_PIN_GROUP(drif3_ctrl_a), 4123 SH_PFC_PIN_GROUP(drif3_data0_a), 4124 SH_PFC_PIN_GROUP(drif3_data1_a), 4125 SH_PFC_PIN_GROUP(drif3_ctrl_b), 4126 SH_PFC_PIN_GROUP(drif3_data0_b), 4127 SH_PFC_PIN_GROUP(drif3_data1_b), 4128 } 4129 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ 4130 }; 4131 4132 static const char * const audio_clk_groups[] = { 4133 "audio_clk_a", 4134 "audio_clk_b_a", 4135 "audio_clk_b_b", 4136 "audio_clk_b_c", 4137 "audio_clk_c_a", 4138 "audio_clk_c_b", 4139 "audio_clk_c_c", 4140 "audio_clkout_a", 4141 "audio_clkout_b", 4142 "audio_clkout1_a", 4143 "audio_clkout1_b", 4144 "audio_clkout1_c", 4145 "audio_clkout2_a", 4146 "audio_clkout2_b", 4147 "audio_clkout2_c", 4148 "audio_clkout3_a", 4149 "audio_clkout3_b", 4150 "audio_clkout3_c", 4151 }; 4152 4153 static const char * const avb_groups[] = { 4154 "avb_link", 4155 "avb_magic", 4156 "avb_phy_int", 4157 "avb_mii", 4158 "avb_avtp_pps", 4159 "avb_avtp_match", 4160 "avb_avtp_capture", 4161 }; 4162 4163 static const char * const can0_groups[] = { 4164 "can0_data", 4165 }; 4166 4167 static const char * const can1_groups[] = { 4168 "can1_data", 4169 }; 4170 4171 static const char * const can_clk_groups[] = { 4172 "can_clk", 4173 }; 4174 4175 static const char * const canfd0_groups[] = { 4176 "canfd0_data", 4177 }; 4178 4179 static const char * const canfd1_groups[] = { 4180 "canfd1_data", 4181 }; 4182 4183 #ifdef CONFIG_PINCTRL_PFC_R8A77990 4184 static const char * const drif0_groups[] = { 4185 "drif0_ctrl_a", 4186 "drif0_data0_a", 4187 "drif0_data1_a", 4188 "drif0_ctrl_b", 4189 "drif0_data0_b", 4190 "drif0_data1_b", 4191 }; 4192 4193 static const char * const drif1_groups[] = { 4194 "drif1_ctrl", 4195 "drif1_data0", 4196 "drif1_data1", 4197 }; 4198 4199 static const char * const drif2_groups[] = { 4200 "drif2_ctrl_a", 4201 "drif2_data0_a", 4202 "drif2_data1_a", 4203 "drif2_ctrl_b", 4204 "drif2_data0_b", 4205 "drif2_data1_b", 4206 }; 4207 4208 static const char * const drif3_groups[] = { 4209 "drif3_ctrl_a", 4210 "drif3_data0_a", 4211 "drif3_data1_a", 4212 "drif3_ctrl_b", 4213 "drif3_data0_b", 4214 "drif3_data1_b", 4215 }; 4216 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ 4217 4218 static const char * const du_groups[] = { 4219 "du_rgb666", 4220 "du_rgb888", 4221 "du_clk_in_0", 4222 "du_clk_in_1", 4223 "du_clk_out_0", 4224 "du_sync", 4225 "du_disp_cde", 4226 "du_cde", 4227 "du_disp", 4228 }; 4229 4230 static const char * const hscif0_groups[] = { 4231 "hscif0_data_a", 4232 "hscif0_clk_a", 4233 "hscif0_ctrl_a", 4234 "hscif0_data_b", 4235 "hscif0_clk_b", 4236 }; 4237 4238 static const char * const hscif1_groups[] = { 4239 "hscif1_data_a", 4240 "hscif1_clk_a", 4241 "hscif1_data_b", 4242 "hscif1_clk_b", 4243 "hscif1_ctrl_b", 4244 }; 4245 4246 static const char * const hscif2_groups[] = { 4247 "hscif2_data_a", 4248 "hscif2_clk_a", 4249 "hscif2_ctrl_a", 4250 "hscif2_data_b", 4251 }; 4252 4253 static const char * const hscif3_groups[] = { 4254 "hscif3_data_a", 4255 "hscif3_data_b", 4256 "hscif3_clk_b", 4257 "hscif3_data_c", 4258 "hscif3_clk_c", 4259 "hscif3_ctrl_c", 4260 "hscif3_data_d", 4261 "hscif3_data_e", 4262 "hscif3_ctrl_e", 4263 }; 4264 4265 static const char * const hscif4_groups[] = { 4266 "hscif4_data_a", 4267 "hscif4_clk_a", 4268 "hscif4_ctrl_a", 4269 "hscif4_data_b", 4270 "hscif4_clk_b", 4271 "hscif4_data_c", 4272 "hscif4_data_d", 4273 "hscif4_data_e", 4274 }; 4275 4276 static const char * const i2c1_groups[] = { 4277 "i2c1_a", 4278 "i2c1_b", 4279 "i2c1_c", 4280 "i2c1_d", 4281 }; 4282 4283 static const char * const i2c2_groups[] = { 4284 "i2c2_a", 4285 "i2c2_b", 4286 "i2c2_c", 4287 "i2c2_d", 4288 "i2c2_e", 4289 }; 4290 4291 static const char * const i2c4_groups[] = { 4292 "i2c4", 4293 }; 4294 4295 static const char * const i2c5_groups[] = { 4296 "i2c5", 4297 }; 4298 4299 static const char * const i2c6_groups[] = { 4300 "i2c6_a", 4301 "i2c6_b", 4302 }; 4303 4304 static const char * const i2c7_groups[] = { 4305 "i2c7_a", 4306 "i2c7_b", 4307 }; 4308 4309 static const char * const intc_ex_groups[] = { 4310 "intc_ex_irq0", 4311 "intc_ex_irq1", 4312 "intc_ex_irq2", 4313 "intc_ex_irq3", 4314 "intc_ex_irq4", 4315 "intc_ex_irq5", 4316 }; 4317 4318 static const char * const msiof0_groups[] = { 4319 "msiof0_clk", 4320 "msiof0_sync", 4321 "msiof0_ss1", 4322 "msiof0_ss2", 4323 "msiof0_txd", 4324 "msiof0_rxd", 4325 }; 4326 4327 static const char * const msiof1_groups[] = { 4328 "msiof1_clk", 4329 "msiof1_sync", 4330 "msiof1_ss1", 4331 "msiof1_ss2", 4332 "msiof1_txd", 4333 "msiof1_rxd", 4334 }; 4335 4336 static const char * const msiof2_groups[] = { 4337 "msiof2_clk_a", 4338 "msiof2_sync_a", 4339 "msiof2_ss1_a", 4340 "msiof2_ss2_a", 4341 "msiof2_txd_a", 4342 "msiof2_rxd_a", 4343 "msiof2_clk_b", 4344 "msiof2_sync_b", 4345 "msiof2_ss1_b", 4346 "msiof2_ss2_b", 4347 "msiof2_txd_b", 4348 "msiof2_rxd_b", 4349 }; 4350 4351 static const char * const msiof3_groups[] = { 4352 "msiof3_clk_a", 4353 "msiof3_sync_a", 4354 "msiof3_ss1_a", 4355 "msiof3_ss2_a", 4356 "msiof3_txd_a", 4357 "msiof3_rxd_a", 4358 "msiof3_clk_b", 4359 "msiof3_sync_b", 4360 "msiof3_ss1_b", 4361 "msiof3_txd_b", 4362 "msiof3_rxd_b", 4363 }; 4364 4365 static const char * const pwm0_groups[] = { 4366 "pwm0_a", 4367 "pwm0_b", 4368 }; 4369 4370 static const char * const pwm1_groups[] = { 4371 "pwm1_a", 4372 "pwm1_b", 4373 }; 4374 4375 static const char * const pwm2_groups[] = { 4376 "pwm2_a", 4377 "pwm2_b", 4378 "pwm2_c", 4379 }; 4380 4381 static const char * const pwm3_groups[] = { 4382 "pwm3_a", 4383 "pwm3_b", 4384 "pwm3_c", 4385 }; 4386 4387 static const char * const pwm4_groups[] = { 4388 "pwm4_a", 4389 "pwm4_b", 4390 }; 4391 4392 static const char * const pwm5_groups[] = { 4393 "pwm5_a", 4394 "pwm5_b", 4395 }; 4396 4397 static const char * const pwm6_groups[] = { 4398 "pwm6_a", 4399 "pwm6_b", 4400 }; 4401 4402 static const char * const qspi0_groups[] = { 4403 "qspi0_ctrl", 4404 "qspi0_data2", 4405 "qspi0_data4", 4406 }; 4407 4408 static const char * const qspi1_groups[] = { 4409 "qspi1_ctrl", 4410 "qspi1_data2", 4411 "qspi1_data4", 4412 }; 4413 4414 static const char * const scif0_groups[] = { 4415 "scif0_data_a", 4416 "scif0_clk_a", 4417 "scif0_ctrl_a", 4418 "scif0_data_b", 4419 "scif0_clk_b", 4420 }; 4421 4422 static const char * const scif1_groups[] = { 4423 "scif1_data", 4424 "scif1_clk", 4425 "scif1_ctrl", 4426 }; 4427 4428 static const char * const scif2_groups[] = { 4429 "scif2_data_a", 4430 "scif2_clk_a", 4431 "scif2_data_b", 4432 }; 4433 4434 static const char * const scif3_groups[] = { 4435 "scif3_data_a", 4436 "scif3_clk_a", 4437 "scif3_ctrl_a", 4438 "scif3_data_b", 4439 "scif3_data_c", 4440 "scif3_clk_c", 4441 }; 4442 4443 static const char * const scif4_groups[] = { 4444 "scif4_data_a", 4445 "scif4_clk_a", 4446 "scif4_ctrl_a", 4447 "scif4_data_b", 4448 "scif4_clk_b", 4449 "scif4_data_c", 4450 "scif4_ctrl_c", 4451 }; 4452 4453 static const char * const scif5_groups[] = { 4454 "scif5_data_a", 4455 "scif5_clk_a", 4456 "scif5_data_b", 4457 "scif5_data_c", 4458 }; 4459 4460 static const char * const scif_clk_groups[] = { 4461 "scif_clk_a", 4462 "scif_clk_b", 4463 }; 4464 4465 static const char * const sdhi0_groups[] = { 4466 "sdhi0_data1", 4467 "sdhi0_data4", 4468 "sdhi0_ctrl", 4469 "sdhi0_cd", 4470 "sdhi0_wp", 4471 }; 4472 4473 static const char * const sdhi1_groups[] = { 4474 "sdhi1_data1", 4475 "sdhi1_data4", 4476 "sdhi1_ctrl", 4477 "sdhi1_cd", 4478 "sdhi1_wp", 4479 }; 4480 4481 static const char * const sdhi3_groups[] = { 4482 "sdhi3_data1", 4483 "sdhi3_data4", 4484 "sdhi3_data8", 4485 "sdhi3_ctrl", 4486 "sdhi3_cd", 4487 "sdhi3_wp", 4488 "sdhi3_ds", 4489 }; 4490 4491 static const char * const ssi_groups[] = { 4492 "ssi0_data", 4493 "ssi01239_ctrl", 4494 "ssi1_data", 4495 "ssi1_ctrl", 4496 "ssi2_data", 4497 "ssi2_ctrl_a", 4498 "ssi2_ctrl_b", 4499 "ssi3_data", 4500 "ssi349_ctrl", 4501 "ssi4_data", 4502 "ssi4_ctrl", 4503 "ssi5_data", 4504 "ssi5_ctrl", 4505 "ssi6_data", 4506 "ssi6_ctrl", 4507 "ssi7_data", 4508 "ssi78_ctrl", 4509 "ssi8_data", 4510 "ssi9_data", 4511 "ssi9_ctrl_a", 4512 "ssi9_ctrl_b", 4513 }; 4514 4515 static const char * const tmu_groups[] = { 4516 "tmu_tclk1_a", 4517 "tmu_tclk1_b", 4518 "tmu_tclk2_a", 4519 "tmu_tclk2_b", 4520 }; 4521 4522 static const char * const usb0_groups[] = { 4523 "usb0_a", 4524 "usb0_b", 4525 "usb0_id", 4526 }; 4527 4528 static const char * const usb30_groups[] = { 4529 "usb30", 4530 "usb30_id", 4531 }; 4532 4533 static const char * const vin4_groups[] = { 4534 "vin4_data8_a", 4535 "vin4_data10_a", 4536 "vin4_data12_a", 4537 "vin4_data16_a", 4538 "vin4_data18_a", 4539 "vin4_data20_a", 4540 "vin4_data24_a", 4541 "vin4_data8_b", 4542 "vin4_data10_b", 4543 "vin4_data12_b", 4544 "vin4_data16_b", 4545 "vin4_data18_b", 4546 "vin4_data20_b", 4547 "vin4_data24_b", 4548 "vin4_g8", 4549 "vin4_sync", 4550 "vin4_field", 4551 "vin4_clkenb", 4552 "vin4_clk", 4553 }; 4554 4555 static const char * const vin5_groups[] = { 4556 "vin5_data8_a", 4557 "vin5_data10_a", 4558 "vin5_data12_a", 4559 "vin5_data16_a", 4560 "vin5_data8_b", 4561 "vin5_high8", 4562 "vin5_sync_a", 4563 "vin5_field_a", 4564 "vin5_clkenb_a", 4565 "vin5_clk_a", 4566 "vin5_clk_b", 4567 }; 4568 4569 static const struct { 4570 struct sh_pfc_function common[49]; 4571 #ifdef CONFIG_PINCTRL_PFC_R8A77990 4572 struct sh_pfc_function automotive[4]; 4573 #endif 4574 } pinmux_functions = { 4575 .common = { 4576 SH_PFC_FUNCTION(audio_clk), 4577 SH_PFC_FUNCTION(avb), 4578 SH_PFC_FUNCTION(can0), 4579 SH_PFC_FUNCTION(can1), 4580 SH_PFC_FUNCTION(can_clk), 4581 SH_PFC_FUNCTION(canfd0), 4582 SH_PFC_FUNCTION(canfd1), 4583 SH_PFC_FUNCTION(du), 4584 SH_PFC_FUNCTION(hscif0), 4585 SH_PFC_FUNCTION(hscif1), 4586 SH_PFC_FUNCTION(hscif2), 4587 SH_PFC_FUNCTION(hscif3), 4588 SH_PFC_FUNCTION(hscif4), 4589 SH_PFC_FUNCTION(i2c1), 4590 SH_PFC_FUNCTION(i2c2), 4591 SH_PFC_FUNCTION(i2c4), 4592 SH_PFC_FUNCTION(i2c5), 4593 SH_PFC_FUNCTION(i2c6), 4594 SH_PFC_FUNCTION(i2c7), 4595 SH_PFC_FUNCTION(intc_ex), 4596 SH_PFC_FUNCTION(msiof0), 4597 SH_PFC_FUNCTION(msiof1), 4598 SH_PFC_FUNCTION(msiof2), 4599 SH_PFC_FUNCTION(msiof3), 4600 SH_PFC_FUNCTION(pwm0), 4601 SH_PFC_FUNCTION(pwm1), 4602 SH_PFC_FUNCTION(pwm2), 4603 SH_PFC_FUNCTION(pwm3), 4604 SH_PFC_FUNCTION(pwm4), 4605 SH_PFC_FUNCTION(pwm5), 4606 SH_PFC_FUNCTION(pwm6), 4607 SH_PFC_FUNCTION(qspi0), 4608 SH_PFC_FUNCTION(qspi1), 4609 SH_PFC_FUNCTION(scif0), 4610 SH_PFC_FUNCTION(scif1), 4611 SH_PFC_FUNCTION(scif2), 4612 SH_PFC_FUNCTION(scif3), 4613 SH_PFC_FUNCTION(scif4), 4614 SH_PFC_FUNCTION(scif5), 4615 SH_PFC_FUNCTION(scif_clk), 4616 SH_PFC_FUNCTION(sdhi0), 4617 SH_PFC_FUNCTION(sdhi1), 4618 SH_PFC_FUNCTION(sdhi3), 4619 SH_PFC_FUNCTION(ssi), 4620 SH_PFC_FUNCTION(tmu), 4621 SH_PFC_FUNCTION(usb0), 4622 SH_PFC_FUNCTION(usb30), 4623 SH_PFC_FUNCTION(vin4), 4624 SH_PFC_FUNCTION(vin5), 4625 }, 4626 #ifdef CONFIG_PINCTRL_PFC_R8A77990 4627 .automotive = { 4628 SH_PFC_FUNCTION(drif0), 4629 SH_PFC_FUNCTION(drif1), 4630 SH_PFC_FUNCTION(drif2), 4631 SH_PFC_FUNCTION(drif3), 4632 } 4633 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ 4634 }; 4635 4636 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4637 #define F_(x, y) FN_##y 4638 #define FM(x) FN_##x 4639 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 4640 0, 0, 4641 0, 0, 4642 0, 0, 4643 0, 0, 4644 0, 0, 4645 0, 0, 4646 0, 0, 4647 0, 0, 4648 0, 0, 4649 0, 0, 4650 0, 0, 4651 0, 0, 4652 0, 0, 4653 0, 0, 4654 GP_0_17_FN, GPSR0_17, 4655 GP_0_16_FN, GPSR0_16, 4656 GP_0_15_FN, GPSR0_15, 4657 GP_0_14_FN, GPSR0_14, 4658 GP_0_13_FN, GPSR0_13, 4659 GP_0_12_FN, GPSR0_12, 4660 GP_0_11_FN, GPSR0_11, 4661 GP_0_10_FN, GPSR0_10, 4662 GP_0_9_FN, GPSR0_9, 4663 GP_0_8_FN, GPSR0_8, 4664 GP_0_7_FN, GPSR0_7, 4665 GP_0_6_FN, GPSR0_6, 4666 GP_0_5_FN, GPSR0_5, 4667 GP_0_4_FN, GPSR0_4, 4668 GP_0_3_FN, GPSR0_3, 4669 GP_0_2_FN, GPSR0_2, 4670 GP_0_1_FN, GPSR0_1, 4671 GP_0_0_FN, GPSR0_0, )) 4672 }, 4673 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 4674 0, 0, 4675 0, 0, 4676 0, 0, 4677 0, 0, 4678 0, 0, 4679 0, 0, 4680 0, 0, 4681 0, 0, 4682 0, 0, 4683 GP_1_22_FN, GPSR1_22, 4684 GP_1_21_FN, GPSR1_21, 4685 GP_1_20_FN, GPSR1_20, 4686 GP_1_19_FN, GPSR1_19, 4687 GP_1_18_FN, GPSR1_18, 4688 GP_1_17_FN, GPSR1_17, 4689 GP_1_16_FN, GPSR1_16, 4690 GP_1_15_FN, GPSR1_15, 4691 GP_1_14_FN, GPSR1_14, 4692 GP_1_13_FN, GPSR1_13, 4693 GP_1_12_FN, GPSR1_12, 4694 GP_1_11_FN, GPSR1_11, 4695 GP_1_10_FN, GPSR1_10, 4696 GP_1_9_FN, GPSR1_9, 4697 GP_1_8_FN, GPSR1_8, 4698 GP_1_7_FN, GPSR1_7, 4699 GP_1_6_FN, GPSR1_6, 4700 GP_1_5_FN, GPSR1_5, 4701 GP_1_4_FN, GPSR1_4, 4702 GP_1_3_FN, GPSR1_3, 4703 GP_1_2_FN, GPSR1_2, 4704 GP_1_1_FN, GPSR1_1, 4705 GP_1_0_FN, GPSR1_0, )) 4706 }, 4707 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 4708 0, 0, 4709 0, 0, 4710 0, 0, 4711 0, 0, 4712 0, 0, 4713 0, 0, 4714 GP_2_25_FN, GPSR2_25, 4715 GP_2_24_FN, GPSR2_24, 4716 GP_2_23_FN, GPSR2_23, 4717 GP_2_22_FN, GPSR2_22, 4718 GP_2_21_FN, GPSR2_21, 4719 GP_2_20_FN, GPSR2_20, 4720 GP_2_19_FN, GPSR2_19, 4721 GP_2_18_FN, GPSR2_18, 4722 GP_2_17_FN, GPSR2_17, 4723 GP_2_16_FN, GPSR2_16, 4724 GP_2_15_FN, GPSR2_15, 4725 GP_2_14_FN, GPSR2_14, 4726 GP_2_13_FN, GPSR2_13, 4727 GP_2_12_FN, GPSR2_12, 4728 GP_2_11_FN, GPSR2_11, 4729 GP_2_10_FN, GPSR2_10, 4730 GP_2_9_FN, GPSR2_9, 4731 GP_2_8_FN, GPSR2_8, 4732 GP_2_7_FN, GPSR2_7, 4733 GP_2_6_FN, GPSR2_6, 4734 GP_2_5_FN, GPSR2_5, 4735 GP_2_4_FN, GPSR2_4, 4736 GP_2_3_FN, GPSR2_3, 4737 GP_2_2_FN, GPSR2_2, 4738 GP_2_1_FN, GPSR2_1, 4739 GP_2_0_FN, GPSR2_0, )) 4740 }, 4741 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 4742 0, 0, 4743 0, 0, 4744 0, 0, 4745 0, 0, 4746 0, 0, 4747 0, 0, 4748 0, 0, 4749 0, 0, 4750 0, 0, 4751 0, 0, 4752 0, 0, 4753 0, 0, 4754 0, 0, 4755 0, 0, 4756 0, 0, 4757 0, 0, 4758 GP_3_15_FN, GPSR3_15, 4759 GP_3_14_FN, GPSR3_14, 4760 GP_3_13_FN, GPSR3_13, 4761 GP_3_12_FN, GPSR3_12, 4762 GP_3_11_FN, GPSR3_11, 4763 GP_3_10_FN, GPSR3_10, 4764 GP_3_9_FN, GPSR3_9, 4765 GP_3_8_FN, GPSR3_8, 4766 GP_3_7_FN, GPSR3_7, 4767 GP_3_6_FN, GPSR3_6, 4768 GP_3_5_FN, GPSR3_5, 4769 GP_3_4_FN, GPSR3_4, 4770 GP_3_3_FN, GPSR3_3, 4771 GP_3_2_FN, GPSR3_2, 4772 GP_3_1_FN, GPSR3_1, 4773 GP_3_0_FN, GPSR3_0, )) 4774 }, 4775 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 4776 0, 0, 4777 0, 0, 4778 0, 0, 4779 0, 0, 4780 0, 0, 4781 0, 0, 4782 0, 0, 4783 0, 0, 4784 0, 0, 4785 0, 0, 4786 0, 0, 4787 0, 0, 4788 0, 0, 4789 0, 0, 4790 0, 0, 4791 0, 0, 4792 0, 0, 4793 0, 0, 4794 0, 0, 4795 0, 0, 4796 0, 0, 4797 GP_4_10_FN, GPSR4_10, 4798 GP_4_9_FN, GPSR4_9, 4799 GP_4_8_FN, GPSR4_8, 4800 GP_4_7_FN, GPSR4_7, 4801 GP_4_6_FN, GPSR4_6, 4802 GP_4_5_FN, GPSR4_5, 4803 GP_4_4_FN, GPSR4_4, 4804 GP_4_3_FN, GPSR4_3, 4805 GP_4_2_FN, GPSR4_2, 4806 GP_4_1_FN, GPSR4_1, 4807 GP_4_0_FN, GPSR4_0, )) 4808 }, 4809 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 4810 0, 0, 4811 0, 0, 4812 0, 0, 4813 0, 0, 4814 0, 0, 4815 0, 0, 4816 0, 0, 4817 0, 0, 4818 0, 0, 4819 0, 0, 4820 0, 0, 4821 0, 0, 4822 GP_5_19_FN, GPSR5_19, 4823 GP_5_18_FN, GPSR5_18, 4824 GP_5_17_FN, GPSR5_17, 4825 GP_5_16_FN, GPSR5_16, 4826 GP_5_15_FN, GPSR5_15, 4827 GP_5_14_FN, GPSR5_14, 4828 GP_5_13_FN, GPSR5_13, 4829 GP_5_12_FN, GPSR5_12, 4830 GP_5_11_FN, GPSR5_11, 4831 GP_5_10_FN, GPSR5_10, 4832 GP_5_9_FN, GPSR5_9, 4833 GP_5_8_FN, GPSR5_8, 4834 GP_5_7_FN, GPSR5_7, 4835 GP_5_6_FN, GPSR5_6, 4836 GP_5_5_FN, GPSR5_5, 4837 GP_5_4_FN, GPSR5_4, 4838 GP_5_3_FN, GPSR5_3, 4839 GP_5_2_FN, GPSR5_2, 4840 GP_5_1_FN, GPSR5_1, 4841 GP_5_0_FN, GPSR5_0, )) 4842 }, 4843 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 4844 0, 0, 4845 0, 0, 4846 0, 0, 4847 0, 0, 4848 0, 0, 4849 0, 0, 4850 0, 0, 4851 0, 0, 4852 0, 0, 4853 0, 0, 4854 0, 0, 4855 0, 0, 4856 0, 0, 4857 0, 0, 4858 GP_6_17_FN, GPSR6_17, 4859 GP_6_16_FN, GPSR6_16, 4860 GP_6_15_FN, GPSR6_15, 4861 GP_6_14_FN, GPSR6_14, 4862 GP_6_13_FN, GPSR6_13, 4863 GP_6_12_FN, GPSR6_12, 4864 GP_6_11_FN, GPSR6_11, 4865 GP_6_10_FN, GPSR6_10, 4866 GP_6_9_FN, GPSR6_9, 4867 GP_6_8_FN, GPSR6_8, 4868 GP_6_7_FN, GPSR6_7, 4869 GP_6_6_FN, GPSR6_6, 4870 GP_6_5_FN, GPSR6_5, 4871 GP_6_4_FN, GPSR6_4, 4872 GP_6_3_FN, GPSR6_3, 4873 GP_6_2_FN, GPSR6_2, 4874 GP_6_1_FN, GPSR6_1, 4875 GP_6_0_FN, GPSR6_0, )) 4876 }, 4877 #undef F_ 4878 #undef FM 4879 4880 #define F_(x, y) x, 4881 #define FM(x) FN_##x, 4882 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 4883 IP0_31_28 4884 IP0_27_24 4885 IP0_23_20 4886 IP0_19_16 4887 IP0_15_12 4888 IP0_11_8 4889 IP0_7_4 4890 IP0_3_0 )) 4891 }, 4892 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 4893 IP1_31_28 4894 IP1_27_24 4895 IP1_23_20 4896 IP1_19_16 4897 IP1_15_12 4898 IP1_11_8 4899 IP1_7_4 4900 IP1_3_0 )) 4901 }, 4902 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 4903 IP2_31_28 4904 IP2_27_24 4905 IP2_23_20 4906 IP2_19_16 4907 IP2_15_12 4908 IP2_11_8 4909 IP2_7_4 4910 IP2_3_0 )) 4911 }, 4912 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 4913 IP3_31_28 4914 IP3_27_24 4915 IP3_23_20 4916 IP3_19_16 4917 IP3_15_12 4918 IP3_11_8 4919 IP3_7_4 4920 IP3_3_0 )) 4921 }, 4922 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 4923 IP4_31_28 4924 IP4_27_24 4925 IP4_23_20 4926 IP4_19_16 4927 IP4_15_12 4928 IP4_11_8 4929 IP4_7_4 4930 IP4_3_0 )) 4931 }, 4932 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 4933 IP5_31_28 4934 IP5_27_24 4935 IP5_23_20 4936 IP5_19_16 4937 IP5_15_12 4938 IP5_11_8 4939 IP5_7_4 4940 IP5_3_0 )) 4941 }, 4942 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 4943 IP6_31_28 4944 IP6_27_24 4945 IP6_23_20 4946 IP6_19_16 4947 IP6_15_12 4948 IP6_11_8 4949 IP6_7_4 4950 IP6_3_0 )) 4951 }, 4952 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 4953 IP7_31_28 4954 IP7_27_24 4955 IP7_23_20 4956 IP7_19_16 4957 IP7_15_12 4958 IP7_11_8 4959 IP7_7_4 4960 IP7_3_0 )) 4961 }, 4962 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 4963 IP8_31_28 4964 IP8_27_24 4965 IP8_23_20 4966 IP8_19_16 4967 IP8_15_12 4968 IP8_11_8 4969 IP8_7_4 4970 IP8_3_0 )) 4971 }, 4972 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 4973 IP9_31_28 4974 IP9_27_24 4975 IP9_23_20 4976 IP9_19_16 4977 IP9_15_12 4978 IP9_11_8 4979 IP9_7_4 4980 IP9_3_0 )) 4981 }, 4982 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 4983 IP10_31_28 4984 IP10_27_24 4985 IP10_23_20 4986 IP10_19_16 4987 IP10_15_12 4988 IP10_11_8 4989 IP10_7_4 4990 IP10_3_0 )) 4991 }, 4992 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 4993 IP11_31_28 4994 IP11_27_24 4995 IP11_23_20 4996 IP11_19_16 4997 IP11_15_12 4998 IP11_11_8 4999 IP11_7_4 5000 IP11_3_0 )) 5001 }, 5002 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 5003 IP12_31_28 5004 IP12_27_24 5005 IP12_23_20 5006 IP12_19_16 5007 IP12_15_12 5008 IP12_11_8 5009 IP12_7_4 5010 IP12_3_0 )) 5011 }, 5012 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 5013 IP13_31_28 5014 IP13_27_24 5015 IP13_23_20 5016 IP13_19_16 5017 IP13_15_12 5018 IP13_11_8 5019 IP13_7_4 5020 IP13_3_0 )) 5021 }, 5022 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( 5023 IP14_31_28 5024 IP14_27_24 5025 IP14_23_20 5026 IP14_19_16 5027 IP14_15_12 5028 IP14_11_8 5029 IP14_7_4 5030 IP14_3_0 )) 5031 }, 5032 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( 5033 IP15_31_28 5034 IP15_27_24 5035 IP15_23_20 5036 IP15_19_16 5037 IP15_15_12 5038 IP15_11_8 5039 IP15_7_4 5040 IP15_3_0 )) 5041 }, 5042 #undef F_ 5043 #undef FM 5044 5045 #define F_(x, y) x, 5046 #define FM(x) FN_##x, 5047 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5048 GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1, 5049 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2), 5050 GROUP( 5051 /* RESERVED 31 */ 5052 0, 0, 5053 MOD_SEL0_30_29 5054 MOD_SEL0_28 5055 MOD_SEL0_27_26 5056 MOD_SEL0_25 5057 MOD_SEL0_24 5058 MOD_SEL0_23 5059 MOD_SEL0_22 5060 MOD_SEL0_21_20 5061 MOD_SEL0_19_18_17 5062 MOD_SEL0_16 5063 MOD_SEL0_15 5064 MOD_SEL0_14 5065 MOD_SEL0_13_12 5066 MOD_SEL0_11_10 5067 MOD_SEL0_9 5068 MOD_SEL0_8 5069 MOD_SEL0_7 5070 MOD_SEL0_6_5 5071 MOD_SEL0_4 5072 MOD_SEL0_3 5073 MOD_SEL0_2 5074 MOD_SEL0_1_0 )) 5075 }, 5076 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5077 GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 5078 1, 2, 2, 2, 1, 1, 2, 1, 4), 5079 GROUP( 5080 MOD_SEL1_31 5081 MOD_SEL1_30 5082 MOD_SEL1_29 5083 MOD_SEL1_28 5084 /* RESERVED 27 */ 5085 0, 0, 5086 MOD_SEL1_26 5087 MOD_SEL1_25 5088 MOD_SEL1_24_23_22 5089 MOD_SEL1_21_20_19 5090 MOD_SEL1_18 5091 MOD_SEL1_17 5092 MOD_SEL1_16 5093 MOD_SEL1_15 5094 MOD_SEL1_14_13 5095 MOD_SEL1_12_11 5096 MOD_SEL1_10_9 5097 MOD_SEL1_8 5098 MOD_SEL1_7 5099 MOD_SEL1_6_5 5100 MOD_SEL1_4 5101 /* RESERVED 3, 2, 1, 0 */ 5102 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 )) 5103 }, 5104 { }, 5105 }; 5106 5107 enum ioctrl_regs { 5108 POCCTRL0, 5109 TDSELCTRL, 5110 }; 5111 5112 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 5113 [POCCTRL0] = { 0xe6060380, }, 5114 [TDSELCTRL] = { 0xe60603c0, }, 5115 { /* sentinel */ }, 5116 }; 5117 5118 static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, 5119 u32 *pocctrl) 5120 { 5121 int bit = -EINVAL; 5122 5123 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; 5124 5125 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 5126 bit = pin & 0x1f; 5127 5128 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10)) 5129 bit = (pin & 0x1f) + 19; 5130 5131 return bit; 5132 } 5133 5134 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 5135 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 5136 [0] = RCAR_GP_PIN(2, 23), /* RD# */ 5137 [1] = RCAR_GP_PIN(2, 22), /* BS# */ 5138 [2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */ 5139 [3] = PIN_AVB_MDC, /* AVB_MDC */ 5140 [4] = PIN_AVB_MDIO, /* AVB_MDIO */ 5141 [5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */ 5142 [6] = PIN_AVB_TD3, /* AVB_TD3 */ 5143 [7] = PIN_AVB_TD2, /* AVB_TD2 */ 5144 [8] = PIN_AVB_TD1, /* AVB_TD1 */ 5145 [9] = PIN_AVB_TD0, /* AVB_TD0 */ 5146 [10] = PIN_AVB_TXC, /* AVB_TXC */ 5147 [11] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ 5148 [12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */ 5149 [13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */ 5150 [14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */ 5151 [15] = RCAR_GP_PIN(2, 16), /* AVB_RD0 */ 5152 [16] = RCAR_GP_PIN(2, 15), /* AVB_RXC */ 5153 [17] = RCAR_GP_PIN(2, 14), /* AVB_RX_CTL */ 5154 [18] = RCAR_GP_PIN(2, 13), /* RPC_RESET# */ 5155 [19] = RCAR_GP_PIN(2, 12), /* RPC_INT# */ 5156 [20] = RCAR_GP_PIN(2, 11), /* QSPI1_SSL */ 5157 [21] = RCAR_GP_PIN(2, 10), /* QSPI1_IO3 */ 5158 [22] = RCAR_GP_PIN(2, 9), /* QSPI1_IO2 */ 5159 [23] = RCAR_GP_PIN(2, 8), /* QSPI1_MISO/IO1 */ 5160 [24] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI/IO0 */ 5161 [25] = RCAR_GP_PIN(2, 6), /* QSPI1_SPCLK */ 5162 [26] = RCAR_GP_PIN(2, 5), /* QSPI0_SSL */ 5163 [27] = RCAR_GP_PIN(2, 4), /* QSPI0_IO3 */ 5164 [28] = RCAR_GP_PIN(2, 3), /* QSPI0_IO2 */ 5165 [29] = RCAR_GP_PIN(2, 2), /* QSPI0_MISO/IO1 */ 5166 [30] = RCAR_GP_PIN(2, 1), /* QSPI0_MOSI/IO0 */ 5167 [31] = RCAR_GP_PIN(2, 0), /* QSPI0_SPCLK */ 5168 } }, 5169 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 5170 [0] = RCAR_GP_PIN(0, 4), /* D4 */ 5171 [1] = RCAR_GP_PIN(0, 3), /* D3 */ 5172 [2] = RCAR_GP_PIN(0, 2), /* D2 */ 5173 [3] = RCAR_GP_PIN(0, 1), /* D1 */ 5174 [4] = RCAR_GP_PIN(0, 0), /* D0 */ 5175 [5] = RCAR_GP_PIN(1, 22), /* WE0# */ 5176 [6] = RCAR_GP_PIN(1, 21), /* CS0# */ 5177 [7] = RCAR_GP_PIN(1, 20), /* CLKOUT */ 5178 [8] = RCAR_GP_PIN(1, 19), /* A19 */ 5179 [9] = RCAR_GP_PIN(1, 18), /* A18 */ 5180 [10] = RCAR_GP_PIN(1, 17), /* A17 */ 5181 [11] = RCAR_GP_PIN(1, 16), /* A16 */ 5182 [12] = RCAR_GP_PIN(1, 15), /* A15 */ 5183 [13] = RCAR_GP_PIN(1, 14), /* A14 */ 5184 [14] = RCAR_GP_PIN(1, 13), /* A13 */ 5185 [15] = RCAR_GP_PIN(1, 12), /* A12 */ 5186 [16] = RCAR_GP_PIN(1, 11), /* A11 */ 5187 [17] = RCAR_GP_PIN(1, 10), /* A10 */ 5188 [18] = RCAR_GP_PIN(1, 9), /* A9 */ 5189 [19] = RCAR_GP_PIN(1, 8), /* A8 */ 5190 [20] = RCAR_GP_PIN(1, 7), /* A7 */ 5191 [21] = RCAR_GP_PIN(1, 6), /* A6 */ 5192 [22] = RCAR_GP_PIN(1, 5), /* A5 */ 5193 [23] = RCAR_GP_PIN(1, 4), /* A4 */ 5194 [24] = RCAR_GP_PIN(1, 3), /* A3 */ 5195 [25] = RCAR_GP_PIN(1, 2), /* A2 */ 5196 [26] = RCAR_GP_PIN(1, 1), /* A1 */ 5197 [27] = RCAR_GP_PIN(1, 0), /* A0 */ 5198 [28] = SH_PFC_PIN_NONE, 5199 [29] = SH_PFC_PIN_NONE, 5200 [30] = RCAR_GP_PIN(2, 25), /* EX_WAIT0 */ 5201 [31] = RCAR_GP_PIN(2, 24), /* RD/WR# */ 5202 } }, 5203 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 5204 [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 5205 [1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 5206 [2] = PIN_ASEBRK, /* ASEBRK */ 5207 [3] = SH_PFC_PIN_NONE, 5208 [4] = PIN_TDI, /* TDI */ 5209 [5] = PIN_TMS, /* TMS */ 5210 [6] = PIN_TCK, /* TCK */ 5211 [7] = PIN_TRST_N, /* TRST# */ 5212 [8] = SH_PFC_PIN_NONE, 5213 [9] = SH_PFC_PIN_NONE, 5214 [10] = SH_PFC_PIN_NONE, 5215 [11] = SH_PFC_PIN_NONE, 5216 [12] = SH_PFC_PIN_NONE, 5217 [13] = SH_PFC_PIN_NONE, 5218 [14] = SH_PFC_PIN_NONE, 5219 [15] = PIN_FSCLKST_N, /* FSCLKST# */ 5220 [16] = RCAR_GP_PIN(0, 17), /* SDA4 */ 5221 [17] = RCAR_GP_PIN(0, 16), /* SCL4 */ 5222 [18] = SH_PFC_PIN_NONE, 5223 [19] = SH_PFC_PIN_NONE, 5224 [20] = PIN_PRESETOUT_N, /* PRESETOUT# */ 5225 [21] = RCAR_GP_PIN(0, 15), /* D15 */ 5226 [22] = RCAR_GP_PIN(0, 14), /* D14 */ 5227 [23] = RCAR_GP_PIN(0, 13), /* D13 */ 5228 [24] = RCAR_GP_PIN(0, 12), /* D12 */ 5229 [25] = RCAR_GP_PIN(0, 11), /* D11 */ 5230 [26] = RCAR_GP_PIN(0, 10), /* D10 */ 5231 [27] = RCAR_GP_PIN(0, 9), /* D9 */ 5232 [28] = RCAR_GP_PIN(0, 8), /* D8 */ 5233 [29] = RCAR_GP_PIN(0, 7), /* D7 */ 5234 [30] = RCAR_GP_PIN(0, 6), /* D6 */ 5235 [31] = RCAR_GP_PIN(0, 5), /* D5 */ 5236 } }, 5237 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 5238 [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */ 5239 [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */ 5240 [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */ 5241 [3] = RCAR_GP_PIN(5, 2), /* TX0_A */ 5242 [4] = RCAR_GP_PIN(5, 1), /* RX0_A */ 5243 [5] = SH_PFC_PIN_NONE, 5244 [6] = SH_PFC_PIN_NONE, 5245 [7] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 5246 [8] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 5247 [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ 5248 [10] = RCAR_GP_PIN(3, 12), /* SD0_CD */ 5249 [11] = RCAR_GP_PIN(4, 10), /* SD3_DS */ 5250 [12] = RCAR_GP_PIN(4, 9), /* SD3_DAT7 */ 5251 [13] = RCAR_GP_PIN(4, 8), /* SD3_DAT6 */ 5252 [14] = RCAR_GP_PIN(4, 7), /* SD3_DAT5 */ 5253 [15] = RCAR_GP_PIN(4, 6), /* SD3_DAT4 */ 5254 [16] = RCAR_GP_PIN(4, 5), /* SD3_DAT3 */ 5255 [17] = RCAR_GP_PIN(4, 4), /* SD3_DAT2 */ 5256 [18] = RCAR_GP_PIN(4, 3), /* SD3_DAT1 */ 5257 [19] = RCAR_GP_PIN(4, 2), /* SD3_DAT0 */ 5258 [20] = RCAR_GP_PIN(4, 1), /* SD3_CMD */ 5259 [21] = RCAR_GP_PIN(4, 0), /* SD3_CLK */ 5260 [22] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ 5261 [23] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ 5262 [24] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ 5263 [25] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ 5264 [26] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ 5265 [27] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ 5266 [28] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 5267 [29] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 5268 [30] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 5269 [31] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 5270 } }, 5271 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 5272 [0] = RCAR_GP_PIN(6, 8), /* AUDIO_CLKA */ 5273 [1] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ 5274 [2] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ 5275 [3] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ 5276 [4] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ 5277 [5] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ 5278 [6] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ 5279 [7] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ 5280 [8] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ 5281 [9] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ 5282 [10] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ 5283 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2 */ 5284 [12] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1 */ 5285 [13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ 5286 [14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ 5287 [15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ 5288 [16] = PIN_MLB_REF, /* MLB_REF */ 5289 [17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */ 5290 [18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */ 5291 [19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */ 5292 [20] = RCAR_GP_PIN(5, 16), /* SSI_SDATA9 */ 5293 [21] = RCAR_GP_PIN(5, 15), /* MSIOF0_SS2 */ 5294 [22] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */ 5295 [23] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */ 5296 [24] = RCAR_GP_PIN(5, 12), /* MSIOF0_TXD */ 5297 [25] = RCAR_GP_PIN(5, 11), /* MSIOF0_RXD */ 5298 [26] = RCAR_GP_PIN(5, 10), /* MSIOF0_SCK */ 5299 [27] = RCAR_GP_PIN(5, 9), /* RX2_A */ 5300 [28] = RCAR_GP_PIN(5, 8), /* TX2_A */ 5301 [29] = RCAR_GP_PIN(5, 7), /* SCK2_A */ 5302 [30] = RCAR_GP_PIN(5, 6), /* TX1 */ 5303 [31] = RCAR_GP_PIN(5, 5), /* RX1 */ 5304 } }, 5305 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { 5306 [0] = SH_PFC_PIN_NONE, 5307 [1] = SH_PFC_PIN_NONE, 5308 [2] = SH_PFC_PIN_NONE, 5309 [3] = SH_PFC_PIN_NONE, 5310 [4] = SH_PFC_PIN_NONE, 5311 [5] = SH_PFC_PIN_NONE, 5312 [6] = SH_PFC_PIN_NONE, 5313 [7] = SH_PFC_PIN_NONE, 5314 [8] = SH_PFC_PIN_NONE, 5315 [9] = SH_PFC_PIN_NONE, 5316 [10] = SH_PFC_PIN_NONE, 5317 [11] = SH_PFC_PIN_NONE, 5318 [12] = SH_PFC_PIN_NONE, 5319 [13] = SH_PFC_PIN_NONE, 5320 [14] = SH_PFC_PIN_NONE, 5321 [15] = SH_PFC_PIN_NONE, 5322 [16] = SH_PFC_PIN_NONE, 5323 [17] = SH_PFC_PIN_NONE, 5324 [18] = SH_PFC_PIN_NONE, 5325 [19] = SH_PFC_PIN_NONE, 5326 [20] = SH_PFC_PIN_NONE, 5327 [21] = SH_PFC_PIN_NONE, 5328 [22] = SH_PFC_PIN_NONE, 5329 [23] = SH_PFC_PIN_NONE, 5330 [24] = SH_PFC_PIN_NONE, 5331 [25] = SH_PFC_PIN_NONE, 5332 [26] = SH_PFC_PIN_NONE, 5333 [27] = SH_PFC_PIN_NONE, 5334 [28] = SH_PFC_PIN_NONE, 5335 [29] = SH_PFC_PIN_NONE, 5336 [30] = RCAR_GP_PIN(6, 9), /* USB30_OVC */ 5337 [31] = RCAR_GP_PIN(6, 17), /* USB30_PWEN */ 5338 } }, 5339 { /* sentinel */ }, 5340 }; 5341 5342 static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = { 5343 .pin_to_pocctrl = r8a77990_pin_to_pocctrl, 5344 .get_bias = rcar_pinmux_get_bias, 5345 .set_bias = rcar_pinmux_set_bias, 5346 }; 5347 5348 #ifdef CONFIG_PINCTRL_PFC_R8A774C0 5349 const struct sh_pfc_soc_info r8a774c0_pinmux_info = { 5350 .name = "r8a774c0_pfc", 5351 .ops = &r8a77990_pinmux_ops, 5352 .unlock_reg = 0xe6060000, /* PMMR */ 5353 5354 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5355 5356 .pins = pinmux_pins, 5357 .nr_pins = ARRAY_SIZE(pinmux_pins), 5358 .groups = pinmux_groups.common, 5359 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 5360 .functions = pinmux_functions.common, 5361 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 5362 5363 .cfg_regs = pinmux_config_regs, 5364 .bias_regs = pinmux_bias_regs, 5365 .ioctrl_regs = pinmux_ioctrl_regs, 5366 5367 .pinmux_data = pinmux_data, 5368 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5369 }; 5370 #endif 5371 5372 #ifdef CONFIG_PINCTRL_PFC_R8A77990 5373 const struct sh_pfc_soc_info r8a77990_pinmux_info = { 5374 .name = "r8a77990_pfc", 5375 .ops = &r8a77990_pinmux_ops, 5376 .unlock_reg = 0xe6060000, /* PMMR */ 5377 5378 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5379 5380 .pins = pinmux_pins, 5381 .nr_pins = ARRAY_SIZE(pinmux_pins), 5382 .groups = pinmux_groups.common, 5383 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 5384 ARRAY_SIZE(pinmux_groups.automotive), 5385 .functions = pinmux_functions.common, 5386 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 5387 ARRAY_SIZE(pinmux_functions.automotive), 5388 5389 .cfg_regs = pinmux_config_regs, 5390 .bias_regs = pinmux_bias_regs, 5391 .ioctrl_regs = pinmux_ioctrl_regs, 5392 5393 .pinmux_data = pinmux_data, 5394 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5395 }; 5396 #endif 5397