1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77965 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 6 * Copyright (C) 2016-2019 Renesas Electronics Corp. 7 * 8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c 9 * 10 * R-Car Gen3 processor support - PFC hardware block. 11 * 12 * Copyright (C) 2015 Renesas Electronics Corporation 13 */ 14 15 #include <linux/errno.h> 16 #include <linux/kernel.h> 17 18 #include "core.h" 19 #include "sh_pfc.h" 20 21 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 22 23 #define CPU_ALL_GP(fn, sfx) \ 24 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ 25 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ 26 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ 27 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 28 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ 29 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ 30 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ 31 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 32 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 33 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ 34 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ 35 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) 36 37 #define CPU_ALL_NOGP(fn) \ 38 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ 39 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ 40 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ 41 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ 42 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ 43 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ 44 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ 45 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ 46 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ 47 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ 48 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ 49 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ 50 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ 51 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ 52 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ 53 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ 54 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ 55 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ 56 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ 57 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \ 58 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ 59 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ 60 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ 61 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ 62 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ 63 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ 64 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ 65 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ 66 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ 67 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ 68 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ 69 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ 70 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ 71 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ 72 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ 73 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ 74 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ 75 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 76 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ 77 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 78 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ 79 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 80 81 /* 82 * F_() : just information 83 * FM() : macro for FN_xxx / xxx_MARK 84 */ 85 86 /* GPSR0 */ 87 #define GPSR0_15 F_(D15, IP7_11_8) 88 #define GPSR0_14 F_(D14, IP7_7_4) 89 #define GPSR0_13 F_(D13, IP7_3_0) 90 #define GPSR0_12 F_(D12, IP6_31_28) 91 #define GPSR0_11 F_(D11, IP6_27_24) 92 #define GPSR0_10 F_(D10, IP6_23_20) 93 #define GPSR0_9 F_(D9, IP6_19_16) 94 #define GPSR0_8 F_(D8, IP6_15_12) 95 #define GPSR0_7 F_(D7, IP6_11_8) 96 #define GPSR0_6 F_(D6, IP6_7_4) 97 #define GPSR0_5 F_(D5, IP6_3_0) 98 #define GPSR0_4 F_(D4, IP5_31_28) 99 #define GPSR0_3 F_(D3, IP5_27_24) 100 #define GPSR0_2 F_(D2, IP5_23_20) 101 #define GPSR0_1 F_(D1, IP5_19_16) 102 #define GPSR0_0 F_(D0, IP5_15_12) 103 104 /* GPSR1 */ 105 #define GPSR1_28 FM(CLKOUT) 106 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) 107 #define GPSR1_26 F_(WE1_N, IP5_7_4) 108 #define GPSR1_25 F_(WE0_N, IP5_3_0) 109 #define GPSR1_24 F_(RD_WR_N, IP4_31_28) 110 #define GPSR1_23 F_(RD_N, IP4_27_24) 111 #define GPSR1_22 F_(BS_N, IP4_23_20) 112 #define GPSR1_21 F_(CS1_N, IP4_19_16) 113 #define GPSR1_20 F_(CS0_N, IP4_15_12) 114 #define GPSR1_19 F_(A19, IP4_11_8) 115 #define GPSR1_18 F_(A18, IP4_7_4) 116 #define GPSR1_17 F_(A17, IP4_3_0) 117 #define GPSR1_16 F_(A16, IP3_31_28) 118 #define GPSR1_15 F_(A15, IP3_27_24) 119 #define GPSR1_14 F_(A14, IP3_23_20) 120 #define GPSR1_13 F_(A13, IP3_19_16) 121 #define GPSR1_12 F_(A12, IP3_15_12) 122 #define GPSR1_11 F_(A11, IP3_11_8) 123 #define GPSR1_10 F_(A10, IP3_7_4) 124 #define GPSR1_9 F_(A9, IP3_3_0) 125 #define GPSR1_8 F_(A8, IP2_31_28) 126 #define GPSR1_7 F_(A7, IP2_27_24) 127 #define GPSR1_6 F_(A6, IP2_23_20) 128 #define GPSR1_5 F_(A5, IP2_19_16) 129 #define GPSR1_4 F_(A4, IP2_15_12) 130 #define GPSR1_3 F_(A3, IP2_11_8) 131 #define GPSR1_2 F_(A2, IP2_7_4) 132 #define GPSR1_1 F_(A1, IP2_3_0) 133 #define GPSR1_0 F_(A0, IP1_31_28) 134 135 /* GPSR2 */ 136 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) 137 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) 138 #define GPSR2_12 F_(AVB_LINK, IP0_15_12) 139 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) 140 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) 141 #define GPSR2_9 F_(AVB_MDC, IP0_3_0) 142 #define GPSR2_8 F_(PWM2_A, IP1_27_24) 143 #define GPSR2_7 F_(PWM1_A, IP1_23_20) 144 #define GPSR2_6 F_(PWM0, IP1_19_16) 145 #define GPSR2_5 F_(IRQ5, IP1_15_12) 146 #define GPSR2_4 F_(IRQ4, IP1_11_8) 147 #define GPSR2_3 F_(IRQ3, IP1_7_4) 148 #define GPSR2_2 F_(IRQ2, IP1_3_0) 149 #define GPSR2_1 F_(IRQ1, IP0_31_28) 150 #define GPSR2_0 F_(IRQ0, IP0_27_24) 151 152 /* GPSR3 */ 153 #define GPSR3_15 F_(SD1_WP, IP11_23_20) 154 #define GPSR3_14 F_(SD1_CD, IP11_19_16) 155 #define GPSR3_13 F_(SD0_WP, IP11_15_12) 156 #define GPSR3_12 F_(SD0_CD, IP11_11_8) 157 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28) 158 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24) 159 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20) 160 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16) 161 #define GPSR3_7 F_(SD1_CMD, IP8_15_12) 162 #define GPSR3_6 F_(SD1_CLK, IP8_11_8) 163 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4) 164 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0) 165 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28) 166 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24) 167 #define GPSR3_1 F_(SD0_CMD, IP7_23_20) 168 #define GPSR3_0 F_(SD0_CLK, IP7_19_16) 169 170 /* GPSR4 */ 171 #define GPSR4_17 F_(SD3_DS, IP11_7_4) 172 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0) 173 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28) 174 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24) 175 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20) 176 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16) 177 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12) 178 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8) 179 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4) 180 #define GPSR4_8 F_(SD3_CMD, IP10_3_0) 181 #define GPSR4_7 F_(SD3_CLK, IP9_31_28) 182 #define GPSR4_6 F_(SD2_DS, IP9_27_24) 183 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20) 184 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16) 185 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12) 186 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8) 187 #define GPSR4_1 F_(SD2_CMD, IP9_7_4) 188 #define GPSR4_0 F_(SD2_CLK, IP9_3_0) 189 190 /* GPSR5 */ 191 #define GPSR5_25 F_(MLB_DAT, IP14_19_16) 192 #define GPSR5_24 F_(MLB_SIG, IP14_15_12) 193 #define GPSR5_23 F_(MLB_CLK, IP14_11_8) 194 #define GPSR5_22 FM(MSIOF0_RXD) 195 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) 196 #define GPSR5_20 FM(MSIOF0_TXD) 197 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) 198 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) 199 #define GPSR5_17 FM(MSIOF0_SCK) 200 #define GPSR5_16 F_(HRTS0_N, IP13_27_24) 201 #define GPSR5_15 F_(HCTS0_N, IP13_23_20) 202 #define GPSR5_14 F_(HTX0, IP13_19_16) 203 #define GPSR5_13 F_(HRX0, IP13_15_12) 204 #define GPSR5_12 F_(HSCK0, IP13_11_8) 205 #define GPSR5_11 F_(RX2_A, IP13_7_4) 206 #define GPSR5_10 F_(TX2_A, IP13_3_0) 207 #define GPSR5_9 F_(SCK2, IP12_31_28) 208 #define GPSR5_8 F_(RTS1_N, IP12_27_24) 209 #define GPSR5_7 F_(CTS1_N, IP12_23_20) 210 #define GPSR5_6 F_(TX1_A, IP12_19_16) 211 #define GPSR5_5 F_(RX1_A, IP12_15_12) 212 #define GPSR5_4 F_(RTS0_N, IP12_11_8) 213 #define GPSR5_3 F_(CTS0_N, IP12_7_4) 214 #define GPSR5_2 F_(TX0, IP12_3_0) 215 #define GPSR5_1 F_(RX0, IP11_31_28) 216 #define GPSR5_0 F_(SCK0, IP11_27_24) 217 218 /* GPSR6 */ 219 #define GPSR6_31 F_(GP6_31, IP18_7_4) 220 #define GPSR6_30 F_(GP6_30, IP18_3_0) 221 #define GPSR6_29 F_(USB30_OVC, IP17_31_28) 222 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24) 223 #define GPSR6_27 F_(USB1_OVC, IP17_23_20) 224 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16) 225 #define GPSR6_25 F_(USB0_OVC, IP17_15_12) 226 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8) 227 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) 228 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) 229 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) 230 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) 231 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) 232 #define GPSR6_18 F_(SSI_WS78, IP16_19_16) 233 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12) 234 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) 235 #define GPSR6_15 F_(SSI_WS6, IP16_7_4) 236 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0) 237 #define GPSR6_13 FM(SSI_SDATA5) 238 #define GPSR6_12 FM(SSI_WS5) 239 #define GPSR6_11 FM(SSI_SCK5) 240 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) 241 #define GPSR6_9 F_(SSI_WS4, IP15_27_24) 242 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20) 243 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) 244 #define GPSR6_6 F_(SSI_WS349, IP15_15_12) 245 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8) 246 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) 247 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) 248 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) 249 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24) 250 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) 251 252 /* GPSR7 */ 253 #define GPSR7_3 FM(GP7_03) 254 #define GPSR7_2 FM(GP7_02) 255 #define GPSR7_1 FM(AVS2) 256 #define GPSR7_0 FM(AVS1) 257 258 259 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 260 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 261 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 269 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 274 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 275 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 276 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 277 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287 288 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 289 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 312 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 313 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 314 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 315 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 316 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 317 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318 319 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 320 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 332 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 333 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 334 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 335 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 336 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 337 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 338 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 339 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 347 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 348 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 349 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 350 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 351 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 352 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 353 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 354 355 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 356 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 363 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 364 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 365 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 366 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 367 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 368 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 369 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 370 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 371 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 372 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 373 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 374 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 375 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 376 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) 377 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 378 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 379 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 380 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 381 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 382 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 383 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 384 385 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 386 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 387 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 388 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 389 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 390 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 391 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 392 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 393 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 394 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 395 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 396 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 397 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 398 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 399 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 400 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 401 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 402 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 403 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 404 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 405 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 406 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 407 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) 408 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) 409 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) 410 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 411 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) 412 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) 413 414 #define PINMUX_GPSR \ 415 \ 416 GPSR6_31 \ 417 GPSR6_30 \ 418 GPSR6_29 \ 419 GPSR1_28 GPSR6_28 \ 420 GPSR1_27 GPSR6_27 \ 421 GPSR1_26 GPSR6_26 \ 422 GPSR1_25 GPSR5_25 GPSR6_25 \ 423 GPSR1_24 GPSR5_24 GPSR6_24 \ 424 GPSR1_23 GPSR5_23 GPSR6_23 \ 425 GPSR1_22 GPSR5_22 GPSR6_22 \ 426 GPSR1_21 GPSR5_21 GPSR6_21 \ 427 GPSR1_20 GPSR5_20 GPSR6_20 \ 428 GPSR1_19 GPSR5_19 GPSR6_19 \ 429 GPSR1_18 GPSR5_18 GPSR6_18 \ 430 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ 431 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ 432 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ 433 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ 434 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ 435 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ 436 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ 437 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ 438 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ 439 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ 440 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ 441 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ 442 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ 443 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ 444 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ 445 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ 446 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ 447 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 448 449 #define PINMUX_IPSR \ 450 \ 451 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ 452 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ 453 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ 454 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ 455 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ 456 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ 457 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 458 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ 459 \ 460 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 461 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 462 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 463 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ 464 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 465 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 466 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 467 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 468 \ 469 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ 470 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ 471 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ 472 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ 473 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ 474 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ 475 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ 476 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ 477 \ 478 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ 479 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ 480 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ 481 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ 482 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ 483 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ 484 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 485 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ 486 \ 487 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ 488 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ 489 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ 490 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ 491 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ 492 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ 493 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ 494 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 495 496 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 497 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) 498 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) 499 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) 500 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) 501 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) 502 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) 503 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) 504 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) 505 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) 506 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 507 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) 508 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 509 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 510 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 511 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 512 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 513 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 514 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) 515 516 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 517 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 518 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) 519 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) 520 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) 521 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) 522 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1) 523 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) 524 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) 525 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) 526 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) 527 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 528 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 529 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 530 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 531 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) 532 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) 533 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 534 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 535 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 536 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) 537 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 538 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 539 540 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 541 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) 542 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) 543 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) 544 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 545 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 546 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 547 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) 548 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 549 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 550 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 551 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) 552 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) 553 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 554 555 #define PINMUX_MOD_SELS \ 556 \ 557 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ 558 MOD_SEL2_30 \ 559 MOD_SEL1_29_28_27 MOD_SEL2_29 \ 560 MOD_SEL0_28_27 MOD_SEL2_28_27 \ 561 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ 562 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ 563 MOD_SEL0_23 MOD_SEL1_23_22_21 \ 564 MOD_SEL0_22 MOD_SEL2_22 \ 565 MOD_SEL0_21 MOD_SEL2_21 \ 566 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ 567 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ 568 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ 569 MOD_SEL2_17 \ 570 MOD_SEL0_16 MOD_SEL1_16 \ 571 MOD_SEL1_15_14 \ 572 MOD_SEL0_14_13 \ 573 MOD_SEL1_13 \ 574 MOD_SEL0_12 MOD_SEL1_12 \ 575 MOD_SEL0_11 MOD_SEL1_11 \ 576 MOD_SEL0_10 MOD_SEL1_10 \ 577 MOD_SEL0_9_8 MOD_SEL1_9 \ 578 MOD_SEL0_7_6 \ 579 MOD_SEL1_6 \ 580 MOD_SEL0_5 MOD_SEL1_5 \ 581 MOD_SEL0_4_3 MOD_SEL1_4 \ 582 MOD_SEL1_3 \ 583 MOD_SEL1_2 \ 584 MOD_SEL1_1 \ 585 MOD_SEL1_0 MOD_SEL2_0 586 587 /* 588 * These pins are not able to be muxed but have other properties 589 * that can be set, such as drive-strength or pull-up/pull-down enable. 590 */ 591 #define PINMUX_STATIC \ 592 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ 593 FM(QSPI0_IO2) FM(QSPI0_IO3) \ 594 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ 595 FM(QSPI1_IO2) FM(QSPI1_IO3) \ 596 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ 597 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ 598 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ 599 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 600 FM(PRESETOUT) \ 601 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \ 602 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 603 604 #define PINMUX_PHYS \ 605 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) 606 607 enum { 608 PINMUX_RESERVED = 0, 609 610 PINMUX_DATA_BEGIN, 611 GP_ALL(DATA), 612 PINMUX_DATA_END, 613 614 #define F_(x, y) 615 #define FM(x) FN_##x, 616 PINMUX_FUNCTION_BEGIN, 617 GP_ALL(FN), 618 PINMUX_GPSR 619 PINMUX_IPSR 620 PINMUX_MOD_SELS 621 PINMUX_FUNCTION_END, 622 #undef F_ 623 #undef FM 624 625 #define F_(x, y) 626 #define FM(x) x##_MARK, 627 PINMUX_MARK_BEGIN, 628 PINMUX_GPSR 629 PINMUX_IPSR 630 PINMUX_MOD_SELS 631 PINMUX_STATIC 632 PINMUX_PHYS 633 PINMUX_MARK_END, 634 #undef F_ 635 #undef FM 636 }; 637 638 static const u16 pinmux_data[] = { 639 PINMUX_DATA_GP_ALL(), 640 641 PINMUX_SINGLE(AVS1), 642 PINMUX_SINGLE(AVS2), 643 PINMUX_SINGLE(CLKOUT), 644 PINMUX_SINGLE(GP7_03), 645 PINMUX_SINGLE(GP7_02), 646 PINMUX_SINGLE(MSIOF0_RXD), 647 PINMUX_SINGLE(MSIOF0_SCK), 648 PINMUX_SINGLE(MSIOF0_TXD), 649 PINMUX_SINGLE(SSI_SCK5), 650 PINMUX_SINGLE(SSI_SDATA5), 651 PINMUX_SINGLE(SSI_WS5), 652 653 /* IPSR0 */ 654 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), 655 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), 656 657 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), 658 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), 659 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), 660 661 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), 662 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), 663 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), 664 665 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), 666 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), 667 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), 668 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), 669 670 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 671 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 672 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 673 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), 674 675 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 676 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 677 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), 678 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), 679 680 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 681 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 682 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), 683 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), 684 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), 685 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), 686 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), 687 688 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), 689 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), 690 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), 691 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), 692 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), 693 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), 694 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), 695 696 /* IPSR1 */ 697 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), 698 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), 699 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), 700 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), 701 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), 702 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), 703 704 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), 705 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), 706 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), 707 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), 708 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), 709 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), 710 711 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 712 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), 713 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), 714 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), 715 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), 716 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), 717 718 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), 719 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), 720 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), 721 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), 722 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), 723 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B), 724 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), 725 726 PINMUX_IPSR_GPSR(IP1_19_16, PWM0), 727 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), 728 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 729 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 730 731 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), 732 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 733 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), 734 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), 735 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), 736 737 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), 738 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), 739 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), 740 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), 741 742 PINMUX_IPSR_GPSR(IP1_31_28, A0), 743 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), 744 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), 745 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), 746 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), 747 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), 748 749 /* IPSR2 */ 750 PINMUX_IPSR_GPSR(IP2_3_0, A1), 751 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), 752 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), 753 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), 754 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), 755 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), 756 757 PINMUX_IPSR_GPSR(IP2_7_4, A2), 758 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), 759 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), 760 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), 761 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), 762 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), 763 764 PINMUX_IPSR_GPSR(IP2_11_8, A3), 765 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), 766 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), 767 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), 768 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), 769 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), 770 771 PINMUX_IPSR_GPSR(IP2_15_12, A4), 772 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), 773 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), 774 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), 775 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), 776 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), 777 778 PINMUX_IPSR_GPSR(IP2_19_16, A5), 779 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), 780 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), 781 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), 782 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), 783 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), 784 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), 785 786 PINMUX_IPSR_GPSR(IP2_23_20, A6), 787 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), 788 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), 789 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), 790 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), 791 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), 792 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), 793 794 PINMUX_IPSR_GPSR(IP2_27_24, A7), 795 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 796 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 797 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 798 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 799 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), 800 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), 801 802 PINMUX_IPSR_GPSR(IP2_31_28, A8), 803 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), 804 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), 805 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), 806 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), 807 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), 808 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), 809 810 /* IPSR3 */ 811 PINMUX_IPSR_GPSR(IP3_3_0, A9), 812 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), 813 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), 814 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), 815 816 PINMUX_IPSR_GPSR(IP3_7_4, A10), 817 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 818 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), 819 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 820 821 PINMUX_IPSR_GPSR(IP3_11_8, A11), 822 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), 823 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), 824 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), 825 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), 826 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), 827 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), 828 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), 829 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), 830 831 PINMUX_IPSR_GPSR(IP3_15_12, A12), 832 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), 833 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), 834 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), 835 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), 836 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), 837 838 PINMUX_IPSR_GPSR(IP3_19_16, A13), 839 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), 840 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), 841 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), 842 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), 843 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), 844 845 PINMUX_IPSR_GPSR(IP3_23_20, A14), 846 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), 847 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), 848 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), 849 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), 850 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), 851 852 PINMUX_IPSR_GPSR(IP3_27_24, A15), 853 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), 854 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), 855 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), 856 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), 857 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), 858 859 PINMUX_IPSR_GPSR(IP3_31_28, A16), 860 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), 861 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), 862 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), 863 864 /* IPSR4 */ 865 PINMUX_IPSR_GPSR(IP4_3_0, A17), 866 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), 867 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), 868 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), 869 870 PINMUX_IPSR_GPSR(IP4_7_4, A18), 871 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), 872 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), 873 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), 874 875 PINMUX_IPSR_GPSR(IP4_11_8, A19), 876 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), 877 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), 878 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), 879 880 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), 881 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), 882 883 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), 884 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), 885 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), 886 887 PINMUX_IPSR_GPSR(IP4_23_20, BS_N), 888 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), 889 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), 890 PINMUX_IPSR_GPSR(IP4_23_20, SCK3), 891 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), 892 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), 893 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), 894 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), 895 896 PINMUX_IPSR_GPSR(IP4_27_24, RD_N), 897 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), 898 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), 899 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), 900 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), 901 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), 902 903 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), 904 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), 905 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), 906 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), 907 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), 908 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), 909 910 /* IPSR5 */ 911 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), 912 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), 913 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), 914 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), 915 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), 916 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), 917 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), 918 919 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 920 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 921 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), 922 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 923 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 924 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 925 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), 926 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), 927 928 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), 929 PINMUX_IPSR_GPSR(IP5_11_8, QCLK), 930 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), 931 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), 932 933 PINMUX_IPSR_GPSR(IP5_15_12, D0), 934 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), 935 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), 936 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), 937 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), 938 939 PINMUX_IPSR_GPSR(IP5_19_16, D1), 940 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), 941 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), 942 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), 943 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), 944 945 PINMUX_IPSR_GPSR(IP5_23_20, D2), 946 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), 947 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), 948 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), 949 950 PINMUX_IPSR_GPSR(IP5_27_24, D3), 951 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), 952 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), 953 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), 954 955 PINMUX_IPSR_GPSR(IP5_31_28, D4), 956 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), 957 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), 958 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), 959 960 /* IPSR6 */ 961 PINMUX_IPSR_GPSR(IP6_3_0, D5), 962 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 963 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), 964 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), 965 966 PINMUX_IPSR_GPSR(IP6_7_4, D6), 967 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), 968 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), 969 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), 970 971 PINMUX_IPSR_GPSR(IP6_11_8, D7), 972 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), 973 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), 974 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), 975 976 PINMUX_IPSR_GPSR(IP6_15_12, D8), 977 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), 978 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), 979 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), 980 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), 981 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), 982 983 PINMUX_IPSR_GPSR(IP6_19_16, D9), 984 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), 985 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), 986 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), 987 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), 988 989 PINMUX_IPSR_GPSR(IP6_23_20, D10), 990 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), 991 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), 992 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), 993 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), 994 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), 995 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), 996 997 PINMUX_IPSR_GPSR(IP6_27_24, D11), 998 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 999 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 1000 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 1001 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 1002 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), 1003 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 1004 1005 PINMUX_IPSR_GPSR(IP6_31_28, D12), 1006 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 1007 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 1008 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 1009 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 1010 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), 1011 1012 /* IPSR7 */ 1013 PINMUX_IPSR_GPSR(IP7_3_0, D13), 1014 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), 1015 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), 1016 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), 1017 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), 1018 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), 1019 1020 PINMUX_IPSR_GPSR(IP7_7_4, D14), 1021 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), 1022 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), 1023 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), 1024 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), 1025 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), 1026 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), 1027 1028 PINMUX_IPSR_GPSR(IP7_11_8, D15), 1029 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), 1030 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), 1031 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), 1032 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), 1033 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), 1034 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), 1035 1036 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), 1037 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), 1038 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), 1039 1040 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), 1041 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), 1042 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), 1043 1044 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), 1045 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), 1046 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), 1047 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), 1048 1049 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), 1050 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), 1051 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), 1052 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), 1053 1054 /* IPSR8 */ 1055 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), 1056 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), 1057 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), 1058 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), 1059 1060 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), 1061 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), 1062 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), 1063 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), 1064 1065 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), 1066 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), 1067 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), 1068 1069 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1070 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1071 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), 1072 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1073 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1074 1075 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1076 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1077 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1078 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), 1079 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1080 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1081 1082 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1083 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1084 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1085 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), 1086 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1087 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1088 1089 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1090 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1091 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1092 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), 1093 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1094 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1095 1096 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1097 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1098 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1099 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), 1100 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1101 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1102 1103 /* IPSR9 */ 1104 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), 1105 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), 1106 1107 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), 1108 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), 1109 1110 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), 1111 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), 1112 1113 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), 1114 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), 1115 1116 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), 1117 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), 1118 1119 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), 1120 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), 1121 1122 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), 1123 PINMUX_IPSR_GPSR(IP9_27_24, NFALE), 1124 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B), 1125 1126 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), 1127 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), 1128 1129 /* IPSR10 */ 1130 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), 1131 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), 1132 1133 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), 1134 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), 1135 1136 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), 1137 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), 1138 1139 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), 1140 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), 1141 1142 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), 1143 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), 1144 1145 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), 1146 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), 1147 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), 1148 1149 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), 1150 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), 1151 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), 1152 1153 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), 1154 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), 1155 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), 1156 1157 /* IPSR11 */ 1158 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), 1159 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), 1160 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), 1161 1162 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), 1163 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), 1164 1165 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), 1166 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0), 1167 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), 1168 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), 1169 1170 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), 1171 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0), 1172 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), 1173 1174 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), 1175 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), 1176 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1177 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), 1178 1179 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), 1180 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), 1181 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1182 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), 1183 1184 PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1185 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1186 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1187 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), 1188 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1189 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1190 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1191 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1192 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), 1193 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), 1194 1195 PINMUX_IPSR_GPSR(IP11_31_28, RX0), 1196 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), 1197 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), 1198 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), 1199 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), 1200 1201 /* IPSR12 */ 1202 PINMUX_IPSR_GPSR(IP12_3_0, TX0), 1203 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), 1204 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), 1205 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), 1206 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), 1207 1208 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), 1209 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), 1210 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), 1211 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), 1212 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), 1213 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), 1214 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), 1215 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), 1216 1217 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), 1218 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1219 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1220 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), 1221 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1222 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1223 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1224 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), 1225 1226 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), 1227 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), 1228 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), 1229 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), 1230 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), 1231 1232 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), 1233 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), 1234 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), 1235 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), 1236 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), 1237 1238 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), 1239 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), 1240 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), 1241 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), 1242 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), 1243 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), 1244 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), 1245 1246 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N), 1247 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1248 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1249 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1250 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), 1251 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), 1252 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), 1253 1254 PINMUX_IPSR_GPSR(IP12_31_28, SCK2), 1255 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), 1256 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), 1257 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), 1258 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), 1259 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), 1260 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), 1261 1262 /* IPSR13 */ 1263 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), 1264 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), 1265 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), 1266 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), 1267 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), 1268 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), 1269 1270 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), 1271 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), 1272 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), 1273 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), 1274 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), 1275 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), 1276 1277 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1278 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1279 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), 1280 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), 1281 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1282 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1283 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), 1284 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), 1285 1286 PINMUX_IPSR_GPSR(IP13_15_12, HRX0), 1287 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), 1288 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1), 1289 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), 1290 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), 1291 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), 1292 1293 PINMUX_IPSR_GPSR(IP13_19_16, HTX0), 1294 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), 1295 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1), 1296 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), 1297 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), 1298 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), 1299 1300 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), 1301 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), 1302 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), 1303 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0), 1304 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), 1305 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), 1306 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), 1307 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), 1308 1309 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), 1310 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), 1311 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), 1312 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0), 1313 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), 1314 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), 1315 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), 1316 1317 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), 1318 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), 1319 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), 1320 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), 1321 1322 /* IPSR14 */ 1323 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1324 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1325 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), 1326 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), 1327 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), 1328 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1329 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1330 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1), 1331 1332 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1333 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1334 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1335 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), 1336 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), 1337 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1338 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1339 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), 1340 1341 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), 1342 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), 1343 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), 1344 1345 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), 1346 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), 1347 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), 1348 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), 1349 1350 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), 1351 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), 1352 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), 1353 1354 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), 1355 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), 1356 1357 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), 1358 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), 1359 1360 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), 1361 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), 1362 1363 /* IPSR15 */ 1364 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0), 1365 1366 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0), 1367 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1), 1368 1369 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), 1370 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), 1371 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), 1372 1373 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), 1374 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), 1375 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), 1376 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), 1377 1378 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), 1379 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1380 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), 1381 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), 1382 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), 1383 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), 1384 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), 1385 1386 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), 1387 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), 1388 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), 1389 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), 1390 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), 1391 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), 1392 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), 1393 1394 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), 1395 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), 1396 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), 1397 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), 1398 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), 1399 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), 1400 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), 1401 1402 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), 1403 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), 1404 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), 1405 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), 1406 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), 1407 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), 1408 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), 1409 1410 /* IPSR16 */ 1411 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), 1412 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), 1413 1414 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), 1415 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), 1416 1417 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), 1418 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), 1419 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A), 1420 1421 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), 1422 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), 1423 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), 1424 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), 1425 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), 1426 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), 1427 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), 1428 1429 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), 1430 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), 1431 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), 1432 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), 1433 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), 1434 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), 1435 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), 1436 1437 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), 1438 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), 1439 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), 1440 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), 1441 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), 1442 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), 1443 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), 1444 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), 1445 1446 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), 1447 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), 1448 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), 1449 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), 1450 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), 1451 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), 1452 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), 1453 1454 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0), 1455 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), 1456 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), 1457 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), 1458 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1), 1459 PINMUX_IPSR_GPSR(IP16_31_28, SCK1), 1460 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), 1461 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1462 1463 /* IPSR17 */ 1464 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), 1465 1466 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), 1467 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1468 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1469 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1470 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), 1471 1472 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), 1473 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), 1474 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), 1475 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), 1476 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), 1477 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), 1478 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), 1479 1480 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), 1481 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), 1482 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), 1483 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), 1484 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), 1485 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), 1486 1487 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), 1488 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), 1489 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0), 1490 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), 1491 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), 1492 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), 1493 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), 1494 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), 1495 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), 1496 1497 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), 1498 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), 1499 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0), 1500 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), 1501 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), 1502 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), 1503 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), 1504 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), 1505 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), 1506 1507 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), 1508 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), 1509 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1), 1510 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1511 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), 1512 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1513 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), 1514 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), 1515 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), 1516 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), 1517 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), 1518 1519 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), 1520 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), 1521 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1), 1522 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), 1523 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), 1524 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), 1525 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), 1526 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), 1527 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), 1528 1529 /* IPSR18 */ 1530 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30), 1531 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), 1532 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1), 1533 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), 1534 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), 1535 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), 1536 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), 1537 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), 1538 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), 1539 1540 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31), 1541 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), 1542 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1), 1543 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), 1544 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), 1545 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), 1546 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), 1547 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1548 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1549 1550 /* 1551 * Static pins can not be muxed between different functions but 1552 * still need mark entries in the pinmux list. Add each static 1553 * pin to the list without an associated function. The sh-pfc 1554 * core will do the right thing and skip trying to mux the pin 1555 * while still applying configuration to it. 1556 */ 1557 #define FM(x) PINMUX_DATA(x##_MARK, 0), 1558 PINMUX_STATIC 1559 #undef FM 1560 }; 1561 1562 /* 1563 * Pins not associated with a GPIO port. 1564 */ 1565 enum { 1566 GP_ASSIGN_LAST(), 1567 NOGP_ALL(), 1568 }; 1569 1570 static const struct sh_pfc_pin pinmux_pins[] = { 1571 PINMUX_GPIO_GP_ALL(), 1572 PINMUX_NOGP_ALL(), 1573 }; 1574 1575 /* - AUDIO CLOCK ------------------------------------------------------------ */ 1576 static const unsigned int audio_clk_a_a_pins[] = { 1577 /* CLK A */ 1578 RCAR_GP_PIN(6, 22), 1579 }; 1580 static const unsigned int audio_clk_a_a_mux[] = { 1581 AUDIO_CLKA_A_MARK, 1582 }; 1583 static const unsigned int audio_clk_a_b_pins[] = { 1584 /* CLK A */ 1585 RCAR_GP_PIN(5, 4), 1586 }; 1587 static const unsigned int audio_clk_a_b_mux[] = { 1588 AUDIO_CLKA_B_MARK, 1589 }; 1590 static const unsigned int audio_clk_a_c_pins[] = { 1591 /* CLK A */ 1592 RCAR_GP_PIN(5, 19), 1593 }; 1594 static const unsigned int audio_clk_a_c_mux[] = { 1595 AUDIO_CLKA_C_MARK, 1596 }; 1597 static const unsigned int audio_clk_b_a_pins[] = { 1598 /* CLK B */ 1599 RCAR_GP_PIN(5, 12), 1600 }; 1601 static const unsigned int audio_clk_b_a_mux[] = { 1602 AUDIO_CLKB_A_MARK, 1603 }; 1604 static const unsigned int audio_clk_b_b_pins[] = { 1605 /* CLK B */ 1606 RCAR_GP_PIN(6, 23), 1607 }; 1608 static const unsigned int audio_clk_b_b_mux[] = { 1609 AUDIO_CLKB_B_MARK, 1610 }; 1611 static const unsigned int audio_clk_c_a_pins[] = { 1612 /* CLK C */ 1613 RCAR_GP_PIN(5, 21), 1614 }; 1615 static const unsigned int audio_clk_c_a_mux[] = { 1616 AUDIO_CLKC_A_MARK, 1617 }; 1618 static const unsigned int audio_clk_c_b_pins[] = { 1619 /* CLK C */ 1620 RCAR_GP_PIN(5, 0), 1621 }; 1622 static const unsigned int audio_clk_c_b_mux[] = { 1623 AUDIO_CLKC_B_MARK, 1624 }; 1625 static const unsigned int audio_clkout_a_pins[] = { 1626 /* CLKOUT */ 1627 RCAR_GP_PIN(5, 18), 1628 }; 1629 static const unsigned int audio_clkout_a_mux[] = { 1630 AUDIO_CLKOUT_A_MARK, 1631 }; 1632 static const unsigned int audio_clkout_b_pins[] = { 1633 /* CLKOUT */ 1634 RCAR_GP_PIN(6, 28), 1635 }; 1636 static const unsigned int audio_clkout_b_mux[] = { 1637 AUDIO_CLKOUT_B_MARK, 1638 }; 1639 static const unsigned int audio_clkout_c_pins[] = { 1640 /* CLKOUT */ 1641 RCAR_GP_PIN(5, 3), 1642 }; 1643 static const unsigned int audio_clkout_c_mux[] = { 1644 AUDIO_CLKOUT_C_MARK, 1645 }; 1646 static const unsigned int audio_clkout_d_pins[] = { 1647 /* CLKOUT */ 1648 RCAR_GP_PIN(5, 21), 1649 }; 1650 static const unsigned int audio_clkout_d_mux[] = { 1651 AUDIO_CLKOUT_D_MARK, 1652 }; 1653 static const unsigned int audio_clkout1_a_pins[] = { 1654 /* CLKOUT1 */ 1655 RCAR_GP_PIN(5, 15), 1656 }; 1657 static const unsigned int audio_clkout1_a_mux[] = { 1658 AUDIO_CLKOUT1_A_MARK, 1659 }; 1660 static const unsigned int audio_clkout1_b_pins[] = { 1661 /* CLKOUT1 */ 1662 RCAR_GP_PIN(6, 29), 1663 }; 1664 static const unsigned int audio_clkout1_b_mux[] = { 1665 AUDIO_CLKOUT1_B_MARK, 1666 }; 1667 static const unsigned int audio_clkout2_a_pins[] = { 1668 /* CLKOUT2 */ 1669 RCAR_GP_PIN(5, 16), 1670 }; 1671 static const unsigned int audio_clkout2_a_mux[] = { 1672 AUDIO_CLKOUT2_A_MARK, 1673 }; 1674 static const unsigned int audio_clkout2_b_pins[] = { 1675 /* CLKOUT2 */ 1676 RCAR_GP_PIN(6, 30), 1677 }; 1678 static const unsigned int audio_clkout2_b_mux[] = { 1679 AUDIO_CLKOUT2_B_MARK, 1680 }; 1681 1682 static const unsigned int audio_clkout3_a_pins[] = { 1683 /* CLKOUT3 */ 1684 RCAR_GP_PIN(5, 19), 1685 }; 1686 static const unsigned int audio_clkout3_a_mux[] = { 1687 AUDIO_CLKOUT3_A_MARK, 1688 }; 1689 static const unsigned int audio_clkout3_b_pins[] = { 1690 /* CLKOUT3 */ 1691 RCAR_GP_PIN(6, 31), 1692 }; 1693 static const unsigned int audio_clkout3_b_mux[] = { 1694 AUDIO_CLKOUT3_B_MARK, 1695 }; 1696 1697 /* - EtherAVB --------------------------------------------------------------- */ 1698 static const unsigned int avb_link_pins[] = { 1699 /* AVB_LINK */ 1700 RCAR_GP_PIN(2, 12), 1701 }; 1702 static const unsigned int avb_link_mux[] = { 1703 AVB_LINK_MARK, 1704 }; 1705 static const unsigned int avb_magic_pins[] = { 1706 /* AVB_MAGIC_ */ 1707 RCAR_GP_PIN(2, 10), 1708 }; 1709 static const unsigned int avb_magic_mux[] = { 1710 AVB_MAGIC_MARK, 1711 }; 1712 static const unsigned int avb_phy_int_pins[] = { 1713 /* AVB_PHY_INT */ 1714 RCAR_GP_PIN(2, 11), 1715 }; 1716 static const unsigned int avb_phy_int_mux[] = { 1717 AVB_PHY_INT_MARK, 1718 }; 1719 static const unsigned int avb_mdio_pins[] = { 1720 /* AVB_MDC, AVB_MDIO */ 1721 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, 1722 }; 1723 static const unsigned int avb_mdio_mux[] = { 1724 AVB_MDC_MARK, AVB_MDIO_MARK, 1725 }; 1726 static const unsigned int avb_mii_pins[] = { 1727 /* 1728 * AVB_TX_CTL, AVB_TXC, AVB_TD0, 1729 * AVB_TD1, AVB_TD2, AVB_TD3, 1730 * AVB_RX_CTL, AVB_RXC, AVB_RD0, 1731 * AVB_RD1, AVB_RD2, AVB_RD3, 1732 * AVB_TXCREFCLK 1733 */ 1734 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, 1735 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, 1736 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, 1737 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, 1738 PIN_AVB_TXCREFCLK, 1739 }; 1740 static const unsigned int avb_mii_mux[] = { 1741 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, 1742 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, 1743 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, 1744 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, 1745 AVB_TXCREFCLK_MARK, 1746 }; 1747 static const unsigned int avb_avtp_pps_pins[] = { 1748 /* AVB_AVTP_PPS */ 1749 RCAR_GP_PIN(2, 6), 1750 }; 1751 static const unsigned int avb_avtp_pps_mux[] = { 1752 AVB_AVTP_PPS_MARK, 1753 }; 1754 static const unsigned int avb_avtp_match_a_pins[] = { 1755 /* AVB_AVTP_MATCH_A */ 1756 RCAR_GP_PIN(2, 13), 1757 }; 1758 static const unsigned int avb_avtp_match_a_mux[] = { 1759 AVB_AVTP_MATCH_A_MARK, 1760 }; 1761 static const unsigned int avb_avtp_capture_a_pins[] = { 1762 /* AVB_AVTP_CAPTURE_A */ 1763 RCAR_GP_PIN(2, 14), 1764 }; 1765 static const unsigned int avb_avtp_capture_a_mux[] = { 1766 AVB_AVTP_CAPTURE_A_MARK, 1767 }; 1768 static const unsigned int avb_avtp_match_b_pins[] = { 1769 /* AVB_AVTP_MATCH_B */ 1770 RCAR_GP_PIN(1, 8), 1771 }; 1772 static const unsigned int avb_avtp_match_b_mux[] = { 1773 AVB_AVTP_MATCH_B_MARK, 1774 }; 1775 static const unsigned int avb_avtp_capture_b_pins[] = { 1776 /* AVB_AVTP_CAPTURE_B */ 1777 RCAR_GP_PIN(1, 11), 1778 }; 1779 static const unsigned int avb_avtp_capture_b_mux[] = { 1780 AVB_AVTP_CAPTURE_B_MARK, 1781 }; 1782 1783 /* - CAN ------------------------------------------------------------------ */ 1784 static const unsigned int can0_data_a_pins[] = { 1785 /* TX, RX */ 1786 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1787 }; 1788 1789 static const unsigned int can0_data_a_mux[] = { 1790 CAN0_TX_A_MARK, CAN0_RX_A_MARK, 1791 }; 1792 1793 static const unsigned int can0_data_b_pins[] = { 1794 /* TX, RX */ 1795 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1796 }; 1797 1798 static const unsigned int can0_data_b_mux[] = { 1799 CAN0_TX_B_MARK, CAN0_RX_B_MARK, 1800 }; 1801 1802 static const unsigned int can1_data_pins[] = { 1803 /* TX, RX */ 1804 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1805 }; 1806 1807 static const unsigned int can1_data_mux[] = { 1808 CAN1_TX_MARK, CAN1_RX_MARK, 1809 }; 1810 1811 /* - CAN Clock -------------------------------------------------------------- */ 1812 static const unsigned int can_clk_pins[] = { 1813 /* CLK */ 1814 RCAR_GP_PIN(1, 25), 1815 }; 1816 1817 static const unsigned int can_clk_mux[] = { 1818 CAN_CLK_MARK, 1819 }; 1820 1821 /* - CAN FD --------------------------------------------------------------- */ 1822 static const unsigned int canfd0_data_a_pins[] = { 1823 /* TX, RX */ 1824 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 1825 }; 1826 1827 static const unsigned int canfd0_data_a_mux[] = { 1828 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, 1829 }; 1830 1831 static const unsigned int canfd0_data_b_pins[] = { 1832 /* TX, RX */ 1833 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1834 }; 1835 1836 static const unsigned int canfd0_data_b_mux[] = { 1837 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, 1838 }; 1839 1840 static const unsigned int canfd1_data_pins[] = { 1841 /* TX, RX */ 1842 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), 1843 }; 1844 1845 static const unsigned int canfd1_data_mux[] = { 1846 CANFD1_TX_MARK, CANFD1_RX_MARK, 1847 }; 1848 1849 #ifdef CONFIG_PINCTRL_PFC_R8A77965 1850 /* - DRIF0 --------------------------------------------------------------- */ 1851 static const unsigned int drif0_ctrl_a_pins[] = { 1852 /* CLK, SYNC */ 1853 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 1854 }; 1855 1856 static const unsigned int drif0_ctrl_a_mux[] = { 1857 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, 1858 }; 1859 1860 static const unsigned int drif0_data0_a_pins[] = { 1861 /* D0 */ 1862 RCAR_GP_PIN(6, 10), 1863 }; 1864 1865 static const unsigned int drif0_data0_a_mux[] = { 1866 RIF0_D0_A_MARK, 1867 }; 1868 1869 static const unsigned int drif0_data1_a_pins[] = { 1870 /* D1 */ 1871 RCAR_GP_PIN(6, 7), 1872 }; 1873 1874 static const unsigned int drif0_data1_a_mux[] = { 1875 RIF0_D1_A_MARK, 1876 }; 1877 1878 static const unsigned int drif0_ctrl_b_pins[] = { 1879 /* CLK, SYNC */ 1880 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 1881 }; 1882 1883 static const unsigned int drif0_ctrl_b_mux[] = { 1884 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, 1885 }; 1886 1887 static const unsigned int drif0_data0_b_pins[] = { 1888 /* D0 */ 1889 RCAR_GP_PIN(5, 1), 1890 }; 1891 1892 static const unsigned int drif0_data0_b_mux[] = { 1893 RIF0_D0_B_MARK, 1894 }; 1895 1896 static const unsigned int drif0_data1_b_pins[] = { 1897 /* D1 */ 1898 RCAR_GP_PIN(5, 2), 1899 }; 1900 1901 static const unsigned int drif0_data1_b_mux[] = { 1902 RIF0_D1_B_MARK, 1903 }; 1904 1905 static const unsigned int drif0_ctrl_c_pins[] = { 1906 /* CLK, SYNC */ 1907 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), 1908 }; 1909 1910 static const unsigned int drif0_ctrl_c_mux[] = { 1911 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, 1912 }; 1913 1914 static const unsigned int drif0_data0_c_pins[] = { 1915 /* D0 */ 1916 RCAR_GP_PIN(5, 13), 1917 }; 1918 1919 static const unsigned int drif0_data0_c_mux[] = { 1920 RIF0_D0_C_MARK, 1921 }; 1922 1923 static const unsigned int drif0_data1_c_pins[] = { 1924 /* D1 */ 1925 RCAR_GP_PIN(5, 14), 1926 }; 1927 1928 static const unsigned int drif0_data1_c_mux[] = { 1929 RIF0_D1_C_MARK, 1930 }; 1931 1932 /* - DRIF1 --------------------------------------------------------------- */ 1933 static const unsigned int drif1_ctrl_a_pins[] = { 1934 /* CLK, SYNC */ 1935 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 1936 }; 1937 1938 static const unsigned int drif1_ctrl_a_mux[] = { 1939 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, 1940 }; 1941 1942 static const unsigned int drif1_data0_a_pins[] = { 1943 /* D0 */ 1944 RCAR_GP_PIN(6, 19), 1945 }; 1946 1947 static const unsigned int drif1_data0_a_mux[] = { 1948 RIF1_D0_A_MARK, 1949 }; 1950 1951 static const unsigned int drif1_data1_a_pins[] = { 1952 /* D1 */ 1953 RCAR_GP_PIN(6, 20), 1954 }; 1955 1956 static const unsigned int drif1_data1_a_mux[] = { 1957 RIF1_D1_A_MARK, 1958 }; 1959 1960 static const unsigned int drif1_ctrl_b_pins[] = { 1961 /* CLK, SYNC */ 1962 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), 1963 }; 1964 1965 static const unsigned int drif1_ctrl_b_mux[] = { 1966 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, 1967 }; 1968 1969 static const unsigned int drif1_data0_b_pins[] = { 1970 /* D0 */ 1971 RCAR_GP_PIN(5, 7), 1972 }; 1973 1974 static const unsigned int drif1_data0_b_mux[] = { 1975 RIF1_D0_B_MARK, 1976 }; 1977 1978 static const unsigned int drif1_data1_b_pins[] = { 1979 /* D1 */ 1980 RCAR_GP_PIN(5, 8), 1981 }; 1982 1983 static const unsigned int drif1_data1_b_mux[] = { 1984 RIF1_D1_B_MARK, 1985 }; 1986 1987 static const unsigned int drif1_ctrl_c_pins[] = { 1988 /* CLK, SYNC */ 1989 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), 1990 }; 1991 1992 static const unsigned int drif1_ctrl_c_mux[] = { 1993 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, 1994 }; 1995 1996 static const unsigned int drif1_data0_c_pins[] = { 1997 /* D0 */ 1998 RCAR_GP_PIN(5, 6), 1999 }; 2000 2001 static const unsigned int drif1_data0_c_mux[] = { 2002 RIF1_D0_C_MARK, 2003 }; 2004 2005 static const unsigned int drif1_data1_c_pins[] = { 2006 /* D1 */ 2007 RCAR_GP_PIN(5, 10), 2008 }; 2009 2010 static const unsigned int drif1_data1_c_mux[] = { 2011 RIF1_D1_C_MARK, 2012 }; 2013 2014 /* - DRIF2 --------------------------------------------------------------- */ 2015 static const unsigned int drif2_ctrl_a_pins[] = { 2016 /* CLK, SYNC */ 2017 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2018 }; 2019 2020 static const unsigned int drif2_ctrl_a_mux[] = { 2021 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, 2022 }; 2023 2024 static const unsigned int drif2_data0_a_pins[] = { 2025 /* D0 */ 2026 RCAR_GP_PIN(6, 7), 2027 }; 2028 2029 static const unsigned int drif2_data0_a_mux[] = { 2030 RIF2_D0_A_MARK, 2031 }; 2032 2033 static const unsigned int drif2_data1_a_pins[] = { 2034 /* D1 */ 2035 RCAR_GP_PIN(6, 10), 2036 }; 2037 2038 static const unsigned int drif2_data1_a_mux[] = { 2039 RIF2_D1_A_MARK, 2040 }; 2041 2042 static const unsigned int drif2_ctrl_b_pins[] = { 2043 /* CLK, SYNC */ 2044 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 2045 }; 2046 2047 static const unsigned int drif2_ctrl_b_mux[] = { 2048 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, 2049 }; 2050 2051 static const unsigned int drif2_data0_b_pins[] = { 2052 /* D0 */ 2053 RCAR_GP_PIN(6, 30), 2054 }; 2055 2056 static const unsigned int drif2_data0_b_mux[] = { 2057 RIF2_D0_B_MARK, 2058 }; 2059 2060 static const unsigned int drif2_data1_b_pins[] = { 2061 /* D1 */ 2062 RCAR_GP_PIN(6, 31), 2063 }; 2064 2065 static const unsigned int drif2_data1_b_mux[] = { 2066 RIF2_D1_B_MARK, 2067 }; 2068 2069 /* - DRIF3 --------------------------------------------------------------- */ 2070 static const unsigned int drif3_ctrl_a_pins[] = { 2071 /* CLK, SYNC */ 2072 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2073 }; 2074 2075 static const unsigned int drif3_ctrl_a_mux[] = { 2076 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, 2077 }; 2078 2079 static const unsigned int drif3_data0_a_pins[] = { 2080 /* D0 */ 2081 RCAR_GP_PIN(6, 19), 2082 }; 2083 2084 static const unsigned int drif3_data0_a_mux[] = { 2085 RIF3_D0_A_MARK, 2086 }; 2087 2088 static const unsigned int drif3_data1_a_pins[] = { 2089 /* D1 */ 2090 RCAR_GP_PIN(6, 20), 2091 }; 2092 2093 static const unsigned int drif3_data1_a_mux[] = { 2094 RIF3_D1_A_MARK, 2095 }; 2096 2097 static const unsigned int drif3_ctrl_b_pins[] = { 2098 /* CLK, SYNC */ 2099 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 2100 }; 2101 2102 static const unsigned int drif3_ctrl_b_mux[] = { 2103 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, 2104 }; 2105 2106 static const unsigned int drif3_data0_b_pins[] = { 2107 /* D0 */ 2108 RCAR_GP_PIN(6, 28), 2109 }; 2110 2111 static const unsigned int drif3_data0_b_mux[] = { 2112 RIF3_D0_B_MARK, 2113 }; 2114 2115 static const unsigned int drif3_data1_b_pins[] = { 2116 /* D1 */ 2117 RCAR_GP_PIN(6, 29), 2118 }; 2119 2120 static const unsigned int drif3_data1_b_mux[] = { 2121 RIF3_D1_B_MARK, 2122 }; 2123 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 2124 2125 /* - DU --------------------------------------------------------------------- */ 2126 static const unsigned int du_rgb666_pins[] = { 2127 /* R[7:2], G[7:2], B[7:2] */ 2128 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2129 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2130 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2131 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2132 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2133 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2134 }; 2135 2136 static const unsigned int du_rgb666_mux[] = { 2137 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2138 DU_DR3_MARK, DU_DR2_MARK, 2139 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2140 DU_DG3_MARK, DU_DG2_MARK, 2141 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2142 DU_DB3_MARK, DU_DB2_MARK, 2143 }; 2144 2145 static const unsigned int du_rgb888_pins[] = { 2146 /* R[7:0], G[7:0], B[7:0] */ 2147 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), 2148 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 2149 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), 2150 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), 2151 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), 2152 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), 2153 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), 2154 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 2155 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 2156 }; 2157 2158 static const unsigned int du_rgb888_mux[] = { 2159 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, 2160 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, 2161 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, 2162 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, 2163 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, 2164 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, 2165 }; 2166 2167 static const unsigned int du_clk_out_0_pins[] = { 2168 /* CLKOUT */ 2169 RCAR_GP_PIN(1, 27), 2170 }; 2171 2172 static const unsigned int du_clk_out_0_mux[] = { 2173 DU_DOTCLKOUT0_MARK 2174 }; 2175 2176 static const unsigned int du_clk_out_1_pins[] = { 2177 /* CLKOUT */ 2178 RCAR_GP_PIN(2, 3), 2179 }; 2180 2181 static const unsigned int du_clk_out_1_mux[] = { 2182 DU_DOTCLKOUT1_MARK 2183 }; 2184 2185 static const unsigned int du_sync_pins[] = { 2186 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ 2187 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), 2188 }; 2189 2190 static const unsigned int du_sync_mux[] = { 2191 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK 2192 }; 2193 2194 static const unsigned int du_oddf_pins[] = { 2195 /* EXDISP/EXODDF/EXCDE */ 2196 RCAR_GP_PIN(2, 2), 2197 }; 2198 2199 static const unsigned int du_oddf_mux[] = { 2200 DU_EXODDF_DU_ODDF_DISP_CDE_MARK, 2201 }; 2202 2203 static const unsigned int du_cde_pins[] = { 2204 /* CDE */ 2205 RCAR_GP_PIN(2, 0), 2206 }; 2207 2208 static const unsigned int du_cde_mux[] = { 2209 DU_CDE_MARK, 2210 }; 2211 2212 static const unsigned int du_disp_pins[] = { 2213 /* DISP */ 2214 RCAR_GP_PIN(2, 1), 2215 }; 2216 2217 static const unsigned int du_disp_mux[] = { 2218 DU_DISP_MARK, 2219 }; 2220 2221 /* - HSCIF0 ----------------------------------------------------------------- */ 2222 static const unsigned int hscif0_data_pins[] = { 2223 /* RX, TX */ 2224 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), 2225 }; 2226 2227 static const unsigned int hscif0_data_mux[] = { 2228 HRX0_MARK, HTX0_MARK, 2229 }; 2230 2231 static const unsigned int hscif0_clk_pins[] = { 2232 /* SCK */ 2233 RCAR_GP_PIN(5, 12), 2234 }; 2235 2236 static const unsigned int hscif0_clk_mux[] = { 2237 HSCK0_MARK, 2238 }; 2239 2240 static const unsigned int hscif0_ctrl_pins[] = { 2241 /* RTS, CTS */ 2242 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), 2243 }; 2244 2245 static const unsigned int hscif0_ctrl_mux[] = { 2246 HRTS0_N_MARK, HCTS0_N_MARK, 2247 }; 2248 2249 /* - HSCIF1 ----------------------------------------------------------------- */ 2250 static const unsigned int hscif1_data_a_pins[] = { 2251 /* RX, TX */ 2252 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 2253 }; 2254 2255 static const unsigned int hscif1_data_a_mux[] = { 2256 HRX1_A_MARK, HTX1_A_MARK, 2257 }; 2258 2259 static const unsigned int hscif1_clk_a_pins[] = { 2260 /* SCK */ 2261 RCAR_GP_PIN(6, 21), 2262 }; 2263 2264 static const unsigned int hscif1_clk_a_mux[] = { 2265 HSCK1_A_MARK, 2266 }; 2267 2268 static const unsigned int hscif1_ctrl_a_pins[] = { 2269 /* RTS, CTS */ 2270 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 2271 }; 2272 2273 static const unsigned int hscif1_ctrl_a_mux[] = { 2274 HRTS1_N_A_MARK, HCTS1_N_A_MARK, 2275 }; 2276 2277 static const unsigned int hscif1_data_b_pins[] = { 2278 /* RX, TX */ 2279 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 2280 }; 2281 2282 static const unsigned int hscif1_data_b_mux[] = { 2283 HRX1_B_MARK, HTX1_B_MARK, 2284 }; 2285 2286 static const unsigned int hscif1_clk_b_pins[] = { 2287 /* SCK */ 2288 RCAR_GP_PIN(5, 0), 2289 }; 2290 2291 static const unsigned int hscif1_clk_b_mux[] = { 2292 HSCK1_B_MARK, 2293 }; 2294 2295 static const unsigned int hscif1_ctrl_b_pins[] = { 2296 /* RTS, CTS */ 2297 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 2298 }; 2299 2300 static const unsigned int hscif1_ctrl_b_mux[] = { 2301 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2302 }; 2303 2304 /* - HSCIF2 ----------------------------------------------------------------- */ 2305 static const unsigned int hscif2_data_a_pins[] = { 2306 /* RX, TX */ 2307 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 2308 }; 2309 2310 static const unsigned int hscif2_data_a_mux[] = { 2311 HRX2_A_MARK, HTX2_A_MARK, 2312 }; 2313 2314 static const unsigned int hscif2_clk_a_pins[] = { 2315 /* SCK */ 2316 RCAR_GP_PIN(6, 10), 2317 }; 2318 2319 static const unsigned int hscif2_clk_a_mux[] = { 2320 HSCK2_A_MARK, 2321 }; 2322 2323 static const unsigned int hscif2_ctrl_a_pins[] = { 2324 /* RTS, CTS */ 2325 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), 2326 }; 2327 2328 static const unsigned int hscif2_ctrl_a_mux[] = { 2329 HRTS2_N_A_MARK, HCTS2_N_A_MARK, 2330 }; 2331 2332 static const unsigned int hscif2_data_b_pins[] = { 2333 /* RX, TX */ 2334 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 2335 }; 2336 2337 static const unsigned int hscif2_data_b_mux[] = { 2338 HRX2_B_MARK, HTX2_B_MARK, 2339 }; 2340 2341 static const unsigned int hscif2_clk_b_pins[] = { 2342 /* SCK */ 2343 RCAR_GP_PIN(6, 21), 2344 }; 2345 2346 static const unsigned int hscif2_clk_b_mux[] = { 2347 HSCK2_B_MARK, 2348 }; 2349 2350 static const unsigned int hscif2_ctrl_b_pins[] = { 2351 /* RTS, CTS */ 2352 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), 2353 }; 2354 2355 static const unsigned int hscif2_ctrl_b_mux[] = { 2356 HRTS2_N_B_MARK, HCTS2_N_B_MARK, 2357 }; 2358 2359 static const unsigned int hscif2_data_c_pins[] = { 2360 /* RX, TX */ 2361 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), 2362 }; 2363 2364 static const unsigned int hscif2_data_c_mux[] = { 2365 HRX2_C_MARK, HTX2_C_MARK, 2366 }; 2367 2368 static const unsigned int hscif2_clk_c_pins[] = { 2369 /* SCK */ 2370 RCAR_GP_PIN(6, 24), 2371 }; 2372 2373 static const unsigned int hscif2_clk_c_mux[] = { 2374 HSCK2_C_MARK, 2375 }; 2376 2377 static const unsigned int hscif2_ctrl_c_pins[] = { 2378 /* RTS, CTS */ 2379 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), 2380 }; 2381 2382 static const unsigned int hscif2_ctrl_c_mux[] = { 2383 HRTS2_N_C_MARK, HCTS2_N_C_MARK, 2384 }; 2385 2386 /* - HSCIF3 ----------------------------------------------------------------- */ 2387 static const unsigned int hscif3_data_a_pins[] = { 2388 /* RX, TX */ 2389 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 2390 }; 2391 2392 static const unsigned int hscif3_data_a_mux[] = { 2393 HRX3_A_MARK, HTX3_A_MARK, 2394 }; 2395 2396 static const unsigned int hscif3_clk_pins[] = { 2397 /* SCK */ 2398 RCAR_GP_PIN(1, 22), 2399 }; 2400 2401 static const unsigned int hscif3_clk_mux[] = { 2402 HSCK3_MARK, 2403 }; 2404 2405 static const unsigned int hscif3_ctrl_pins[] = { 2406 /* RTS, CTS */ 2407 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2408 }; 2409 2410 static const unsigned int hscif3_ctrl_mux[] = { 2411 HRTS3_N_MARK, HCTS3_N_MARK, 2412 }; 2413 2414 static const unsigned int hscif3_data_b_pins[] = { 2415 /* RX, TX */ 2416 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 2417 }; 2418 2419 static const unsigned int hscif3_data_b_mux[] = { 2420 HRX3_B_MARK, HTX3_B_MARK, 2421 }; 2422 2423 static const unsigned int hscif3_data_c_pins[] = { 2424 /* RX, TX */ 2425 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 2426 }; 2427 2428 static const unsigned int hscif3_data_c_mux[] = { 2429 HRX3_C_MARK, HTX3_C_MARK, 2430 }; 2431 2432 static const unsigned int hscif3_data_d_pins[] = { 2433 /* RX, TX */ 2434 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2435 }; 2436 2437 static const unsigned int hscif3_data_d_mux[] = { 2438 HRX3_D_MARK, HTX3_D_MARK, 2439 }; 2440 2441 /* - HSCIF4 ----------------------------------------------------------------- */ 2442 static const unsigned int hscif4_data_a_pins[] = { 2443 /* RX, TX */ 2444 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 2445 }; 2446 2447 static const unsigned int hscif4_data_a_mux[] = { 2448 HRX4_A_MARK, HTX4_A_MARK, 2449 }; 2450 2451 static const unsigned int hscif4_clk_pins[] = { 2452 /* SCK */ 2453 RCAR_GP_PIN(1, 11), 2454 }; 2455 2456 static const unsigned int hscif4_clk_mux[] = { 2457 HSCK4_MARK, 2458 }; 2459 2460 static const unsigned int hscif4_ctrl_pins[] = { 2461 /* RTS, CTS */ 2462 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), 2463 }; 2464 2465 static const unsigned int hscif4_ctrl_mux[] = { 2466 HRTS4_N_MARK, HCTS4_N_MARK, 2467 }; 2468 2469 static const unsigned int hscif4_data_b_pins[] = { 2470 /* RX, TX */ 2471 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2472 }; 2473 2474 static const unsigned int hscif4_data_b_mux[] = { 2475 HRX4_B_MARK, HTX4_B_MARK, 2476 }; 2477 2478 /* - I2C -------------------------------------------------------------------- */ 2479 static const unsigned int i2c0_pins[] = { 2480 /* SCL, SDA */ 2481 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), 2482 }; 2483 2484 static const unsigned int i2c0_mux[] = { 2485 SCL0_MARK, SDA0_MARK, 2486 }; 2487 2488 static const unsigned int i2c1_a_pins[] = { 2489 /* SDA, SCL */ 2490 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2491 }; 2492 2493 static const unsigned int i2c1_a_mux[] = { 2494 SDA1_A_MARK, SCL1_A_MARK, 2495 }; 2496 2497 static const unsigned int i2c1_b_pins[] = { 2498 /* SDA, SCL */ 2499 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 2500 }; 2501 2502 static const unsigned int i2c1_b_mux[] = { 2503 SDA1_B_MARK, SCL1_B_MARK, 2504 }; 2505 2506 static const unsigned int i2c2_a_pins[] = { 2507 /* SDA, SCL */ 2508 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 2509 }; 2510 2511 static const unsigned int i2c2_a_mux[] = { 2512 SDA2_A_MARK, SCL2_A_MARK, 2513 }; 2514 2515 static const unsigned int i2c2_b_pins[] = { 2516 /* SDA, SCL */ 2517 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 2518 }; 2519 2520 static const unsigned int i2c2_b_mux[] = { 2521 SDA2_B_MARK, SCL2_B_MARK, 2522 }; 2523 2524 static const unsigned int i2c3_pins[] = { 2525 /* SCL, SDA */ 2526 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 2527 }; 2528 2529 static const unsigned int i2c3_mux[] = { 2530 SCL3_MARK, SDA3_MARK, 2531 }; 2532 2533 static const unsigned int i2c5_pins[] = { 2534 /* SCL, SDA */ 2535 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), 2536 }; 2537 2538 static const unsigned int i2c5_mux[] = { 2539 SCL5_MARK, SDA5_MARK, 2540 }; 2541 2542 static const unsigned int i2c6_a_pins[] = { 2543 /* SDA, SCL */ 2544 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2545 }; 2546 2547 static const unsigned int i2c6_a_mux[] = { 2548 SDA6_A_MARK, SCL6_A_MARK, 2549 }; 2550 2551 static const unsigned int i2c6_b_pins[] = { 2552 /* SDA, SCL */ 2553 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2554 }; 2555 2556 static const unsigned int i2c6_b_mux[] = { 2557 SDA6_B_MARK, SCL6_B_MARK, 2558 }; 2559 2560 static const unsigned int i2c6_c_pins[] = { 2561 /* SDA, SCL */ 2562 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 2563 }; 2564 2565 static const unsigned int i2c6_c_mux[] = { 2566 SDA6_C_MARK, SCL6_C_MARK, 2567 }; 2568 2569 /* - INTC-EX ---------------------------------------------------------------- */ 2570 static const unsigned int intc_ex_irq0_pins[] = { 2571 /* IRQ0 */ 2572 RCAR_GP_PIN(2, 0), 2573 }; 2574 static const unsigned int intc_ex_irq0_mux[] = { 2575 IRQ0_MARK, 2576 }; 2577 static const unsigned int intc_ex_irq1_pins[] = { 2578 /* IRQ1 */ 2579 RCAR_GP_PIN(2, 1), 2580 }; 2581 static const unsigned int intc_ex_irq1_mux[] = { 2582 IRQ1_MARK, 2583 }; 2584 static const unsigned int intc_ex_irq2_pins[] = { 2585 /* IRQ2 */ 2586 RCAR_GP_PIN(2, 2), 2587 }; 2588 static const unsigned int intc_ex_irq2_mux[] = { 2589 IRQ2_MARK, 2590 }; 2591 static const unsigned int intc_ex_irq3_pins[] = { 2592 /* IRQ3 */ 2593 RCAR_GP_PIN(2, 3), 2594 }; 2595 static const unsigned int intc_ex_irq3_mux[] = { 2596 IRQ3_MARK, 2597 }; 2598 static const unsigned int intc_ex_irq4_pins[] = { 2599 /* IRQ4 */ 2600 RCAR_GP_PIN(2, 4), 2601 }; 2602 static const unsigned int intc_ex_irq4_mux[] = { 2603 IRQ4_MARK, 2604 }; 2605 static const unsigned int intc_ex_irq5_pins[] = { 2606 /* IRQ5 */ 2607 RCAR_GP_PIN(2, 5), 2608 }; 2609 static const unsigned int intc_ex_irq5_mux[] = { 2610 IRQ5_MARK, 2611 }; 2612 2613 /* - MSIOF0 ----------------------------------------------------------------- */ 2614 static const unsigned int msiof0_clk_pins[] = { 2615 /* SCK */ 2616 RCAR_GP_PIN(5, 17), 2617 }; 2618 static const unsigned int msiof0_clk_mux[] = { 2619 MSIOF0_SCK_MARK, 2620 }; 2621 static const unsigned int msiof0_sync_pins[] = { 2622 /* SYNC */ 2623 RCAR_GP_PIN(5, 18), 2624 }; 2625 static const unsigned int msiof0_sync_mux[] = { 2626 MSIOF0_SYNC_MARK, 2627 }; 2628 static const unsigned int msiof0_ss1_pins[] = { 2629 /* SS1 */ 2630 RCAR_GP_PIN(5, 19), 2631 }; 2632 static const unsigned int msiof0_ss1_mux[] = { 2633 MSIOF0_SS1_MARK, 2634 }; 2635 static const unsigned int msiof0_ss2_pins[] = { 2636 /* SS2 */ 2637 RCAR_GP_PIN(5, 21), 2638 }; 2639 static const unsigned int msiof0_ss2_mux[] = { 2640 MSIOF0_SS2_MARK, 2641 }; 2642 static const unsigned int msiof0_txd_pins[] = { 2643 /* TXD */ 2644 RCAR_GP_PIN(5, 20), 2645 }; 2646 static const unsigned int msiof0_txd_mux[] = { 2647 MSIOF0_TXD_MARK, 2648 }; 2649 static const unsigned int msiof0_rxd_pins[] = { 2650 /* RXD */ 2651 RCAR_GP_PIN(5, 22), 2652 }; 2653 static const unsigned int msiof0_rxd_mux[] = { 2654 MSIOF0_RXD_MARK, 2655 }; 2656 /* - MSIOF1 ----------------------------------------------------------------- */ 2657 static const unsigned int msiof1_clk_a_pins[] = { 2658 /* SCK */ 2659 RCAR_GP_PIN(6, 8), 2660 }; 2661 static const unsigned int msiof1_clk_a_mux[] = { 2662 MSIOF1_SCK_A_MARK, 2663 }; 2664 static const unsigned int msiof1_sync_a_pins[] = { 2665 /* SYNC */ 2666 RCAR_GP_PIN(6, 9), 2667 }; 2668 static const unsigned int msiof1_sync_a_mux[] = { 2669 MSIOF1_SYNC_A_MARK, 2670 }; 2671 static const unsigned int msiof1_ss1_a_pins[] = { 2672 /* SS1 */ 2673 RCAR_GP_PIN(6, 5), 2674 }; 2675 static const unsigned int msiof1_ss1_a_mux[] = { 2676 MSIOF1_SS1_A_MARK, 2677 }; 2678 static const unsigned int msiof1_ss2_a_pins[] = { 2679 /* SS2 */ 2680 RCAR_GP_PIN(6, 6), 2681 }; 2682 static const unsigned int msiof1_ss2_a_mux[] = { 2683 MSIOF1_SS2_A_MARK, 2684 }; 2685 static const unsigned int msiof1_txd_a_pins[] = { 2686 /* TXD */ 2687 RCAR_GP_PIN(6, 7), 2688 }; 2689 static const unsigned int msiof1_txd_a_mux[] = { 2690 MSIOF1_TXD_A_MARK, 2691 }; 2692 static const unsigned int msiof1_rxd_a_pins[] = { 2693 /* RXD */ 2694 RCAR_GP_PIN(6, 10), 2695 }; 2696 static const unsigned int msiof1_rxd_a_mux[] = { 2697 MSIOF1_RXD_A_MARK, 2698 }; 2699 static const unsigned int msiof1_clk_b_pins[] = { 2700 /* SCK */ 2701 RCAR_GP_PIN(5, 9), 2702 }; 2703 static const unsigned int msiof1_clk_b_mux[] = { 2704 MSIOF1_SCK_B_MARK, 2705 }; 2706 static const unsigned int msiof1_sync_b_pins[] = { 2707 /* SYNC */ 2708 RCAR_GP_PIN(5, 3), 2709 }; 2710 static const unsigned int msiof1_sync_b_mux[] = { 2711 MSIOF1_SYNC_B_MARK, 2712 }; 2713 static const unsigned int msiof1_ss1_b_pins[] = { 2714 /* SS1 */ 2715 RCAR_GP_PIN(5, 4), 2716 }; 2717 static const unsigned int msiof1_ss1_b_mux[] = { 2718 MSIOF1_SS1_B_MARK, 2719 }; 2720 static const unsigned int msiof1_ss2_b_pins[] = { 2721 /* SS2 */ 2722 RCAR_GP_PIN(5, 0), 2723 }; 2724 static const unsigned int msiof1_ss2_b_mux[] = { 2725 MSIOF1_SS2_B_MARK, 2726 }; 2727 static const unsigned int msiof1_txd_b_pins[] = { 2728 /* TXD */ 2729 RCAR_GP_PIN(5, 8), 2730 }; 2731 static const unsigned int msiof1_txd_b_mux[] = { 2732 MSIOF1_TXD_B_MARK, 2733 }; 2734 static const unsigned int msiof1_rxd_b_pins[] = { 2735 /* RXD */ 2736 RCAR_GP_PIN(5, 7), 2737 }; 2738 static const unsigned int msiof1_rxd_b_mux[] = { 2739 MSIOF1_RXD_B_MARK, 2740 }; 2741 static const unsigned int msiof1_clk_c_pins[] = { 2742 /* SCK */ 2743 RCAR_GP_PIN(6, 17), 2744 }; 2745 static const unsigned int msiof1_clk_c_mux[] = { 2746 MSIOF1_SCK_C_MARK, 2747 }; 2748 static const unsigned int msiof1_sync_c_pins[] = { 2749 /* SYNC */ 2750 RCAR_GP_PIN(6, 18), 2751 }; 2752 static const unsigned int msiof1_sync_c_mux[] = { 2753 MSIOF1_SYNC_C_MARK, 2754 }; 2755 static const unsigned int msiof1_ss1_c_pins[] = { 2756 /* SS1 */ 2757 RCAR_GP_PIN(6, 21), 2758 }; 2759 static const unsigned int msiof1_ss1_c_mux[] = { 2760 MSIOF1_SS1_C_MARK, 2761 }; 2762 static const unsigned int msiof1_ss2_c_pins[] = { 2763 /* SS2 */ 2764 RCAR_GP_PIN(6, 27), 2765 }; 2766 static const unsigned int msiof1_ss2_c_mux[] = { 2767 MSIOF1_SS2_C_MARK, 2768 }; 2769 static const unsigned int msiof1_txd_c_pins[] = { 2770 /* TXD */ 2771 RCAR_GP_PIN(6, 20), 2772 }; 2773 static const unsigned int msiof1_txd_c_mux[] = { 2774 MSIOF1_TXD_C_MARK, 2775 }; 2776 static const unsigned int msiof1_rxd_c_pins[] = { 2777 /* RXD */ 2778 RCAR_GP_PIN(6, 19), 2779 }; 2780 static const unsigned int msiof1_rxd_c_mux[] = { 2781 MSIOF1_RXD_C_MARK, 2782 }; 2783 static const unsigned int msiof1_clk_d_pins[] = { 2784 /* SCK */ 2785 RCAR_GP_PIN(5, 12), 2786 }; 2787 static const unsigned int msiof1_clk_d_mux[] = { 2788 MSIOF1_SCK_D_MARK, 2789 }; 2790 static const unsigned int msiof1_sync_d_pins[] = { 2791 /* SYNC */ 2792 RCAR_GP_PIN(5, 15), 2793 }; 2794 static const unsigned int msiof1_sync_d_mux[] = { 2795 MSIOF1_SYNC_D_MARK, 2796 }; 2797 static const unsigned int msiof1_ss1_d_pins[] = { 2798 /* SS1 */ 2799 RCAR_GP_PIN(5, 16), 2800 }; 2801 static const unsigned int msiof1_ss1_d_mux[] = { 2802 MSIOF1_SS1_D_MARK, 2803 }; 2804 static const unsigned int msiof1_ss2_d_pins[] = { 2805 /* SS2 */ 2806 RCAR_GP_PIN(5, 21), 2807 }; 2808 static const unsigned int msiof1_ss2_d_mux[] = { 2809 MSIOF1_SS2_D_MARK, 2810 }; 2811 static const unsigned int msiof1_txd_d_pins[] = { 2812 /* TXD */ 2813 RCAR_GP_PIN(5, 14), 2814 }; 2815 static const unsigned int msiof1_txd_d_mux[] = { 2816 MSIOF1_TXD_D_MARK, 2817 }; 2818 static const unsigned int msiof1_rxd_d_pins[] = { 2819 /* RXD */ 2820 RCAR_GP_PIN(5, 13), 2821 }; 2822 static const unsigned int msiof1_rxd_d_mux[] = { 2823 MSIOF1_RXD_D_MARK, 2824 }; 2825 static const unsigned int msiof1_clk_e_pins[] = { 2826 /* SCK */ 2827 RCAR_GP_PIN(3, 0), 2828 }; 2829 static const unsigned int msiof1_clk_e_mux[] = { 2830 MSIOF1_SCK_E_MARK, 2831 }; 2832 static const unsigned int msiof1_sync_e_pins[] = { 2833 /* SYNC */ 2834 RCAR_GP_PIN(3, 1), 2835 }; 2836 static const unsigned int msiof1_sync_e_mux[] = { 2837 MSIOF1_SYNC_E_MARK, 2838 }; 2839 static const unsigned int msiof1_ss1_e_pins[] = { 2840 /* SS1 */ 2841 RCAR_GP_PIN(3, 4), 2842 }; 2843 static const unsigned int msiof1_ss1_e_mux[] = { 2844 MSIOF1_SS1_E_MARK, 2845 }; 2846 static const unsigned int msiof1_ss2_e_pins[] = { 2847 /* SS2 */ 2848 RCAR_GP_PIN(3, 5), 2849 }; 2850 static const unsigned int msiof1_ss2_e_mux[] = { 2851 MSIOF1_SS2_E_MARK, 2852 }; 2853 static const unsigned int msiof1_txd_e_pins[] = { 2854 /* TXD */ 2855 RCAR_GP_PIN(3, 3), 2856 }; 2857 static const unsigned int msiof1_txd_e_mux[] = { 2858 MSIOF1_TXD_E_MARK, 2859 }; 2860 static const unsigned int msiof1_rxd_e_pins[] = { 2861 /* RXD */ 2862 RCAR_GP_PIN(3, 2), 2863 }; 2864 static const unsigned int msiof1_rxd_e_mux[] = { 2865 MSIOF1_RXD_E_MARK, 2866 }; 2867 static const unsigned int msiof1_clk_f_pins[] = { 2868 /* SCK */ 2869 RCAR_GP_PIN(5, 23), 2870 }; 2871 static const unsigned int msiof1_clk_f_mux[] = { 2872 MSIOF1_SCK_F_MARK, 2873 }; 2874 static const unsigned int msiof1_sync_f_pins[] = { 2875 /* SYNC */ 2876 RCAR_GP_PIN(5, 24), 2877 }; 2878 static const unsigned int msiof1_sync_f_mux[] = { 2879 MSIOF1_SYNC_F_MARK, 2880 }; 2881 static const unsigned int msiof1_ss1_f_pins[] = { 2882 /* SS1 */ 2883 RCAR_GP_PIN(6, 1), 2884 }; 2885 static const unsigned int msiof1_ss1_f_mux[] = { 2886 MSIOF1_SS1_F_MARK, 2887 }; 2888 static const unsigned int msiof1_ss2_f_pins[] = { 2889 /* SS2 */ 2890 RCAR_GP_PIN(6, 2), 2891 }; 2892 static const unsigned int msiof1_ss2_f_mux[] = { 2893 MSIOF1_SS2_F_MARK, 2894 }; 2895 static const unsigned int msiof1_txd_f_pins[] = { 2896 /* TXD */ 2897 RCAR_GP_PIN(6, 0), 2898 }; 2899 static const unsigned int msiof1_txd_f_mux[] = { 2900 MSIOF1_TXD_F_MARK, 2901 }; 2902 static const unsigned int msiof1_rxd_f_pins[] = { 2903 /* RXD */ 2904 RCAR_GP_PIN(5, 25), 2905 }; 2906 static const unsigned int msiof1_rxd_f_mux[] = { 2907 MSIOF1_RXD_F_MARK, 2908 }; 2909 static const unsigned int msiof1_clk_g_pins[] = { 2910 /* SCK */ 2911 RCAR_GP_PIN(3, 6), 2912 }; 2913 static const unsigned int msiof1_clk_g_mux[] = { 2914 MSIOF1_SCK_G_MARK, 2915 }; 2916 static const unsigned int msiof1_sync_g_pins[] = { 2917 /* SYNC */ 2918 RCAR_GP_PIN(3, 7), 2919 }; 2920 static const unsigned int msiof1_sync_g_mux[] = { 2921 MSIOF1_SYNC_G_MARK, 2922 }; 2923 static const unsigned int msiof1_ss1_g_pins[] = { 2924 /* SS1 */ 2925 RCAR_GP_PIN(3, 10), 2926 }; 2927 static const unsigned int msiof1_ss1_g_mux[] = { 2928 MSIOF1_SS1_G_MARK, 2929 }; 2930 static const unsigned int msiof1_ss2_g_pins[] = { 2931 /* SS2 */ 2932 RCAR_GP_PIN(3, 11), 2933 }; 2934 static const unsigned int msiof1_ss2_g_mux[] = { 2935 MSIOF1_SS2_G_MARK, 2936 }; 2937 static const unsigned int msiof1_txd_g_pins[] = { 2938 /* TXD */ 2939 RCAR_GP_PIN(3, 9), 2940 }; 2941 static const unsigned int msiof1_txd_g_mux[] = { 2942 MSIOF1_TXD_G_MARK, 2943 }; 2944 static const unsigned int msiof1_rxd_g_pins[] = { 2945 /* RXD */ 2946 RCAR_GP_PIN(3, 8), 2947 }; 2948 static const unsigned int msiof1_rxd_g_mux[] = { 2949 MSIOF1_RXD_G_MARK, 2950 }; 2951 /* - MSIOF2 ----------------------------------------------------------------- */ 2952 static const unsigned int msiof2_clk_a_pins[] = { 2953 /* SCK */ 2954 RCAR_GP_PIN(1, 9), 2955 }; 2956 static const unsigned int msiof2_clk_a_mux[] = { 2957 MSIOF2_SCK_A_MARK, 2958 }; 2959 static const unsigned int msiof2_sync_a_pins[] = { 2960 /* SYNC */ 2961 RCAR_GP_PIN(1, 8), 2962 }; 2963 static const unsigned int msiof2_sync_a_mux[] = { 2964 MSIOF2_SYNC_A_MARK, 2965 }; 2966 static const unsigned int msiof2_ss1_a_pins[] = { 2967 /* SS1 */ 2968 RCAR_GP_PIN(1, 6), 2969 }; 2970 static const unsigned int msiof2_ss1_a_mux[] = { 2971 MSIOF2_SS1_A_MARK, 2972 }; 2973 static const unsigned int msiof2_ss2_a_pins[] = { 2974 /* SS2 */ 2975 RCAR_GP_PIN(1, 7), 2976 }; 2977 static const unsigned int msiof2_ss2_a_mux[] = { 2978 MSIOF2_SS2_A_MARK, 2979 }; 2980 static const unsigned int msiof2_txd_a_pins[] = { 2981 /* TXD */ 2982 RCAR_GP_PIN(1, 11), 2983 }; 2984 static const unsigned int msiof2_txd_a_mux[] = { 2985 MSIOF2_TXD_A_MARK, 2986 }; 2987 static const unsigned int msiof2_rxd_a_pins[] = { 2988 /* RXD */ 2989 RCAR_GP_PIN(1, 10), 2990 }; 2991 static const unsigned int msiof2_rxd_a_mux[] = { 2992 MSIOF2_RXD_A_MARK, 2993 }; 2994 static const unsigned int msiof2_clk_b_pins[] = { 2995 /* SCK */ 2996 RCAR_GP_PIN(0, 4), 2997 }; 2998 static const unsigned int msiof2_clk_b_mux[] = { 2999 MSIOF2_SCK_B_MARK, 3000 }; 3001 static const unsigned int msiof2_sync_b_pins[] = { 3002 /* SYNC */ 3003 RCAR_GP_PIN(0, 5), 3004 }; 3005 static const unsigned int msiof2_sync_b_mux[] = { 3006 MSIOF2_SYNC_B_MARK, 3007 }; 3008 static const unsigned int msiof2_ss1_b_pins[] = { 3009 /* SS1 */ 3010 RCAR_GP_PIN(0, 0), 3011 }; 3012 static const unsigned int msiof2_ss1_b_mux[] = { 3013 MSIOF2_SS1_B_MARK, 3014 }; 3015 static const unsigned int msiof2_ss2_b_pins[] = { 3016 /* SS2 */ 3017 RCAR_GP_PIN(0, 1), 3018 }; 3019 static const unsigned int msiof2_ss2_b_mux[] = { 3020 MSIOF2_SS2_B_MARK, 3021 }; 3022 static const unsigned int msiof2_txd_b_pins[] = { 3023 /* TXD */ 3024 RCAR_GP_PIN(0, 7), 3025 }; 3026 static const unsigned int msiof2_txd_b_mux[] = { 3027 MSIOF2_TXD_B_MARK, 3028 }; 3029 static const unsigned int msiof2_rxd_b_pins[] = { 3030 /* RXD */ 3031 RCAR_GP_PIN(0, 6), 3032 }; 3033 static const unsigned int msiof2_rxd_b_mux[] = { 3034 MSIOF2_RXD_B_MARK, 3035 }; 3036 static const unsigned int msiof2_clk_c_pins[] = { 3037 /* SCK */ 3038 RCAR_GP_PIN(2, 12), 3039 }; 3040 static const unsigned int msiof2_clk_c_mux[] = { 3041 MSIOF2_SCK_C_MARK, 3042 }; 3043 static const unsigned int msiof2_sync_c_pins[] = { 3044 /* SYNC */ 3045 RCAR_GP_PIN(2, 11), 3046 }; 3047 static const unsigned int msiof2_sync_c_mux[] = { 3048 MSIOF2_SYNC_C_MARK, 3049 }; 3050 static const unsigned int msiof2_ss1_c_pins[] = { 3051 /* SS1 */ 3052 RCAR_GP_PIN(2, 10), 3053 }; 3054 static const unsigned int msiof2_ss1_c_mux[] = { 3055 MSIOF2_SS1_C_MARK, 3056 }; 3057 static const unsigned int msiof2_ss2_c_pins[] = { 3058 /* SS2 */ 3059 RCAR_GP_PIN(2, 9), 3060 }; 3061 static const unsigned int msiof2_ss2_c_mux[] = { 3062 MSIOF2_SS2_C_MARK, 3063 }; 3064 static const unsigned int msiof2_txd_c_pins[] = { 3065 /* TXD */ 3066 RCAR_GP_PIN(2, 14), 3067 }; 3068 static const unsigned int msiof2_txd_c_mux[] = { 3069 MSIOF2_TXD_C_MARK, 3070 }; 3071 static const unsigned int msiof2_rxd_c_pins[] = { 3072 /* RXD */ 3073 RCAR_GP_PIN(2, 13), 3074 }; 3075 static const unsigned int msiof2_rxd_c_mux[] = { 3076 MSIOF2_RXD_C_MARK, 3077 }; 3078 static const unsigned int msiof2_clk_d_pins[] = { 3079 /* SCK */ 3080 RCAR_GP_PIN(0, 8), 3081 }; 3082 static const unsigned int msiof2_clk_d_mux[] = { 3083 MSIOF2_SCK_D_MARK, 3084 }; 3085 static const unsigned int msiof2_sync_d_pins[] = { 3086 /* SYNC */ 3087 RCAR_GP_PIN(0, 9), 3088 }; 3089 static const unsigned int msiof2_sync_d_mux[] = { 3090 MSIOF2_SYNC_D_MARK, 3091 }; 3092 static const unsigned int msiof2_ss1_d_pins[] = { 3093 /* SS1 */ 3094 RCAR_GP_PIN(0, 12), 3095 }; 3096 static const unsigned int msiof2_ss1_d_mux[] = { 3097 MSIOF2_SS1_D_MARK, 3098 }; 3099 static const unsigned int msiof2_ss2_d_pins[] = { 3100 /* SS2 */ 3101 RCAR_GP_PIN(0, 13), 3102 }; 3103 static const unsigned int msiof2_ss2_d_mux[] = { 3104 MSIOF2_SS2_D_MARK, 3105 }; 3106 static const unsigned int msiof2_txd_d_pins[] = { 3107 /* TXD */ 3108 RCAR_GP_PIN(0, 11), 3109 }; 3110 static const unsigned int msiof2_txd_d_mux[] = { 3111 MSIOF2_TXD_D_MARK, 3112 }; 3113 static const unsigned int msiof2_rxd_d_pins[] = { 3114 /* RXD */ 3115 RCAR_GP_PIN(0, 10), 3116 }; 3117 static const unsigned int msiof2_rxd_d_mux[] = { 3118 MSIOF2_RXD_D_MARK, 3119 }; 3120 /* - MSIOF3 ----------------------------------------------------------------- */ 3121 static const unsigned int msiof3_clk_a_pins[] = { 3122 /* SCK */ 3123 RCAR_GP_PIN(0, 0), 3124 }; 3125 static const unsigned int msiof3_clk_a_mux[] = { 3126 MSIOF3_SCK_A_MARK, 3127 }; 3128 static const unsigned int msiof3_sync_a_pins[] = { 3129 /* SYNC */ 3130 RCAR_GP_PIN(0, 1), 3131 }; 3132 static const unsigned int msiof3_sync_a_mux[] = { 3133 MSIOF3_SYNC_A_MARK, 3134 }; 3135 static const unsigned int msiof3_ss1_a_pins[] = { 3136 /* SS1 */ 3137 RCAR_GP_PIN(0, 14), 3138 }; 3139 static const unsigned int msiof3_ss1_a_mux[] = { 3140 MSIOF3_SS1_A_MARK, 3141 }; 3142 static const unsigned int msiof3_ss2_a_pins[] = { 3143 /* SS2 */ 3144 RCAR_GP_PIN(0, 15), 3145 }; 3146 static const unsigned int msiof3_ss2_a_mux[] = { 3147 MSIOF3_SS2_A_MARK, 3148 }; 3149 static const unsigned int msiof3_txd_a_pins[] = { 3150 /* TXD */ 3151 RCAR_GP_PIN(0, 3), 3152 }; 3153 static const unsigned int msiof3_txd_a_mux[] = { 3154 MSIOF3_TXD_A_MARK, 3155 }; 3156 static const unsigned int msiof3_rxd_a_pins[] = { 3157 /* RXD */ 3158 RCAR_GP_PIN(0, 2), 3159 }; 3160 static const unsigned int msiof3_rxd_a_mux[] = { 3161 MSIOF3_RXD_A_MARK, 3162 }; 3163 static const unsigned int msiof3_clk_b_pins[] = { 3164 /* SCK */ 3165 RCAR_GP_PIN(1, 2), 3166 }; 3167 static const unsigned int msiof3_clk_b_mux[] = { 3168 MSIOF3_SCK_B_MARK, 3169 }; 3170 static const unsigned int msiof3_sync_b_pins[] = { 3171 /* SYNC */ 3172 RCAR_GP_PIN(1, 0), 3173 }; 3174 static const unsigned int msiof3_sync_b_mux[] = { 3175 MSIOF3_SYNC_B_MARK, 3176 }; 3177 static const unsigned int msiof3_ss1_b_pins[] = { 3178 /* SS1 */ 3179 RCAR_GP_PIN(1, 4), 3180 }; 3181 static const unsigned int msiof3_ss1_b_mux[] = { 3182 MSIOF3_SS1_B_MARK, 3183 }; 3184 static const unsigned int msiof3_ss2_b_pins[] = { 3185 /* SS2 */ 3186 RCAR_GP_PIN(1, 5), 3187 }; 3188 static const unsigned int msiof3_ss2_b_mux[] = { 3189 MSIOF3_SS2_B_MARK, 3190 }; 3191 static const unsigned int msiof3_txd_b_pins[] = { 3192 /* TXD */ 3193 RCAR_GP_PIN(1, 1), 3194 }; 3195 static const unsigned int msiof3_txd_b_mux[] = { 3196 MSIOF3_TXD_B_MARK, 3197 }; 3198 static const unsigned int msiof3_rxd_b_pins[] = { 3199 /* RXD */ 3200 RCAR_GP_PIN(1, 3), 3201 }; 3202 static const unsigned int msiof3_rxd_b_mux[] = { 3203 MSIOF3_RXD_B_MARK, 3204 }; 3205 static const unsigned int msiof3_clk_c_pins[] = { 3206 /* SCK */ 3207 RCAR_GP_PIN(1, 12), 3208 }; 3209 static const unsigned int msiof3_clk_c_mux[] = { 3210 MSIOF3_SCK_C_MARK, 3211 }; 3212 static const unsigned int msiof3_sync_c_pins[] = { 3213 /* SYNC */ 3214 RCAR_GP_PIN(1, 13), 3215 }; 3216 static const unsigned int msiof3_sync_c_mux[] = { 3217 MSIOF3_SYNC_C_MARK, 3218 }; 3219 static const unsigned int msiof3_txd_c_pins[] = { 3220 /* TXD */ 3221 RCAR_GP_PIN(1, 15), 3222 }; 3223 static const unsigned int msiof3_txd_c_mux[] = { 3224 MSIOF3_TXD_C_MARK, 3225 }; 3226 static const unsigned int msiof3_rxd_c_pins[] = { 3227 /* RXD */ 3228 RCAR_GP_PIN(1, 14), 3229 }; 3230 static const unsigned int msiof3_rxd_c_mux[] = { 3231 MSIOF3_RXD_C_MARK, 3232 }; 3233 static const unsigned int msiof3_clk_d_pins[] = { 3234 /* SCK */ 3235 RCAR_GP_PIN(1, 22), 3236 }; 3237 static const unsigned int msiof3_clk_d_mux[] = { 3238 MSIOF3_SCK_D_MARK, 3239 }; 3240 static const unsigned int msiof3_sync_d_pins[] = { 3241 /* SYNC */ 3242 RCAR_GP_PIN(1, 23), 3243 }; 3244 static const unsigned int msiof3_sync_d_mux[] = { 3245 MSIOF3_SYNC_D_MARK, 3246 }; 3247 static const unsigned int msiof3_ss1_d_pins[] = { 3248 /* SS1 */ 3249 RCAR_GP_PIN(1, 26), 3250 }; 3251 static const unsigned int msiof3_ss1_d_mux[] = { 3252 MSIOF3_SS1_D_MARK, 3253 }; 3254 static const unsigned int msiof3_txd_d_pins[] = { 3255 /* TXD */ 3256 RCAR_GP_PIN(1, 25), 3257 }; 3258 static const unsigned int msiof3_txd_d_mux[] = { 3259 MSIOF3_TXD_D_MARK, 3260 }; 3261 static const unsigned int msiof3_rxd_d_pins[] = { 3262 /* RXD */ 3263 RCAR_GP_PIN(1, 24), 3264 }; 3265 static const unsigned int msiof3_rxd_d_mux[] = { 3266 MSIOF3_RXD_D_MARK, 3267 }; 3268 static const unsigned int msiof3_clk_e_pins[] = { 3269 /* SCK */ 3270 RCAR_GP_PIN(2, 3), 3271 }; 3272 static const unsigned int msiof3_clk_e_mux[] = { 3273 MSIOF3_SCK_E_MARK, 3274 }; 3275 static const unsigned int msiof3_sync_e_pins[] = { 3276 /* SYNC */ 3277 RCAR_GP_PIN(2, 2), 3278 }; 3279 static const unsigned int msiof3_sync_e_mux[] = { 3280 MSIOF3_SYNC_E_MARK, 3281 }; 3282 static const unsigned int msiof3_ss1_e_pins[] = { 3283 /* SS1 */ 3284 RCAR_GP_PIN(2, 1), 3285 }; 3286 static const unsigned int msiof3_ss1_e_mux[] = { 3287 MSIOF3_SS1_E_MARK, 3288 }; 3289 static const unsigned int msiof3_ss2_e_pins[] = { 3290 /* SS2 */ 3291 RCAR_GP_PIN(2, 0), 3292 }; 3293 static const unsigned int msiof3_ss2_e_mux[] = { 3294 MSIOF3_SS2_E_MARK, 3295 }; 3296 static const unsigned int msiof3_txd_e_pins[] = { 3297 /* TXD */ 3298 RCAR_GP_PIN(2, 5), 3299 }; 3300 static const unsigned int msiof3_txd_e_mux[] = { 3301 MSIOF3_TXD_E_MARK, 3302 }; 3303 static const unsigned int msiof3_rxd_e_pins[] = { 3304 /* RXD */ 3305 RCAR_GP_PIN(2, 4), 3306 }; 3307 static const unsigned int msiof3_rxd_e_mux[] = { 3308 MSIOF3_RXD_E_MARK, 3309 }; 3310 3311 /* - PWM0 --------------------------------------------------------------------*/ 3312 static const unsigned int pwm0_pins[] = { 3313 /* PWM */ 3314 RCAR_GP_PIN(2, 6), 3315 }; 3316 static const unsigned int pwm0_mux[] = { 3317 PWM0_MARK, 3318 }; 3319 /* - PWM1 --------------------------------------------------------------------*/ 3320 static const unsigned int pwm1_a_pins[] = { 3321 /* PWM */ 3322 RCAR_GP_PIN(2, 7), 3323 }; 3324 static const unsigned int pwm1_a_mux[] = { 3325 PWM1_A_MARK, 3326 }; 3327 static const unsigned int pwm1_b_pins[] = { 3328 /* PWM */ 3329 RCAR_GP_PIN(1, 8), 3330 }; 3331 static const unsigned int pwm1_b_mux[] = { 3332 PWM1_B_MARK, 3333 }; 3334 /* - PWM2 --------------------------------------------------------------------*/ 3335 static const unsigned int pwm2_a_pins[] = { 3336 /* PWM */ 3337 RCAR_GP_PIN(2, 8), 3338 }; 3339 static const unsigned int pwm2_a_mux[] = { 3340 PWM2_A_MARK, 3341 }; 3342 static const unsigned int pwm2_b_pins[] = { 3343 /* PWM */ 3344 RCAR_GP_PIN(1, 11), 3345 }; 3346 static const unsigned int pwm2_b_mux[] = { 3347 PWM2_B_MARK, 3348 }; 3349 /* - PWM3 --------------------------------------------------------------------*/ 3350 static const unsigned int pwm3_a_pins[] = { 3351 /* PWM */ 3352 RCAR_GP_PIN(1, 0), 3353 }; 3354 static const unsigned int pwm3_a_mux[] = { 3355 PWM3_A_MARK, 3356 }; 3357 static const unsigned int pwm3_b_pins[] = { 3358 /* PWM */ 3359 RCAR_GP_PIN(2, 2), 3360 }; 3361 static const unsigned int pwm3_b_mux[] = { 3362 PWM3_B_MARK, 3363 }; 3364 /* - PWM4 --------------------------------------------------------------------*/ 3365 static const unsigned int pwm4_a_pins[] = { 3366 /* PWM */ 3367 RCAR_GP_PIN(1, 1), 3368 }; 3369 static const unsigned int pwm4_a_mux[] = { 3370 PWM4_A_MARK, 3371 }; 3372 static const unsigned int pwm4_b_pins[] = { 3373 /* PWM */ 3374 RCAR_GP_PIN(2, 3), 3375 }; 3376 static const unsigned int pwm4_b_mux[] = { 3377 PWM4_B_MARK, 3378 }; 3379 /* - PWM5 --------------------------------------------------------------------*/ 3380 static const unsigned int pwm5_a_pins[] = { 3381 /* PWM */ 3382 RCAR_GP_PIN(1, 2), 3383 }; 3384 static const unsigned int pwm5_a_mux[] = { 3385 PWM5_A_MARK, 3386 }; 3387 static const unsigned int pwm5_b_pins[] = { 3388 /* PWM */ 3389 RCAR_GP_PIN(2, 4), 3390 }; 3391 static const unsigned int pwm5_b_mux[] = { 3392 PWM5_B_MARK, 3393 }; 3394 /* - PWM6 --------------------------------------------------------------------*/ 3395 static const unsigned int pwm6_a_pins[] = { 3396 /* PWM */ 3397 RCAR_GP_PIN(1, 3), 3398 }; 3399 static const unsigned int pwm6_a_mux[] = { 3400 PWM6_A_MARK, 3401 }; 3402 static const unsigned int pwm6_b_pins[] = { 3403 /* PWM */ 3404 RCAR_GP_PIN(2, 5), 3405 }; 3406 static const unsigned int pwm6_b_mux[] = { 3407 PWM6_B_MARK, 3408 }; 3409 3410 /* - QSPI0 ------------------------------------------------------------------ */ 3411 static const unsigned int qspi0_ctrl_pins[] = { 3412 /* QSPI0_SPCLK, QSPI0_SSL */ 3413 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, 3414 }; 3415 static const unsigned int qspi0_ctrl_mux[] = { 3416 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 3417 }; 3418 static const unsigned int qspi0_data2_pins[] = { 3419 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ 3420 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, 3421 }; 3422 static const unsigned int qspi0_data2_mux[] = { 3423 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 3424 }; 3425 static const unsigned int qspi0_data4_pins[] = { 3426 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ 3427 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, 3428 /* QSPI0_IO2, QSPI0_IO3 */ 3429 PIN_QSPI0_IO2, PIN_QSPI0_IO3, 3430 }; 3431 static const unsigned int qspi0_data4_mux[] = { 3432 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 3433 QSPI0_IO2_MARK, QSPI0_IO3_MARK, 3434 }; 3435 /* - QSPI1 ------------------------------------------------------------------ */ 3436 static const unsigned int qspi1_ctrl_pins[] = { 3437 /* QSPI1_SPCLK, QSPI1_SSL */ 3438 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, 3439 }; 3440 static const unsigned int qspi1_ctrl_mux[] = { 3441 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 3442 }; 3443 static const unsigned int qspi1_data2_pins[] = { 3444 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ 3445 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, 3446 }; 3447 static const unsigned int qspi1_data2_mux[] = { 3448 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 3449 }; 3450 static const unsigned int qspi1_data4_pins[] = { 3451 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ 3452 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, 3453 /* QSPI1_IO2, QSPI1_IO3 */ 3454 PIN_QSPI1_IO2, PIN_QSPI1_IO3, 3455 }; 3456 static const unsigned int qspi1_data4_mux[] = { 3457 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 3458 QSPI1_IO2_MARK, QSPI1_IO3_MARK, 3459 }; 3460 3461 /* - SATA --------------------------------------------------------------------*/ 3462 static const unsigned int sata0_devslp_a_pins[] = { 3463 /* DEVSLP */ 3464 RCAR_GP_PIN(6, 16), 3465 }; 3466 3467 static const unsigned int sata0_devslp_a_mux[] = { 3468 SATA_DEVSLP_A_MARK, 3469 }; 3470 3471 static const unsigned int sata0_devslp_b_pins[] = { 3472 /* DEVSLP */ 3473 RCAR_GP_PIN(4, 6), 3474 }; 3475 3476 static const unsigned int sata0_devslp_b_mux[] = { 3477 SATA_DEVSLP_B_MARK, 3478 }; 3479 3480 /* - SCIF0 ------------------------------------------------------------------ */ 3481 static const unsigned int scif0_data_pins[] = { 3482 /* RX, TX */ 3483 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), 3484 }; 3485 static const unsigned int scif0_data_mux[] = { 3486 RX0_MARK, TX0_MARK, 3487 }; 3488 static const unsigned int scif0_clk_pins[] = { 3489 /* SCK */ 3490 RCAR_GP_PIN(5, 0), 3491 }; 3492 static const unsigned int scif0_clk_mux[] = { 3493 SCK0_MARK, 3494 }; 3495 static const unsigned int scif0_ctrl_pins[] = { 3496 /* RTS, CTS */ 3497 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3498 }; 3499 static const unsigned int scif0_ctrl_mux[] = { 3500 RTS0_N_MARK, CTS0_N_MARK, 3501 }; 3502 /* - SCIF1 ------------------------------------------------------------------ */ 3503 static const unsigned int scif1_data_a_pins[] = { 3504 /* RX, TX */ 3505 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), 3506 }; 3507 static const unsigned int scif1_data_a_mux[] = { 3508 RX1_A_MARK, TX1_A_MARK, 3509 }; 3510 static const unsigned int scif1_clk_pins[] = { 3511 /* SCK */ 3512 RCAR_GP_PIN(6, 21), 3513 }; 3514 static const unsigned int scif1_clk_mux[] = { 3515 SCK1_MARK, 3516 }; 3517 static const unsigned int scif1_ctrl_pins[] = { 3518 /* RTS, CTS */ 3519 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3520 }; 3521 static const unsigned int scif1_ctrl_mux[] = { 3522 RTS1_N_MARK, CTS1_N_MARK, 3523 }; 3524 static const unsigned int scif1_data_b_pins[] = { 3525 /* RX, TX */ 3526 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), 3527 }; 3528 static const unsigned int scif1_data_b_mux[] = { 3529 RX1_B_MARK, TX1_B_MARK, 3530 }; 3531 /* - SCIF2 ------------------------------------------------------------------ */ 3532 static const unsigned int scif2_data_a_pins[] = { 3533 /* RX, TX */ 3534 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 3535 }; 3536 static const unsigned int scif2_data_a_mux[] = { 3537 RX2_A_MARK, TX2_A_MARK, 3538 }; 3539 static const unsigned int scif2_clk_pins[] = { 3540 /* SCK */ 3541 RCAR_GP_PIN(5, 9), 3542 }; 3543 static const unsigned int scif2_clk_mux[] = { 3544 SCK2_MARK, 3545 }; 3546 static const unsigned int scif2_data_b_pins[] = { 3547 /* RX, TX */ 3548 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 3549 }; 3550 static const unsigned int scif2_data_b_mux[] = { 3551 RX2_B_MARK, TX2_B_MARK, 3552 }; 3553 /* - SCIF3 ------------------------------------------------------------------ */ 3554 static const unsigned int scif3_data_a_pins[] = { 3555 /* RX, TX */ 3556 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), 3557 }; 3558 static const unsigned int scif3_data_a_mux[] = { 3559 RX3_A_MARK, TX3_A_MARK, 3560 }; 3561 static const unsigned int scif3_clk_pins[] = { 3562 /* SCK */ 3563 RCAR_GP_PIN(1, 22), 3564 }; 3565 static const unsigned int scif3_clk_mux[] = { 3566 SCK3_MARK, 3567 }; 3568 static const unsigned int scif3_ctrl_pins[] = { 3569 /* RTS, CTS */ 3570 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3571 }; 3572 static const unsigned int scif3_ctrl_mux[] = { 3573 RTS3_N_MARK, CTS3_N_MARK, 3574 }; 3575 static const unsigned int scif3_data_b_pins[] = { 3576 /* RX, TX */ 3577 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 3578 }; 3579 static const unsigned int scif3_data_b_mux[] = { 3580 RX3_B_MARK, TX3_B_MARK, 3581 }; 3582 /* - SCIF4 ------------------------------------------------------------------ */ 3583 static const unsigned int scif4_data_a_pins[] = { 3584 /* RX, TX */ 3585 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3586 }; 3587 static const unsigned int scif4_data_a_mux[] = { 3588 RX4_A_MARK, TX4_A_MARK, 3589 }; 3590 static const unsigned int scif4_clk_a_pins[] = { 3591 /* SCK */ 3592 RCAR_GP_PIN(2, 10), 3593 }; 3594 static const unsigned int scif4_clk_a_mux[] = { 3595 SCK4_A_MARK, 3596 }; 3597 static const unsigned int scif4_ctrl_a_pins[] = { 3598 /* RTS, CTS */ 3599 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3600 }; 3601 static const unsigned int scif4_ctrl_a_mux[] = { 3602 RTS4_N_A_MARK, CTS4_N_A_MARK, 3603 }; 3604 static const unsigned int scif4_data_b_pins[] = { 3605 /* RX, TX */ 3606 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 3607 }; 3608 static const unsigned int scif4_data_b_mux[] = { 3609 RX4_B_MARK, TX4_B_MARK, 3610 }; 3611 static const unsigned int scif4_clk_b_pins[] = { 3612 /* SCK */ 3613 RCAR_GP_PIN(1, 5), 3614 }; 3615 static const unsigned int scif4_clk_b_mux[] = { 3616 SCK4_B_MARK, 3617 }; 3618 static const unsigned int scif4_ctrl_b_pins[] = { 3619 /* RTS, CTS */ 3620 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3621 }; 3622 static const unsigned int scif4_ctrl_b_mux[] = { 3623 RTS4_N_B_MARK, CTS4_N_B_MARK, 3624 }; 3625 static const unsigned int scif4_data_c_pins[] = { 3626 /* RX, TX */ 3627 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 3628 }; 3629 static const unsigned int scif4_data_c_mux[] = { 3630 RX4_C_MARK, TX4_C_MARK, 3631 }; 3632 static const unsigned int scif4_clk_c_pins[] = { 3633 /* SCK */ 3634 RCAR_GP_PIN(0, 8), 3635 }; 3636 static const unsigned int scif4_clk_c_mux[] = { 3637 SCK4_C_MARK, 3638 }; 3639 static const unsigned int scif4_ctrl_c_pins[] = { 3640 /* RTS, CTS */ 3641 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3642 }; 3643 static const unsigned int scif4_ctrl_c_mux[] = { 3644 RTS4_N_C_MARK, CTS4_N_C_MARK, 3645 }; 3646 /* - SCIF5 ------------------------------------------------------------------ */ 3647 static const unsigned int scif5_data_a_pins[] = { 3648 /* RX, TX */ 3649 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 3650 }; 3651 static const unsigned int scif5_data_a_mux[] = { 3652 RX5_A_MARK, TX5_A_MARK, 3653 }; 3654 static const unsigned int scif5_clk_a_pins[] = { 3655 /* SCK */ 3656 RCAR_GP_PIN(6, 21), 3657 }; 3658 static const unsigned int scif5_clk_a_mux[] = { 3659 SCK5_A_MARK, 3660 }; 3661 static const unsigned int scif5_data_b_pins[] = { 3662 /* RX, TX */ 3663 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), 3664 }; 3665 static const unsigned int scif5_data_b_mux[] = { 3666 RX5_B_MARK, TX5_B_MARK, 3667 }; 3668 static const unsigned int scif5_clk_b_pins[] = { 3669 /* SCK */ 3670 RCAR_GP_PIN(5, 0), 3671 }; 3672 static const unsigned int scif5_clk_b_mux[] = { 3673 SCK5_B_MARK, 3674 }; 3675 /* - SCIF Clock ------------------------------------------------------------- */ 3676 static const unsigned int scif_clk_a_pins[] = { 3677 /* SCIF_CLK */ 3678 RCAR_GP_PIN(6, 23), 3679 }; 3680 static const unsigned int scif_clk_a_mux[] = { 3681 SCIF_CLK_A_MARK, 3682 }; 3683 static const unsigned int scif_clk_b_pins[] = { 3684 /* SCIF_CLK */ 3685 RCAR_GP_PIN(5, 9), 3686 }; 3687 static const unsigned int scif_clk_b_mux[] = { 3688 SCIF_CLK_B_MARK, 3689 }; 3690 3691 /* - SDHI0 ------------------------------------------------------------------ */ 3692 static const unsigned int sdhi0_data1_pins[] = { 3693 /* D0 */ 3694 RCAR_GP_PIN(3, 2), 3695 }; 3696 3697 static const unsigned int sdhi0_data1_mux[] = { 3698 SD0_DAT0_MARK, 3699 }; 3700 3701 static const unsigned int sdhi0_data4_pins[] = { 3702 /* D[0:3] */ 3703 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), 3704 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 3705 }; 3706 3707 static const unsigned int sdhi0_data4_mux[] = { 3708 SD0_DAT0_MARK, SD0_DAT1_MARK, 3709 SD0_DAT2_MARK, SD0_DAT3_MARK, 3710 }; 3711 3712 static const unsigned int sdhi0_ctrl_pins[] = { 3713 /* CLK, CMD */ 3714 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 3715 }; 3716 3717 static const unsigned int sdhi0_ctrl_mux[] = { 3718 SD0_CLK_MARK, SD0_CMD_MARK, 3719 }; 3720 3721 static const unsigned int sdhi0_cd_pins[] = { 3722 /* CD */ 3723 RCAR_GP_PIN(3, 12), 3724 }; 3725 3726 static const unsigned int sdhi0_cd_mux[] = { 3727 SD0_CD_MARK, 3728 }; 3729 3730 static const unsigned int sdhi0_wp_pins[] = { 3731 /* WP */ 3732 RCAR_GP_PIN(3, 13), 3733 }; 3734 3735 static const unsigned int sdhi0_wp_mux[] = { 3736 SD0_WP_MARK, 3737 }; 3738 3739 /* - SDHI1 ------------------------------------------------------------------ */ 3740 static const unsigned int sdhi1_data1_pins[] = { 3741 /* D0 */ 3742 RCAR_GP_PIN(3, 8), 3743 }; 3744 3745 static const unsigned int sdhi1_data1_mux[] = { 3746 SD1_DAT0_MARK, 3747 }; 3748 3749 static const unsigned int sdhi1_data4_pins[] = { 3750 /* D[0:3] */ 3751 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3752 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3753 }; 3754 3755 static const unsigned int sdhi1_data4_mux[] = { 3756 SD1_DAT0_MARK, SD1_DAT1_MARK, 3757 SD1_DAT2_MARK, SD1_DAT3_MARK, 3758 }; 3759 3760 static const unsigned int sdhi1_ctrl_pins[] = { 3761 /* CLK, CMD */ 3762 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 3763 }; 3764 3765 static const unsigned int sdhi1_ctrl_mux[] = { 3766 SD1_CLK_MARK, SD1_CMD_MARK, 3767 }; 3768 3769 static const unsigned int sdhi1_cd_pins[] = { 3770 /* CD */ 3771 RCAR_GP_PIN(3, 14), 3772 }; 3773 3774 static const unsigned int sdhi1_cd_mux[] = { 3775 SD1_CD_MARK, 3776 }; 3777 3778 static const unsigned int sdhi1_wp_pins[] = { 3779 /* WP */ 3780 RCAR_GP_PIN(3, 15), 3781 }; 3782 3783 static const unsigned int sdhi1_wp_mux[] = { 3784 SD1_WP_MARK, 3785 }; 3786 3787 /* - SDHI2 ------------------------------------------------------------------ */ 3788 static const unsigned int sdhi2_data1_pins[] = { 3789 /* D0 */ 3790 RCAR_GP_PIN(4, 2), 3791 }; 3792 3793 static const unsigned int sdhi2_data1_mux[] = { 3794 SD2_DAT0_MARK, 3795 }; 3796 3797 static const unsigned int sdhi2_data4_pins[] = { 3798 /* D[0:3] */ 3799 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3800 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3801 }; 3802 3803 static const unsigned int sdhi2_data4_mux[] = { 3804 SD2_DAT0_MARK, SD2_DAT1_MARK, 3805 SD2_DAT2_MARK, SD2_DAT3_MARK, 3806 }; 3807 3808 static const unsigned int sdhi2_data8_pins[] = { 3809 /* D[0:7] */ 3810 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 3811 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 3812 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 3813 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 3814 }; 3815 3816 static const unsigned int sdhi2_data8_mux[] = { 3817 SD2_DAT0_MARK, SD2_DAT1_MARK, 3818 SD2_DAT2_MARK, SD2_DAT3_MARK, 3819 SD2_DAT4_MARK, SD2_DAT5_MARK, 3820 SD2_DAT6_MARK, SD2_DAT7_MARK, 3821 }; 3822 3823 static const unsigned int sdhi2_ctrl_pins[] = { 3824 /* CLK, CMD */ 3825 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 3826 }; 3827 3828 static const unsigned int sdhi2_ctrl_mux[] = { 3829 SD2_CLK_MARK, SD2_CMD_MARK, 3830 }; 3831 3832 static const unsigned int sdhi2_cd_a_pins[] = { 3833 /* CD */ 3834 RCAR_GP_PIN(4, 13), 3835 }; 3836 3837 static const unsigned int sdhi2_cd_a_mux[] = { 3838 SD2_CD_A_MARK, 3839 }; 3840 3841 static const unsigned int sdhi2_cd_b_pins[] = { 3842 /* CD */ 3843 RCAR_GP_PIN(5, 10), 3844 }; 3845 3846 static const unsigned int sdhi2_cd_b_mux[] = { 3847 SD2_CD_B_MARK, 3848 }; 3849 3850 static const unsigned int sdhi2_wp_a_pins[] = { 3851 /* WP */ 3852 RCAR_GP_PIN(4, 14), 3853 }; 3854 3855 static const unsigned int sdhi2_wp_a_mux[] = { 3856 SD2_WP_A_MARK, 3857 }; 3858 3859 static const unsigned int sdhi2_wp_b_pins[] = { 3860 /* WP */ 3861 RCAR_GP_PIN(5, 11), 3862 }; 3863 3864 static const unsigned int sdhi2_wp_b_mux[] = { 3865 SD2_WP_B_MARK, 3866 }; 3867 3868 static const unsigned int sdhi2_ds_pins[] = { 3869 /* DS */ 3870 RCAR_GP_PIN(4, 6), 3871 }; 3872 3873 static const unsigned int sdhi2_ds_mux[] = { 3874 SD2_DS_MARK, 3875 }; 3876 3877 /* - SDHI3 ------------------------------------------------------------------ */ 3878 static const unsigned int sdhi3_data1_pins[] = { 3879 /* D0 */ 3880 RCAR_GP_PIN(4, 9), 3881 }; 3882 3883 static const unsigned int sdhi3_data1_mux[] = { 3884 SD3_DAT0_MARK, 3885 }; 3886 3887 static const unsigned int sdhi3_data4_pins[] = { 3888 /* D[0:3] */ 3889 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3890 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3891 }; 3892 3893 static const unsigned int sdhi3_data4_mux[] = { 3894 SD3_DAT0_MARK, SD3_DAT1_MARK, 3895 SD3_DAT2_MARK, SD3_DAT3_MARK, 3896 }; 3897 3898 static const unsigned int sdhi3_data8_pins[] = { 3899 /* D[0:7] */ 3900 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), 3901 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), 3902 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), 3903 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), 3904 }; 3905 3906 static const unsigned int sdhi3_data8_mux[] = { 3907 SD3_DAT0_MARK, SD3_DAT1_MARK, 3908 SD3_DAT2_MARK, SD3_DAT3_MARK, 3909 SD3_DAT4_MARK, SD3_DAT5_MARK, 3910 SD3_DAT6_MARK, SD3_DAT7_MARK, 3911 }; 3912 3913 static const unsigned int sdhi3_ctrl_pins[] = { 3914 /* CLK, CMD */ 3915 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), 3916 }; 3917 3918 static const unsigned int sdhi3_ctrl_mux[] = { 3919 SD3_CLK_MARK, SD3_CMD_MARK, 3920 }; 3921 3922 static const unsigned int sdhi3_cd_pins[] = { 3923 /* CD */ 3924 RCAR_GP_PIN(4, 15), 3925 }; 3926 3927 static const unsigned int sdhi3_cd_mux[] = { 3928 SD3_CD_MARK, 3929 }; 3930 3931 static const unsigned int sdhi3_wp_pins[] = { 3932 /* WP */ 3933 RCAR_GP_PIN(4, 16), 3934 }; 3935 3936 static const unsigned int sdhi3_wp_mux[] = { 3937 SD3_WP_MARK, 3938 }; 3939 3940 static const unsigned int sdhi3_ds_pins[] = { 3941 /* DS */ 3942 RCAR_GP_PIN(4, 17), 3943 }; 3944 3945 static const unsigned int sdhi3_ds_mux[] = { 3946 SD3_DS_MARK, 3947 }; 3948 3949 /* - SSI -------------------------------------------------------------------- */ 3950 static const unsigned int ssi0_data_pins[] = { 3951 /* SDATA */ 3952 RCAR_GP_PIN(6, 2), 3953 }; 3954 static const unsigned int ssi0_data_mux[] = { 3955 SSI_SDATA0_MARK, 3956 }; 3957 static const unsigned int ssi01239_ctrl_pins[] = { 3958 /* SCK, WS */ 3959 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), 3960 }; 3961 static const unsigned int ssi01239_ctrl_mux[] = { 3962 SSI_SCK01239_MARK, SSI_WS01239_MARK, 3963 }; 3964 static const unsigned int ssi1_data_a_pins[] = { 3965 /* SDATA */ 3966 RCAR_GP_PIN(6, 3), 3967 }; 3968 static const unsigned int ssi1_data_a_mux[] = { 3969 SSI_SDATA1_A_MARK, 3970 }; 3971 static const unsigned int ssi1_data_b_pins[] = { 3972 /* SDATA */ 3973 RCAR_GP_PIN(5, 12), 3974 }; 3975 static const unsigned int ssi1_data_b_mux[] = { 3976 SSI_SDATA1_B_MARK, 3977 }; 3978 static const unsigned int ssi1_ctrl_a_pins[] = { 3979 /* SCK, WS */ 3980 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 3981 }; 3982 static const unsigned int ssi1_ctrl_a_mux[] = { 3983 SSI_SCK1_A_MARK, SSI_WS1_A_MARK, 3984 }; 3985 static const unsigned int ssi1_ctrl_b_pins[] = { 3986 /* SCK, WS */ 3987 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), 3988 }; 3989 static const unsigned int ssi1_ctrl_b_mux[] = { 3990 SSI_SCK1_B_MARK, SSI_WS1_B_MARK, 3991 }; 3992 static const unsigned int ssi2_data_a_pins[] = { 3993 /* SDATA */ 3994 RCAR_GP_PIN(6, 4), 3995 }; 3996 static const unsigned int ssi2_data_a_mux[] = { 3997 SSI_SDATA2_A_MARK, 3998 }; 3999 static const unsigned int ssi2_data_b_pins[] = { 4000 /* SDATA */ 4001 RCAR_GP_PIN(5, 13), 4002 }; 4003 static const unsigned int ssi2_data_b_mux[] = { 4004 SSI_SDATA2_B_MARK, 4005 }; 4006 static const unsigned int ssi2_ctrl_a_pins[] = { 4007 /* SCK, WS */ 4008 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), 4009 }; 4010 static const unsigned int ssi2_ctrl_a_mux[] = { 4011 SSI_SCK2_A_MARK, SSI_WS2_A_MARK, 4012 }; 4013 static const unsigned int ssi2_ctrl_b_pins[] = { 4014 /* SCK, WS */ 4015 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4016 }; 4017 static const unsigned int ssi2_ctrl_b_mux[] = { 4018 SSI_SCK2_B_MARK, SSI_WS2_B_MARK, 4019 }; 4020 static const unsigned int ssi3_data_pins[] = { 4021 /* SDATA */ 4022 RCAR_GP_PIN(6, 7), 4023 }; 4024 static const unsigned int ssi3_data_mux[] = { 4025 SSI_SDATA3_MARK, 4026 }; 4027 static const unsigned int ssi349_ctrl_pins[] = { 4028 /* SCK, WS */ 4029 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), 4030 }; 4031 static const unsigned int ssi349_ctrl_mux[] = { 4032 SSI_SCK349_MARK, SSI_WS349_MARK, 4033 }; 4034 static const unsigned int ssi4_data_pins[] = { 4035 /* SDATA */ 4036 RCAR_GP_PIN(6, 10), 4037 }; 4038 static const unsigned int ssi4_data_mux[] = { 4039 SSI_SDATA4_MARK, 4040 }; 4041 static const unsigned int ssi4_ctrl_pins[] = { 4042 /* SCK, WS */ 4043 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), 4044 }; 4045 static const unsigned int ssi4_ctrl_mux[] = { 4046 SSI_SCK4_MARK, SSI_WS4_MARK, 4047 }; 4048 static const unsigned int ssi5_data_pins[] = { 4049 /* SDATA */ 4050 RCAR_GP_PIN(6, 13), 4051 }; 4052 static const unsigned int ssi5_data_mux[] = { 4053 SSI_SDATA5_MARK, 4054 }; 4055 static const unsigned int ssi5_ctrl_pins[] = { 4056 /* SCK, WS */ 4057 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), 4058 }; 4059 static const unsigned int ssi5_ctrl_mux[] = { 4060 SSI_SCK5_MARK, SSI_WS5_MARK, 4061 }; 4062 static const unsigned int ssi6_data_pins[] = { 4063 /* SDATA */ 4064 RCAR_GP_PIN(6, 16), 4065 }; 4066 static const unsigned int ssi6_data_mux[] = { 4067 SSI_SDATA6_MARK, 4068 }; 4069 static const unsigned int ssi6_ctrl_pins[] = { 4070 /* SCK, WS */ 4071 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), 4072 }; 4073 static const unsigned int ssi6_ctrl_mux[] = { 4074 SSI_SCK6_MARK, SSI_WS6_MARK, 4075 }; 4076 static const unsigned int ssi7_data_pins[] = { 4077 /* SDATA */ 4078 RCAR_GP_PIN(6, 19), 4079 }; 4080 static const unsigned int ssi7_data_mux[] = { 4081 SSI_SDATA7_MARK, 4082 }; 4083 static const unsigned int ssi78_ctrl_pins[] = { 4084 /* SCK, WS */ 4085 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), 4086 }; 4087 static const unsigned int ssi78_ctrl_mux[] = { 4088 SSI_SCK78_MARK, SSI_WS78_MARK, 4089 }; 4090 static const unsigned int ssi8_data_pins[] = { 4091 /* SDATA */ 4092 RCAR_GP_PIN(6, 20), 4093 }; 4094 static const unsigned int ssi8_data_mux[] = { 4095 SSI_SDATA8_MARK, 4096 }; 4097 static const unsigned int ssi9_data_a_pins[] = { 4098 /* SDATA */ 4099 RCAR_GP_PIN(6, 21), 4100 }; 4101 static const unsigned int ssi9_data_a_mux[] = { 4102 SSI_SDATA9_A_MARK, 4103 }; 4104 static const unsigned int ssi9_data_b_pins[] = { 4105 /* SDATA */ 4106 RCAR_GP_PIN(5, 14), 4107 }; 4108 static const unsigned int ssi9_data_b_mux[] = { 4109 SSI_SDATA9_B_MARK, 4110 }; 4111 static const unsigned int ssi9_ctrl_a_pins[] = { 4112 /* SCK, WS */ 4113 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), 4114 }; 4115 static const unsigned int ssi9_ctrl_a_mux[] = { 4116 SSI_SCK9_A_MARK, SSI_WS9_A_MARK, 4117 }; 4118 static const unsigned int ssi9_ctrl_b_pins[] = { 4119 /* SCK, WS */ 4120 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), 4121 }; 4122 static const unsigned int ssi9_ctrl_b_mux[] = { 4123 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 4124 }; 4125 4126 /* - TMU -------------------------------------------------------------------- */ 4127 static const unsigned int tmu_tclk1_a_pins[] = { 4128 /* TCLK */ 4129 RCAR_GP_PIN(6, 23), 4130 }; 4131 4132 static const unsigned int tmu_tclk1_a_mux[] = { 4133 TCLK1_A_MARK, 4134 }; 4135 4136 static const unsigned int tmu_tclk1_b_pins[] = { 4137 /* TCLK */ 4138 RCAR_GP_PIN(5, 19), 4139 }; 4140 4141 static const unsigned int tmu_tclk1_b_mux[] = { 4142 TCLK1_B_MARK, 4143 }; 4144 4145 static const unsigned int tmu_tclk2_a_pins[] = { 4146 /* TCLK */ 4147 RCAR_GP_PIN(6, 19), 4148 }; 4149 4150 static const unsigned int tmu_tclk2_a_mux[] = { 4151 TCLK2_A_MARK, 4152 }; 4153 4154 static const unsigned int tmu_tclk2_b_pins[] = { 4155 /* TCLK */ 4156 RCAR_GP_PIN(6, 28), 4157 }; 4158 4159 static const unsigned int tmu_tclk2_b_mux[] = { 4160 TCLK2_B_MARK, 4161 }; 4162 4163 /* - TPU ------------------------------------------------------------------- */ 4164 static const unsigned int tpu_to0_pins[] = { 4165 /* TPU0TO0 */ 4166 RCAR_GP_PIN(6, 28), 4167 }; 4168 static const unsigned int tpu_to0_mux[] = { 4169 TPU0TO0_MARK, 4170 }; 4171 static const unsigned int tpu_to1_pins[] = { 4172 /* TPU0TO1 */ 4173 RCAR_GP_PIN(6, 29), 4174 }; 4175 static const unsigned int tpu_to1_mux[] = { 4176 TPU0TO1_MARK, 4177 }; 4178 static const unsigned int tpu_to2_pins[] = { 4179 /* TPU0TO2 */ 4180 RCAR_GP_PIN(6, 30), 4181 }; 4182 static const unsigned int tpu_to2_mux[] = { 4183 TPU0TO2_MARK, 4184 }; 4185 static const unsigned int tpu_to3_pins[] = { 4186 /* TPU0TO3 */ 4187 RCAR_GP_PIN(6, 31), 4188 }; 4189 static const unsigned int tpu_to3_mux[] = { 4190 TPU0TO3_MARK, 4191 }; 4192 4193 /* - USB0 ------------------------------------------------------------------- */ 4194 static const unsigned int usb0_pins[] = { 4195 /* PWEN, OVC */ 4196 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), 4197 }; 4198 4199 static const unsigned int usb0_mux[] = { 4200 USB0_PWEN_MARK, USB0_OVC_MARK, 4201 }; 4202 4203 /* - USB1 ------------------------------------------------------------------- */ 4204 static const unsigned int usb1_pins[] = { 4205 /* PWEN, OVC */ 4206 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), 4207 }; 4208 4209 static const unsigned int usb1_mux[] = { 4210 USB1_PWEN_MARK, USB1_OVC_MARK, 4211 }; 4212 4213 /* - USB30 ------------------------------------------------------------------ */ 4214 static const unsigned int usb30_pins[] = { 4215 /* PWEN, OVC */ 4216 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), 4217 }; 4218 4219 static const unsigned int usb30_mux[] = { 4220 USB30_PWEN_MARK, USB30_OVC_MARK, 4221 }; 4222 4223 /* - VIN4 ------------------------------------------------------------------- */ 4224 static const unsigned int vin4_data18_a_pins[] = { 4225 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4226 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4227 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4228 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4229 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4230 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4231 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4232 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4233 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4234 }; 4235 4236 static const unsigned int vin4_data18_a_mux[] = { 4237 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4238 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4239 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4240 VI4_DATA10_MARK, VI4_DATA11_MARK, 4241 VI4_DATA12_MARK, VI4_DATA13_MARK, 4242 VI4_DATA14_MARK, VI4_DATA15_MARK, 4243 VI4_DATA18_MARK, VI4_DATA19_MARK, 4244 VI4_DATA20_MARK, VI4_DATA21_MARK, 4245 VI4_DATA22_MARK, VI4_DATA23_MARK, 4246 }; 4247 4248 static const union vin_data vin4_data_a_pins = { 4249 .data24 = { 4250 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), 4251 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), 4252 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 4253 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), 4254 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4255 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4256 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4257 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4258 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4259 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4260 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4261 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4262 }, 4263 }; 4264 4265 static const union vin_data vin4_data_a_mux = { 4266 .data24 = { 4267 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, 4268 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, 4269 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, 4270 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, 4271 VI4_DATA8_MARK, VI4_DATA9_MARK, 4272 VI4_DATA10_MARK, VI4_DATA11_MARK, 4273 VI4_DATA12_MARK, VI4_DATA13_MARK, 4274 VI4_DATA14_MARK, VI4_DATA15_MARK, 4275 VI4_DATA16_MARK, VI4_DATA17_MARK, 4276 VI4_DATA18_MARK, VI4_DATA19_MARK, 4277 VI4_DATA20_MARK, VI4_DATA21_MARK, 4278 VI4_DATA22_MARK, VI4_DATA23_MARK, 4279 }, 4280 }; 4281 4282 static const unsigned int vin4_data18_b_pins[] = { 4283 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4284 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4285 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4286 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4287 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4288 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4289 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4290 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4291 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4292 }; 4293 4294 static const unsigned int vin4_data18_b_mux[] = { 4295 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4296 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4297 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4298 VI4_DATA10_MARK, VI4_DATA11_MARK, 4299 VI4_DATA12_MARK, VI4_DATA13_MARK, 4300 VI4_DATA14_MARK, VI4_DATA15_MARK, 4301 VI4_DATA18_MARK, VI4_DATA19_MARK, 4302 VI4_DATA20_MARK, VI4_DATA21_MARK, 4303 VI4_DATA22_MARK, VI4_DATA23_MARK, 4304 }; 4305 4306 static const union vin_data vin4_data_b_pins = { 4307 .data24 = { 4308 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 4309 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 4310 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 4311 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 4312 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 4313 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 4314 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4315 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4316 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4317 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4318 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4319 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4320 }, 4321 }; 4322 4323 static const union vin_data vin4_data_b_mux = { 4324 .data24 = { 4325 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, 4326 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, 4327 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, 4328 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, 4329 VI4_DATA8_MARK, VI4_DATA9_MARK, 4330 VI4_DATA10_MARK, VI4_DATA11_MARK, 4331 VI4_DATA12_MARK, VI4_DATA13_MARK, 4332 VI4_DATA14_MARK, VI4_DATA15_MARK, 4333 VI4_DATA16_MARK, VI4_DATA17_MARK, 4334 VI4_DATA18_MARK, VI4_DATA19_MARK, 4335 VI4_DATA20_MARK, VI4_DATA21_MARK, 4336 VI4_DATA22_MARK, VI4_DATA23_MARK, 4337 }, 4338 }; 4339 4340 static const unsigned int vin4_sync_pins[] = { 4341 /* VSYNC_N, HSYNC_N */ 4342 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), 4343 }; 4344 4345 static const unsigned int vin4_sync_mux[] = { 4346 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, 4347 }; 4348 4349 static const unsigned int vin4_field_pins[] = { 4350 RCAR_GP_PIN(1, 16), 4351 }; 4352 4353 static const unsigned int vin4_field_mux[] = { 4354 VI4_FIELD_MARK, 4355 }; 4356 4357 static const unsigned int vin4_clkenb_pins[] = { 4358 RCAR_GP_PIN(1, 19), 4359 }; 4360 4361 static const unsigned int vin4_clkenb_mux[] = { 4362 VI4_CLKENB_MARK, 4363 }; 4364 4365 static const unsigned int vin4_clk_pins[] = { 4366 RCAR_GP_PIN(1, 27), 4367 }; 4368 4369 static const unsigned int vin4_clk_mux[] = { 4370 VI4_CLK_MARK, 4371 }; 4372 4373 /* - VIN5 ------------------------------------------------------------------- */ 4374 static const union vin_data16 vin5_data_pins = { 4375 .data16 = { 4376 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4377 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4378 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4379 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4380 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), 4381 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), 4382 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), 4383 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 4384 }, 4385 }; 4386 4387 static const union vin_data16 vin5_data_mux = { 4388 .data16 = { 4389 VI5_DATA0_MARK, VI5_DATA1_MARK, 4390 VI5_DATA2_MARK, VI5_DATA3_MARK, 4391 VI5_DATA4_MARK, VI5_DATA5_MARK, 4392 VI5_DATA6_MARK, VI5_DATA7_MARK, 4393 VI5_DATA8_MARK, VI5_DATA9_MARK, 4394 VI5_DATA10_MARK, VI5_DATA11_MARK, 4395 VI5_DATA12_MARK, VI5_DATA13_MARK, 4396 VI5_DATA14_MARK, VI5_DATA15_MARK, 4397 }, 4398 }; 4399 4400 static const unsigned int vin5_sync_pins[] = { 4401 /* VSYNC_N, HSYNC_N */ 4402 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), 4403 }; 4404 4405 static const unsigned int vin5_sync_mux[] = { 4406 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, 4407 }; 4408 4409 static const unsigned int vin5_field_pins[] = { 4410 RCAR_GP_PIN(1, 11), 4411 }; 4412 4413 static const unsigned int vin5_field_mux[] = { 4414 VI5_FIELD_MARK, 4415 }; 4416 4417 static const unsigned int vin5_clkenb_pins[] = { 4418 RCAR_GP_PIN(1, 20), 4419 }; 4420 4421 static const unsigned int vin5_clkenb_mux[] = { 4422 VI5_CLKENB_MARK, 4423 }; 4424 4425 static const unsigned int vin5_clk_pins[] = { 4426 RCAR_GP_PIN(1, 21), 4427 }; 4428 4429 static const unsigned int vin5_clk_mux[] = { 4430 VI5_CLK_MARK, 4431 }; 4432 4433 static const struct { 4434 struct sh_pfc_pin_group common[324]; 4435 #ifdef CONFIG_PINCTRL_PFC_R8A77965 4436 struct sh_pfc_pin_group automotive[30]; 4437 #endif 4438 } pinmux_groups = { 4439 .common = { 4440 SH_PFC_PIN_GROUP(audio_clk_a_a), 4441 SH_PFC_PIN_GROUP(audio_clk_a_b), 4442 SH_PFC_PIN_GROUP(audio_clk_a_c), 4443 SH_PFC_PIN_GROUP(audio_clk_b_a), 4444 SH_PFC_PIN_GROUP(audio_clk_b_b), 4445 SH_PFC_PIN_GROUP(audio_clk_c_a), 4446 SH_PFC_PIN_GROUP(audio_clk_c_b), 4447 SH_PFC_PIN_GROUP(audio_clkout_a), 4448 SH_PFC_PIN_GROUP(audio_clkout_b), 4449 SH_PFC_PIN_GROUP(audio_clkout_c), 4450 SH_PFC_PIN_GROUP(audio_clkout_d), 4451 SH_PFC_PIN_GROUP(audio_clkout1_a), 4452 SH_PFC_PIN_GROUP(audio_clkout1_b), 4453 SH_PFC_PIN_GROUP(audio_clkout2_a), 4454 SH_PFC_PIN_GROUP(audio_clkout2_b), 4455 SH_PFC_PIN_GROUP(audio_clkout3_a), 4456 SH_PFC_PIN_GROUP(audio_clkout3_b), 4457 SH_PFC_PIN_GROUP(avb_link), 4458 SH_PFC_PIN_GROUP(avb_magic), 4459 SH_PFC_PIN_GROUP(avb_phy_int), 4460 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ 4461 SH_PFC_PIN_GROUP(avb_mdio), 4462 SH_PFC_PIN_GROUP(avb_mii), 4463 SH_PFC_PIN_GROUP(avb_avtp_pps), 4464 SH_PFC_PIN_GROUP(avb_avtp_match_a), 4465 SH_PFC_PIN_GROUP(avb_avtp_capture_a), 4466 SH_PFC_PIN_GROUP(avb_avtp_match_b), 4467 SH_PFC_PIN_GROUP(avb_avtp_capture_b), 4468 SH_PFC_PIN_GROUP(can0_data_a), 4469 SH_PFC_PIN_GROUP(can0_data_b), 4470 SH_PFC_PIN_GROUP(can1_data), 4471 SH_PFC_PIN_GROUP(can_clk), 4472 SH_PFC_PIN_GROUP(canfd0_data_a), 4473 SH_PFC_PIN_GROUP(canfd0_data_b), 4474 SH_PFC_PIN_GROUP(canfd1_data), 4475 SH_PFC_PIN_GROUP(du_rgb666), 4476 SH_PFC_PIN_GROUP(du_rgb888), 4477 SH_PFC_PIN_GROUP(du_clk_out_0), 4478 SH_PFC_PIN_GROUP(du_clk_out_1), 4479 SH_PFC_PIN_GROUP(du_sync), 4480 SH_PFC_PIN_GROUP(du_oddf), 4481 SH_PFC_PIN_GROUP(du_cde), 4482 SH_PFC_PIN_GROUP(du_disp), 4483 SH_PFC_PIN_GROUP(hscif0_data), 4484 SH_PFC_PIN_GROUP(hscif0_clk), 4485 SH_PFC_PIN_GROUP(hscif0_ctrl), 4486 SH_PFC_PIN_GROUP(hscif1_data_a), 4487 SH_PFC_PIN_GROUP(hscif1_clk_a), 4488 SH_PFC_PIN_GROUP(hscif1_ctrl_a), 4489 SH_PFC_PIN_GROUP(hscif1_data_b), 4490 SH_PFC_PIN_GROUP(hscif1_clk_b), 4491 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 4492 SH_PFC_PIN_GROUP(hscif2_data_a), 4493 SH_PFC_PIN_GROUP(hscif2_clk_a), 4494 SH_PFC_PIN_GROUP(hscif2_ctrl_a), 4495 SH_PFC_PIN_GROUP(hscif2_data_b), 4496 SH_PFC_PIN_GROUP(hscif2_clk_b), 4497 SH_PFC_PIN_GROUP(hscif2_ctrl_b), 4498 SH_PFC_PIN_GROUP(hscif2_data_c), 4499 SH_PFC_PIN_GROUP(hscif2_clk_c), 4500 SH_PFC_PIN_GROUP(hscif2_ctrl_c), 4501 SH_PFC_PIN_GROUP(hscif3_data_a), 4502 SH_PFC_PIN_GROUP(hscif3_clk), 4503 SH_PFC_PIN_GROUP(hscif3_ctrl), 4504 SH_PFC_PIN_GROUP(hscif3_data_b), 4505 SH_PFC_PIN_GROUP(hscif3_data_c), 4506 SH_PFC_PIN_GROUP(hscif3_data_d), 4507 SH_PFC_PIN_GROUP(hscif4_data_a), 4508 SH_PFC_PIN_GROUP(hscif4_clk), 4509 SH_PFC_PIN_GROUP(hscif4_ctrl), 4510 SH_PFC_PIN_GROUP(hscif4_data_b), 4511 SH_PFC_PIN_GROUP(i2c0), 4512 SH_PFC_PIN_GROUP(i2c1_a), 4513 SH_PFC_PIN_GROUP(i2c1_b), 4514 SH_PFC_PIN_GROUP(i2c2_a), 4515 SH_PFC_PIN_GROUP(i2c2_b), 4516 SH_PFC_PIN_GROUP(i2c3), 4517 SH_PFC_PIN_GROUP(i2c5), 4518 SH_PFC_PIN_GROUP(i2c6_a), 4519 SH_PFC_PIN_GROUP(i2c6_b), 4520 SH_PFC_PIN_GROUP(i2c6_c), 4521 SH_PFC_PIN_GROUP(intc_ex_irq0), 4522 SH_PFC_PIN_GROUP(intc_ex_irq1), 4523 SH_PFC_PIN_GROUP(intc_ex_irq2), 4524 SH_PFC_PIN_GROUP(intc_ex_irq3), 4525 SH_PFC_PIN_GROUP(intc_ex_irq4), 4526 SH_PFC_PIN_GROUP(intc_ex_irq5), 4527 SH_PFC_PIN_GROUP(msiof0_clk), 4528 SH_PFC_PIN_GROUP(msiof0_sync), 4529 SH_PFC_PIN_GROUP(msiof0_ss1), 4530 SH_PFC_PIN_GROUP(msiof0_ss2), 4531 SH_PFC_PIN_GROUP(msiof0_txd), 4532 SH_PFC_PIN_GROUP(msiof0_rxd), 4533 SH_PFC_PIN_GROUP(msiof1_clk_a), 4534 SH_PFC_PIN_GROUP(msiof1_sync_a), 4535 SH_PFC_PIN_GROUP(msiof1_ss1_a), 4536 SH_PFC_PIN_GROUP(msiof1_ss2_a), 4537 SH_PFC_PIN_GROUP(msiof1_txd_a), 4538 SH_PFC_PIN_GROUP(msiof1_rxd_a), 4539 SH_PFC_PIN_GROUP(msiof1_clk_b), 4540 SH_PFC_PIN_GROUP(msiof1_sync_b), 4541 SH_PFC_PIN_GROUP(msiof1_ss1_b), 4542 SH_PFC_PIN_GROUP(msiof1_ss2_b), 4543 SH_PFC_PIN_GROUP(msiof1_txd_b), 4544 SH_PFC_PIN_GROUP(msiof1_rxd_b), 4545 SH_PFC_PIN_GROUP(msiof1_clk_c), 4546 SH_PFC_PIN_GROUP(msiof1_sync_c), 4547 SH_PFC_PIN_GROUP(msiof1_ss1_c), 4548 SH_PFC_PIN_GROUP(msiof1_ss2_c), 4549 SH_PFC_PIN_GROUP(msiof1_txd_c), 4550 SH_PFC_PIN_GROUP(msiof1_rxd_c), 4551 SH_PFC_PIN_GROUP(msiof1_clk_d), 4552 SH_PFC_PIN_GROUP(msiof1_sync_d), 4553 SH_PFC_PIN_GROUP(msiof1_ss1_d), 4554 SH_PFC_PIN_GROUP(msiof1_ss2_d), 4555 SH_PFC_PIN_GROUP(msiof1_txd_d), 4556 SH_PFC_PIN_GROUP(msiof1_rxd_d), 4557 SH_PFC_PIN_GROUP(msiof1_clk_e), 4558 SH_PFC_PIN_GROUP(msiof1_sync_e), 4559 SH_PFC_PIN_GROUP(msiof1_ss1_e), 4560 SH_PFC_PIN_GROUP(msiof1_ss2_e), 4561 SH_PFC_PIN_GROUP(msiof1_txd_e), 4562 SH_PFC_PIN_GROUP(msiof1_rxd_e), 4563 SH_PFC_PIN_GROUP(msiof1_clk_f), 4564 SH_PFC_PIN_GROUP(msiof1_sync_f), 4565 SH_PFC_PIN_GROUP(msiof1_ss1_f), 4566 SH_PFC_PIN_GROUP(msiof1_ss2_f), 4567 SH_PFC_PIN_GROUP(msiof1_txd_f), 4568 SH_PFC_PIN_GROUP(msiof1_rxd_f), 4569 SH_PFC_PIN_GROUP(msiof1_clk_g), 4570 SH_PFC_PIN_GROUP(msiof1_sync_g), 4571 SH_PFC_PIN_GROUP(msiof1_ss1_g), 4572 SH_PFC_PIN_GROUP(msiof1_ss2_g), 4573 SH_PFC_PIN_GROUP(msiof1_txd_g), 4574 SH_PFC_PIN_GROUP(msiof1_rxd_g), 4575 SH_PFC_PIN_GROUP(msiof2_clk_a), 4576 SH_PFC_PIN_GROUP(msiof2_sync_a), 4577 SH_PFC_PIN_GROUP(msiof2_ss1_a), 4578 SH_PFC_PIN_GROUP(msiof2_ss2_a), 4579 SH_PFC_PIN_GROUP(msiof2_txd_a), 4580 SH_PFC_PIN_GROUP(msiof2_rxd_a), 4581 SH_PFC_PIN_GROUP(msiof2_clk_b), 4582 SH_PFC_PIN_GROUP(msiof2_sync_b), 4583 SH_PFC_PIN_GROUP(msiof2_ss1_b), 4584 SH_PFC_PIN_GROUP(msiof2_ss2_b), 4585 SH_PFC_PIN_GROUP(msiof2_txd_b), 4586 SH_PFC_PIN_GROUP(msiof2_rxd_b), 4587 SH_PFC_PIN_GROUP(msiof2_clk_c), 4588 SH_PFC_PIN_GROUP(msiof2_sync_c), 4589 SH_PFC_PIN_GROUP(msiof2_ss1_c), 4590 SH_PFC_PIN_GROUP(msiof2_ss2_c), 4591 SH_PFC_PIN_GROUP(msiof2_txd_c), 4592 SH_PFC_PIN_GROUP(msiof2_rxd_c), 4593 SH_PFC_PIN_GROUP(msiof2_clk_d), 4594 SH_PFC_PIN_GROUP(msiof2_sync_d), 4595 SH_PFC_PIN_GROUP(msiof2_ss1_d), 4596 SH_PFC_PIN_GROUP(msiof2_ss2_d), 4597 SH_PFC_PIN_GROUP(msiof2_txd_d), 4598 SH_PFC_PIN_GROUP(msiof2_rxd_d), 4599 SH_PFC_PIN_GROUP(msiof3_clk_a), 4600 SH_PFC_PIN_GROUP(msiof3_sync_a), 4601 SH_PFC_PIN_GROUP(msiof3_ss1_a), 4602 SH_PFC_PIN_GROUP(msiof3_ss2_a), 4603 SH_PFC_PIN_GROUP(msiof3_txd_a), 4604 SH_PFC_PIN_GROUP(msiof3_rxd_a), 4605 SH_PFC_PIN_GROUP(msiof3_clk_b), 4606 SH_PFC_PIN_GROUP(msiof3_sync_b), 4607 SH_PFC_PIN_GROUP(msiof3_ss1_b), 4608 SH_PFC_PIN_GROUP(msiof3_ss2_b), 4609 SH_PFC_PIN_GROUP(msiof3_txd_b), 4610 SH_PFC_PIN_GROUP(msiof3_rxd_b), 4611 SH_PFC_PIN_GROUP(msiof3_clk_c), 4612 SH_PFC_PIN_GROUP(msiof3_sync_c), 4613 SH_PFC_PIN_GROUP(msiof3_txd_c), 4614 SH_PFC_PIN_GROUP(msiof3_rxd_c), 4615 SH_PFC_PIN_GROUP(msiof3_clk_d), 4616 SH_PFC_PIN_GROUP(msiof3_sync_d), 4617 SH_PFC_PIN_GROUP(msiof3_ss1_d), 4618 SH_PFC_PIN_GROUP(msiof3_txd_d), 4619 SH_PFC_PIN_GROUP(msiof3_rxd_d), 4620 SH_PFC_PIN_GROUP(msiof3_clk_e), 4621 SH_PFC_PIN_GROUP(msiof3_sync_e), 4622 SH_PFC_PIN_GROUP(msiof3_ss1_e), 4623 SH_PFC_PIN_GROUP(msiof3_ss2_e), 4624 SH_PFC_PIN_GROUP(msiof3_txd_e), 4625 SH_PFC_PIN_GROUP(msiof3_rxd_e), 4626 SH_PFC_PIN_GROUP(pwm0), 4627 SH_PFC_PIN_GROUP(pwm1_a), 4628 SH_PFC_PIN_GROUP(pwm1_b), 4629 SH_PFC_PIN_GROUP(pwm2_a), 4630 SH_PFC_PIN_GROUP(pwm2_b), 4631 SH_PFC_PIN_GROUP(pwm3_a), 4632 SH_PFC_PIN_GROUP(pwm3_b), 4633 SH_PFC_PIN_GROUP(pwm4_a), 4634 SH_PFC_PIN_GROUP(pwm4_b), 4635 SH_PFC_PIN_GROUP(pwm5_a), 4636 SH_PFC_PIN_GROUP(pwm5_b), 4637 SH_PFC_PIN_GROUP(pwm6_a), 4638 SH_PFC_PIN_GROUP(pwm6_b), 4639 SH_PFC_PIN_GROUP(qspi0_ctrl), 4640 SH_PFC_PIN_GROUP(qspi0_data2), 4641 SH_PFC_PIN_GROUP(qspi0_data4), 4642 SH_PFC_PIN_GROUP(qspi1_ctrl), 4643 SH_PFC_PIN_GROUP(qspi1_data2), 4644 SH_PFC_PIN_GROUP(qspi1_data4), 4645 SH_PFC_PIN_GROUP(sata0_devslp_a), 4646 SH_PFC_PIN_GROUP(sata0_devslp_b), 4647 SH_PFC_PIN_GROUP(scif0_data), 4648 SH_PFC_PIN_GROUP(scif0_clk), 4649 SH_PFC_PIN_GROUP(scif0_ctrl), 4650 SH_PFC_PIN_GROUP(scif1_data_a), 4651 SH_PFC_PIN_GROUP(scif1_clk), 4652 SH_PFC_PIN_GROUP(scif1_ctrl), 4653 SH_PFC_PIN_GROUP(scif1_data_b), 4654 SH_PFC_PIN_GROUP(scif2_data_a), 4655 SH_PFC_PIN_GROUP(scif2_clk), 4656 SH_PFC_PIN_GROUP(scif2_data_b), 4657 SH_PFC_PIN_GROUP(scif3_data_a), 4658 SH_PFC_PIN_GROUP(scif3_clk), 4659 SH_PFC_PIN_GROUP(scif3_ctrl), 4660 SH_PFC_PIN_GROUP(scif3_data_b), 4661 SH_PFC_PIN_GROUP(scif4_data_a), 4662 SH_PFC_PIN_GROUP(scif4_clk_a), 4663 SH_PFC_PIN_GROUP(scif4_ctrl_a), 4664 SH_PFC_PIN_GROUP(scif4_data_b), 4665 SH_PFC_PIN_GROUP(scif4_clk_b), 4666 SH_PFC_PIN_GROUP(scif4_ctrl_b), 4667 SH_PFC_PIN_GROUP(scif4_data_c), 4668 SH_PFC_PIN_GROUP(scif4_clk_c), 4669 SH_PFC_PIN_GROUP(scif4_ctrl_c), 4670 SH_PFC_PIN_GROUP(scif5_data_a), 4671 SH_PFC_PIN_GROUP(scif5_clk_a), 4672 SH_PFC_PIN_GROUP(scif5_data_b), 4673 SH_PFC_PIN_GROUP(scif5_clk_b), 4674 SH_PFC_PIN_GROUP(scif_clk_a), 4675 SH_PFC_PIN_GROUP(scif_clk_b), 4676 SH_PFC_PIN_GROUP(sdhi0_data1), 4677 SH_PFC_PIN_GROUP(sdhi0_data4), 4678 SH_PFC_PIN_GROUP(sdhi0_ctrl), 4679 SH_PFC_PIN_GROUP(sdhi0_cd), 4680 SH_PFC_PIN_GROUP(sdhi0_wp), 4681 SH_PFC_PIN_GROUP(sdhi1_data1), 4682 SH_PFC_PIN_GROUP(sdhi1_data4), 4683 SH_PFC_PIN_GROUP(sdhi1_ctrl), 4684 SH_PFC_PIN_GROUP(sdhi1_cd), 4685 SH_PFC_PIN_GROUP(sdhi1_wp), 4686 SH_PFC_PIN_GROUP(sdhi2_data1), 4687 SH_PFC_PIN_GROUP(sdhi2_data4), 4688 SH_PFC_PIN_GROUP(sdhi2_data8), 4689 SH_PFC_PIN_GROUP(sdhi2_ctrl), 4690 SH_PFC_PIN_GROUP(sdhi2_cd_a), 4691 SH_PFC_PIN_GROUP(sdhi2_wp_a), 4692 SH_PFC_PIN_GROUP(sdhi2_cd_b), 4693 SH_PFC_PIN_GROUP(sdhi2_wp_b), 4694 SH_PFC_PIN_GROUP(sdhi2_ds), 4695 SH_PFC_PIN_GROUP(sdhi3_data1), 4696 SH_PFC_PIN_GROUP(sdhi3_data4), 4697 SH_PFC_PIN_GROUP(sdhi3_data8), 4698 SH_PFC_PIN_GROUP(sdhi3_ctrl), 4699 SH_PFC_PIN_GROUP(sdhi3_cd), 4700 SH_PFC_PIN_GROUP(sdhi3_wp), 4701 SH_PFC_PIN_GROUP(sdhi3_ds), 4702 SH_PFC_PIN_GROUP(ssi0_data), 4703 SH_PFC_PIN_GROUP(ssi01239_ctrl), 4704 SH_PFC_PIN_GROUP(ssi1_data_a), 4705 SH_PFC_PIN_GROUP(ssi1_data_b), 4706 SH_PFC_PIN_GROUP(ssi1_ctrl_a), 4707 SH_PFC_PIN_GROUP(ssi1_ctrl_b), 4708 SH_PFC_PIN_GROUP(ssi2_data_a), 4709 SH_PFC_PIN_GROUP(ssi2_data_b), 4710 SH_PFC_PIN_GROUP(ssi2_ctrl_a), 4711 SH_PFC_PIN_GROUP(ssi2_ctrl_b), 4712 SH_PFC_PIN_GROUP(ssi3_data), 4713 SH_PFC_PIN_GROUP(ssi349_ctrl), 4714 SH_PFC_PIN_GROUP(ssi4_data), 4715 SH_PFC_PIN_GROUP(ssi4_ctrl), 4716 SH_PFC_PIN_GROUP(ssi5_data), 4717 SH_PFC_PIN_GROUP(ssi5_ctrl), 4718 SH_PFC_PIN_GROUP(ssi6_data), 4719 SH_PFC_PIN_GROUP(ssi6_ctrl), 4720 SH_PFC_PIN_GROUP(ssi7_data), 4721 SH_PFC_PIN_GROUP(ssi78_ctrl), 4722 SH_PFC_PIN_GROUP(ssi8_data), 4723 SH_PFC_PIN_GROUP(ssi9_data_a), 4724 SH_PFC_PIN_GROUP(ssi9_data_b), 4725 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4726 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4727 SH_PFC_PIN_GROUP(tmu_tclk1_a), 4728 SH_PFC_PIN_GROUP(tmu_tclk1_b), 4729 SH_PFC_PIN_GROUP(tmu_tclk2_a), 4730 SH_PFC_PIN_GROUP(tmu_tclk2_b), 4731 SH_PFC_PIN_GROUP(tpu_to0), 4732 SH_PFC_PIN_GROUP(tpu_to1), 4733 SH_PFC_PIN_GROUP(tpu_to2), 4734 SH_PFC_PIN_GROUP(tpu_to3), 4735 SH_PFC_PIN_GROUP(usb0), 4736 SH_PFC_PIN_GROUP(usb1), 4737 SH_PFC_PIN_GROUP(usb30), 4738 VIN_DATA_PIN_GROUP(vin4_data, 8, _a), 4739 VIN_DATA_PIN_GROUP(vin4_data, 10, _a), 4740 VIN_DATA_PIN_GROUP(vin4_data, 12, _a), 4741 VIN_DATA_PIN_GROUP(vin4_data, 16, _a), 4742 SH_PFC_PIN_GROUP(vin4_data18_a), 4743 VIN_DATA_PIN_GROUP(vin4_data, 20, _a), 4744 VIN_DATA_PIN_GROUP(vin4_data, 24, _a), 4745 VIN_DATA_PIN_GROUP(vin4_data, 8, _b), 4746 VIN_DATA_PIN_GROUP(vin4_data, 10, _b), 4747 VIN_DATA_PIN_GROUP(vin4_data, 12, _b), 4748 VIN_DATA_PIN_GROUP(vin4_data, 16, _b), 4749 SH_PFC_PIN_GROUP(vin4_data18_b), 4750 VIN_DATA_PIN_GROUP(vin4_data, 20, _b), 4751 VIN_DATA_PIN_GROUP(vin4_data, 24, _b), 4752 SH_PFC_PIN_GROUP(vin4_sync), 4753 SH_PFC_PIN_GROUP(vin4_field), 4754 SH_PFC_PIN_GROUP(vin4_clkenb), 4755 SH_PFC_PIN_GROUP(vin4_clk), 4756 VIN_DATA_PIN_GROUP(vin5_data, 8), 4757 VIN_DATA_PIN_GROUP(vin5_data, 10), 4758 VIN_DATA_PIN_GROUP(vin5_data, 12), 4759 VIN_DATA_PIN_GROUP(vin5_data, 16), 4760 SH_PFC_PIN_GROUP(vin5_sync), 4761 SH_PFC_PIN_GROUP(vin5_field), 4762 SH_PFC_PIN_GROUP(vin5_clkenb), 4763 SH_PFC_PIN_GROUP(vin5_clk), 4764 }, 4765 #ifdef CONFIG_PINCTRL_PFC_R8A77965 4766 .automotive = { 4767 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4768 SH_PFC_PIN_GROUP(drif0_data0_a), 4769 SH_PFC_PIN_GROUP(drif0_data1_a), 4770 SH_PFC_PIN_GROUP(drif0_ctrl_b), 4771 SH_PFC_PIN_GROUP(drif0_data0_b), 4772 SH_PFC_PIN_GROUP(drif0_data1_b), 4773 SH_PFC_PIN_GROUP(drif0_ctrl_c), 4774 SH_PFC_PIN_GROUP(drif0_data0_c), 4775 SH_PFC_PIN_GROUP(drif0_data1_c), 4776 SH_PFC_PIN_GROUP(drif1_ctrl_a), 4777 SH_PFC_PIN_GROUP(drif1_data0_a), 4778 SH_PFC_PIN_GROUP(drif1_data1_a), 4779 SH_PFC_PIN_GROUP(drif1_ctrl_b), 4780 SH_PFC_PIN_GROUP(drif1_data0_b), 4781 SH_PFC_PIN_GROUP(drif1_data1_b), 4782 SH_PFC_PIN_GROUP(drif1_ctrl_c), 4783 SH_PFC_PIN_GROUP(drif1_data0_c), 4784 SH_PFC_PIN_GROUP(drif1_data1_c), 4785 SH_PFC_PIN_GROUP(drif2_ctrl_a), 4786 SH_PFC_PIN_GROUP(drif2_data0_a), 4787 SH_PFC_PIN_GROUP(drif2_data1_a), 4788 SH_PFC_PIN_GROUP(drif2_ctrl_b), 4789 SH_PFC_PIN_GROUP(drif2_data0_b), 4790 SH_PFC_PIN_GROUP(drif2_data1_b), 4791 SH_PFC_PIN_GROUP(drif3_ctrl_a), 4792 SH_PFC_PIN_GROUP(drif3_data0_a), 4793 SH_PFC_PIN_GROUP(drif3_data1_a), 4794 SH_PFC_PIN_GROUP(drif3_ctrl_b), 4795 SH_PFC_PIN_GROUP(drif3_data0_b), 4796 SH_PFC_PIN_GROUP(drif3_data1_b), 4797 } 4798 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 4799 }; 4800 4801 static const char * const audio_clk_groups[] = { 4802 "audio_clk_a_a", 4803 "audio_clk_a_b", 4804 "audio_clk_a_c", 4805 "audio_clk_b_a", 4806 "audio_clk_b_b", 4807 "audio_clk_c_a", 4808 "audio_clk_c_b", 4809 "audio_clkout_a", 4810 "audio_clkout_b", 4811 "audio_clkout_c", 4812 "audio_clkout_d", 4813 "audio_clkout1_a", 4814 "audio_clkout1_b", 4815 "audio_clkout2_a", 4816 "audio_clkout2_b", 4817 "audio_clkout3_a", 4818 "audio_clkout3_b", 4819 }; 4820 4821 static const char * const avb_groups[] = { 4822 "avb_link", 4823 "avb_magic", 4824 "avb_phy_int", 4825 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */ 4826 "avb_mdio", 4827 "avb_mii", 4828 "avb_avtp_pps", 4829 "avb_avtp_match_a", 4830 "avb_avtp_capture_a", 4831 "avb_avtp_match_b", 4832 "avb_avtp_capture_b", 4833 }; 4834 4835 static const char * const can0_groups[] = { 4836 "can0_data_a", 4837 "can0_data_b", 4838 }; 4839 4840 static const char * const can1_groups[] = { 4841 "can1_data", 4842 }; 4843 4844 static const char * const can_clk_groups[] = { 4845 "can_clk", 4846 }; 4847 4848 static const char * const canfd0_groups[] = { 4849 "canfd0_data_a", 4850 "canfd0_data_b", 4851 }; 4852 4853 static const char * const canfd1_groups[] = { 4854 "canfd1_data", 4855 }; 4856 4857 #ifdef CONFIG_PINCTRL_PFC_R8A77965 4858 static const char * const drif0_groups[] = { 4859 "drif0_ctrl_a", 4860 "drif0_data0_a", 4861 "drif0_data1_a", 4862 "drif0_ctrl_b", 4863 "drif0_data0_b", 4864 "drif0_data1_b", 4865 "drif0_ctrl_c", 4866 "drif0_data0_c", 4867 "drif0_data1_c", 4868 }; 4869 4870 static const char * const drif1_groups[] = { 4871 "drif1_ctrl_a", 4872 "drif1_data0_a", 4873 "drif1_data1_a", 4874 "drif1_ctrl_b", 4875 "drif1_data0_b", 4876 "drif1_data1_b", 4877 "drif1_ctrl_c", 4878 "drif1_data0_c", 4879 "drif1_data1_c", 4880 }; 4881 4882 static const char * const drif2_groups[] = { 4883 "drif2_ctrl_a", 4884 "drif2_data0_a", 4885 "drif2_data1_a", 4886 "drif2_ctrl_b", 4887 "drif2_data0_b", 4888 "drif2_data1_b", 4889 }; 4890 4891 static const char * const drif3_groups[] = { 4892 "drif3_ctrl_a", 4893 "drif3_data0_a", 4894 "drif3_data1_a", 4895 "drif3_ctrl_b", 4896 "drif3_data0_b", 4897 "drif3_data1_b", 4898 }; 4899 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 4900 4901 static const char * const du_groups[] = { 4902 "du_rgb666", 4903 "du_rgb888", 4904 "du_clk_out_0", 4905 "du_clk_out_1", 4906 "du_sync", 4907 "du_oddf", 4908 "du_cde", 4909 "du_disp", 4910 }; 4911 4912 static const char * const hscif0_groups[] = { 4913 "hscif0_data", 4914 "hscif0_clk", 4915 "hscif0_ctrl", 4916 }; 4917 4918 static const char * const hscif1_groups[] = { 4919 "hscif1_data_a", 4920 "hscif1_clk_a", 4921 "hscif1_ctrl_a", 4922 "hscif1_data_b", 4923 "hscif1_clk_b", 4924 "hscif1_ctrl_b", 4925 }; 4926 4927 static const char * const hscif2_groups[] = { 4928 "hscif2_data_a", 4929 "hscif2_clk_a", 4930 "hscif2_ctrl_a", 4931 "hscif2_data_b", 4932 "hscif2_clk_b", 4933 "hscif2_ctrl_b", 4934 "hscif2_data_c", 4935 "hscif2_clk_c", 4936 "hscif2_ctrl_c", 4937 }; 4938 4939 static const char * const hscif3_groups[] = { 4940 "hscif3_data_a", 4941 "hscif3_clk", 4942 "hscif3_ctrl", 4943 "hscif3_data_b", 4944 "hscif3_data_c", 4945 "hscif3_data_d", 4946 }; 4947 4948 static const char * const hscif4_groups[] = { 4949 "hscif4_data_a", 4950 "hscif4_clk", 4951 "hscif4_ctrl", 4952 "hscif4_data_b", 4953 }; 4954 4955 static const char * const i2c0_groups[] = { 4956 "i2c0", 4957 }; 4958 4959 static const char * const i2c1_groups[] = { 4960 "i2c1_a", 4961 "i2c1_b", 4962 }; 4963 4964 static const char * const i2c2_groups[] = { 4965 "i2c2_a", 4966 "i2c2_b", 4967 }; 4968 4969 static const char * const i2c3_groups[] = { 4970 "i2c3", 4971 }; 4972 4973 static const char * const i2c5_groups[] = { 4974 "i2c5", 4975 }; 4976 4977 static const char * const i2c6_groups[] = { 4978 "i2c6_a", 4979 "i2c6_b", 4980 "i2c6_c", 4981 }; 4982 4983 static const char * const intc_ex_groups[] = { 4984 "intc_ex_irq0", 4985 "intc_ex_irq1", 4986 "intc_ex_irq2", 4987 "intc_ex_irq3", 4988 "intc_ex_irq4", 4989 "intc_ex_irq5", 4990 }; 4991 4992 static const char * const msiof0_groups[] = { 4993 "msiof0_clk", 4994 "msiof0_sync", 4995 "msiof0_ss1", 4996 "msiof0_ss2", 4997 "msiof0_txd", 4998 "msiof0_rxd", 4999 }; 5000 5001 static const char * const msiof1_groups[] = { 5002 "msiof1_clk_a", 5003 "msiof1_sync_a", 5004 "msiof1_ss1_a", 5005 "msiof1_ss2_a", 5006 "msiof1_txd_a", 5007 "msiof1_rxd_a", 5008 "msiof1_clk_b", 5009 "msiof1_sync_b", 5010 "msiof1_ss1_b", 5011 "msiof1_ss2_b", 5012 "msiof1_txd_b", 5013 "msiof1_rxd_b", 5014 "msiof1_clk_c", 5015 "msiof1_sync_c", 5016 "msiof1_ss1_c", 5017 "msiof1_ss2_c", 5018 "msiof1_txd_c", 5019 "msiof1_rxd_c", 5020 "msiof1_clk_d", 5021 "msiof1_sync_d", 5022 "msiof1_ss1_d", 5023 "msiof1_ss2_d", 5024 "msiof1_txd_d", 5025 "msiof1_rxd_d", 5026 "msiof1_clk_e", 5027 "msiof1_sync_e", 5028 "msiof1_ss1_e", 5029 "msiof1_ss2_e", 5030 "msiof1_txd_e", 5031 "msiof1_rxd_e", 5032 "msiof1_clk_f", 5033 "msiof1_sync_f", 5034 "msiof1_ss1_f", 5035 "msiof1_ss2_f", 5036 "msiof1_txd_f", 5037 "msiof1_rxd_f", 5038 "msiof1_clk_g", 5039 "msiof1_sync_g", 5040 "msiof1_ss1_g", 5041 "msiof1_ss2_g", 5042 "msiof1_txd_g", 5043 "msiof1_rxd_g", 5044 }; 5045 5046 static const char * const msiof2_groups[] = { 5047 "msiof2_clk_a", 5048 "msiof2_sync_a", 5049 "msiof2_ss1_a", 5050 "msiof2_ss2_a", 5051 "msiof2_txd_a", 5052 "msiof2_rxd_a", 5053 "msiof2_clk_b", 5054 "msiof2_sync_b", 5055 "msiof2_ss1_b", 5056 "msiof2_ss2_b", 5057 "msiof2_txd_b", 5058 "msiof2_rxd_b", 5059 "msiof2_clk_c", 5060 "msiof2_sync_c", 5061 "msiof2_ss1_c", 5062 "msiof2_ss2_c", 5063 "msiof2_txd_c", 5064 "msiof2_rxd_c", 5065 "msiof2_clk_d", 5066 "msiof2_sync_d", 5067 "msiof2_ss1_d", 5068 "msiof2_ss2_d", 5069 "msiof2_txd_d", 5070 "msiof2_rxd_d", 5071 }; 5072 5073 static const char * const msiof3_groups[] = { 5074 "msiof3_clk_a", 5075 "msiof3_sync_a", 5076 "msiof3_ss1_a", 5077 "msiof3_ss2_a", 5078 "msiof3_txd_a", 5079 "msiof3_rxd_a", 5080 "msiof3_clk_b", 5081 "msiof3_sync_b", 5082 "msiof3_ss1_b", 5083 "msiof3_ss2_b", 5084 "msiof3_txd_b", 5085 "msiof3_rxd_b", 5086 "msiof3_clk_c", 5087 "msiof3_sync_c", 5088 "msiof3_txd_c", 5089 "msiof3_rxd_c", 5090 "msiof3_clk_d", 5091 "msiof3_sync_d", 5092 "msiof3_ss1_d", 5093 "msiof3_txd_d", 5094 "msiof3_rxd_d", 5095 "msiof3_clk_e", 5096 "msiof3_sync_e", 5097 "msiof3_ss1_e", 5098 "msiof3_ss2_e", 5099 "msiof3_txd_e", 5100 "msiof3_rxd_e", 5101 }; 5102 5103 static const char * const pwm0_groups[] = { 5104 "pwm0", 5105 }; 5106 5107 static const char * const pwm1_groups[] = { 5108 "pwm1_a", 5109 "pwm1_b", 5110 }; 5111 5112 static const char * const pwm2_groups[] = { 5113 "pwm2_a", 5114 "pwm2_b", 5115 }; 5116 5117 static const char * const pwm3_groups[] = { 5118 "pwm3_a", 5119 "pwm3_b", 5120 }; 5121 5122 static const char * const pwm4_groups[] = { 5123 "pwm4_a", 5124 "pwm4_b", 5125 }; 5126 5127 static const char * const pwm5_groups[] = { 5128 "pwm5_a", 5129 "pwm5_b", 5130 }; 5131 5132 static const char * const pwm6_groups[] = { 5133 "pwm6_a", 5134 "pwm6_b", 5135 }; 5136 5137 static const char * const qspi0_groups[] = { 5138 "qspi0_ctrl", 5139 "qspi0_data2", 5140 "qspi0_data4", 5141 }; 5142 5143 static const char * const qspi1_groups[] = { 5144 "qspi1_ctrl", 5145 "qspi1_data2", 5146 "qspi1_data4", 5147 }; 5148 5149 static const char * const sata0_groups[] = { 5150 "sata0_devslp_a", 5151 "sata0_devslp_b", 5152 }; 5153 5154 static const char * const scif0_groups[] = { 5155 "scif0_data", 5156 "scif0_clk", 5157 "scif0_ctrl", 5158 }; 5159 5160 static const char * const scif1_groups[] = { 5161 "scif1_data_a", 5162 "scif1_clk", 5163 "scif1_ctrl", 5164 "scif1_data_b", 5165 }; 5166 static const char * const scif2_groups[] = { 5167 "scif2_data_a", 5168 "scif2_clk", 5169 "scif2_data_b", 5170 }; 5171 5172 static const char * const scif3_groups[] = { 5173 "scif3_data_a", 5174 "scif3_clk", 5175 "scif3_ctrl", 5176 "scif3_data_b", 5177 }; 5178 5179 static const char * const scif4_groups[] = { 5180 "scif4_data_a", 5181 "scif4_clk_a", 5182 "scif4_ctrl_a", 5183 "scif4_data_b", 5184 "scif4_clk_b", 5185 "scif4_ctrl_b", 5186 "scif4_data_c", 5187 "scif4_clk_c", 5188 "scif4_ctrl_c", 5189 }; 5190 5191 static const char * const scif5_groups[] = { 5192 "scif5_data_a", 5193 "scif5_clk_a", 5194 "scif5_data_b", 5195 "scif5_clk_b", 5196 }; 5197 5198 static const char * const scif_clk_groups[] = { 5199 "scif_clk_a", 5200 "scif_clk_b", 5201 }; 5202 5203 static const char * const sdhi0_groups[] = { 5204 "sdhi0_data1", 5205 "sdhi0_data4", 5206 "sdhi0_ctrl", 5207 "sdhi0_cd", 5208 "sdhi0_wp", 5209 }; 5210 5211 static const char * const sdhi1_groups[] = { 5212 "sdhi1_data1", 5213 "sdhi1_data4", 5214 "sdhi1_ctrl", 5215 "sdhi1_cd", 5216 "sdhi1_wp", 5217 }; 5218 5219 static const char * const sdhi2_groups[] = { 5220 "sdhi2_data1", 5221 "sdhi2_data4", 5222 "sdhi2_data8", 5223 "sdhi2_ctrl", 5224 "sdhi2_cd_a", 5225 "sdhi2_wp_a", 5226 "sdhi2_cd_b", 5227 "sdhi2_wp_b", 5228 "sdhi2_ds", 5229 }; 5230 5231 static const char * const sdhi3_groups[] = { 5232 "sdhi3_data1", 5233 "sdhi3_data4", 5234 "sdhi3_data8", 5235 "sdhi3_ctrl", 5236 "sdhi3_cd", 5237 "sdhi3_wp", 5238 "sdhi3_ds", 5239 }; 5240 5241 static const char * const ssi_groups[] = { 5242 "ssi0_data", 5243 "ssi01239_ctrl", 5244 "ssi1_data_a", 5245 "ssi1_data_b", 5246 "ssi1_ctrl_a", 5247 "ssi1_ctrl_b", 5248 "ssi2_data_a", 5249 "ssi2_data_b", 5250 "ssi2_ctrl_a", 5251 "ssi2_ctrl_b", 5252 "ssi3_data", 5253 "ssi349_ctrl", 5254 "ssi4_data", 5255 "ssi4_ctrl", 5256 "ssi5_data", 5257 "ssi5_ctrl", 5258 "ssi6_data", 5259 "ssi6_ctrl", 5260 "ssi7_data", 5261 "ssi78_ctrl", 5262 "ssi8_data", 5263 "ssi9_data_a", 5264 "ssi9_data_b", 5265 "ssi9_ctrl_a", 5266 "ssi9_ctrl_b", 5267 }; 5268 5269 static const char * const tmu_groups[] = { 5270 "tmu_tclk1_a", 5271 "tmu_tclk1_b", 5272 "tmu_tclk2_a", 5273 "tmu_tclk2_b", 5274 }; 5275 5276 static const char * const tpu_groups[] = { 5277 "tpu_to0", 5278 "tpu_to1", 5279 "tpu_to2", 5280 "tpu_to3", 5281 }; 5282 5283 static const char * const usb0_groups[] = { 5284 "usb0", 5285 }; 5286 5287 static const char * const usb1_groups[] = { 5288 "usb1", 5289 }; 5290 5291 static const char * const usb30_groups[] = { 5292 "usb30", 5293 }; 5294 5295 static const char * const vin4_groups[] = { 5296 "vin4_data8_a", 5297 "vin4_data10_a", 5298 "vin4_data12_a", 5299 "vin4_data16_a", 5300 "vin4_data18_a", 5301 "vin4_data20_a", 5302 "vin4_data24_a", 5303 "vin4_data8_b", 5304 "vin4_data10_b", 5305 "vin4_data12_b", 5306 "vin4_data16_b", 5307 "vin4_data18_b", 5308 "vin4_data20_b", 5309 "vin4_data24_b", 5310 "vin4_sync", 5311 "vin4_field", 5312 "vin4_clkenb", 5313 "vin4_clk", 5314 }; 5315 5316 static const char * const vin5_groups[] = { 5317 "vin5_data8", 5318 "vin5_data10", 5319 "vin5_data12", 5320 "vin5_data16", 5321 "vin5_sync", 5322 "vin5_field", 5323 "vin5_clkenb", 5324 "vin5_clk", 5325 }; 5326 5327 static const struct { 5328 struct sh_pfc_function common[53]; 5329 #ifdef CONFIG_PINCTRL_PFC_R8A77965 5330 struct sh_pfc_function automotive[4]; 5331 #endif 5332 } pinmux_functions = { 5333 .common = { 5334 SH_PFC_FUNCTION(audio_clk), 5335 SH_PFC_FUNCTION(avb), 5336 SH_PFC_FUNCTION(can0), 5337 SH_PFC_FUNCTION(can1), 5338 SH_PFC_FUNCTION(can_clk), 5339 SH_PFC_FUNCTION(canfd0), 5340 SH_PFC_FUNCTION(canfd1), 5341 SH_PFC_FUNCTION(du), 5342 SH_PFC_FUNCTION(hscif0), 5343 SH_PFC_FUNCTION(hscif1), 5344 SH_PFC_FUNCTION(hscif2), 5345 SH_PFC_FUNCTION(hscif3), 5346 SH_PFC_FUNCTION(hscif4), 5347 SH_PFC_FUNCTION(i2c0), 5348 SH_PFC_FUNCTION(i2c1), 5349 SH_PFC_FUNCTION(i2c2), 5350 SH_PFC_FUNCTION(i2c3), 5351 SH_PFC_FUNCTION(i2c5), 5352 SH_PFC_FUNCTION(i2c6), 5353 SH_PFC_FUNCTION(intc_ex), 5354 SH_PFC_FUNCTION(msiof0), 5355 SH_PFC_FUNCTION(msiof1), 5356 SH_PFC_FUNCTION(msiof2), 5357 SH_PFC_FUNCTION(msiof3), 5358 SH_PFC_FUNCTION(pwm0), 5359 SH_PFC_FUNCTION(pwm1), 5360 SH_PFC_FUNCTION(pwm2), 5361 SH_PFC_FUNCTION(pwm3), 5362 SH_PFC_FUNCTION(pwm4), 5363 SH_PFC_FUNCTION(pwm5), 5364 SH_PFC_FUNCTION(pwm6), 5365 SH_PFC_FUNCTION(qspi0), 5366 SH_PFC_FUNCTION(qspi1), 5367 SH_PFC_FUNCTION(sata0), 5368 SH_PFC_FUNCTION(scif0), 5369 SH_PFC_FUNCTION(scif1), 5370 SH_PFC_FUNCTION(scif2), 5371 SH_PFC_FUNCTION(scif3), 5372 SH_PFC_FUNCTION(scif4), 5373 SH_PFC_FUNCTION(scif5), 5374 SH_PFC_FUNCTION(scif_clk), 5375 SH_PFC_FUNCTION(sdhi0), 5376 SH_PFC_FUNCTION(sdhi1), 5377 SH_PFC_FUNCTION(sdhi2), 5378 SH_PFC_FUNCTION(sdhi3), 5379 SH_PFC_FUNCTION(ssi), 5380 SH_PFC_FUNCTION(tmu), 5381 SH_PFC_FUNCTION(tpu), 5382 SH_PFC_FUNCTION(usb0), 5383 SH_PFC_FUNCTION(usb1), 5384 SH_PFC_FUNCTION(usb30), 5385 SH_PFC_FUNCTION(vin4), 5386 SH_PFC_FUNCTION(vin5), 5387 }, 5388 #ifdef CONFIG_PINCTRL_PFC_R8A77965 5389 .automotive = { 5390 SH_PFC_FUNCTION(drif0), 5391 SH_PFC_FUNCTION(drif1), 5392 SH_PFC_FUNCTION(drif2), 5393 SH_PFC_FUNCTION(drif3), 5394 } 5395 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ 5396 }; 5397 5398 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5399 #define F_(x, y) FN_##y 5400 #define FM(x) FN_##x 5401 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 5402 0, 0, 5403 0, 0, 5404 0, 0, 5405 0, 0, 5406 0, 0, 5407 0, 0, 5408 0, 0, 5409 0, 0, 5410 0, 0, 5411 0, 0, 5412 0, 0, 5413 0, 0, 5414 0, 0, 5415 0, 0, 5416 0, 0, 5417 0, 0, 5418 GP_0_15_FN, GPSR0_15, 5419 GP_0_14_FN, GPSR0_14, 5420 GP_0_13_FN, GPSR0_13, 5421 GP_0_12_FN, GPSR0_12, 5422 GP_0_11_FN, GPSR0_11, 5423 GP_0_10_FN, GPSR0_10, 5424 GP_0_9_FN, GPSR0_9, 5425 GP_0_8_FN, GPSR0_8, 5426 GP_0_7_FN, GPSR0_7, 5427 GP_0_6_FN, GPSR0_6, 5428 GP_0_5_FN, GPSR0_5, 5429 GP_0_4_FN, GPSR0_4, 5430 GP_0_3_FN, GPSR0_3, 5431 GP_0_2_FN, GPSR0_2, 5432 GP_0_1_FN, GPSR0_1, 5433 GP_0_0_FN, GPSR0_0, )) 5434 }, 5435 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 5436 0, 0, 5437 0, 0, 5438 0, 0, 5439 GP_1_28_FN, GPSR1_28, 5440 GP_1_27_FN, GPSR1_27, 5441 GP_1_26_FN, GPSR1_26, 5442 GP_1_25_FN, GPSR1_25, 5443 GP_1_24_FN, GPSR1_24, 5444 GP_1_23_FN, GPSR1_23, 5445 GP_1_22_FN, GPSR1_22, 5446 GP_1_21_FN, GPSR1_21, 5447 GP_1_20_FN, GPSR1_20, 5448 GP_1_19_FN, GPSR1_19, 5449 GP_1_18_FN, GPSR1_18, 5450 GP_1_17_FN, GPSR1_17, 5451 GP_1_16_FN, GPSR1_16, 5452 GP_1_15_FN, GPSR1_15, 5453 GP_1_14_FN, GPSR1_14, 5454 GP_1_13_FN, GPSR1_13, 5455 GP_1_12_FN, GPSR1_12, 5456 GP_1_11_FN, GPSR1_11, 5457 GP_1_10_FN, GPSR1_10, 5458 GP_1_9_FN, GPSR1_9, 5459 GP_1_8_FN, GPSR1_8, 5460 GP_1_7_FN, GPSR1_7, 5461 GP_1_6_FN, GPSR1_6, 5462 GP_1_5_FN, GPSR1_5, 5463 GP_1_4_FN, GPSR1_4, 5464 GP_1_3_FN, GPSR1_3, 5465 GP_1_2_FN, GPSR1_2, 5466 GP_1_1_FN, GPSR1_1, 5467 GP_1_0_FN, GPSR1_0, )) 5468 }, 5469 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 5470 0, 0, 5471 0, 0, 5472 0, 0, 5473 0, 0, 5474 0, 0, 5475 0, 0, 5476 0, 0, 5477 0, 0, 5478 0, 0, 5479 0, 0, 5480 0, 0, 5481 0, 0, 5482 0, 0, 5483 0, 0, 5484 0, 0, 5485 0, 0, 5486 0, 0, 5487 GP_2_14_FN, GPSR2_14, 5488 GP_2_13_FN, GPSR2_13, 5489 GP_2_12_FN, GPSR2_12, 5490 GP_2_11_FN, GPSR2_11, 5491 GP_2_10_FN, GPSR2_10, 5492 GP_2_9_FN, GPSR2_9, 5493 GP_2_8_FN, GPSR2_8, 5494 GP_2_7_FN, GPSR2_7, 5495 GP_2_6_FN, GPSR2_6, 5496 GP_2_5_FN, GPSR2_5, 5497 GP_2_4_FN, GPSR2_4, 5498 GP_2_3_FN, GPSR2_3, 5499 GP_2_2_FN, GPSR2_2, 5500 GP_2_1_FN, GPSR2_1, 5501 GP_2_0_FN, GPSR2_0, )) 5502 }, 5503 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 5504 0, 0, 5505 0, 0, 5506 0, 0, 5507 0, 0, 5508 0, 0, 5509 0, 0, 5510 0, 0, 5511 0, 0, 5512 0, 0, 5513 0, 0, 5514 0, 0, 5515 0, 0, 5516 0, 0, 5517 0, 0, 5518 0, 0, 5519 0, 0, 5520 GP_3_15_FN, GPSR3_15, 5521 GP_3_14_FN, GPSR3_14, 5522 GP_3_13_FN, GPSR3_13, 5523 GP_3_12_FN, GPSR3_12, 5524 GP_3_11_FN, GPSR3_11, 5525 GP_3_10_FN, GPSR3_10, 5526 GP_3_9_FN, GPSR3_9, 5527 GP_3_8_FN, GPSR3_8, 5528 GP_3_7_FN, GPSR3_7, 5529 GP_3_6_FN, GPSR3_6, 5530 GP_3_5_FN, GPSR3_5, 5531 GP_3_4_FN, GPSR3_4, 5532 GP_3_3_FN, GPSR3_3, 5533 GP_3_2_FN, GPSR3_2, 5534 GP_3_1_FN, GPSR3_1, 5535 GP_3_0_FN, GPSR3_0, )) 5536 }, 5537 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 5538 0, 0, 5539 0, 0, 5540 0, 0, 5541 0, 0, 5542 0, 0, 5543 0, 0, 5544 0, 0, 5545 0, 0, 5546 0, 0, 5547 0, 0, 5548 0, 0, 5549 0, 0, 5550 0, 0, 5551 0, 0, 5552 GP_4_17_FN, GPSR4_17, 5553 GP_4_16_FN, GPSR4_16, 5554 GP_4_15_FN, GPSR4_15, 5555 GP_4_14_FN, GPSR4_14, 5556 GP_4_13_FN, GPSR4_13, 5557 GP_4_12_FN, GPSR4_12, 5558 GP_4_11_FN, GPSR4_11, 5559 GP_4_10_FN, GPSR4_10, 5560 GP_4_9_FN, GPSR4_9, 5561 GP_4_8_FN, GPSR4_8, 5562 GP_4_7_FN, GPSR4_7, 5563 GP_4_6_FN, GPSR4_6, 5564 GP_4_5_FN, GPSR4_5, 5565 GP_4_4_FN, GPSR4_4, 5566 GP_4_3_FN, GPSR4_3, 5567 GP_4_2_FN, GPSR4_2, 5568 GP_4_1_FN, GPSR4_1, 5569 GP_4_0_FN, GPSR4_0, )) 5570 }, 5571 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 5572 0, 0, 5573 0, 0, 5574 0, 0, 5575 0, 0, 5576 0, 0, 5577 0, 0, 5578 GP_5_25_FN, GPSR5_25, 5579 GP_5_24_FN, GPSR5_24, 5580 GP_5_23_FN, GPSR5_23, 5581 GP_5_22_FN, GPSR5_22, 5582 GP_5_21_FN, GPSR5_21, 5583 GP_5_20_FN, GPSR5_20, 5584 GP_5_19_FN, GPSR5_19, 5585 GP_5_18_FN, GPSR5_18, 5586 GP_5_17_FN, GPSR5_17, 5587 GP_5_16_FN, GPSR5_16, 5588 GP_5_15_FN, GPSR5_15, 5589 GP_5_14_FN, GPSR5_14, 5590 GP_5_13_FN, GPSR5_13, 5591 GP_5_12_FN, GPSR5_12, 5592 GP_5_11_FN, GPSR5_11, 5593 GP_5_10_FN, GPSR5_10, 5594 GP_5_9_FN, GPSR5_9, 5595 GP_5_8_FN, GPSR5_8, 5596 GP_5_7_FN, GPSR5_7, 5597 GP_5_6_FN, GPSR5_6, 5598 GP_5_5_FN, GPSR5_5, 5599 GP_5_4_FN, GPSR5_4, 5600 GP_5_3_FN, GPSR5_3, 5601 GP_5_2_FN, GPSR5_2, 5602 GP_5_1_FN, GPSR5_1, 5603 GP_5_0_FN, GPSR5_0, )) 5604 }, 5605 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 5606 GP_6_31_FN, GPSR6_31, 5607 GP_6_30_FN, GPSR6_30, 5608 GP_6_29_FN, GPSR6_29, 5609 GP_6_28_FN, GPSR6_28, 5610 GP_6_27_FN, GPSR6_27, 5611 GP_6_26_FN, GPSR6_26, 5612 GP_6_25_FN, GPSR6_25, 5613 GP_6_24_FN, GPSR6_24, 5614 GP_6_23_FN, GPSR6_23, 5615 GP_6_22_FN, GPSR6_22, 5616 GP_6_21_FN, GPSR6_21, 5617 GP_6_20_FN, GPSR6_20, 5618 GP_6_19_FN, GPSR6_19, 5619 GP_6_18_FN, GPSR6_18, 5620 GP_6_17_FN, GPSR6_17, 5621 GP_6_16_FN, GPSR6_16, 5622 GP_6_15_FN, GPSR6_15, 5623 GP_6_14_FN, GPSR6_14, 5624 GP_6_13_FN, GPSR6_13, 5625 GP_6_12_FN, GPSR6_12, 5626 GP_6_11_FN, GPSR6_11, 5627 GP_6_10_FN, GPSR6_10, 5628 GP_6_9_FN, GPSR6_9, 5629 GP_6_8_FN, GPSR6_8, 5630 GP_6_7_FN, GPSR6_7, 5631 GP_6_6_FN, GPSR6_6, 5632 GP_6_5_FN, GPSR6_5, 5633 GP_6_4_FN, GPSR6_4, 5634 GP_6_3_FN, GPSR6_3, 5635 GP_6_2_FN, GPSR6_2, 5636 GP_6_1_FN, GPSR6_1, 5637 GP_6_0_FN, GPSR6_0, )) 5638 }, 5639 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 5640 0, 0, 5641 0, 0, 5642 0, 0, 5643 0, 0, 5644 0, 0, 5645 0, 0, 5646 0, 0, 5647 0, 0, 5648 0, 0, 5649 0, 0, 5650 0, 0, 5651 0, 0, 5652 0, 0, 5653 0, 0, 5654 0, 0, 5655 0, 0, 5656 0, 0, 5657 0, 0, 5658 0, 0, 5659 0, 0, 5660 0, 0, 5661 0, 0, 5662 0, 0, 5663 0, 0, 5664 0, 0, 5665 0, 0, 5666 0, 0, 5667 0, 0, 5668 GP_7_3_FN, GPSR7_3, 5669 GP_7_2_FN, GPSR7_2, 5670 GP_7_1_FN, GPSR7_1, 5671 GP_7_0_FN, GPSR7_0, )) 5672 }, 5673 #undef F_ 5674 #undef FM 5675 5676 #define F_(x, y) x, 5677 #define FM(x) FN_##x, 5678 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( 5679 IP0_31_28 5680 IP0_27_24 5681 IP0_23_20 5682 IP0_19_16 5683 IP0_15_12 5684 IP0_11_8 5685 IP0_7_4 5686 IP0_3_0 )) 5687 }, 5688 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( 5689 IP1_31_28 5690 IP1_27_24 5691 IP1_23_20 5692 IP1_19_16 5693 IP1_15_12 5694 IP1_11_8 5695 IP1_7_4 5696 IP1_3_0 )) 5697 }, 5698 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( 5699 IP2_31_28 5700 IP2_27_24 5701 IP2_23_20 5702 IP2_19_16 5703 IP2_15_12 5704 IP2_11_8 5705 IP2_7_4 5706 IP2_3_0 )) 5707 }, 5708 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( 5709 IP3_31_28 5710 IP3_27_24 5711 IP3_23_20 5712 IP3_19_16 5713 IP3_15_12 5714 IP3_11_8 5715 IP3_7_4 5716 IP3_3_0 )) 5717 }, 5718 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( 5719 IP4_31_28 5720 IP4_27_24 5721 IP4_23_20 5722 IP4_19_16 5723 IP4_15_12 5724 IP4_11_8 5725 IP4_7_4 5726 IP4_3_0 )) 5727 }, 5728 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( 5729 IP5_31_28 5730 IP5_27_24 5731 IP5_23_20 5732 IP5_19_16 5733 IP5_15_12 5734 IP5_11_8 5735 IP5_7_4 5736 IP5_3_0 )) 5737 }, 5738 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( 5739 IP6_31_28 5740 IP6_27_24 5741 IP6_23_20 5742 IP6_19_16 5743 IP6_15_12 5744 IP6_11_8 5745 IP6_7_4 5746 IP6_3_0 )) 5747 }, 5748 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( 5749 IP7_31_28 5750 IP7_27_24 5751 IP7_23_20 5752 IP7_19_16 5753 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5754 IP7_11_8 5755 IP7_7_4 5756 IP7_3_0 )) 5757 }, 5758 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( 5759 IP8_31_28 5760 IP8_27_24 5761 IP8_23_20 5762 IP8_19_16 5763 IP8_15_12 5764 IP8_11_8 5765 IP8_7_4 5766 IP8_3_0 )) 5767 }, 5768 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( 5769 IP9_31_28 5770 IP9_27_24 5771 IP9_23_20 5772 IP9_19_16 5773 IP9_15_12 5774 IP9_11_8 5775 IP9_7_4 5776 IP9_3_0 )) 5777 }, 5778 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( 5779 IP10_31_28 5780 IP10_27_24 5781 IP10_23_20 5782 IP10_19_16 5783 IP10_15_12 5784 IP10_11_8 5785 IP10_7_4 5786 IP10_3_0 )) 5787 }, 5788 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( 5789 IP11_31_28 5790 IP11_27_24 5791 IP11_23_20 5792 IP11_19_16 5793 IP11_15_12 5794 IP11_11_8 5795 IP11_7_4 5796 IP11_3_0 )) 5797 }, 5798 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( 5799 IP12_31_28 5800 IP12_27_24 5801 IP12_23_20 5802 IP12_19_16 5803 IP12_15_12 5804 IP12_11_8 5805 IP12_7_4 5806 IP12_3_0 )) 5807 }, 5808 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( 5809 IP13_31_28 5810 IP13_27_24 5811 IP13_23_20 5812 IP13_19_16 5813 IP13_15_12 5814 IP13_11_8 5815 IP13_7_4 5816 IP13_3_0 )) 5817 }, 5818 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( 5819 IP14_31_28 5820 IP14_27_24 5821 IP14_23_20 5822 IP14_19_16 5823 IP14_15_12 5824 IP14_11_8 5825 IP14_7_4 5826 IP14_3_0 )) 5827 }, 5828 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( 5829 IP15_31_28 5830 IP15_27_24 5831 IP15_23_20 5832 IP15_19_16 5833 IP15_15_12 5834 IP15_11_8 5835 IP15_7_4 5836 IP15_3_0 )) 5837 }, 5838 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( 5839 IP16_31_28 5840 IP16_27_24 5841 IP16_23_20 5842 IP16_19_16 5843 IP16_15_12 5844 IP16_11_8 5845 IP16_7_4 5846 IP16_3_0 )) 5847 }, 5848 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( 5849 IP17_31_28 5850 IP17_27_24 5851 IP17_23_20 5852 IP17_19_16 5853 IP17_15_12 5854 IP17_11_8 5855 IP17_7_4 5856 IP17_3_0 )) 5857 }, 5858 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( 5859 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5860 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5861 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5862 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5863 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5864 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5865 IP18_7_4 5866 IP18_3_0 )) 5867 }, 5868 #undef F_ 5869 #undef FM 5870 5871 #define F_(x, y) x, 5872 #define FM(x) FN_##x, 5873 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5874 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, 5875 1, 1, 1, 2, 2, 1, 2, 3), 5876 GROUP( 5877 MOD_SEL0_31_30_29 5878 MOD_SEL0_28_27 5879 MOD_SEL0_26_25_24 5880 MOD_SEL0_23 5881 MOD_SEL0_22 5882 MOD_SEL0_21 5883 MOD_SEL0_20 5884 MOD_SEL0_19 5885 MOD_SEL0_18_17 5886 MOD_SEL0_16 5887 0, 0, /* RESERVED 15 */ 5888 MOD_SEL0_14_13 5889 MOD_SEL0_12 5890 MOD_SEL0_11 5891 MOD_SEL0_10 5892 MOD_SEL0_9_8 5893 MOD_SEL0_7_6 5894 MOD_SEL0_5 5895 MOD_SEL0_4_3 5896 /* RESERVED 2, 1, 0 */ 5897 0, 0, 0, 0, 0, 0, 0, 0 )) 5898 }, 5899 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5900 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, 5901 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), 5902 GROUP( 5903 MOD_SEL1_31_30 5904 MOD_SEL1_29_28_27 5905 MOD_SEL1_26 5906 MOD_SEL1_25_24 5907 MOD_SEL1_23_22_21 5908 MOD_SEL1_20 5909 MOD_SEL1_19 5910 MOD_SEL1_18_17 5911 MOD_SEL1_16 5912 MOD_SEL1_15_14 5913 MOD_SEL1_13 5914 MOD_SEL1_12 5915 MOD_SEL1_11 5916 MOD_SEL1_10 5917 MOD_SEL1_9 5918 0, 0, 0, 0, /* RESERVED 8, 7 */ 5919 MOD_SEL1_6 5920 MOD_SEL1_5 5921 MOD_SEL1_4 5922 MOD_SEL1_3 5923 MOD_SEL1_2 5924 MOD_SEL1_1 5925 MOD_SEL1_0 )) 5926 }, 5927 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 5928 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 5929 1, 4, 4, 4, 3, 1), 5930 GROUP( 5931 MOD_SEL2_31 5932 MOD_SEL2_30 5933 MOD_SEL2_29 5934 MOD_SEL2_28_27 5935 MOD_SEL2_26 5936 MOD_SEL2_25_24_23 5937 MOD_SEL2_22 5938 MOD_SEL2_21 5939 MOD_SEL2_20 5940 MOD_SEL2_19 5941 MOD_SEL2_18 5942 MOD_SEL2_17 5943 /* RESERVED 16 */ 5944 0, 0, 5945 /* RESERVED 15, 14, 13, 12 */ 5946 0, 0, 0, 0, 0, 0, 0, 0, 5947 0, 0, 0, 0, 0, 0, 0, 0, 5948 /* RESERVED 11, 10, 9, 8 */ 5949 0, 0, 0, 0, 0, 0, 0, 0, 5950 0, 0, 0, 0, 0, 0, 0, 0, 5951 /* RESERVED 7, 6, 5, 4 */ 5952 0, 0, 0, 0, 0, 0, 0, 0, 5953 0, 0, 0, 0, 0, 0, 0, 0, 5954 /* RESERVED 3, 2, 1 */ 5955 0, 0, 0, 0, 0, 0, 0, 0, 5956 MOD_SEL2_0 )) 5957 }, 5958 { }, 5959 }; 5960 5961 static const struct pinmux_drive_reg pinmux_drive_regs[] = { 5962 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { 5963 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ 5964 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ 5965 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ 5966 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ 5967 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ 5968 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ 5969 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ 5970 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ 5971 } }, 5972 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { 5973 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ 5974 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ 5975 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ 5976 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ 5977 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ 5978 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ 5979 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ 5980 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ 5981 } }, 5982 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { 5983 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ 5984 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ 5985 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ 5986 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ 5987 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ 5988 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ 5989 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ 5990 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ 5991 } }, 5992 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { 5993 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ 5994 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ 5995 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ 5996 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ 5997 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ 5998 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ 5999 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ 6000 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ 6001 } }, 6002 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { 6003 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ 6004 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ 6005 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ 6006 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ 6007 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ 6008 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ 6009 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ 6010 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ 6011 } }, 6012 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { 6013 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ 6014 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ 6015 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ 6016 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ 6017 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ 6018 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ 6019 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ 6020 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ 6021 } }, 6022 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { 6023 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ 6024 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ 6025 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ 6026 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ 6027 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ 6028 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ 6029 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ 6030 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ 6031 } }, 6032 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { 6033 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ 6034 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ 6035 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ 6036 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ 6037 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ 6038 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ 6039 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ 6040 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ 6041 } }, 6042 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { 6043 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ 6044 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ 6045 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ 6046 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ 6047 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ 6048 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ 6049 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ 6050 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ 6051 } }, 6052 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { 6053 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ 6054 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ 6055 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ 6056 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ 6057 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ 6058 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ 6059 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ 6060 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ 6061 } }, 6062 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { 6063 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ 6064 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ 6065 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ 6066 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ 6067 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ 6068 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ 6069 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ 6070 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ 6071 } }, 6072 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { 6073 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ 6074 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 6075 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 6076 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 6077 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ 6078 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ 6079 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ 6080 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ 6081 } }, 6082 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { 6083 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ 6084 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */ 6085 { PIN_TMS, 4, 2 }, /* TMS */ 6086 } }, 6087 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { 6088 { PIN_TDO, 28, 2 }, /* TDO */ 6089 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ 6090 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ 6091 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ 6092 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ 6093 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ 6094 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ 6095 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ 6096 } }, 6097 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { 6098 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ 6099 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ 6100 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ 6101 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ 6102 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ 6103 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ 6104 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ 6105 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ 6106 } }, 6107 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { 6108 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ 6109 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ 6110 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ 6111 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ 6112 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ 6113 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ 6114 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ 6115 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ 6116 } }, 6117 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { 6118 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ 6119 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ 6120 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ 6121 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ 6122 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ 6123 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ 6124 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ 6125 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ 6126 } }, 6127 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { 6128 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ 6129 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ 6130 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ 6131 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ 6132 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ 6133 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ 6134 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ 6135 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 6136 } }, 6137 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 6138 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ 6139 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 6140 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 6141 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 6142 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ 6143 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 6144 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 6145 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 6146 } }, 6147 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { 6148 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ 6149 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ 6150 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ 6151 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ 6152 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ 6153 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ 6154 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ 6155 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ 6156 } }, 6157 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { 6158 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ 6159 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ 6160 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ 6161 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ 6162 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ 6163 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ 6164 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ 6165 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ 6166 } }, 6167 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { 6168 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ 6169 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ 6170 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ 6171 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ 6172 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ 6173 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ 6174 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ 6175 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ 6176 } }, 6177 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { 6178 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ 6179 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ 6180 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ 6181 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ 6182 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ 6183 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ 6184 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ 6185 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ 6186 } }, 6187 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { 6188 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ 6189 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ 6190 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ 6191 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ 6192 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ 6193 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ 6194 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ 6195 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ 6196 } }, 6197 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { 6198 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ 6199 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ 6200 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ 6201 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ 6202 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ 6203 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */ 6204 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */ 6205 } }, 6206 { }, 6207 }; 6208 6209 enum ioctrl_regs { 6210 POCCTRL, 6211 TDSELCTRL, 6212 }; 6213 6214 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 6215 [POCCTRL] = { 0xe6060380, }, 6216 [TDSELCTRL] = { 0xe60603c0, }, 6217 { /* sentinel */ }, 6218 }; 6219 6220 static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 6221 { 6222 int bit = -EINVAL; 6223 6224 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; 6225 6226 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 6227 bit = pin & 0x1f; 6228 6229 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) 6230 bit = (pin & 0x1f) + 12; 6231 6232 return bit; 6233 } 6234 6235 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 6236 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { 6237 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ 6238 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ 6239 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ 6240 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ 6241 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ 6242 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ 6243 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ 6244 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ 6245 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ 6246 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ 6247 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ 6248 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ 6249 [12] = PIN_RPC_INT_N, /* RPC_INT# */ 6250 [13] = PIN_RPC_WP_N, /* RPC_WP# */ 6251 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ 6252 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ 6253 [16] = PIN_AVB_RXC, /* AVB_RXC */ 6254 [17] = PIN_AVB_RD0, /* AVB_RD0 */ 6255 [18] = PIN_AVB_RD1, /* AVB_RD1 */ 6256 [19] = PIN_AVB_RD2, /* AVB_RD2 */ 6257 [20] = PIN_AVB_RD3, /* AVB_RD3 */ 6258 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ 6259 [22] = PIN_AVB_TXC, /* AVB_TXC */ 6260 [23] = PIN_AVB_TD0, /* AVB_TD0 */ 6261 [24] = PIN_AVB_TD1, /* AVB_TD1 */ 6262 [25] = PIN_AVB_TD2, /* AVB_TD2 */ 6263 [26] = PIN_AVB_TD3, /* AVB_TD3 */ 6264 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ 6265 [28] = PIN_AVB_MDIO, /* AVB_MDIO */ 6266 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ 6267 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ 6268 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ 6269 } }, 6270 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { 6271 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ 6272 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ 6273 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ 6274 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ 6275 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ 6276 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ 6277 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ 6278 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ 6279 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ 6280 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ 6281 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ 6282 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ 6283 [12] = RCAR_GP_PIN(1, 0), /* A0 */ 6284 [13] = RCAR_GP_PIN(1, 1), /* A1 */ 6285 [14] = RCAR_GP_PIN(1, 2), /* A2 */ 6286 [15] = RCAR_GP_PIN(1, 3), /* A3 */ 6287 [16] = RCAR_GP_PIN(1, 4), /* A4 */ 6288 [17] = RCAR_GP_PIN(1, 5), /* A5 */ 6289 [18] = RCAR_GP_PIN(1, 6), /* A6 */ 6290 [19] = RCAR_GP_PIN(1, 7), /* A7 */ 6291 [20] = RCAR_GP_PIN(1, 8), /* A8 */ 6292 [21] = RCAR_GP_PIN(1, 9), /* A9 */ 6293 [22] = RCAR_GP_PIN(1, 10), /* A10 */ 6294 [23] = RCAR_GP_PIN(1, 11), /* A11 */ 6295 [24] = RCAR_GP_PIN(1, 12), /* A12 */ 6296 [25] = RCAR_GP_PIN(1, 13), /* A13 */ 6297 [26] = RCAR_GP_PIN(1, 14), /* A14 */ 6298 [27] = RCAR_GP_PIN(1, 15), /* A15 */ 6299 [28] = RCAR_GP_PIN(1, 16), /* A16 */ 6300 [29] = RCAR_GP_PIN(1, 17), /* A17 */ 6301 [30] = RCAR_GP_PIN(1, 18), /* A18 */ 6302 [31] = RCAR_GP_PIN(1, 19), /* A19 */ 6303 } }, 6304 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { 6305 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ 6306 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ 6307 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ 6308 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ 6309 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ 6310 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ 6311 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ 6312 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ 6313 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ 6314 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ 6315 [10] = RCAR_GP_PIN(0, 0), /* D0 */ 6316 [11] = RCAR_GP_PIN(0, 1), /* D1 */ 6317 [12] = RCAR_GP_PIN(0, 2), /* D2 */ 6318 [13] = RCAR_GP_PIN(0, 3), /* D3 */ 6319 [14] = RCAR_GP_PIN(0, 4), /* D4 */ 6320 [15] = RCAR_GP_PIN(0, 5), /* D5 */ 6321 [16] = RCAR_GP_PIN(0, 6), /* D6 */ 6322 [17] = RCAR_GP_PIN(0, 7), /* D7 */ 6323 [18] = RCAR_GP_PIN(0, 8), /* D8 */ 6324 [19] = RCAR_GP_PIN(0, 9), /* D9 */ 6325 [20] = RCAR_GP_PIN(0, 10), /* D10 */ 6326 [21] = RCAR_GP_PIN(0, 11), /* D11 */ 6327 [22] = RCAR_GP_PIN(0, 12), /* D12 */ 6328 [23] = RCAR_GP_PIN(0, 13), /* D13 */ 6329 [24] = RCAR_GP_PIN(0, 14), /* D14 */ 6330 [25] = RCAR_GP_PIN(0, 15), /* D15 */ 6331 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 6332 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 6333 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ 6334 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ 6335 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ 6336 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ 6337 } }, 6338 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 6339 [ 0] = SH_PFC_PIN_NONE, 6340 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ 6341 [ 2] = PIN_FSCLKST, /* FSCLKST */ 6342 [ 3] = PIN_EXTALR, /* EXTALR*/ 6343 [ 4] = PIN_TRST_N, /* TRST# */ 6344 [ 5] = PIN_TCK, /* TCK */ 6345 [ 6] = PIN_TMS, /* TMS */ 6346 [ 7] = PIN_TDI, /* TDI */ 6347 [ 8] = SH_PFC_PIN_NONE, 6348 [ 9] = PIN_ASEBRK, /* ASEBRK */ 6349 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ 6350 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ 6351 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ 6352 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ 6353 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ 6354 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ 6355 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ 6356 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ 6357 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ 6358 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ 6359 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ 6360 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ 6361 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ 6362 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ 6363 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ 6364 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ 6365 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ 6366 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ 6367 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ 6368 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ 6369 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ 6370 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ 6371 } }, 6372 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { 6373 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ 6374 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ 6375 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ 6376 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ 6377 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ 6378 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ 6379 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ 6380 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ 6381 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ 6382 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ 6383 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ 6384 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ 6385 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ 6386 [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 6387 [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 6388 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 6389 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ 6390 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 6391 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 6392 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 6393 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ 6394 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 6395 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 6396 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 6397 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ 6398 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ 6399 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ 6400 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ 6401 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ 6402 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ 6403 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ 6404 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ 6405 } }, 6406 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { 6407 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ 6408 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ 6409 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ 6410 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ 6411 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ 6412 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ 6413 [ 6] = PIN_MLB_REF, /* MLB_REF */ 6414 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ 6415 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ 6416 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ 6417 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ 6418 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ 6419 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ 6420 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ 6421 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ 6422 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ 6423 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ 6424 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ 6425 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ 6426 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ 6427 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ 6428 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ 6429 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ 6430 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ 6431 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ 6432 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ 6433 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ 6434 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ 6435 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ 6436 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ 6437 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ 6438 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ 6439 } }, 6440 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { 6441 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ 6442 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ 6443 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ 6444 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ 6445 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ 6446 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ 6447 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ 6448 [ 7] = SH_PFC_PIN_NONE, 6449 [ 8] = SH_PFC_PIN_NONE, 6450 [ 9] = SH_PFC_PIN_NONE, 6451 [10] = SH_PFC_PIN_NONE, 6452 [11] = SH_PFC_PIN_NONE, 6453 [12] = SH_PFC_PIN_NONE, 6454 [13] = SH_PFC_PIN_NONE, 6455 [14] = SH_PFC_PIN_NONE, 6456 [15] = SH_PFC_PIN_NONE, 6457 [16] = SH_PFC_PIN_NONE, 6458 [17] = SH_PFC_PIN_NONE, 6459 [18] = SH_PFC_PIN_NONE, 6460 [19] = SH_PFC_PIN_NONE, 6461 [20] = SH_PFC_PIN_NONE, 6462 [21] = SH_PFC_PIN_NONE, 6463 [22] = SH_PFC_PIN_NONE, 6464 [23] = SH_PFC_PIN_NONE, 6465 [24] = SH_PFC_PIN_NONE, 6466 [25] = SH_PFC_PIN_NONE, 6467 [26] = SH_PFC_PIN_NONE, 6468 [27] = SH_PFC_PIN_NONE, 6469 [28] = SH_PFC_PIN_NONE, 6470 [29] = SH_PFC_PIN_NONE, 6471 [30] = SH_PFC_PIN_NONE, 6472 [31] = SH_PFC_PIN_NONE, 6473 } }, 6474 { /* sentinel */ }, 6475 }; 6476 6477 static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = { 6478 .pin_to_pocctrl = r8a77965_pin_to_pocctrl, 6479 .get_bias = rcar_pinmux_get_bias, 6480 .set_bias = rcar_pinmux_set_bias, 6481 }; 6482 6483 #ifdef CONFIG_PINCTRL_PFC_R8A774B1 6484 const struct sh_pfc_soc_info r8a774b1_pinmux_info = { 6485 .name = "r8a774b1_pfc", 6486 .ops = &r8a77965_pinmux_ops, 6487 .unlock_reg = 0xe6060000, /* PMMR */ 6488 6489 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6490 6491 .pins = pinmux_pins, 6492 .nr_pins = ARRAY_SIZE(pinmux_pins), 6493 .groups = pinmux_groups.common, 6494 .nr_groups = ARRAY_SIZE(pinmux_groups.common), 6495 .functions = pinmux_functions.common, 6496 .nr_functions = ARRAY_SIZE(pinmux_functions.common), 6497 6498 .cfg_regs = pinmux_config_regs, 6499 .drive_regs = pinmux_drive_regs, 6500 .bias_regs = pinmux_bias_regs, 6501 .ioctrl_regs = pinmux_ioctrl_regs, 6502 6503 .pinmux_data = pinmux_data, 6504 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6505 }; 6506 #endif 6507 6508 #ifdef CONFIG_PINCTRL_PFC_R8A77965 6509 const struct sh_pfc_soc_info r8a77965_pinmux_info = { 6510 .name = "r8a77965_pfc", 6511 .ops = &r8a77965_pinmux_ops, 6512 .unlock_reg = 0xe6060000, /* PMMR */ 6513 6514 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 6515 6516 .pins = pinmux_pins, 6517 .nr_pins = ARRAY_SIZE(pinmux_pins), 6518 .groups = pinmux_groups.common, 6519 .nr_groups = ARRAY_SIZE(pinmux_groups.common) + 6520 ARRAY_SIZE(pinmux_groups.automotive), 6521 .functions = pinmux_functions.common, 6522 .nr_functions = ARRAY_SIZE(pinmux_functions.common) + 6523 ARRAY_SIZE(pinmux_functions.automotive), 6524 6525 .cfg_regs = pinmux_config_regs, 6526 .drive_regs = pinmux_drive_regs, 6527 .bias_regs = pinmux_bias_regs, 6528 .ioctrl_regs = pinmux_ioctrl_regs, 6529 6530 .pinmux_data = pinmux_data, 6531 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 6532 }; 6533 #endif 6534