1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pin Control and GPIO driver for SuperH Pin Function Controller. 4 * 5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart 6 * 7 * Copyright (C) 2008 Magnus Damm 8 * Copyright (C) 2009 - 2012 Paul Mundt 9 */ 10 11 #define DRV_NAME "sh-pfc" 12 13 #include <linux/bitops.h> 14 #include <linux/err.h> 15 #include <linux/errno.h> 16 #include <linux/init.h> 17 #include <linux/io.h> 18 #include <linux/ioport.h> 19 #include <linux/kernel.h> 20 #include <linux/math.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/pinctrl/machine.h> 24 #include <linux/platform_device.h> 25 #include <linux/psci.h> 26 #include <linux/slab.h> 27 #include <linux/sys_soc.h> 28 29 #include "core.h" 30 31 static int sh_pfc_map_resources(struct sh_pfc *pfc, 32 struct platform_device *pdev) 33 { 34 struct sh_pfc_window *windows; 35 unsigned int *irqs = NULL; 36 unsigned int num_windows; 37 struct resource *res; 38 unsigned int i; 39 int num_irqs; 40 41 /* Count the MEM and IRQ resources. */ 42 for (num_windows = 0;; num_windows++) { 43 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows); 44 if (!res) 45 break; 46 } 47 if (num_windows == 0) 48 return -EINVAL; 49 50 num_irqs = platform_irq_count(pdev); 51 if (num_irqs < 0) 52 return num_irqs; 53 54 /* Allocate memory windows and IRQs arrays. */ 55 windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows), 56 GFP_KERNEL); 57 if (windows == NULL) 58 return -ENOMEM; 59 60 pfc->num_windows = num_windows; 61 pfc->windows = windows; 62 63 if (num_irqs) { 64 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs), 65 GFP_KERNEL); 66 if (irqs == NULL) 67 return -ENOMEM; 68 69 pfc->num_irqs = num_irqs; 70 pfc->irqs = irqs; 71 } 72 73 /* Fill them. */ 74 for (i = 0; i < num_windows; i++) { 75 windows->virt = devm_platform_get_and_ioremap_resource(pdev, i, &res); 76 if (IS_ERR(windows->virt)) 77 return -ENOMEM; 78 windows->phys = res->start; 79 windows->size = resource_size(res); 80 windows++; 81 } 82 for (i = 0; i < num_irqs; i++) 83 *irqs++ = platform_get_irq(pdev, i); 84 85 return 0; 86 } 87 88 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg) 89 { 90 struct sh_pfc_window *window; 91 phys_addr_t address = reg; 92 unsigned int i; 93 94 /* scan through physical windows and convert address */ 95 for (i = 0; i < pfc->num_windows; i++) { 96 window = pfc->windows + i; 97 98 if (address < window->phys) 99 continue; 100 101 if (address >= (window->phys + window->size)) 102 continue; 103 104 return window->virt + (address - window->phys); 105 } 106 107 BUG(); 108 return NULL; 109 } 110 111 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) 112 { 113 unsigned int offset; 114 unsigned int i; 115 116 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) { 117 const struct sh_pfc_pin_range *range = &pfc->ranges[i]; 118 119 if (pin <= range->end) 120 return pin >= range->start 121 ? offset + pin - range->start : -1; 122 123 offset += range->end - range->start + 1; 124 } 125 126 return -EINVAL; 127 } 128 129 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r) 130 { 131 if (enum_id < r->begin) 132 return 0; 133 134 if (enum_id > r->end) 135 return 0; 136 137 return 1; 138 } 139 140 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width) 141 { 142 switch (reg_width) { 143 case 8: 144 return ioread8(mapped_reg); 145 case 16: 146 return ioread16(mapped_reg); 147 case 32: 148 return ioread32(mapped_reg); 149 } 150 151 BUG(); 152 return 0; 153 } 154 155 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, 156 u32 data) 157 { 158 switch (reg_width) { 159 case 8: 160 iowrite8(data, mapped_reg); 161 return; 162 case 16: 163 iowrite16(data, mapped_reg); 164 return; 165 case 32: 166 iowrite32(data, mapped_reg); 167 return; 168 } 169 170 BUG(); 171 } 172 173 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg) 174 { 175 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32); 176 } 177 178 static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data) 179 { 180 u32 unlock; 181 182 if (!pfc->info->unlock_reg) 183 return; 184 185 if (pfc->info->unlock_reg >= 0x80000000UL) 186 unlock = pfc->info->unlock_reg; 187 else 188 /* unlock_reg is a mask */ 189 unlock = reg & ~pfc->info->unlock_reg; 190 191 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, unlock), 32, ~data); 192 } 193 194 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data) 195 { 196 sh_pfc_unlock_reg(pfc, reg, data); 197 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data); 198 } 199 200 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, 201 const struct pinmux_cfg_reg *crp, 202 unsigned int in_pos, 203 void __iomem **mapped_regp, u32 *maskp, 204 unsigned int *posp) 205 { 206 unsigned int k; 207 208 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg); 209 210 if (crp->field_width) { 211 *maskp = (1 << crp->field_width) - 1; 212 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); 213 } else { 214 *maskp = (1 << crp->var_field_width[in_pos]) - 1; 215 *posp = crp->reg_width; 216 for (k = 0; k <= in_pos; k++) 217 *posp -= abs(crp->var_field_width[k]); 218 } 219 } 220 221 static void sh_pfc_write_config_reg(struct sh_pfc *pfc, 222 const struct pinmux_cfg_reg *crp, 223 unsigned int field, u32 value) 224 { 225 void __iomem *mapped_reg; 226 unsigned int pos; 227 u32 mask, data; 228 229 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); 230 231 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, " 232 "r_width = %u, f_width = %u\n", 233 crp->reg, value, field, crp->reg_width, hweight32(mask)); 234 235 mask = ~(mask << pos); 236 value = value << pos; 237 238 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width); 239 data &= mask; 240 data |= value; 241 242 sh_pfc_unlock_reg(pfc, crp->reg, data); 243 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); 244 } 245 246 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, 247 const struct pinmux_cfg_reg **crp, 248 unsigned int *fieldp, u32 *valuep) 249 { 250 unsigned int k = 0; 251 252 while (1) { 253 const struct pinmux_cfg_reg *config_reg = 254 pfc->info->cfg_regs + k; 255 unsigned int r_width = config_reg->reg_width; 256 unsigned int f_width = config_reg->field_width; 257 unsigned int curr_width; 258 unsigned int bit_pos; 259 unsigned int pos = 0; 260 unsigned int m = 0; 261 262 if (!r_width) 263 break; 264 265 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width, m++) { 266 u32 ncomb; 267 u32 n; 268 269 if (f_width) { 270 curr_width = f_width; 271 } else { 272 curr_width = abs(config_reg->var_field_width[m]); 273 if (config_reg->var_field_width[m] < 0) 274 continue; 275 } 276 277 ncomb = 1 << curr_width; 278 for (n = 0; n < ncomb; n++) { 279 if (config_reg->enum_ids[pos + n] == enum_id) { 280 *crp = config_reg; 281 *fieldp = m; 282 *valuep = n; 283 return 0; 284 } 285 } 286 pos += ncomb; 287 } 288 k++; 289 } 290 291 return -EINVAL; 292 } 293 294 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, 295 u16 *enum_idp) 296 { 297 const u16 *data = pfc->info->pinmux_data; 298 unsigned int k; 299 300 if (pos) { 301 *enum_idp = data[pos + 1]; 302 return pos + 1; 303 } 304 305 for (k = 0; k < pfc->info->pinmux_data_size; k++) { 306 if (data[k] == mark) { 307 *enum_idp = data[k + 1]; 308 return k + 1; 309 } 310 } 311 312 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n", 313 mark); 314 return -EINVAL; 315 } 316 317 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) 318 { 319 const struct pinmux_range *range; 320 int pos = 0; 321 322 switch (pinmux_type) { 323 case PINMUX_TYPE_GPIO: 324 case PINMUX_TYPE_FUNCTION: 325 range = NULL; 326 break; 327 328 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO 329 case PINMUX_TYPE_OUTPUT: 330 range = &pfc->info->output; 331 break; 332 333 case PINMUX_TYPE_INPUT: 334 range = &pfc->info->input; 335 break; 336 #endif /* CONFIG_PINCTRL_SH_PFC_GPIO */ 337 338 default: 339 return -EINVAL; 340 } 341 342 /* Iterate over all the configuration fields we need to update. */ 343 while (1) { 344 const struct pinmux_cfg_reg *cr; 345 unsigned int field; 346 u16 enum_id; 347 u32 value; 348 int in_range; 349 int ret; 350 351 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); 352 if (pos < 0) 353 return pos; 354 355 if (!enum_id) 356 break; 357 358 /* Check if the configuration field selects a function. If it 359 * doesn't, skip the field if it's not applicable to the 360 * requested pinmux type. 361 */ 362 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); 363 if (!in_range) { 364 if (pinmux_type == PINMUX_TYPE_FUNCTION) { 365 /* Functions are allowed to modify all 366 * fields. 367 */ 368 in_range = 1; 369 } else if (pinmux_type != PINMUX_TYPE_GPIO) { 370 /* Input/output types can only modify fields 371 * that correspond to their respective ranges. 372 */ 373 in_range = sh_pfc_enum_in_range(enum_id, range); 374 375 /* 376 * special case pass through for fixed 377 * input-only or output-only pins without 378 * function enum register association. 379 */ 380 if (in_range && enum_id == range->force) 381 continue; 382 } 383 /* GPIOs are only allowed to modify function fields. */ 384 } 385 386 if (!in_range) 387 continue; 388 389 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value); 390 if (ret < 0) 391 return ret; 392 393 sh_pfc_write_config_reg(pfc, cr, field, value); 394 } 395 396 return 0; 397 } 398 399 static int sh_pfc_init_ranges(struct sh_pfc *pfc) 400 { 401 struct sh_pfc_pin_range *range; 402 unsigned int nr_ranges; 403 unsigned int i; 404 405 if (pfc->info->pins[0].pin == (u16)-1) { 406 /* Pin number -1 denotes that the SoC doesn't report pin numbers 407 * in its pin arrays yet. Consider the pin numbers range as 408 * continuous and allocate a single range. 409 */ 410 pfc->nr_ranges = 1; 411 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges), 412 GFP_KERNEL); 413 if (pfc->ranges == NULL) 414 return -ENOMEM; 415 416 pfc->ranges->start = 0; 417 pfc->ranges->end = pfc->info->nr_pins - 1; 418 pfc->nr_gpio_pins = pfc->info->nr_pins; 419 420 return 0; 421 } 422 423 /* Count, allocate and fill the ranges. The PFC SoC data pins array must 424 * be sorted by pin numbers, and pins without a GPIO port must come 425 * last. 426 */ 427 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) { 428 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) 429 nr_ranges++; 430 } 431 432 pfc->nr_ranges = nr_ranges; 433 pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges), 434 GFP_KERNEL); 435 if (pfc->ranges == NULL) 436 return -ENOMEM; 437 438 range = pfc->ranges; 439 range->start = pfc->info->pins[0].pin; 440 441 for (i = 1; i < pfc->info->nr_pins; ++i) { 442 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1) 443 continue; 444 445 range->end = pfc->info->pins[i-1].pin; 446 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) 447 pfc->nr_gpio_pins = range->end + 1; 448 449 range++; 450 range->start = pfc->info->pins[i].pin; 451 } 452 453 range->end = pfc->info->pins[i-1].pin; 454 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) 455 pfc->nr_gpio_pins = range->end + 1; 456 457 return 0; 458 } 459 460 #ifdef CONFIG_OF 461 static const struct of_device_id sh_pfc_of_table[] = { 462 #ifdef CONFIG_PINCTRL_PFC_EMEV2 463 { 464 .compatible = "renesas,pfc-emev2", 465 .data = &emev2_pinmux_info, 466 }, 467 #endif 468 #ifdef CONFIG_PINCTRL_PFC_R8A73A4 469 { 470 .compatible = "renesas,pfc-r8a73a4", 471 .data = &r8a73a4_pinmux_info, 472 }, 473 #endif 474 #ifdef CONFIG_PINCTRL_PFC_R8A7740 475 { 476 .compatible = "renesas,pfc-r8a7740", 477 .data = &r8a7740_pinmux_info, 478 }, 479 #endif 480 #ifdef CONFIG_PINCTRL_PFC_R8A7742 481 { 482 .compatible = "renesas,pfc-r8a7742", 483 .data = &r8a7742_pinmux_info, 484 }, 485 #endif 486 #ifdef CONFIG_PINCTRL_PFC_R8A7743 487 { 488 .compatible = "renesas,pfc-r8a7743", 489 .data = &r8a7743_pinmux_info, 490 }, 491 #endif 492 #ifdef CONFIG_PINCTRL_PFC_R8A7744 493 { 494 .compatible = "renesas,pfc-r8a7744", 495 .data = &r8a7744_pinmux_info, 496 }, 497 #endif 498 #ifdef CONFIG_PINCTRL_PFC_R8A7745 499 { 500 .compatible = "renesas,pfc-r8a7745", 501 .data = &r8a7745_pinmux_info, 502 }, 503 #endif 504 #ifdef CONFIG_PINCTRL_PFC_R8A77470 505 { 506 .compatible = "renesas,pfc-r8a77470", 507 .data = &r8a77470_pinmux_info, 508 }, 509 #endif 510 #ifdef CONFIG_PINCTRL_PFC_R8A774A1 511 { 512 .compatible = "renesas,pfc-r8a774a1", 513 .data = &r8a774a1_pinmux_info, 514 }, 515 #endif 516 #ifdef CONFIG_PINCTRL_PFC_R8A774B1 517 { 518 .compatible = "renesas,pfc-r8a774b1", 519 .data = &r8a774b1_pinmux_info, 520 }, 521 #endif 522 #ifdef CONFIG_PINCTRL_PFC_R8A774C0 523 { 524 .compatible = "renesas,pfc-r8a774c0", 525 .data = &r8a774c0_pinmux_info, 526 }, 527 #endif 528 #ifdef CONFIG_PINCTRL_PFC_R8A774E1 529 { 530 .compatible = "renesas,pfc-r8a774e1", 531 .data = &r8a774e1_pinmux_info, 532 }, 533 #endif 534 #ifdef CONFIG_PINCTRL_PFC_R8A7778 535 { 536 .compatible = "renesas,pfc-r8a7778", 537 .data = &r8a7778_pinmux_info, 538 }, 539 #endif 540 #ifdef CONFIG_PINCTRL_PFC_R8A7779 541 { 542 .compatible = "renesas,pfc-r8a7779", 543 .data = &r8a7779_pinmux_info, 544 }, 545 #endif 546 #ifdef CONFIG_PINCTRL_PFC_R8A7790 547 { 548 .compatible = "renesas,pfc-r8a7790", 549 .data = &r8a7790_pinmux_info, 550 }, 551 #endif 552 #ifdef CONFIG_PINCTRL_PFC_R8A7791 553 { 554 .compatible = "renesas,pfc-r8a7791", 555 .data = &r8a7791_pinmux_info, 556 }, 557 #endif 558 #ifdef CONFIG_PINCTRL_PFC_R8A7792 559 { 560 .compatible = "renesas,pfc-r8a7792", 561 .data = &r8a7792_pinmux_info, 562 }, 563 #endif 564 #ifdef CONFIG_PINCTRL_PFC_R8A7793 565 { 566 .compatible = "renesas,pfc-r8a7793", 567 .data = &r8a7793_pinmux_info, 568 }, 569 #endif 570 #ifdef CONFIG_PINCTRL_PFC_R8A7794 571 { 572 .compatible = "renesas,pfc-r8a7794", 573 .data = &r8a7794_pinmux_info, 574 }, 575 #endif 576 #ifdef CONFIG_PINCTRL_PFC_R8A77951 577 { 578 .compatible = "renesas,pfc-r8a7795", 579 .data = &r8a77951_pinmux_info, 580 }, 581 #endif 582 #ifdef CONFIG_PINCTRL_PFC_R8A77960 583 { 584 .compatible = "renesas,pfc-r8a7796", 585 .data = &r8a77960_pinmux_info, 586 }, 587 #endif 588 #ifdef CONFIG_PINCTRL_PFC_R8A77961 589 { 590 .compatible = "renesas,pfc-r8a77961", 591 .data = &r8a77961_pinmux_info, 592 }, 593 #endif 594 #ifdef CONFIG_PINCTRL_PFC_R8A77965 595 { 596 .compatible = "renesas,pfc-r8a77965", 597 .data = &r8a77965_pinmux_info, 598 }, 599 #endif 600 #ifdef CONFIG_PINCTRL_PFC_R8A77970 601 { 602 .compatible = "renesas,pfc-r8a77970", 603 .data = &r8a77970_pinmux_info, 604 }, 605 #endif 606 #ifdef CONFIG_PINCTRL_PFC_R8A77980 607 { 608 .compatible = "renesas,pfc-r8a77980", 609 .data = &r8a77980_pinmux_info, 610 }, 611 #endif 612 #ifdef CONFIG_PINCTRL_PFC_R8A77990 613 { 614 .compatible = "renesas,pfc-r8a77990", 615 .data = &r8a77990_pinmux_info, 616 }, 617 #endif 618 #ifdef CONFIG_PINCTRL_PFC_R8A77995 619 { 620 .compatible = "renesas,pfc-r8a77995", 621 .data = &r8a77995_pinmux_info, 622 }, 623 #endif 624 #ifdef CONFIG_PINCTRL_PFC_R8A779A0 625 { 626 .compatible = "renesas,pfc-r8a779a0", 627 .data = &r8a779a0_pinmux_info, 628 }, 629 #endif 630 #ifdef CONFIG_PINCTRL_PFC_R8A779F0 631 { 632 .compatible = "renesas,pfc-r8a779f0", 633 .data = &r8a779f0_pinmux_info, 634 }, 635 #endif 636 #ifdef CONFIG_PINCTRL_PFC_R8A779G0 637 { 638 .compatible = "renesas,pfc-r8a779g0", 639 .data = &r8a779g0_pinmux_info, 640 }, 641 #endif 642 #ifdef CONFIG_PINCTRL_PFC_SH73A0 643 { 644 .compatible = "renesas,pfc-sh73a0", 645 .data = &sh73a0_pinmux_info, 646 }, 647 #endif 648 { /* sentinel */ } 649 }; 650 #endif 651 652 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW) 653 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) 654 { 655 } 656 657 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) 658 { 659 pfc->saved_regs[idx] = sh_pfc_read(pfc, reg); 660 } 661 662 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) 663 { 664 sh_pfc_write(pfc, reg, pfc->saved_regs[idx]); 665 } 666 667 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc, 668 void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx)) 669 { 670 unsigned int i, n = 0; 671 672 if (pfc->info->cfg_regs) 673 for (i = 0; pfc->info->cfg_regs[i].reg; i++) 674 do_reg(pfc, pfc->info->cfg_regs[i].reg, n++); 675 676 if (pfc->info->drive_regs) 677 for (i = 0; pfc->info->drive_regs[i].reg; i++) 678 do_reg(pfc, pfc->info->drive_regs[i].reg, n++); 679 680 if (pfc->info->bias_regs) 681 for (i = 0; pfc->info->bias_regs[i].puen || 682 pfc->info->bias_regs[i].pud; i++) { 683 if (pfc->info->bias_regs[i].puen) 684 do_reg(pfc, pfc->info->bias_regs[i].puen, n++); 685 if (pfc->info->bias_regs[i].pud) 686 do_reg(pfc, pfc->info->bias_regs[i].pud, n++); 687 } 688 689 if (pfc->info->ioctrl_regs) 690 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++) 691 do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++); 692 693 return n; 694 } 695 696 static int sh_pfc_suspend_init(struct sh_pfc *pfc) 697 { 698 unsigned int n; 699 700 /* This is the best we can do to check for the presence of PSCI */ 701 if (!psci_ops.cpu_suspend) 702 return 0; 703 704 n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg); 705 if (!n) 706 return 0; 707 708 pfc->saved_regs = devm_kmalloc_array(pfc->dev, n, 709 sizeof(*pfc->saved_regs), 710 GFP_KERNEL); 711 if (!pfc->saved_regs) 712 return -ENOMEM; 713 714 dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n); 715 return 0; 716 } 717 718 static int sh_pfc_suspend_noirq(struct device *dev) 719 { 720 struct sh_pfc *pfc = dev_get_drvdata(dev); 721 722 if (pfc->saved_regs) 723 sh_pfc_walk_regs(pfc, sh_pfc_save_reg); 724 return 0; 725 } 726 727 static int sh_pfc_resume_noirq(struct device *dev) 728 { 729 struct sh_pfc *pfc = dev_get_drvdata(dev); 730 731 if (pfc->saved_regs) 732 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg); 733 return 0; 734 } 735 736 static const struct dev_pm_ops sh_pfc_pm = { 737 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq) 738 }; 739 #define DEV_PM_OPS &sh_pfc_pm 740 #else 741 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } 742 #define DEV_PM_OPS NULL 743 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ 744 745 #ifdef DEBUG 746 #define SH_PFC_MAX_REGS 300 747 #define SH_PFC_MAX_ENUMS 5000 748 749 static unsigned int sh_pfc_errors __initdata; 750 static unsigned int sh_pfc_warnings __initdata; 751 static bool sh_pfc_bias_done __initdata; 752 static bool sh_pfc_drive_done __initdata; 753 static bool sh_pfc_power_done __initdata; 754 static struct { 755 u32 reg; 756 u32 bits; 757 } *sh_pfc_regs __initdata; 758 static u32 sh_pfc_num_regs __initdata; 759 static u16 *sh_pfc_enums __initdata; 760 static u32 sh_pfc_num_enums __initdata; 761 762 #define sh_pfc_err(fmt, ...) \ 763 do { \ 764 pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \ 765 sh_pfc_errors++; \ 766 } while (0) 767 768 #define sh_pfc_err_once(type, fmt, ...) \ 769 do { \ 770 if (!sh_pfc_ ## type ## _done) { \ 771 sh_pfc_ ## type ## _done = true; \ 772 sh_pfc_err(fmt, ##__VA_ARGS__); \ 773 } \ 774 } while (0) 775 776 #define sh_pfc_warn(fmt, ...) \ 777 do { \ 778 pr_warn("%s: " fmt, drvname, ##__VA_ARGS__); \ 779 sh_pfc_warnings++; \ 780 } while (0) 781 782 static bool __init is0s(const u16 *enum_ids, unsigned int n) 783 { 784 unsigned int i; 785 786 for (i = 0; i < n; i++) 787 if (enum_ids[i]) 788 return false; 789 790 return true; 791 } 792 793 static bool __init same_name(const char *a, const char *b) 794 { 795 return a && b && !strcmp(a, b); 796 } 797 798 static void __init sh_pfc_check_reg(const char *drvname, u32 reg, u32 bits) 799 { 800 unsigned int i; 801 802 for (i = 0; i < sh_pfc_num_regs; i++) { 803 if (reg != sh_pfc_regs[i].reg) 804 continue; 805 806 if (bits & sh_pfc_regs[i].bits) 807 sh_pfc_err("reg 0x%x: bits 0x%x conflict\n", reg, 808 bits & sh_pfc_regs[i].bits); 809 810 sh_pfc_regs[i].bits |= bits; 811 return; 812 } 813 814 if (sh_pfc_num_regs == SH_PFC_MAX_REGS) { 815 pr_warn_once("%s: Please increase SH_PFC_MAX_REGS\n", drvname); 816 return; 817 } 818 819 sh_pfc_regs[sh_pfc_num_regs].reg = reg; 820 sh_pfc_regs[sh_pfc_num_regs].bits = bits; 821 sh_pfc_num_regs++; 822 } 823 824 static int __init sh_pfc_check_enum(const char *drvname, u16 enum_id) 825 { 826 unsigned int i; 827 828 for (i = 0; i < sh_pfc_num_enums; i++) { 829 if (enum_id == sh_pfc_enums[i]) 830 return -EINVAL; 831 } 832 833 if (sh_pfc_num_enums == SH_PFC_MAX_ENUMS) { 834 pr_warn_once("%s: Please increase SH_PFC_MAX_ENUMS\n", drvname); 835 return 0; 836 } 837 838 sh_pfc_enums[sh_pfc_num_enums++] = enum_id; 839 return 0; 840 } 841 842 static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg, 843 const u16 *enums, unsigned int n) 844 { 845 unsigned int i; 846 847 for (i = 0; i < n; i++) { 848 if (enums[i] && sh_pfc_check_enum(drvname, enums[i])) 849 sh_pfc_err("reg 0x%x enum_id %u conflict\n", reg, 850 enums[i]); 851 } 852 } 853 854 static const struct sh_pfc_pin __init *sh_pfc_find_pin( 855 const struct sh_pfc_soc_info *info, u32 reg, unsigned int pin) 856 { 857 const char *drvname = info->name; 858 unsigned int i; 859 860 if (pin == SH_PFC_PIN_NONE) 861 return NULL; 862 863 for (i = 0; i < info->nr_pins; i++) { 864 if (pin == info->pins[i].pin) 865 return &info->pins[i]; 866 } 867 868 sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin); 869 return NULL; 870 } 871 872 static void __init sh_pfc_check_cfg_reg(const char *drvname, 873 const struct pinmux_cfg_reg *cfg_reg) 874 { 875 unsigned int i, n, rw, r; 876 int fw; 877 878 sh_pfc_check_reg(drvname, cfg_reg->reg, 879 GENMASK(cfg_reg->reg_width - 1, 0)); 880 881 if (cfg_reg->field_width) { 882 fw = cfg_reg->field_width; 883 n = (cfg_reg->reg_width / fw) << fw; 884 for (i = 0, r = 0; i < n; i += 1 << fw) { 885 if (is0s(&cfg_reg->enum_ids[i], 1 << fw)) 886 r++; 887 } 888 889 if ((r << fw) * sizeof(u16) > cfg_reg->reg_width / fw) 890 sh_pfc_warn("reg 0x%x can be described with variable-width reserved fields\n", 891 cfg_reg->reg); 892 893 /* Skip field checks (done at build time) */ 894 goto check_enum_ids; 895 } 896 897 for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) { 898 if (fw < 0) { 899 rw += -fw; 900 } else { 901 if (is0s(&cfg_reg->enum_ids[n], 1 << fw)) 902 sh_pfc_warn("reg 0x%x: field [%u:%u] can be described as reserved\n", 903 cfg_reg->reg, rw, rw + fw - 1); 904 n += 1 << fw; 905 rw += fw; 906 } 907 } 908 909 if (rw != cfg_reg->reg_width) 910 sh_pfc_err("reg 0x%x: var_field_width declares %u instead of %u bits\n", 911 cfg_reg->reg, rw, cfg_reg->reg_width); 912 913 if (n != cfg_reg->nr_enum_ids) 914 sh_pfc_err("reg 0x%x: enum_ids[] has %u instead of %u values\n", 915 cfg_reg->reg, cfg_reg->nr_enum_ids, n); 916 917 check_enum_ids: 918 sh_pfc_check_reg_enums(drvname, cfg_reg->reg, cfg_reg->enum_ids, n); 919 } 920 921 static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info, 922 const struct pinmux_drive_reg *drive) 923 { 924 const char *drvname = info->name; 925 const struct sh_pfc_pin *pin; 926 unsigned int i; 927 928 for (i = 0; i < ARRAY_SIZE(drive->fields); i++) { 929 const struct pinmux_drive_reg_field *field = &drive->fields[i]; 930 931 if (!field->pin && !field->offset && !field->size) 932 continue; 933 934 sh_pfc_check_reg(info->name, drive->reg, 935 GENMASK(field->offset + field->size - 1, 936 field->offset)); 937 938 pin = sh_pfc_find_pin(info, drive->reg, field->pin); 939 if (pin && !(pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH)) 940 sh_pfc_err("drive_reg 0x%x: field %u: pin %s lacks SH_PFC_PIN_CFG_DRIVE_STRENGTH flag\n", 941 drive->reg, i, pin->name); 942 } 943 } 944 945 static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info, 946 const struct pinmux_bias_reg *bias) 947 { 948 const char *drvname = info->name; 949 const struct sh_pfc_pin *pin; 950 unsigned int i; 951 u32 bits; 952 953 for (i = 0, bits = 0; i < ARRAY_SIZE(bias->pins); i++) 954 if (bias->pins[i] != SH_PFC_PIN_NONE) 955 bits |= BIT(i); 956 957 if (bias->puen) 958 sh_pfc_check_reg(info->name, bias->puen, bits); 959 if (bias->pud) 960 sh_pfc_check_reg(info->name, bias->pud, bits); 961 for (i = 0; i < ARRAY_SIZE(bias->pins); i++) { 962 pin = sh_pfc_find_pin(info, bias->puen, bias->pins[i]); 963 if (!pin) 964 continue; 965 966 if (bias->puen && bias->pud) { 967 /* 968 * Pull-enable and pull-up/down control registers 969 * As some SoCs have pins that support only pull-up 970 * or pull-down, we just check for one of them 971 */ 972 if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN)) 973 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks one or more SH_PFC_PIN_CFG_PULL_* flags\n", 974 bias->puen, i, pin->name); 975 } else if (bias->puen) { 976 /* Pull-up control register only */ 977 if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP)) 978 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_UP flag\n", 979 bias->puen, i, pin->name); 980 } else if (bias->pud) { 981 /* Pull-down control register only */ 982 if (!(pin->configs & SH_PFC_PIN_CFG_PULL_DOWN)) 983 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_DOWN flag\n", 984 bias->pud, i, pin->name); 985 } 986 } 987 } 988 989 static void __init sh_pfc_compare_groups(const char *drvname, 990 const struct sh_pfc_pin_group *a, 991 const struct sh_pfc_pin_group *b) 992 { 993 unsigned int i; 994 size_t len; 995 996 if (same_name(a->name, b->name)) 997 sh_pfc_err("group %s: name conflict\n", a->name); 998 999 if (a->nr_pins > b->nr_pins) 1000 swap(a, b); 1001 1002 len = a->nr_pins * sizeof(a->pins[0]); 1003 for (i = 0; i <= b->nr_pins - a->nr_pins; i++) { 1004 if (a->pins == b->pins + i || a->mux == b->mux + i || 1005 memcmp(a->pins, b->pins + i, len) || 1006 memcmp(a->mux, b->mux + i, len)) 1007 continue; 1008 1009 if (a->nr_pins == b->nr_pins) 1010 sh_pfc_warn("group %s can be an alias for %s\n", 1011 a->name, b->name); 1012 else 1013 sh_pfc_warn("group %s is a subset of %s\n", a->name, 1014 b->name); 1015 } 1016 } 1017 1018 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) 1019 { 1020 const struct pinmux_drive_reg *drive_regs = info->drive_regs; 1021 #define drive_nfields ARRAY_SIZE(drive_regs->fields) 1022 #define drive_ofs(i) drive_regs[(i) / drive_nfields] 1023 #define drive_reg(i) drive_ofs(i).reg 1024 #define drive_bit(i) ((i) % drive_nfields) 1025 #define drive_field(i) drive_ofs(i).fields[drive_bit(i)] 1026 const struct pinmux_bias_reg *bias_regs = info->bias_regs; 1027 #define bias_npins ARRAY_SIZE(bias_regs->pins) 1028 #define bias_ofs(i) bias_regs[(i) / bias_npins] 1029 #define bias_puen(i) bias_ofs(i).puen 1030 #define bias_pud(i) bias_ofs(i).pud 1031 #define bias_bit(i) ((i) % bias_npins) 1032 #define bias_pin(i) bias_ofs(i).pins[bias_bit(i)] 1033 const char *drvname = info->name; 1034 unsigned int *refcnts; 1035 unsigned int i, j, k; 1036 1037 pr_info("sh_pfc: Checking %s\n", drvname); 1038 sh_pfc_num_regs = 0; 1039 sh_pfc_num_enums = 0; 1040 sh_pfc_bias_done = false; 1041 sh_pfc_drive_done = false; 1042 sh_pfc_power_done = false; 1043 1044 /* Check pins */ 1045 for (i = 0; i < info->nr_pins; i++) { 1046 const struct sh_pfc_pin *pin = &info->pins[i]; 1047 unsigned int x; 1048 1049 if (!pin->name) { 1050 sh_pfc_err("empty pin %u\n", i); 1051 continue; 1052 } 1053 for (j = 0; j < i; j++) { 1054 const struct sh_pfc_pin *pin2 = &info->pins[j]; 1055 1056 if (same_name(pin->name, pin2->name)) 1057 sh_pfc_err("pin %s: name conflict\n", 1058 pin->name); 1059 1060 if (pin->pin != (u16)-1 && pin->pin == pin2->pin) 1061 sh_pfc_err("pin %s/%s: pin %u conflict\n", 1062 pin->name, pin2->name, pin->pin); 1063 1064 if (pin->enum_id && pin->enum_id == pin2->enum_id) 1065 sh_pfc_err("pin %s/%s: enum_id %u conflict\n", 1066 pin->name, pin2->name, 1067 pin->enum_id); 1068 } 1069 1070 if (pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) { 1071 if (!info->ops || !info->ops->get_bias || 1072 !info->ops->set_bias) 1073 sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_* flag set but .[gs]et_bias() not implemented\n"); 1074 1075 if (!bias_regs && 1076 (!info->ops || !info->ops->pin_to_portcr)) 1077 sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_UP flag set but no bias_regs defined and .pin_to_portcr() not implemented\n"); 1078 } 1079 1080 if ((pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) && bias_regs) { 1081 const struct pinmux_bias_reg *bias_reg = 1082 rcar_pin_to_bias_reg(info, pin->pin, &x); 1083 1084 if (!bias_reg || 1085 ((pin->configs & SH_PFC_PIN_CFG_PULL_UP) && 1086 !bias_reg->puen)) 1087 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_UP flag set but pin not in bias_regs\n", 1088 pin->name); 1089 1090 if (!bias_reg || 1091 ((pin->configs & SH_PFC_PIN_CFG_PULL_DOWN) && 1092 !bias_reg->pud)) 1093 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_DOWN flag set but pin not in bias_regs\n", 1094 pin->name); 1095 } 1096 1097 if (pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH) { 1098 if (!drive_regs) { 1099 sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n"); 1100 } else { 1101 for (j = 0; drive_reg(j); j++) { 1102 if (!drive_field(j).pin && 1103 !drive_field(j).offset && 1104 !drive_field(j).size) 1105 continue; 1106 1107 if (drive_field(j).pin == pin->pin) 1108 break; 1109 } 1110 1111 if (!drive_reg(j)) 1112 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n", 1113 pin->name); 1114 } 1115 } 1116 1117 if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK) { 1118 if (!info->ops || !info->ops->pin_to_pocctrl) 1119 sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE set but .pin_to_pocctrl() not implemented\n"); 1120 else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0) 1121 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n", 1122 pin->name); 1123 } else if (info->ops && info->ops->pin_to_pocctrl && 1124 info->ops->pin_to_pocctrl(pin->pin, &x) >= 0) { 1125 sh_pfc_warn("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE not set but valid pin_to_pocctrl()\n", 1126 pin->name); 1127 } 1128 } 1129 1130 /* Check groups and functions */ 1131 refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL); 1132 if (!refcnts) 1133 return; 1134 1135 for (i = 0; i < info->nr_functions; i++) { 1136 const struct sh_pfc_function *func = &info->functions[i]; 1137 1138 if (!func->name) { 1139 sh_pfc_err("empty function %u\n", i); 1140 continue; 1141 } 1142 for (j = 0; j < i; j++) { 1143 if (same_name(func->name, info->functions[j].name)) 1144 sh_pfc_err("function %s: name conflict\n", 1145 func->name); 1146 } 1147 for (j = 0; j < func->nr_groups; j++) { 1148 for (k = 0; k < info->nr_groups; k++) { 1149 if (same_name(func->groups[j], 1150 info->groups[k].name)) { 1151 refcnts[k]++; 1152 break; 1153 } 1154 } 1155 1156 if (k == info->nr_groups) 1157 sh_pfc_err("function %s: group %s not found\n", 1158 func->name, func->groups[j]); 1159 } 1160 } 1161 1162 for (i = 0; i < info->nr_groups; i++) { 1163 const struct sh_pfc_pin_group *group = &info->groups[i]; 1164 1165 if (!group->name) { 1166 sh_pfc_err("empty group %u\n", i); 1167 continue; 1168 } 1169 for (j = 0; j < i; j++) 1170 sh_pfc_compare_groups(drvname, group, &info->groups[j]); 1171 1172 if (!refcnts[i]) 1173 sh_pfc_err("orphan group %s\n", group->name); 1174 else if (refcnts[i] > 1) 1175 sh_pfc_warn("group %s referenced by %u functions\n", 1176 group->name, refcnts[i]); 1177 } 1178 1179 kfree(refcnts); 1180 1181 /* Check config register descriptions */ 1182 for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++) 1183 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]); 1184 1185 /* Check drive strength registers */ 1186 for (i = 0; drive_regs && drive_regs[i].reg; i++) 1187 sh_pfc_check_drive_reg(info, &drive_regs[i]); 1188 1189 for (i = 0; drive_regs && drive_reg(i); i++) { 1190 if (!drive_field(i).pin && !drive_field(i).offset && 1191 !drive_field(i).size) 1192 continue; 1193 1194 for (j = 0; j < i; j++) { 1195 if (drive_field(i).pin == drive_field(j).pin && 1196 drive_field(j).offset && drive_field(j).size) { 1197 sh_pfc_err("drive_reg 0x%x:%zu/0x%x:%zu: pin conflict\n", 1198 drive_reg(i), drive_bit(i), 1199 drive_reg(j), drive_bit(j)); 1200 } 1201 } 1202 } 1203 1204 /* Check bias registers */ 1205 for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++) 1206 sh_pfc_check_bias_reg(info, &bias_regs[i]); 1207 1208 for (i = 0; bias_regs && (bias_puen(i) || bias_pud(i)); i++) { 1209 if (bias_pin(i) == SH_PFC_PIN_NONE) 1210 continue; 1211 1212 for (j = 0; j < i; j++) { 1213 if (bias_pin(i) != bias_pin(j)) 1214 continue; 1215 1216 if (bias_puen(i) && bias_puen(j)) 1217 sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n", 1218 bias_puen(i), bias_bit(i), 1219 bias_puen(j), bias_bit(j)); 1220 if (bias_pud(i) && bias_pud(j)) 1221 sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n", 1222 bias_pud(i), bias_bit(i), 1223 bias_pud(j), bias_bit(j)); 1224 } 1225 } 1226 1227 /* Check ioctrl registers */ 1228 for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++) 1229 sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX); 1230 1231 /* Check data registers */ 1232 for (i = 0; info->data_regs && info->data_regs[i].reg; i++) { 1233 sh_pfc_check_reg(drvname, info->data_regs[i].reg, 1234 GENMASK(info->data_regs[i].reg_width - 1, 0)); 1235 sh_pfc_check_reg_enums(drvname, info->data_regs[i].reg, 1236 info->data_regs[i].enum_ids, 1237 info->data_regs[i].reg_width); 1238 } 1239 1240 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO 1241 /* Check function GPIOs */ 1242 for (i = 0; i < info->nr_func_gpios; i++) { 1243 const struct pinmux_func *func = &info->func_gpios[i]; 1244 1245 if (!func->name) { 1246 sh_pfc_err("empty function gpio %u\n", i); 1247 continue; 1248 } 1249 for (j = 0; j < i; j++) { 1250 if (same_name(func->name, info->func_gpios[j].name)) 1251 sh_pfc_err("func_gpio %s: name conflict\n", 1252 func->name); 1253 } 1254 if (sh_pfc_check_enum(drvname, func->enum_id)) 1255 sh_pfc_err("%s enum_id %u conflict\n", func->name, 1256 func->enum_id); 1257 } 1258 #endif 1259 } 1260 1261 static void __init sh_pfc_check_driver(const struct platform_driver *pdrv) 1262 { 1263 unsigned int i; 1264 1265 if (!IS_ENABLED(CONFIG_SUPERH) && 1266 !of_find_matching_node(NULL, pdrv->driver.of_match_table)) 1267 return; 1268 1269 sh_pfc_regs = kcalloc(SH_PFC_MAX_REGS, sizeof(*sh_pfc_regs), 1270 GFP_KERNEL); 1271 if (!sh_pfc_regs) 1272 return; 1273 1274 sh_pfc_enums = kcalloc(SH_PFC_MAX_ENUMS, sizeof(*sh_pfc_enums), 1275 GFP_KERNEL); 1276 if (!sh_pfc_enums) 1277 goto free_regs; 1278 1279 pr_warn("sh_pfc: Checking builtin pinmux tables\n"); 1280 1281 for (i = 0; pdrv->id_table[i].name[0]; i++) 1282 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data); 1283 1284 #ifdef CONFIG_OF 1285 for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++) 1286 sh_pfc_check_info(pdrv->driver.of_match_table[i].data); 1287 #endif 1288 1289 pr_warn("sh_pfc: Detected %u errors and %u warnings\n", sh_pfc_errors, 1290 sh_pfc_warnings); 1291 1292 kfree(sh_pfc_enums); 1293 free_regs: 1294 kfree(sh_pfc_regs); 1295 } 1296 1297 #else /* !DEBUG */ 1298 static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {} 1299 #endif /* !DEBUG */ 1300 1301 static int sh_pfc_probe(struct platform_device *pdev) 1302 { 1303 const struct sh_pfc_soc_info *info; 1304 struct sh_pfc *pfc; 1305 int ret; 1306 1307 if (pdev->dev.of_node) 1308 info = of_device_get_match_data(&pdev->dev); 1309 else 1310 info = (const void *)platform_get_device_id(pdev)->driver_data; 1311 1312 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL); 1313 if (pfc == NULL) 1314 return -ENOMEM; 1315 1316 pfc->info = info; 1317 pfc->dev = &pdev->dev; 1318 1319 ret = sh_pfc_map_resources(pfc, pdev); 1320 if (unlikely(ret < 0)) 1321 return ret; 1322 1323 spin_lock_init(&pfc->lock); 1324 1325 if (info->ops && info->ops->init) { 1326 ret = info->ops->init(pfc); 1327 if (ret < 0) 1328 return ret; 1329 1330 /* .init() may have overridden pfc->info */ 1331 info = pfc->info; 1332 } 1333 1334 ret = sh_pfc_suspend_init(pfc); 1335 if (ret) 1336 return ret; 1337 1338 /* Enable dummy states for those platforms without pinctrl support */ 1339 if (!of_have_populated_dt()) 1340 pinctrl_provide_dummies(); 1341 1342 ret = sh_pfc_init_ranges(pfc); 1343 if (ret < 0) 1344 return ret; 1345 1346 /* 1347 * Initialize pinctrl bindings first 1348 */ 1349 ret = sh_pfc_register_pinctrl(pfc); 1350 if (unlikely(ret != 0)) 1351 return ret; 1352 1353 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO 1354 /* 1355 * Then the GPIO chip 1356 */ 1357 ret = sh_pfc_register_gpiochip(pfc); 1358 if (unlikely(ret != 0)) { 1359 /* 1360 * If the GPIO chip fails to come up we still leave the 1361 * PFC state as it is, given that there are already 1362 * extant users of it that have succeeded by this point. 1363 */ 1364 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n"); 1365 } 1366 #endif 1367 1368 platform_set_drvdata(pdev, pfc); 1369 1370 dev_info(pfc->dev, "%s support registered\n", info->name); 1371 1372 return 0; 1373 } 1374 1375 static const struct platform_device_id sh_pfc_id_table[] = { 1376 #ifdef CONFIG_PINCTRL_PFC_SH7203 1377 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, 1378 #endif 1379 #ifdef CONFIG_PINCTRL_PFC_SH7264 1380 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info }, 1381 #endif 1382 #ifdef CONFIG_PINCTRL_PFC_SH7269 1383 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info }, 1384 #endif 1385 #ifdef CONFIG_PINCTRL_PFC_SH7720 1386 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info }, 1387 #endif 1388 #ifdef CONFIG_PINCTRL_PFC_SH7722 1389 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info }, 1390 #endif 1391 #ifdef CONFIG_PINCTRL_PFC_SH7723 1392 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info }, 1393 #endif 1394 #ifdef CONFIG_PINCTRL_PFC_SH7724 1395 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info }, 1396 #endif 1397 #ifdef CONFIG_PINCTRL_PFC_SH7734 1398 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info }, 1399 #endif 1400 #ifdef CONFIG_PINCTRL_PFC_SH7757 1401 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info }, 1402 #endif 1403 #ifdef CONFIG_PINCTRL_PFC_SH7785 1404 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info }, 1405 #endif 1406 #ifdef CONFIG_PINCTRL_PFC_SH7786 1407 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info }, 1408 #endif 1409 #ifdef CONFIG_PINCTRL_PFC_SHX3 1410 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info }, 1411 #endif 1412 { /* sentinel */ } 1413 }; 1414 1415 static struct platform_driver sh_pfc_driver = { 1416 .probe = sh_pfc_probe, 1417 .id_table = sh_pfc_id_table, 1418 .driver = { 1419 .name = DRV_NAME, 1420 .of_match_table = of_match_ptr(sh_pfc_of_table), 1421 .pm = DEV_PM_OPS, 1422 }, 1423 }; 1424 1425 static int __init sh_pfc_init(void) 1426 { 1427 sh_pfc_check_driver(&sh_pfc_driver); 1428 return platform_driver_register(&sh_pfc_driver); 1429 } 1430 postcore_initcall(sh_pfc_init); 1431