1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, Sony Mobile Communications AB. 4 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/gpio/driver.h> 8 #include <linux/interrupt.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_irq.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/seq_file.h> 15 #include <linux/slab.h> 16 #include <linux/string_choices.h> 17 18 #include <linux/pinctrl/pinconf-generic.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinctrl.h> 21 #include <linux/pinctrl/pinmux.h> 22 23 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 24 25 #include "../core.h" 26 #include "../pinctrl-utils.h" 27 28 /* mode */ 29 #define PM8XXX_GPIO_MODE_ENABLED BIT(0) 30 #define PM8XXX_GPIO_MODE_INPUT 0 31 #define PM8XXX_GPIO_MODE_OUTPUT 2 32 33 /* output buffer */ 34 #define PM8XXX_GPIO_PUSH_PULL 0 35 #define PM8XXX_GPIO_OPEN_DRAIN 1 36 37 /* bias */ 38 #define PM8XXX_GPIO_BIAS_PU_30 0 39 #define PM8XXX_GPIO_BIAS_PU_1P5 1 40 #define PM8XXX_GPIO_BIAS_PU_31P5 2 41 #define PM8XXX_GPIO_BIAS_PU_1P5_30 3 42 #define PM8XXX_GPIO_BIAS_PD 4 43 #define PM8XXX_GPIO_BIAS_NP 5 44 45 /* GPIO registers */ 46 #define SSBI_REG_ADDR_GPIO_BASE 0x150 47 #define SSBI_REG_ADDR_GPIO(n) (SSBI_REG_ADDR_GPIO_BASE + n) 48 49 #define PM8XXX_BANK_WRITE BIT(7) 50 51 #define PM8XXX_MAX_GPIOS 44 52 53 #define PM8XXX_GPIO_PHYSICAL_OFFSET 1 54 55 /* custom pinconf parameters */ 56 #define PM8XXX_QCOM_DRIVE_STRENGH (PIN_CONFIG_END + 1) 57 #define PM8XXX_QCOM_PULL_UP_STRENGTH (PIN_CONFIG_END + 2) 58 59 /** 60 * struct pm8xxx_pin_data - dynamic configuration for a pin 61 * @reg: address of the control register 62 * @power_source: logical selected voltage source, mapping in static data 63 * is used translate to register values 64 * @mode: operating mode for the pin (input/output) 65 * @open_drain: output buffer configured as open-drain (vs push-pull) 66 * @output_value: configured output value 67 * @bias: register view of configured bias 68 * @pull_up_strength: placeholder for selected pull up strength 69 * only used to configure bias when pull up is selected 70 * @output_strength: selector of output-strength 71 * @disable: pin disabled / configured as tristate 72 * @function: pinmux selector 73 * @inverted: pin logic is inverted 74 */ 75 struct pm8xxx_pin_data { 76 unsigned reg; 77 u8 power_source; 78 u8 mode; 79 bool open_drain; 80 bool output_value; 81 u8 bias; 82 u8 pull_up_strength; 83 u8 output_strength; 84 bool disable; 85 u8 function; 86 bool inverted; 87 }; 88 89 struct pm8xxx_gpio { 90 struct device *dev; 91 struct regmap *regmap; 92 struct pinctrl_dev *pctrl; 93 struct gpio_chip chip; 94 95 struct pinctrl_desc desc; 96 unsigned npins; 97 }; 98 99 static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = { 100 {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGH, 0}, 101 {"qcom,pull-up-strength", PM8XXX_QCOM_PULL_UP_STRENGTH, 0}, 102 }; 103 104 #ifdef CONFIG_DEBUG_FS 105 static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = { 106 PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true), 107 PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH, "pull up strength", NULL, true), 108 }; 109 #endif 110 111 static const char * const pm8xxx_groups[PM8XXX_MAX_GPIOS] = { 112 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", 113 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", 114 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", 115 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 116 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", 117 "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", 118 "gpio44", 119 }; 120 121 static const char * const pm8xxx_gpio_functions[] = { 122 PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED, 123 PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2, 124 PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2, 125 PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4, 126 }; 127 128 static int pm8xxx_read_bank(struct pm8xxx_gpio *pctrl, 129 struct pm8xxx_pin_data *pin, int bank) 130 { 131 unsigned int val = bank << 4; 132 int ret; 133 134 ret = regmap_write(pctrl->regmap, pin->reg, val); 135 if (ret) { 136 dev_err(pctrl->dev, "failed to select bank %d\n", bank); 137 return ret; 138 } 139 140 ret = regmap_read(pctrl->regmap, pin->reg, &val); 141 if (ret) { 142 dev_err(pctrl->dev, "failed to read register %d\n", bank); 143 return ret; 144 } 145 146 return val; 147 } 148 149 static int pm8xxx_write_bank(struct pm8xxx_gpio *pctrl, 150 struct pm8xxx_pin_data *pin, 151 int bank, 152 u8 val) 153 { 154 int ret; 155 156 val |= PM8XXX_BANK_WRITE; 157 val |= bank << 4; 158 159 ret = regmap_write(pctrl->regmap, pin->reg, val); 160 if (ret) 161 dev_err(pctrl->dev, "failed to write register\n"); 162 163 return ret; 164 } 165 166 static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev) 167 { 168 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 169 170 return pctrl->npins; 171 } 172 173 static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev, 174 unsigned group) 175 { 176 return pm8xxx_groups[group]; 177 } 178 179 180 static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev, 181 unsigned group, 182 const unsigned **pins, 183 unsigned *num_pins) 184 { 185 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 186 187 *pins = &pctrl->desc.pins[group].number; 188 *num_pins = 1; 189 190 return 0; 191 } 192 193 static const struct pinctrl_ops pm8xxx_pinctrl_ops = { 194 .get_groups_count = pm8xxx_get_groups_count, 195 .get_group_name = pm8xxx_get_group_name, 196 .get_group_pins = pm8xxx_get_group_pins, 197 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 198 .dt_free_map = pinctrl_utils_free_map, 199 }; 200 201 static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev) 202 { 203 return ARRAY_SIZE(pm8xxx_gpio_functions); 204 } 205 206 static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev, 207 unsigned function) 208 { 209 return pm8xxx_gpio_functions[function]; 210 } 211 212 static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev, 213 unsigned function, 214 const char * const **groups, 215 unsigned * const num_groups) 216 { 217 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 218 219 *groups = pm8xxx_groups; 220 *num_groups = pctrl->npins; 221 return 0; 222 } 223 224 static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev, 225 unsigned function, 226 unsigned group) 227 { 228 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 229 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; 230 u8 val; 231 232 pin->function = function; 233 val = pin->function << 1; 234 235 pm8xxx_write_bank(pctrl, pin, 4, val); 236 237 return 0; 238 } 239 240 static const struct pinmux_ops pm8xxx_pinmux_ops = { 241 .get_functions_count = pm8xxx_get_functions_count, 242 .get_function_name = pm8xxx_get_function_name, 243 .get_function_groups = pm8xxx_get_function_groups, 244 .set_mux = pm8xxx_pinmux_set_mux, 245 }; 246 247 static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev, 248 unsigned int offset, 249 unsigned long *config) 250 { 251 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 252 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 253 unsigned param = pinconf_to_config_param(*config); 254 unsigned arg; 255 256 switch (param) { 257 case PIN_CONFIG_BIAS_DISABLE: 258 if (pin->bias != PM8XXX_GPIO_BIAS_NP) 259 return -EINVAL; 260 arg = 1; 261 break; 262 case PIN_CONFIG_BIAS_PULL_DOWN: 263 if (pin->bias != PM8XXX_GPIO_BIAS_PD) 264 return -EINVAL; 265 arg = 1; 266 break; 267 case PIN_CONFIG_BIAS_PULL_UP: 268 if (pin->bias > PM8XXX_GPIO_BIAS_PU_1P5_30) 269 return -EINVAL; 270 arg = 1; 271 break; 272 case PM8XXX_QCOM_PULL_UP_STRENGTH: 273 arg = pin->pull_up_strength; 274 break; 275 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 276 if (!pin->disable) 277 return -EINVAL; 278 arg = 1; 279 break; 280 case PIN_CONFIG_INPUT_ENABLE: 281 if (pin->mode != PM8XXX_GPIO_MODE_INPUT) 282 return -EINVAL; 283 arg = 1; 284 break; 285 case PIN_CONFIG_OUTPUT: 286 if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT) 287 arg = pin->output_value; 288 else 289 arg = 0; 290 break; 291 case PIN_CONFIG_POWER_SOURCE: 292 arg = pin->power_source; 293 break; 294 case PM8XXX_QCOM_DRIVE_STRENGH: 295 arg = pin->output_strength; 296 break; 297 case PIN_CONFIG_DRIVE_PUSH_PULL: 298 if (pin->open_drain) 299 return -EINVAL; 300 arg = 1; 301 break; 302 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 303 if (!pin->open_drain) 304 return -EINVAL; 305 arg = 1; 306 break; 307 default: 308 return -EINVAL; 309 } 310 311 *config = pinconf_to_config_packed(param, arg); 312 313 return 0; 314 } 315 316 static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev, 317 unsigned int offset, 318 unsigned long *configs, 319 unsigned num_configs) 320 { 321 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 322 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 323 unsigned param; 324 unsigned arg; 325 unsigned i; 326 u8 banks = 0; 327 u8 val; 328 329 for (i = 0; i < num_configs; i++) { 330 param = pinconf_to_config_param(configs[i]); 331 arg = pinconf_to_config_argument(configs[i]); 332 333 switch (param) { 334 case PIN_CONFIG_BIAS_DISABLE: 335 pin->bias = PM8XXX_GPIO_BIAS_NP; 336 banks |= BIT(2); 337 pin->disable = 0; 338 banks |= BIT(3); 339 break; 340 case PIN_CONFIG_BIAS_PULL_DOWN: 341 pin->bias = PM8XXX_GPIO_BIAS_PD; 342 banks |= BIT(2); 343 pin->disable = 0; 344 banks |= BIT(3); 345 break; 346 case PM8XXX_QCOM_PULL_UP_STRENGTH: 347 if (arg > PM8XXX_GPIO_BIAS_PU_1P5_30) { 348 dev_err(pctrl->dev, "invalid pull-up strength\n"); 349 return -EINVAL; 350 } 351 pin->pull_up_strength = arg; 352 fallthrough; 353 case PIN_CONFIG_BIAS_PULL_UP: 354 pin->bias = pin->pull_up_strength; 355 banks |= BIT(2); 356 pin->disable = 0; 357 banks |= BIT(3); 358 break; 359 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 360 pin->disable = 1; 361 banks |= BIT(3); 362 break; 363 case PIN_CONFIG_INPUT_ENABLE: 364 pin->mode = PM8XXX_GPIO_MODE_INPUT; 365 banks |= BIT(0) | BIT(1); 366 break; 367 case PIN_CONFIG_OUTPUT: 368 pin->mode = PM8XXX_GPIO_MODE_OUTPUT; 369 pin->output_value = !!arg; 370 banks |= BIT(0) | BIT(1); 371 break; 372 case PIN_CONFIG_POWER_SOURCE: 373 pin->power_source = arg; 374 banks |= BIT(0); 375 break; 376 case PM8XXX_QCOM_DRIVE_STRENGH: 377 if (arg > PMIC_GPIO_STRENGTH_LOW) { 378 dev_err(pctrl->dev, "invalid drive strength\n"); 379 return -EINVAL; 380 } 381 pin->output_strength = arg; 382 banks |= BIT(3); 383 break; 384 case PIN_CONFIG_DRIVE_PUSH_PULL: 385 pin->open_drain = 0; 386 banks |= BIT(1); 387 break; 388 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 389 pin->open_drain = 1; 390 banks |= BIT(1); 391 break; 392 default: 393 dev_err(pctrl->dev, 394 "unsupported config parameter: %x\n", 395 param); 396 return -EINVAL; 397 } 398 } 399 400 if (banks & BIT(0)) { 401 val = pin->power_source << 1; 402 val |= PM8XXX_GPIO_MODE_ENABLED; 403 pm8xxx_write_bank(pctrl, pin, 0, val); 404 } 405 406 if (banks & BIT(1)) { 407 val = pin->mode << 2; 408 val |= pin->open_drain << 1; 409 val |= pin->output_value; 410 pm8xxx_write_bank(pctrl, pin, 1, val); 411 } 412 413 if (banks & BIT(2)) { 414 val = pin->bias << 1; 415 pm8xxx_write_bank(pctrl, pin, 2, val); 416 } 417 418 if (banks & BIT(3)) { 419 val = pin->output_strength << 2; 420 val |= pin->disable; 421 pm8xxx_write_bank(pctrl, pin, 3, val); 422 } 423 424 if (banks & BIT(4)) { 425 val = pin->function << 1; 426 pm8xxx_write_bank(pctrl, pin, 4, val); 427 } 428 429 if (banks & BIT(5)) { 430 val = 0; 431 if (!pin->inverted) 432 val |= BIT(3); 433 pm8xxx_write_bank(pctrl, pin, 5, val); 434 } 435 436 return 0; 437 } 438 439 static const struct pinconf_ops pm8xxx_pinconf_ops = { 440 .is_generic = true, 441 .pin_config_group_get = pm8xxx_pin_config_get, 442 .pin_config_group_set = pm8xxx_pin_config_set, 443 }; 444 445 static const struct pinctrl_desc pm8xxx_pinctrl_desc = { 446 .name = "pm8xxx_gpio", 447 .pctlops = &pm8xxx_pinctrl_ops, 448 .pmxops = &pm8xxx_pinmux_ops, 449 .confops = &pm8xxx_pinconf_ops, 450 .owner = THIS_MODULE, 451 }; 452 453 static int pm8xxx_gpio_direction_input(struct gpio_chip *chip, 454 unsigned offset) 455 { 456 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); 457 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 458 u8 val; 459 460 pin->mode = PM8XXX_GPIO_MODE_INPUT; 461 val = pin->mode << 2; 462 463 pm8xxx_write_bank(pctrl, pin, 1, val); 464 465 return 0; 466 } 467 468 static int pm8xxx_gpio_direction_output(struct gpio_chip *chip, 469 unsigned offset, 470 int value) 471 { 472 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); 473 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 474 u8 val; 475 476 pin->mode = PM8XXX_GPIO_MODE_OUTPUT; 477 pin->output_value = !!value; 478 479 val = pin->mode << 2; 480 val |= pin->open_drain << 1; 481 val |= pin->output_value; 482 483 pm8xxx_write_bank(pctrl, pin, 1, val); 484 485 return 0; 486 } 487 488 static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset) 489 { 490 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); 491 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 492 int ret, irq; 493 bool state; 494 495 if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) 496 return pin->output_value; 497 498 irq = chip->to_irq(chip, offset); 499 if (irq >= 0) { 500 ret = irq_get_irqchip_state(irq, IRQCHIP_STATE_LINE_LEVEL, 501 &state); 502 if (!ret) 503 ret = !!state; 504 } else 505 ret = -EINVAL; 506 507 return ret; 508 } 509 510 static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 511 { 512 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); 513 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 514 u8 val; 515 516 pin->output_value = !!value; 517 518 val = pin->mode << 2; 519 val |= pin->open_drain << 1; 520 val |= pin->output_value; 521 522 pm8xxx_write_bank(pctrl, pin, 1, val); 523 } 524 525 static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip, 526 const struct of_phandle_args *gpio_desc, 527 u32 *flags) 528 { 529 if (chip->of_gpio_n_cells < 2) 530 return -EINVAL; 531 532 if (flags) 533 *flags = gpio_desc->args[1]; 534 535 return gpio_desc->args[0] - PM8XXX_GPIO_PHYSICAL_OFFSET; 536 } 537 538 539 #ifdef CONFIG_DEBUG_FS 540 541 static void pm8xxx_gpio_dbg_show_one(struct seq_file *s, 542 struct pinctrl_dev *pctldev, 543 struct gpio_chip *chip, 544 unsigned offset, 545 unsigned gpio) 546 { 547 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); 548 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 549 550 static const char * const modes[] = { 551 "in", "both", "out", "off" 552 }; 553 static const char * const biases[] = { 554 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", 555 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" 556 }; 557 static const char * const buffer_types[] = { 558 "push-pull", "open-drain" 559 }; 560 static const char * const strengths[] = { 561 "no", "high", "medium", "low" 562 }; 563 564 seq_printf(s, " gpio%-2d:", offset + PM8XXX_GPIO_PHYSICAL_OFFSET); 565 if (pin->disable) { 566 seq_puts(s, " ---"); 567 } else { 568 seq_printf(s, " %-4s", modes[pin->mode]); 569 seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]); 570 seq_printf(s, " VIN%d", pin->power_source); 571 seq_printf(s, " %-27s", biases[pin->bias]); 572 seq_printf(s, " %-10s", buffer_types[pin->open_drain]); 573 seq_printf(s, " %-4s", str_high_low(pin->output_value)); 574 seq_printf(s, " %-7s", strengths[pin->output_strength]); 575 if (pin->inverted) 576 seq_puts(s, " inverted"); 577 } 578 } 579 580 static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 581 { 582 unsigned gpio = chip->base; 583 unsigned i; 584 585 for (i = 0; i < chip->ngpio; i++, gpio++) { 586 pm8xxx_gpio_dbg_show_one(s, NULL, chip, i, gpio); 587 seq_puts(s, "\n"); 588 } 589 } 590 591 #else 592 #define pm8xxx_gpio_dbg_show NULL 593 #endif 594 595 static const struct gpio_chip pm8xxx_gpio_template = { 596 .direction_input = pm8xxx_gpio_direction_input, 597 .direction_output = pm8xxx_gpio_direction_output, 598 .get = pm8xxx_gpio_get, 599 .set = pm8xxx_gpio_set, 600 .of_xlate = pm8xxx_gpio_of_xlate, 601 .dbg_show = pm8xxx_gpio_dbg_show, 602 .owner = THIS_MODULE, 603 }; 604 605 static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl, 606 struct pm8xxx_pin_data *pin) 607 { 608 int val; 609 610 val = pm8xxx_read_bank(pctrl, pin, 0); 611 if (val < 0) 612 return val; 613 614 pin->power_source = (val >> 1) & 0x7; 615 616 val = pm8xxx_read_bank(pctrl, pin, 1); 617 if (val < 0) 618 return val; 619 620 pin->mode = (val >> 2) & 0x3; 621 pin->open_drain = !!(val & BIT(1)); 622 pin->output_value = val & BIT(0); 623 624 val = pm8xxx_read_bank(pctrl, pin, 2); 625 if (val < 0) 626 return val; 627 628 pin->bias = (val >> 1) & 0x7; 629 if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30) 630 pin->pull_up_strength = pin->bias; 631 else 632 pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30; 633 634 val = pm8xxx_read_bank(pctrl, pin, 3); 635 if (val < 0) 636 return val; 637 638 pin->output_strength = (val >> 2) & 0x3; 639 pin->disable = val & BIT(0); 640 641 val = pm8xxx_read_bank(pctrl, pin, 4); 642 if (val < 0) 643 return val; 644 645 pin->function = (val >> 1) & 0x7; 646 647 val = pm8xxx_read_bank(pctrl, pin, 5); 648 if (val < 0) 649 return val; 650 651 pin->inverted = !(val & BIT(3)); 652 653 return 0; 654 } 655 656 static void pm8xxx_irq_disable(struct irq_data *d) 657 { 658 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 659 660 gpiochip_disable_irq(gc, irqd_to_hwirq(d)); 661 } 662 663 static void pm8xxx_irq_enable(struct irq_data *d) 664 { 665 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 666 667 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); 668 } 669 670 static const struct irq_chip pm8xxx_irq_chip = { 671 .name = "ssbi-gpio", 672 .irq_mask_ack = irq_chip_mask_ack_parent, 673 .irq_unmask = irq_chip_unmask_parent, 674 .irq_disable = pm8xxx_irq_disable, 675 .irq_enable = pm8xxx_irq_enable, 676 .irq_set_type = irq_chip_set_type_parent, 677 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE | 678 IRQCHIP_IMMUTABLE, 679 GPIOCHIP_IRQ_RESOURCE_HELPERS, 680 }; 681 682 static int pm8xxx_domain_translate(struct irq_domain *domain, 683 struct irq_fwspec *fwspec, 684 unsigned long *hwirq, 685 unsigned int *type) 686 { 687 struct pm8xxx_gpio *pctrl = container_of(domain->host_data, 688 struct pm8xxx_gpio, chip); 689 690 if (fwspec->param_count != 2 || fwspec->param[0] < 1 || 691 fwspec->param[0] > pctrl->chip.ngpio) 692 return -EINVAL; 693 694 *hwirq = fwspec->param[0] - PM8XXX_GPIO_PHYSICAL_OFFSET; 695 *type = fwspec->param[1]; 696 697 return 0; 698 } 699 700 static unsigned int pm8xxx_child_offset_to_irq(struct gpio_chip *chip, 701 unsigned int offset) 702 { 703 return offset + PM8XXX_GPIO_PHYSICAL_OFFSET; 704 } 705 706 static int pm8xxx_child_to_parent_hwirq(struct gpio_chip *chip, 707 unsigned int child_hwirq, 708 unsigned int child_type, 709 unsigned int *parent_hwirq, 710 unsigned int *parent_type) 711 { 712 *parent_hwirq = child_hwirq + 0xc0; 713 *parent_type = child_type; 714 715 return 0; 716 } 717 718 static const struct of_device_id pm8xxx_gpio_of_match[] = { 719 { .compatible = "qcom,pm8018-gpio", .data = (void *) 6 }, 720 { .compatible = "qcom,pm8038-gpio", .data = (void *) 12 }, 721 { .compatible = "qcom,pm8058-gpio", .data = (void *) 44 }, 722 { .compatible = "qcom,pm8917-gpio", .data = (void *) 38 }, 723 { .compatible = "qcom,pm8921-gpio", .data = (void *) 44 }, 724 { }, 725 }; 726 MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match); 727 728 static int pm8xxx_gpio_probe(struct platform_device *pdev) 729 { 730 struct pm8xxx_pin_data *pin_data; 731 struct irq_domain *parent_domain; 732 struct device_node *parent_node; 733 struct pinctrl_pin_desc *pins; 734 struct gpio_irq_chip *girq; 735 struct pm8xxx_gpio *pctrl; 736 int ret, i; 737 738 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 739 if (!pctrl) 740 return -ENOMEM; 741 742 pctrl->dev = &pdev->dev; 743 pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev); 744 745 pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); 746 if (!pctrl->regmap) { 747 dev_err(&pdev->dev, "parent regmap unavailable\n"); 748 return -ENXIO; 749 } 750 751 pctrl->desc = pm8xxx_pinctrl_desc; 752 pctrl->desc.npins = pctrl->npins; 753 754 pins = devm_kcalloc(&pdev->dev, 755 pctrl->desc.npins, 756 sizeof(struct pinctrl_pin_desc), 757 GFP_KERNEL); 758 if (!pins) 759 return -ENOMEM; 760 761 pin_data = devm_kcalloc(&pdev->dev, 762 pctrl->desc.npins, 763 sizeof(struct pm8xxx_pin_data), 764 GFP_KERNEL); 765 if (!pin_data) 766 return -ENOMEM; 767 768 for (i = 0; i < pctrl->desc.npins; i++) { 769 pin_data[i].reg = SSBI_REG_ADDR_GPIO(i); 770 771 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]); 772 if (ret) 773 return ret; 774 775 pins[i].number = i; 776 pins[i].name = pm8xxx_groups[i]; 777 pins[i].drv_data = &pin_data[i]; 778 } 779 pctrl->desc.pins = pins; 780 781 pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings); 782 pctrl->desc.custom_params = pm8xxx_gpio_bindings; 783 #ifdef CONFIG_DEBUG_FS 784 pctrl->desc.custom_conf_items = pm8xxx_conf_items; 785 #endif 786 787 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); 788 if (IS_ERR(pctrl->pctrl)) { 789 dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n"); 790 return PTR_ERR(pctrl->pctrl); 791 } 792 793 pctrl->chip = pm8xxx_gpio_template; 794 pctrl->chip.base = -1; 795 pctrl->chip.parent = &pdev->dev; 796 pctrl->chip.of_gpio_n_cells = 2; 797 pctrl->chip.label = dev_name(pctrl->dev); 798 pctrl->chip.ngpio = pctrl->npins; 799 800 parent_node = of_irq_find_parent(pctrl->dev->of_node); 801 if (!parent_node) 802 return -ENXIO; 803 804 parent_domain = irq_find_host(parent_node); 805 of_node_put(parent_node); 806 if (!parent_domain) 807 return -ENXIO; 808 809 girq = &pctrl->chip.irq; 810 gpio_irq_chip_set_chip(girq, &pm8xxx_irq_chip); 811 girq->default_type = IRQ_TYPE_NONE; 812 girq->handler = handle_level_irq; 813 girq->fwnode = dev_fwnode(pctrl->dev); 814 girq->parent_domain = parent_domain; 815 girq->child_to_parent_hwirq = pm8xxx_child_to_parent_hwirq; 816 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; 817 girq->child_offset_to_irq = pm8xxx_child_offset_to_irq; 818 girq->child_irq_domain_ops.translate = pm8xxx_domain_translate; 819 820 ret = gpiochip_add_data(&pctrl->chip, pctrl); 821 if (ret) { 822 dev_err(&pdev->dev, "failed register gpiochip\n"); 823 return ret; 824 } 825 826 /* 827 * For DeviceTree-supported systems, the gpio core checks the 828 * pinctrl's device node for the "gpio-ranges" property. 829 * If it is present, it takes care of adding the pin ranges 830 * for the driver. In this case the driver can skip ahead. 831 * 832 * In order to remain compatible with older, existing DeviceTree 833 * files which don't set the "gpio-ranges" property or systems that 834 * utilize ACPI the driver has to call gpiochip_add_pin_range(). 835 */ 836 if (!of_property_present(pctrl->dev->of_node, "gpio-ranges")) { 837 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 838 0, 0, pctrl->chip.ngpio); 839 if (ret) { 840 dev_err(pctrl->dev, "failed to add pin range\n"); 841 goto unregister_gpiochip; 842 } 843 } 844 845 platform_set_drvdata(pdev, pctrl); 846 847 dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n"); 848 849 return 0; 850 851 unregister_gpiochip: 852 gpiochip_remove(&pctrl->chip); 853 854 return ret; 855 } 856 857 static void pm8xxx_gpio_remove(struct platform_device *pdev) 858 { 859 struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev); 860 861 gpiochip_remove(&pctrl->chip); 862 } 863 864 static struct platform_driver pm8xxx_gpio_driver = { 865 .driver = { 866 .name = "qcom-ssbi-gpio", 867 .of_match_table = pm8xxx_gpio_of_match, 868 }, 869 .probe = pm8xxx_gpio_probe, 870 .remove = pm8xxx_gpio_remove, 871 }; 872 873 module_platform_driver(pm8xxx_gpio_driver); 874 875 MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); 876 MODULE_DESCRIPTION("Qualcomm PM8xxx GPIO driver"); 877 MODULE_LICENSE("GPL v2"); 878