1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, Sony Mobile Communications AB. 4 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/gpio/driver.h> 8 #include <linux/interrupt.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_irq.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/seq_file.h> 15 #include <linux/slab.h> 16 #include <linux/string_choices.h> 17 18 #include <linux/pinctrl/pinconf-generic.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinctrl.h> 21 #include <linux/pinctrl/pinmux.h> 22 23 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 24 25 #include "../core.h" 26 #include "../pinctrl-utils.h" 27 28 /* mode */ 29 #define PM8XXX_GPIO_MODE_ENABLED BIT(0) 30 #define PM8XXX_GPIO_MODE_INPUT 0 31 #define PM8XXX_GPIO_MODE_OUTPUT 2 32 33 /* output buffer */ 34 #define PM8XXX_GPIO_PUSH_PULL 0 35 #define PM8XXX_GPIO_OPEN_DRAIN 1 36 37 /* bias */ 38 #define PM8XXX_GPIO_BIAS_PU_30 0 39 #define PM8XXX_GPIO_BIAS_PU_1P5 1 40 #define PM8XXX_GPIO_BIAS_PU_31P5 2 41 #define PM8XXX_GPIO_BIAS_PU_1P5_30 3 42 #define PM8XXX_GPIO_BIAS_PD 4 43 #define PM8XXX_GPIO_BIAS_NP 5 44 45 /* GPIO registers */ 46 #define SSBI_REG_ADDR_GPIO_BASE 0x150 47 #define SSBI_REG_ADDR_GPIO(n) (SSBI_REG_ADDR_GPIO_BASE + n) 48 49 #define PM8XXX_BANK_WRITE BIT(7) 50 51 #define PM8XXX_MAX_GPIOS 44 52 53 #define PM8XXX_GPIO_PHYSICAL_OFFSET 1 54 55 /* custom pinconf parameters */ 56 #define PM8XXX_QCOM_DRIVE_STRENGH (PIN_CONFIG_END + 1) 57 #define PM8XXX_QCOM_PULL_UP_STRENGTH (PIN_CONFIG_END + 2) 58 59 /** 60 * struct pm8xxx_pin_data - dynamic configuration for a pin 61 * @reg: address of the control register 62 * @power_source: logical selected voltage source, mapping in static data 63 * is used translate to register values 64 * @mode: operating mode for the pin (input/output) 65 * @open_drain: output buffer configured as open-drain (vs push-pull) 66 * @output_value: configured output value 67 * @bias: register view of configured bias 68 * @pull_up_strength: placeholder for selected pull up strength 69 * only used to configure bias when pull up is selected 70 * @output_strength: selector of output-strength 71 * @disable: pin disabled / configured as tristate 72 * @function: pinmux selector 73 * @inverted: pin logic is inverted 74 */ 75 struct pm8xxx_pin_data { 76 unsigned reg; 77 u8 power_source; 78 u8 mode; 79 bool open_drain; 80 bool output_value; 81 u8 bias; 82 u8 pull_up_strength; 83 u8 output_strength; 84 bool disable; 85 u8 function; 86 bool inverted; 87 }; 88 89 struct pm8xxx_gpio { 90 struct device *dev; 91 struct regmap *regmap; 92 struct pinctrl_dev *pctrl; 93 struct gpio_chip chip; 94 95 struct pinctrl_desc desc; 96 unsigned npins; 97 }; 98 99 static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = { 100 {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGH, 0}, 101 {"qcom,pull-up-strength", PM8XXX_QCOM_PULL_UP_STRENGTH, 0}, 102 }; 103 104 #ifdef CONFIG_DEBUG_FS 105 static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = { 106 PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true), 107 PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH, "pull up strength", NULL, true), 108 }; 109 #endif 110 111 static const char * const pm8xxx_groups[PM8XXX_MAX_GPIOS] = { 112 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", 113 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", 114 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", 115 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 116 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", 117 "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", 118 "gpio44", 119 }; 120 121 static const char * const pm8xxx_gpio_functions[] = { 122 PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED, 123 PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2, 124 PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2, 125 PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4, 126 }; 127 128 static int pm8xxx_read_bank(struct pm8xxx_gpio *pctrl, 129 struct pm8xxx_pin_data *pin, int bank) 130 { 131 unsigned int val = bank << 4; 132 int ret; 133 134 ret = regmap_write(pctrl->regmap, pin->reg, val); 135 if (ret) { 136 dev_err(pctrl->dev, "failed to select bank %d\n", bank); 137 return ret; 138 } 139 140 ret = regmap_read(pctrl->regmap, pin->reg, &val); 141 if (ret) { 142 dev_err(pctrl->dev, "failed to read register %d\n", bank); 143 return ret; 144 } 145 146 return val; 147 } 148 149 static int pm8xxx_write_bank(struct pm8xxx_gpio *pctrl, 150 struct pm8xxx_pin_data *pin, 151 int bank, 152 u8 val) 153 { 154 int ret; 155 156 val |= PM8XXX_BANK_WRITE; 157 val |= bank << 4; 158 159 ret = regmap_write(pctrl->regmap, pin->reg, val); 160 if (ret) 161 dev_err(pctrl->dev, "failed to write register\n"); 162 163 return ret; 164 } 165 166 static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev) 167 { 168 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 169 170 return pctrl->npins; 171 } 172 173 static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev, 174 unsigned group) 175 { 176 return pm8xxx_groups[group]; 177 } 178 179 180 static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev, 181 unsigned group, 182 const unsigned **pins, 183 unsigned *num_pins) 184 { 185 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 186 187 *pins = &pctrl->desc.pins[group].number; 188 *num_pins = 1; 189 190 return 0; 191 } 192 193 static const struct pinctrl_ops pm8xxx_pinctrl_ops = { 194 .get_groups_count = pm8xxx_get_groups_count, 195 .get_group_name = pm8xxx_get_group_name, 196 .get_group_pins = pm8xxx_get_group_pins, 197 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 198 .dt_free_map = pinctrl_utils_free_map, 199 }; 200 201 static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev) 202 { 203 return ARRAY_SIZE(pm8xxx_gpio_functions); 204 } 205 206 static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev, 207 unsigned function) 208 { 209 return pm8xxx_gpio_functions[function]; 210 } 211 212 static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev, 213 unsigned function, 214 const char * const **groups, 215 unsigned * const num_groups) 216 { 217 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 218 219 *groups = pm8xxx_groups; 220 *num_groups = pctrl->npins; 221 return 0; 222 } 223 224 static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev, 225 unsigned function, 226 unsigned group) 227 { 228 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 229 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data; 230 u8 val; 231 232 pin->function = function; 233 val = pin->function << 1; 234 235 pm8xxx_write_bank(pctrl, pin, 4, val); 236 237 return 0; 238 } 239 240 static const struct pinmux_ops pm8xxx_pinmux_ops = { 241 .get_functions_count = pm8xxx_get_functions_count, 242 .get_function_name = pm8xxx_get_function_name, 243 .get_function_groups = pm8xxx_get_function_groups, 244 .set_mux = pm8xxx_pinmux_set_mux, 245 }; 246 247 static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev, 248 unsigned int offset, 249 unsigned long *config) 250 { 251 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 252 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 253 unsigned param = pinconf_to_config_param(*config); 254 unsigned arg; 255 256 switch (param) { 257 case PIN_CONFIG_BIAS_DISABLE: 258 if (pin->bias != PM8XXX_GPIO_BIAS_NP) 259 return -EINVAL; 260 arg = 1; 261 break; 262 case PIN_CONFIG_BIAS_PULL_DOWN: 263 if (pin->bias != PM8XXX_GPIO_BIAS_PD) 264 return -EINVAL; 265 arg = 1; 266 break; 267 case PIN_CONFIG_BIAS_PULL_UP: 268 if (pin->bias > PM8XXX_GPIO_BIAS_PU_1P5_30) 269 return -EINVAL; 270 arg = 1; 271 break; 272 case PM8XXX_QCOM_PULL_UP_STRENGTH: 273 arg = pin->pull_up_strength; 274 break; 275 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 276 if (!pin->disable) 277 return -EINVAL; 278 arg = 1; 279 break; 280 case PIN_CONFIG_INPUT_ENABLE: 281 if (pin->mode != PM8XXX_GPIO_MODE_INPUT) 282 return -EINVAL; 283 arg = 1; 284 break; 285 case PIN_CONFIG_OUTPUT: 286 if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT) 287 arg = pin->output_value; 288 else 289 arg = 0; 290 break; 291 case PIN_CONFIG_POWER_SOURCE: 292 arg = pin->power_source; 293 break; 294 case PM8XXX_QCOM_DRIVE_STRENGH: 295 arg = pin->output_strength; 296 break; 297 case PIN_CONFIG_DRIVE_PUSH_PULL: 298 if (pin->open_drain) 299 return -EINVAL; 300 arg = 1; 301 break; 302 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 303 if (!pin->open_drain) 304 return -EINVAL; 305 arg = 1; 306 break; 307 default: 308 return -EINVAL; 309 } 310 311 *config = pinconf_to_config_packed(param, arg); 312 313 return 0; 314 } 315 316 static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev, 317 unsigned int offset, 318 unsigned long *configs, 319 unsigned num_configs) 320 { 321 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev); 322 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 323 unsigned param; 324 unsigned arg; 325 unsigned i; 326 u8 banks = 0; 327 u8 val; 328 329 for (i = 0; i < num_configs; i++) { 330 param = pinconf_to_config_param(configs[i]); 331 arg = pinconf_to_config_argument(configs[i]); 332 333 switch (param) { 334 case PIN_CONFIG_BIAS_DISABLE: 335 pin->bias = PM8XXX_GPIO_BIAS_NP; 336 banks |= BIT(2); 337 pin->disable = 0; 338 banks |= BIT(3); 339 break; 340 case PIN_CONFIG_BIAS_PULL_DOWN: 341 pin->bias = PM8XXX_GPIO_BIAS_PD; 342 banks |= BIT(2); 343 pin->disable = 0; 344 banks |= BIT(3); 345 break; 346 case PM8XXX_QCOM_PULL_UP_STRENGTH: 347 if (arg > PM8XXX_GPIO_BIAS_PU_1P5_30) { 348 dev_err(pctrl->dev, "invalid pull-up strength\n"); 349 return -EINVAL; 350 } 351 pin->pull_up_strength = arg; 352 fallthrough; 353 case PIN_CONFIG_BIAS_PULL_UP: 354 pin->bias = pin->pull_up_strength; 355 banks |= BIT(2); 356 pin->disable = 0; 357 banks |= BIT(3); 358 break; 359 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 360 pin->disable = 1; 361 banks |= BIT(3); 362 break; 363 case PIN_CONFIG_INPUT_ENABLE: 364 pin->mode = PM8XXX_GPIO_MODE_INPUT; 365 banks |= BIT(0) | BIT(1); 366 break; 367 case PIN_CONFIG_OUTPUT: 368 pin->mode = PM8XXX_GPIO_MODE_OUTPUT; 369 pin->output_value = !!arg; 370 banks |= BIT(0) | BIT(1); 371 break; 372 case PIN_CONFIG_POWER_SOURCE: 373 pin->power_source = arg; 374 banks |= BIT(0); 375 break; 376 case PM8XXX_QCOM_DRIVE_STRENGH: 377 if (arg > PMIC_GPIO_STRENGTH_LOW) { 378 dev_err(pctrl->dev, "invalid drive strength\n"); 379 return -EINVAL; 380 } 381 pin->output_strength = arg; 382 banks |= BIT(3); 383 break; 384 case PIN_CONFIG_DRIVE_PUSH_PULL: 385 pin->open_drain = 0; 386 banks |= BIT(1); 387 break; 388 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 389 pin->open_drain = 1; 390 banks |= BIT(1); 391 break; 392 default: 393 dev_err(pctrl->dev, 394 "unsupported config parameter: %x\n", 395 param); 396 return -EINVAL; 397 } 398 } 399 400 if (banks & BIT(0)) { 401 val = pin->power_source << 1; 402 val |= PM8XXX_GPIO_MODE_ENABLED; 403 pm8xxx_write_bank(pctrl, pin, 0, val); 404 } 405 406 if (banks & BIT(1)) { 407 val = pin->mode << 2; 408 val |= pin->open_drain << 1; 409 val |= pin->output_value; 410 pm8xxx_write_bank(pctrl, pin, 1, val); 411 } 412 413 if (banks & BIT(2)) { 414 val = pin->bias << 1; 415 pm8xxx_write_bank(pctrl, pin, 2, val); 416 } 417 418 if (banks & BIT(3)) { 419 val = pin->output_strength << 2; 420 val |= pin->disable; 421 pm8xxx_write_bank(pctrl, pin, 3, val); 422 } 423 424 if (banks & BIT(4)) { 425 val = pin->function << 1; 426 pm8xxx_write_bank(pctrl, pin, 4, val); 427 } 428 429 if (banks & BIT(5)) { 430 val = 0; 431 if (!pin->inverted) 432 val |= BIT(3); 433 pm8xxx_write_bank(pctrl, pin, 5, val); 434 } 435 436 return 0; 437 } 438 439 static const struct pinconf_ops pm8xxx_pinconf_ops = { 440 .is_generic = true, 441 .pin_config_group_get = pm8xxx_pin_config_get, 442 .pin_config_group_set = pm8xxx_pin_config_set, 443 }; 444 445 static const struct pinctrl_desc pm8xxx_pinctrl_desc = { 446 .name = "pm8xxx_gpio", 447 .pctlops = &pm8xxx_pinctrl_ops, 448 .pmxops = &pm8xxx_pinmux_ops, 449 .confops = &pm8xxx_pinconf_ops, 450 .owner = THIS_MODULE, 451 }; 452 453 static int pm8xxx_gpio_direction_input(struct gpio_chip *chip, 454 unsigned offset) 455 { 456 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); 457 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 458 u8 val; 459 460 pin->mode = PM8XXX_GPIO_MODE_INPUT; 461 val = pin->mode << 2; 462 463 pm8xxx_write_bank(pctrl, pin, 1, val); 464 465 return 0; 466 } 467 468 static int pm8xxx_gpio_direction_output(struct gpio_chip *chip, 469 unsigned offset, 470 int value) 471 { 472 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); 473 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 474 u8 val; 475 476 pin->mode = PM8XXX_GPIO_MODE_OUTPUT; 477 pin->output_value = !!value; 478 479 val = pin->mode << 2; 480 val |= pin->open_drain << 1; 481 val |= pin->output_value; 482 483 pm8xxx_write_bank(pctrl, pin, 1, val); 484 485 return 0; 486 } 487 488 static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset) 489 { 490 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); 491 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 492 int ret, irq; 493 bool state; 494 495 if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) 496 return pin->output_value; 497 498 irq = chip->to_irq(chip, offset); 499 if (irq >= 0) { 500 ret = irq_get_irqchip_state(irq, IRQCHIP_STATE_LINE_LEVEL, 501 &state); 502 if (!ret) 503 ret = !!state; 504 } else 505 ret = -EINVAL; 506 507 return ret; 508 } 509 510 static int pm8xxx_gpio_set(struct gpio_chip *chip, unsigned int offset, 511 int value) 512 { 513 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); 514 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 515 u8 val; 516 517 pin->output_value = !!value; 518 519 val = pin->mode << 2; 520 val |= pin->open_drain << 1; 521 val |= pin->output_value; 522 523 return pm8xxx_write_bank(pctrl, pin, 1, val); 524 } 525 526 static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip, 527 const struct of_phandle_args *gpio_desc, 528 u32 *flags) 529 { 530 if (chip->of_gpio_n_cells < 2) 531 return -EINVAL; 532 533 if (flags) 534 *flags = gpio_desc->args[1]; 535 536 return gpio_desc->args[0] - PM8XXX_GPIO_PHYSICAL_OFFSET; 537 } 538 539 540 #ifdef CONFIG_DEBUG_FS 541 542 static void pm8xxx_gpio_dbg_show_one(struct seq_file *s, 543 struct pinctrl_dev *pctldev, 544 struct gpio_chip *chip, 545 unsigned offset, 546 unsigned gpio) 547 { 548 struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); 549 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; 550 551 static const char * const modes[] = { 552 "in", "both", "out", "off" 553 }; 554 static const char * const biases[] = { 555 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", 556 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" 557 }; 558 static const char * const buffer_types[] = { 559 "push-pull", "open-drain" 560 }; 561 static const char * const strengths[] = { 562 "no", "high", "medium", "low" 563 }; 564 565 seq_printf(s, " gpio%-2d:", offset + PM8XXX_GPIO_PHYSICAL_OFFSET); 566 if (pin->disable) { 567 seq_puts(s, " ---"); 568 } else { 569 seq_printf(s, " %-4s", modes[pin->mode]); 570 seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]); 571 seq_printf(s, " VIN%d", pin->power_source); 572 seq_printf(s, " %-27s", biases[pin->bias]); 573 seq_printf(s, " %-10s", buffer_types[pin->open_drain]); 574 seq_printf(s, " %-4s", str_high_low(pin->output_value)); 575 seq_printf(s, " %-7s", strengths[pin->output_strength]); 576 if (pin->inverted) 577 seq_puts(s, " inverted"); 578 } 579 } 580 581 static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 582 { 583 unsigned gpio = chip->base; 584 unsigned i; 585 586 for (i = 0; i < chip->ngpio; i++, gpio++) { 587 pm8xxx_gpio_dbg_show_one(s, NULL, chip, i, gpio); 588 seq_puts(s, "\n"); 589 } 590 } 591 592 #else 593 #define pm8xxx_gpio_dbg_show NULL 594 #endif 595 596 static const struct gpio_chip pm8xxx_gpio_template = { 597 .direction_input = pm8xxx_gpio_direction_input, 598 .direction_output = pm8xxx_gpio_direction_output, 599 .get = pm8xxx_gpio_get, 600 .set = pm8xxx_gpio_set, 601 .of_xlate = pm8xxx_gpio_of_xlate, 602 .dbg_show = pm8xxx_gpio_dbg_show, 603 .owner = THIS_MODULE, 604 }; 605 606 static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl, 607 struct pm8xxx_pin_data *pin) 608 { 609 int val; 610 611 val = pm8xxx_read_bank(pctrl, pin, 0); 612 if (val < 0) 613 return val; 614 615 pin->power_source = (val >> 1) & 0x7; 616 617 val = pm8xxx_read_bank(pctrl, pin, 1); 618 if (val < 0) 619 return val; 620 621 pin->mode = (val >> 2) & 0x3; 622 pin->open_drain = !!(val & BIT(1)); 623 pin->output_value = val & BIT(0); 624 625 val = pm8xxx_read_bank(pctrl, pin, 2); 626 if (val < 0) 627 return val; 628 629 pin->bias = (val >> 1) & 0x7; 630 if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30) 631 pin->pull_up_strength = pin->bias; 632 else 633 pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30; 634 635 val = pm8xxx_read_bank(pctrl, pin, 3); 636 if (val < 0) 637 return val; 638 639 pin->output_strength = (val >> 2) & 0x3; 640 pin->disable = val & BIT(0); 641 642 val = pm8xxx_read_bank(pctrl, pin, 4); 643 if (val < 0) 644 return val; 645 646 pin->function = (val >> 1) & 0x7; 647 648 val = pm8xxx_read_bank(pctrl, pin, 5); 649 if (val < 0) 650 return val; 651 652 pin->inverted = !(val & BIT(3)); 653 654 return 0; 655 } 656 657 static void pm8xxx_irq_disable(struct irq_data *d) 658 { 659 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 660 661 gpiochip_disable_irq(gc, irqd_to_hwirq(d)); 662 } 663 664 static void pm8xxx_irq_enable(struct irq_data *d) 665 { 666 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 667 668 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); 669 } 670 671 static const struct irq_chip pm8xxx_irq_chip = { 672 .name = "ssbi-gpio", 673 .irq_mask_ack = irq_chip_mask_ack_parent, 674 .irq_unmask = irq_chip_unmask_parent, 675 .irq_disable = pm8xxx_irq_disable, 676 .irq_enable = pm8xxx_irq_enable, 677 .irq_set_type = irq_chip_set_type_parent, 678 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE | 679 IRQCHIP_IMMUTABLE, 680 GPIOCHIP_IRQ_RESOURCE_HELPERS, 681 }; 682 683 static int pm8xxx_domain_translate(struct irq_domain *domain, 684 struct irq_fwspec *fwspec, 685 unsigned long *hwirq, 686 unsigned int *type) 687 { 688 struct pm8xxx_gpio *pctrl = container_of(domain->host_data, 689 struct pm8xxx_gpio, chip); 690 691 if (fwspec->param_count != 2 || fwspec->param[0] < 1 || 692 fwspec->param[0] > pctrl->chip.ngpio) 693 return -EINVAL; 694 695 *hwirq = fwspec->param[0] - PM8XXX_GPIO_PHYSICAL_OFFSET; 696 *type = fwspec->param[1]; 697 698 return 0; 699 } 700 701 static unsigned int pm8xxx_child_offset_to_irq(struct gpio_chip *chip, 702 unsigned int offset) 703 { 704 return offset + PM8XXX_GPIO_PHYSICAL_OFFSET; 705 } 706 707 static int pm8xxx_child_to_parent_hwirq(struct gpio_chip *chip, 708 unsigned int child_hwirq, 709 unsigned int child_type, 710 unsigned int *parent_hwirq, 711 unsigned int *parent_type) 712 { 713 *parent_hwirq = child_hwirq + 0xc0; 714 *parent_type = child_type; 715 716 return 0; 717 } 718 719 static const struct of_device_id pm8xxx_gpio_of_match[] = { 720 { .compatible = "qcom,pm8018-gpio", .data = (void *) 6 }, 721 { .compatible = "qcom,pm8038-gpio", .data = (void *) 12 }, 722 { .compatible = "qcom,pm8058-gpio", .data = (void *) 44 }, 723 { .compatible = "qcom,pm8917-gpio", .data = (void *) 38 }, 724 { .compatible = "qcom,pm8921-gpio", .data = (void *) 44 }, 725 { }, 726 }; 727 MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match); 728 729 static int pm8xxx_gpio_probe(struct platform_device *pdev) 730 { 731 struct pm8xxx_pin_data *pin_data; 732 struct irq_domain *parent_domain; 733 struct device_node *parent_node; 734 struct pinctrl_pin_desc *pins; 735 struct gpio_irq_chip *girq; 736 struct pm8xxx_gpio *pctrl; 737 int ret, i; 738 739 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 740 if (!pctrl) 741 return -ENOMEM; 742 743 pctrl->dev = &pdev->dev; 744 pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev); 745 746 pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); 747 if (!pctrl->regmap) { 748 dev_err(&pdev->dev, "parent regmap unavailable\n"); 749 return -ENXIO; 750 } 751 752 pctrl->desc = pm8xxx_pinctrl_desc; 753 pctrl->desc.npins = pctrl->npins; 754 755 pins = devm_kcalloc(&pdev->dev, 756 pctrl->desc.npins, 757 sizeof(struct pinctrl_pin_desc), 758 GFP_KERNEL); 759 if (!pins) 760 return -ENOMEM; 761 762 pin_data = devm_kcalloc(&pdev->dev, 763 pctrl->desc.npins, 764 sizeof(struct pm8xxx_pin_data), 765 GFP_KERNEL); 766 if (!pin_data) 767 return -ENOMEM; 768 769 for (i = 0; i < pctrl->desc.npins; i++) { 770 pin_data[i].reg = SSBI_REG_ADDR_GPIO(i); 771 772 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]); 773 if (ret) 774 return ret; 775 776 pins[i].number = i; 777 pins[i].name = pm8xxx_groups[i]; 778 pins[i].drv_data = &pin_data[i]; 779 } 780 pctrl->desc.pins = pins; 781 782 pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings); 783 pctrl->desc.custom_params = pm8xxx_gpio_bindings; 784 #ifdef CONFIG_DEBUG_FS 785 pctrl->desc.custom_conf_items = pm8xxx_conf_items; 786 #endif 787 788 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); 789 if (IS_ERR(pctrl->pctrl)) { 790 dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n"); 791 return PTR_ERR(pctrl->pctrl); 792 } 793 794 pctrl->chip = pm8xxx_gpio_template; 795 pctrl->chip.base = -1; 796 pctrl->chip.parent = &pdev->dev; 797 pctrl->chip.of_gpio_n_cells = 2; 798 pctrl->chip.label = dev_name(pctrl->dev); 799 pctrl->chip.ngpio = pctrl->npins; 800 801 parent_node = of_irq_find_parent(pctrl->dev->of_node); 802 if (!parent_node) 803 return -ENXIO; 804 805 parent_domain = irq_find_host(parent_node); 806 of_node_put(parent_node); 807 if (!parent_domain) 808 return -ENXIO; 809 810 girq = &pctrl->chip.irq; 811 gpio_irq_chip_set_chip(girq, &pm8xxx_irq_chip); 812 girq->default_type = IRQ_TYPE_NONE; 813 girq->handler = handle_level_irq; 814 girq->fwnode = dev_fwnode(pctrl->dev); 815 girq->parent_domain = parent_domain; 816 girq->child_to_parent_hwirq = pm8xxx_child_to_parent_hwirq; 817 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; 818 girq->child_offset_to_irq = pm8xxx_child_offset_to_irq; 819 girq->child_irq_domain_ops.translate = pm8xxx_domain_translate; 820 821 ret = gpiochip_add_data(&pctrl->chip, pctrl); 822 if (ret) { 823 dev_err(&pdev->dev, "failed register gpiochip\n"); 824 return ret; 825 } 826 827 /* 828 * For DeviceTree-supported systems, the gpio core checks the 829 * pinctrl's device node for the "gpio-ranges" property. 830 * If it is present, it takes care of adding the pin ranges 831 * for the driver. In this case the driver can skip ahead. 832 * 833 * In order to remain compatible with older, existing DeviceTree 834 * files which don't set the "gpio-ranges" property or systems that 835 * utilize ACPI the driver has to call gpiochip_add_pin_range(). 836 */ 837 if (!of_property_present(pctrl->dev->of_node, "gpio-ranges")) { 838 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 839 0, 0, pctrl->chip.ngpio); 840 if (ret) { 841 dev_err(pctrl->dev, "failed to add pin range\n"); 842 goto unregister_gpiochip; 843 } 844 } 845 846 platform_set_drvdata(pdev, pctrl); 847 848 dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n"); 849 850 return 0; 851 852 unregister_gpiochip: 853 gpiochip_remove(&pctrl->chip); 854 855 return ret; 856 } 857 858 static void pm8xxx_gpio_remove(struct platform_device *pdev) 859 { 860 struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev); 861 862 gpiochip_remove(&pctrl->chip); 863 } 864 865 static struct platform_driver pm8xxx_gpio_driver = { 866 .driver = { 867 .name = "qcom-ssbi-gpio", 868 .of_match_table = pm8xxx_gpio_of_match, 869 }, 870 .probe = pm8xxx_gpio_probe, 871 .remove = pm8xxx_gpio_remove, 872 }; 873 874 module_platform_driver(pm8xxx_gpio_driver); 875 876 MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); 877 MODULE_DESCRIPTION("Qualcomm PM8xxx GPIO driver"); 878 MODULE_LICENSE("GPL v2"); 879