1 /* 2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/gpio.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/pinctrl/pinconf-generic.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinmux.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/slab.h> 23 #include <linux/types.h> 24 25 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> 26 27 #include "../core.h" 28 #include "../pinctrl-utils.h" 29 30 #define PMIC_MPP_ADDRESS_RANGE 0x100 31 32 /* 33 * Pull Up Values - it indicates whether a pull-up should be 34 * applied for bidirectional mode only. The hardware ignores the 35 * configuration when operating in other modes. 36 */ 37 #define PMIC_MPP_PULL_UP_0P6KOHM 0 38 #define PMIC_MPP_PULL_UP_10KOHM 1 39 #define PMIC_MPP_PULL_UP_30KOHM 2 40 #define PMIC_MPP_PULL_UP_OPEN 3 41 42 /* type registers base address bases */ 43 #define PMIC_MPP_REG_TYPE 0x4 44 #define PMIC_MPP_REG_SUBTYPE 0x5 45 46 /* mpp peripheral type and subtype values */ 47 #define PMIC_MPP_TYPE 0x11 48 #define PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3 49 #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4 50 #define PMIC_MPP_SUBTYPE_4CH_NO_SINK 0x5 51 #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6 52 #define PMIC_MPP_SUBTYPE_4CH_FULL_FUNC 0x7 53 #define PMIC_MPP_SUBTYPE_8CH_FULL_FUNC 0xf 54 55 #define PMIC_MPP_REG_RT_STS 0x10 56 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 57 58 /* control register base address bases */ 59 #define PMIC_MPP_REG_MODE_CTL 0x40 60 #define PMIC_MPP_REG_DIG_VIN_CTL 0x41 61 #define PMIC_MPP_REG_DIG_PULL_CTL 0x42 62 #define PMIC_MPP_REG_DIG_IN_CTL 0x43 63 #define PMIC_MPP_REG_EN_CTL 0x46 64 #define PMIC_MPP_REG_AOUT_CTL 0x48 65 #define PMIC_MPP_REG_AIN_CTL 0x4a 66 #define PMIC_MPP_REG_SINK_CTL 0x4c 67 68 /* PMIC_MPP_REG_MODE_CTL */ 69 #define PMIC_MPP_REG_MODE_VALUE_MASK 0x1 70 #define PMIC_MPP_REG_MODE_FUNCTION_SHIFT 1 71 #define PMIC_MPP_REG_MODE_FUNCTION_MASK 0x7 72 #define PMIC_MPP_REG_MODE_DIR_SHIFT 4 73 #define PMIC_MPP_REG_MODE_DIR_MASK 0x7 74 75 /* PMIC_MPP_REG_DIG_VIN_CTL */ 76 #define PMIC_MPP_REG_VIN_SHIFT 0 77 #define PMIC_MPP_REG_VIN_MASK 0x7 78 79 /* PMIC_MPP_REG_DIG_PULL_CTL */ 80 #define PMIC_MPP_REG_PULL_SHIFT 0 81 #define PMIC_MPP_REG_PULL_MASK 0x7 82 83 /* PMIC_MPP_REG_EN_CTL */ 84 #define PMIC_MPP_REG_MASTER_EN_SHIFT 7 85 86 /* PMIC_MPP_REG_AIN_CTL */ 87 #define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0 88 #define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7 89 90 #define PMIC_MPP_MODE_DIGITAL_INPUT 0 91 #define PMIC_MPP_MODE_DIGITAL_OUTPUT 1 92 #define PMIC_MPP_MODE_DIGITAL_BIDIR 2 93 #define PMIC_MPP_MODE_ANALOG_BIDIR 3 94 #define PMIC_MPP_MODE_ANALOG_INPUT 4 95 #define PMIC_MPP_MODE_ANALOG_OUTPUT 5 96 #define PMIC_MPP_MODE_CURRENT_SINK 6 97 98 #define PMIC_MPP_SELECTOR_NORMAL 0 99 #define PMIC_MPP_SELECTOR_PAIRED 1 100 #define PMIC_MPP_SELECTOR_DTEST_FIRST 4 101 102 #define PMIC_MPP_PHYSICAL_OFFSET 1 103 104 /* Qualcomm specific pin configurations */ 105 #define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1) 106 #define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 2) 107 #define PMIC_MPP_CONF_DTEST_SELECTOR (PIN_CONFIG_END + 3) 108 #define PMIC_MPP_CONF_PAIRED (PIN_CONFIG_END + 4) 109 110 /** 111 * struct pmic_mpp_pad - keep current MPP settings 112 * @base: Address base in SPMI device. 113 * @irq: IRQ number which this MPP generate. 114 * @is_enabled: Set to false when MPP should be put in high Z state. 115 * @out_value: Cached pin output value. 116 * @output_enabled: Set to true if MPP output logic is enabled. 117 * @input_enabled: Set to true if MPP input buffer logic is enabled. 118 * @paired: Pin operates in paired mode 119 * @num_sources: Number of power-sources supported by this MPP. 120 * @power_source: Current power-source used. 121 * @amux_input: Set the source for analog input. 122 * @aout_level: Analog output level 123 * @pullup: Pullup resistor value. Valid in Bidirectional mode only. 124 * @function: See pmic_mpp_functions[]. 125 * @drive_strength: Amount of current in sink mode 126 * @dtest: DTEST route selector 127 */ 128 struct pmic_mpp_pad { 129 u16 base; 130 int irq; 131 bool is_enabled; 132 bool out_value; 133 bool output_enabled; 134 bool input_enabled; 135 bool paired; 136 unsigned int num_sources; 137 unsigned int power_source; 138 unsigned int amux_input; 139 unsigned int aout_level; 140 unsigned int pullup; 141 unsigned int function; 142 unsigned int drive_strength; 143 unsigned int dtest; 144 }; 145 146 struct pmic_mpp_state { 147 struct device *dev; 148 struct regmap *map; 149 struct pinctrl_dev *ctrl; 150 struct gpio_chip chip; 151 }; 152 153 static const struct pinconf_generic_params pmic_mpp_bindings[] = { 154 {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0}, 155 {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0}, 156 {"qcom,dtest", PMIC_MPP_CONF_DTEST_SELECTOR, 0}, 157 {"qcom,paired", PMIC_MPP_CONF_PAIRED, 0}, 158 }; 159 160 #ifdef CONFIG_DEBUG_FS 161 static const struct pin_config_item pmic_conf_items[] = { 162 PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true), 163 PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true), 164 PCONFDUMP(PMIC_MPP_CONF_DTEST_SELECTOR, "dtest", NULL, true), 165 PCONFDUMP(PMIC_MPP_CONF_PAIRED, "paired", NULL, false), 166 }; 167 #endif 168 169 static const char *const pmic_mpp_groups[] = { 170 "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", 171 }; 172 173 #define PMIC_MPP_DIGITAL 0 174 #define PMIC_MPP_ANALOG 1 175 #define PMIC_MPP_SINK 2 176 177 static const char *const pmic_mpp_functions[] = { 178 "digital", "analog", "sink" 179 }; 180 181 static inline struct pmic_mpp_state *to_mpp_state(struct gpio_chip *chip) 182 { 183 return container_of(chip, struct pmic_mpp_state, chip); 184 }; 185 186 static int pmic_mpp_read(struct pmic_mpp_state *state, 187 struct pmic_mpp_pad *pad, unsigned int addr) 188 { 189 unsigned int val; 190 int ret; 191 192 ret = regmap_read(state->map, pad->base + addr, &val); 193 if (ret < 0) 194 dev_err(state->dev, "read 0x%x failed\n", addr); 195 else 196 ret = val; 197 198 return ret; 199 } 200 201 static int pmic_mpp_write(struct pmic_mpp_state *state, 202 struct pmic_mpp_pad *pad, unsigned int addr, 203 unsigned int val) 204 { 205 int ret; 206 207 ret = regmap_write(state->map, pad->base + addr, val); 208 if (ret < 0) 209 dev_err(state->dev, "write 0x%x failed\n", addr); 210 211 return ret; 212 } 213 214 static int pmic_mpp_get_groups_count(struct pinctrl_dev *pctldev) 215 { 216 /* Every PIN is a group */ 217 return pctldev->desc->npins; 218 } 219 220 static const char *pmic_mpp_get_group_name(struct pinctrl_dev *pctldev, 221 unsigned pin) 222 { 223 return pctldev->desc->pins[pin].name; 224 } 225 226 static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev, 227 unsigned pin, 228 const unsigned **pins, unsigned *num_pins) 229 { 230 *pins = &pctldev->desc->pins[pin].number; 231 *num_pins = 1; 232 return 0; 233 } 234 235 static const struct pinctrl_ops pmic_mpp_pinctrl_ops = { 236 .get_groups_count = pmic_mpp_get_groups_count, 237 .get_group_name = pmic_mpp_get_group_name, 238 .get_group_pins = pmic_mpp_get_group_pins, 239 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 240 .dt_free_map = pinctrl_utils_dt_free_map, 241 }; 242 243 static int pmic_mpp_get_functions_count(struct pinctrl_dev *pctldev) 244 { 245 return ARRAY_SIZE(pmic_mpp_functions); 246 } 247 248 static const char *pmic_mpp_get_function_name(struct pinctrl_dev *pctldev, 249 unsigned function) 250 { 251 return pmic_mpp_functions[function]; 252 } 253 254 static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev, 255 unsigned function, 256 const char *const **groups, 257 unsigned *const num_qgroups) 258 { 259 *groups = pmic_mpp_groups; 260 *num_qgroups = pctldev->desc->npins; 261 return 0; 262 } 263 264 static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state, 265 struct pmic_mpp_pad *pad) 266 { 267 unsigned int mode; 268 unsigned int sel; 269 unsigned int val; 270 unsigned int en; 271 272 switch (pad->function) { 273 case PMIC_MPP_ANALOG: 274 if (pad->input_enabled && pad->output_enabled) 275 mode = PMIC_MPP_MODE_ANALOG_BIDIR; 276 else if (pad->input_enabled) 277 mode = PMIC_MPP_MODE_ANALOG_INPUT; 278 else 279 mode = PMIC_MPP_MODE_ANALOG_OUTPUT; 280 break; 281 case PMIC_MPP_DIGITAL: 282 if (pad->input_enabled && pad->output_enabled) 283 mode = PMIC_MPP_MODE_DIGITAL_BIDIR; 284 else if (pad->input_enabled) 285 mode = PMIC_MPP_MODE_DIGITAL_INPUT; 286 else 287 mode = PMIC_MPP_MODE_DIGITAL_OUTPUT; 288 break; 289 case PMIC_MPP_SINK: 290 default: 291 mode = PMIC_MPP_MODE_CURRENT_SINK; 292 break; 293 } 294 295 if (pad->dtest) 296 sel = PMIC_MPP_SELECTOR_DTEST_FIRST + pad->dtest - 1; 297 else if (pad->paired) 298 sel = PMIC_MPP_SELECTOR_PAIRED; 299 else 300 sel = PMIC_MPP_SELECTOR_NORMAL; 301 302 en = !!pad->out_value; 303 304 val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT | 305 sel << PMIC_MPP_REG_MODE_FUNCTION_SHIFT | 306 en; 307 308 return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); 309 } 310 311 static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function, 312 unsigned pin) 313 { 314 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); 315 struct pmic_mpp_pad *pad; 316 unsigned int val; 317 int ret; 318 319 pad = pctldev->desc->pins[pin].drv_data; 320 321 pad->function = function; 322 323 ret = pmic_mpp_write_mode_ctl(state, pad); 324 325 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; 326 327 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); 328 } 329 330 static const struct pinmux_ops pmic_mpp_pinmux_ops = { 331 .get_functions_count = pmic_mpp_get_functions_count, 332 .get_function_name = pmic_mpp_get_function_name, 333 .get_function_groups = pmic_mpp_get_function_groups, 334 .set_mux = pmic_mpp_set_mux, 335 }; 336 337 static int pmic_mpp_config_get(struct pinctrl_dev *pctldev, 338 unsigned int pin, unsigned long *config) 339 { 340 unsigned param = pinconf_to_config_param(*config); 341 struct pmic_mpp_pad *pad; 342 unsigned arg = 0; 343 344 pad = pctldev->desc->pins[pin].drv_data; 345 346 switch (param) { 347 case PIN_CONFIG_BIAS_DISABLE: 348 arg = pad->pullup == PMIC_MPP_PULL_UP_OPEN; 349 break; 350 case PIN_CONFIG_BIAS_PULL_UP: 351 switch (pad->pullup) { 352 case PMIC_MPP_PULL_UP_OPEN: 353 arg = 0; 354 break; 355 case PMIC_MPP_PULL_UP_0P6KOHM: 356 arg = 600; 357 break; 358 case PMIC_MPP_PULL_UP_10KOHM: 359 arg = 10000; 360 break; 361 case PMIC_MPP_PULL_UP_30KOHM: 362 arg = 30000; 363 break; 364 default: 365 return -EINVAL; 366 } 367 break; 368 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 369 arg = !pad->is_enabled; 370 break; 371 case PIN_CONFIG_POWER_SOURCE: 372 arg = pad->power_source; 373 break; 374 case PIN_CONFIG_INPUT_ENABLE: 375 arg = pad->input_enabled; 376 break; 377 case PIN_CONFIG_OUTPUT: 378 arg = pad->out_value; 379 break; 380 case PMIC_MPP_CONF_DTEST_SELECTOR: 381 arg = pad->dtest; 382 break; 383 case PMIC_MPP_CONF_AMUX_ROUTE: 384 arg = pad->amux_input; 385 break; 386 case PMIC_MPP_CONF_PAIRED: 387 arg = pad->paired; 388 break; 389 case PIN_CONFIG_DRIVE_STRENGTH: 390 arg = pad->drive_strength; 391 break; 392 case PMIC_MPP_CONF_ANALOG_LEVEL: 393 arg = pad->aout_level; 394 break; 395 default: 396 return -EINVAL; 397 } 398 399 /* Convert register value to pinconf value */ 400 *config = pinconf_to_config_packed(param, arg); 401 return 0; 402 } 403 404 static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 405 unsigned long *configs, unsigned nconfs) 406 { 407 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); 408 struct pmic_mpp_pad *pad; 409 unsigned param, arg; 410 unsigned int val; 411 int i, ret; 412 413 pad = pctldev->desc->pins[pin].drv_data; 414 415 /* Make it possible to enable the pin, by not setting high impedance */ 416 pad->is_enabled = true; 417 418 for (i = 0; i < nconfs; i++) { 419 param = pinconf_to_config_param(configs[i]); 420 arg = pinconf_to_config_argument(configs[i]); 421 422 switch (param) { 423 case PIN_CONFIG_BIAS_DISABLE: 424 pad->pullup = PMIC_MPP_PULL_UP_OPEN; 425 break; 426 case PIN_CONFIG_BIAS_PULL_UP: 427 switch (arg) { 428 case 600: 429 pad->pullup = PMIC_MPP_PULL_UP_0P6KOHM; 430 break; 431 case 10000: 432 pad->pullup = PMIC_MPP_PULL_UP_10KOHM; 433 break; 434 case 30000: 435 pad->pullup = PMIC_MPP_PULL_UP_30KOHM; 436 break; 437 default: 438 return -EINVAL; 439 } 440 break; 441 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 442 pad->is_enabled = false; 443 break; 444 case PIN_CONFIG_POWER_SOURCE: 445 if (arg >= pad->num_sources) 446 return -EINVAL; 447 pad->power_source = arg; 448 break; 449 case PIN_CONFIG_INPUT_ENABLE: 450 pad->input_enabled = arg ? true : false; 451 break; 452 case PIN_CONFIG_OUTPUT: 453 pad->output_enabled = true; 454 pad->out_value = arg; 455 break; 456 case PMIC_MPP_CONF_DTEST_SELECTOR: 457 pad->dtest = arg; 458 break; 459 case PIN_CONFIG_DRIVE_STRENGTH: 460 arg = pad->drive_strength; 461 break; 462 case PMIC_MPP_CONF_AMUX_ROUTE: 463 if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4) 464 return -EINVAL; 465 pad->amux_input = arg; 466 break; 467 case PMIC_MPP_CONF_ANALOG_LEVEL: 468 pad->aout_level = arg; 469 break; 470 case PMIC_MPP_CONF_PAIRED: 471 pad->paired = !!arg; 472 break; 473 default: 474 return -EINVAL; 475 } 476 } 477 478 val = pad->power_source << PMIC_MPP_REG_VIN_SHIFT; 479 480 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val); 481 if (ret < 0) 482 return ret; 483 484 val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT; 485 486 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL, val); 487 if (ret < 0) 488 return ret; 489 490 val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK; 491 492 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val); 493 if (ret < 0) 494 return ret; 495 496 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level); 497 if (ret < 0) 498 return ret; 499 500 ret = pmic_mpp_write_mode_ctl(state, pad); 501 if (ret < 0) 502 return ret; 503 504 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; 505 506 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); 507 } 508 509 static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, 510 struct seq_file *s, unsigned pin) 511 { 512 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); 513 struct pmic_mpp_pad *pad; 514 int ret; 515 516 static const char *const biases[] = { 517 "0.6kOhm", "10kOhm", "30kOhm", "Disabled" 518 }; 519 520 pad = pctldev->desc->pins[pin].drv_data; 521 522 seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET); 523 524 if (!pad->is_enabled) { 525 seq_puts(s, " ---"); 526 } else { 527 528 if (pad->input_enabled) { 529 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); 530 if (ret < 0) 531 return; 532 533 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; 534 pad->out_value = ret; 535 } 536 537 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in"); 538 seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]); 539 seq_printf(s, " vin-%d", pad->power_source); 540 seq_printf(s, " %d", pad->aout_level); 541 seq_printf(s, " %-8s", biases[pad->pullup]); 542 seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); 543 if (pad->dtest) 544 seq_printf(s, " dtest%d", pad->dtest); 545 if (pad->paired) 546 seq_puts(s, " paired"); 547 } 548 } 549 550 static const struct pinconf_ops pmic_mpp_pinconf_ops = { 551 .is_generic = true, 552 .pin_config_group_get = pmic_mpp_config_get, 553 .pin_config_group_set = pmic_mpp_config_set, 554 .pin_config_group_dbg_show = pmic_mpp_config_dbg_show, 555 }; 556 557 static int pmic_mpp_direction_input(struct gpio_chip *chip, unsigned pin) 558 { 559 struct pmic_mpp_state *state = to_mpp_state(chip); 560 unsigned long config; 561 562 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); 563 564 return pmic_mpp_config_set(state->ctrl, pin, &config, 1); 565 } 566 567 static int pmic_mpp_direction_output(struct gpio_chip *chip, 568 unsigned pin, int val) 569 { 570 struct pmic_mpp_state *state = to_mpp_state(chip); 571 unsigned long config; 572 573 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); 574 575 return pmic_mpp_config_set(state->ctrl, pin, &config, 1); 576 } 577 578 static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin) 579 { 580 struct pmic_mpp_state *state = to_mpp_state(chip); 581 struct pmic_mpp_pad *pad; 582 int ret; 583 584 pad = state->ctrl->desc->pins[pin].drv_data; 585 586 if (pad->input_enabled) { 587 ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); 588 if (ret < 0) 589 return ret; 590 591 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; 592 } 593 594 return pad->out_value; 595 } 596 597 static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value) 598 { 599 struct pmic_mpp_state *state = to_mpp_state(chip); 600 unsigned long config; 601 602 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); 603 604 pmic_mpp_config_set(state->ctrl, pin, &config, 1); 605 } 606 607 static int pmic_mpp_request(struct gpio_chip *chip, unsigned base) 608 { 609 return pinctrl_request_gpio(chip->base + base); 610 } 611 612 static void pmic_mpp_free(struct gpio_chip *chip, unsigned base) 613 { 614 pinctrl_free_gpio(chip->base + base); 615 } 616 617 static int pmic_mpp_of_xlate(struct gpio_chip *chip, 618 const struct of_phandle_args *gpio_desc, 619 u32 *flags) 620 { 621 if (chip->of_gpio_n_cells < 2) 622 return -EINVAL; 623 624 if (flags) 625 *flags = gpio_desc->args[1]; 626 627 return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET; 628 } 629 630 static int pmic_mpp_to_irq(struct gpio_chip *chip, unsigned pin) 631 { 632 struct pmic_mpp_state *state = to_mpp_state(chip); 633 struct pmic_mpp_pad *pad; 634 635 pad = state->ctrl->desc->pins[pin].drv_data; 636 637 return pad->irq; 638 } 639 640 static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) 641 { 642 struct pmic_mpp_state *state = to_mpp_state(chip); 643 unsigned i; 644 645 for (i = 0; i < chip->ngpio; i++) { 646 pmic_mpp_config_dbg_show(state->ctrl, s, i); 647 seq_puts(s, "\n"); 648 } 649 } 650 651 static const struct gpio_chip pmic_mpp_gpio_template = { 652 .direction_input = pmic_mpp_direction_input, 653 .direction_output = pmic_mpp_direction_output, 654 .get = pmic_mpp_get, 655 .set = pmic_mpp_set, 656 .request = pmic_mpp_request, 657 .free = pmic_mpp_free, 658 .of_xlate = pmic_mpp_of_xlate, 659 .to_irq = pmic_mpp_to_irq, 660 .dbg_show = pmic_mpp_dbg_show, 661 }; 662 663 static int pmic_mpp_populate(struct pmic_mpp_state *state, 664 struct pmic_mpp_pad *pad) 665 { 666 int type, subtype, val, dir; 667 unsigned int sel; 668 669 type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE); 670 if (type < 0) 671 return type; 672 673 if (type != PMIC_MPP_TYPE) { 674 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", 675 type, pad->base); 676 return -ENODEV; 677 } 678 679 subtype = pmic_mpp_read(state, pad, PMIC_MPP_REG_SUBTYPE); 680 if (subtype < 0) 681 return subtype; 682 683 switch (subtype) { 684 case PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT: 685 case PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT: 686 case PMIC_MPP_SUBTYPE_4CH_NO_SINK: 687 case PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK: 688 case PMIC_MPP_SUBTYPE_4CH_FULL_FUNC: 689 pad->num_sources = 4; 690 break; 691 case PMIC_MPP_SUBTYPE_8CH_FULL_FUNC: 692 pad->num_sources = 8; 693 break; 694 default: 695 dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n", 696 subtype, pad->base); 697 return -ENODEV; 698 } 699 700 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL); 701 if (val < 0) 702 return val; 703 704 pad->out_value = val & PMIC_MPP_REG_MODE_VALUE_MASK; 705 706 dir = val >> PMIC_MPP_REG_MODE_DIR_SHIFT; 707 dir &= PMIC_MPP_REG_MODE_DIR_MASK; 708 709 switch (dir) { 710 case PMIC_MPP_MODE_DIGITAL_INPUT: 711 pad->input_enabled = true; 712 pad->output_enabled = false; 713 pad->function = PMIC_MPP_DIGITAL; 714 break; 715 case PMIC_MPP_MODE_DIGITAL_OUTPUT: 716 pad->input_enabled = false; 717 pad->output_enabled = true; 718 pad->function = PMIC_MPP_DIGITAL; 719 break; 720 case PMIC_MPP_MODE_DIGITAL_BIDIR: 721 pad->input_enabled = true; 722 pad->output_enabled = true; 723 pad->function = PMIC_MPP_DIGITAL; 724 break; 725 case PMIC_MPP_MODE_ANALOG_BIDIR: 726 pad->input_enabled = true; 727 pad->output_enabled = true; 728 pad->function = PMIC_MPP_ANALOG; 729 break; 730 case PMIC_MPP_MODE_ANALOG_INPUT: 731 pad->input_enabled = true; 732 pad->output_enabled = false; 733 pad->function = PMIC_MPP_ANALOG; 734 break; 735 case PMIC_MPP_MODE_ANALOG_OUTPUT: 736 pad->input_enabled = false; 737 pad->output_enabled = true; 738 pad->function = PMIC_MPP_ANALOG; 739 break; 740 case PMIC_MPP_MODE_CURRENT_SINK: 741 pad->input_enabled = false; 742 pad->output_enabled = true; 743 pad->function = PMIC_MPP_SINK; 744 break; 745 default: 746 dev_err(state->dev, "unknown MPP direction\n"); 747 return -ENODEV; 748 } 749 750 sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT; 751 sel &= PMIC_MPP_REG_MODE_FUNCTION_MASK; 752 753 if (sel >= PMIC_MPP_SELECTOR_DTEST_FIRST) 754 pad->dtest = sel + 1; 755 else if (sel == PMIC_MPP_SELECTOR_PAIRED) 756 pad->paired = true; 757 758 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL); 759 if (val < 0) 760 return val; 761 762 pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT; 763 pad->power_source &= PMIC_MPP_REG_VIN_MASK; 764 765 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL); 766 if (val < 0) 767 return val; 768 769 pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT; 770 pad->pullup &= PMIC_MPP_REG_PULL_MASK; 771 772 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL); 773 if (val < 0) 774 return val; 775 776 pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT; 777 pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK; 778 779 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL); 780 if (val < 0) 781 return val; 782 783 pad->drive_strength = val; 784 785 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL); 786 if (val < 0) 787 return val; 788 789 pad->aout_level = val; 790 791 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL); 792 if (val < 0) 793 return val; 794 795 pad->is_enabled = !!val; 796 797 return 0; 798 } 799 800 static int pmic_mpp_probe(struct platform_device *pdev) 801 { 802 struct device *dev = &pdev->dev; 803 struct pinctrl_pin_desc *pindesc; 804 struct pinctrl_desc *pctrldesc; 805 struct pmic_mpp_pad *pad, *pads; 806 struct pmic_mpp_state *state; 807 int ret, npins, i; 808 u32 res[2]; 809 810 ret = of_property_read_u32_array(dev->of_node, "reg", res, 2); 811 if (ret < 0) { 812 dev_err(dev, "missing base address and/or range"); 813 return ret; 814 } 815 816 npins = res[1] / PMIC_MPP_ADDRESS_RANGE; 817 if (!npins) 818 return -EINVAL; 819 820 BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups)); 821 822 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); 823 if (!state) 824 return -ENOMEM; 825 826 platform_set_drvdata(pdev, state); 827 828 state->dev = &pdev->dev; 829 state->map = dev_get_regmap(dev->parent, NULL); 830 831 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); 832 if (!pindesc) 833 return -ENOMEM; 834 835 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); 836 if (!pads) 837 return -ENOMEM; 838 839 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); 840 if (!pctrldesc) 841 return -ENOMEM; 842 843 pctrldesc->pctlops = &pmic_mpp_pinctrl_ops; 844 pctrldesc->pmxops = &pmic_mpp_pinmux_ops; 845 pctrldesc->confops = &pmic_mpp_pinconf_ops; 846 pctrldesc->owner = THIS_MODULE; 847 pctrldesc->name = dev_name(dev); 848 pctrldesc->pins = pindesc; 849 pctrldesc->npins = npins; 850 851 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings); 852 pctrldesc->custom_params = pmic_mpp_bindings; 853 #ifdef CONFIG_DEBUG_FS 854 pctrldesc->custom_conf_items = pmic_conf_items; 855 #endif 856 857 for (i = 0; i < npins; i++, pindesc++) { 858 pad = &pads[i]; 859 pindesc->drv_data = pad; 860 pindesc->number = i; 861 pindesc->name = pmic_mpp_groups[i]; 862 863 pad->irq = platform_get_irq(pdev, i); 864 if (pad->irq < 0) 865 return pad->irq; 866 867 pad->base = res[0] + i * PMIC_MPP_ADDRESS_RANGE; 868 869 ret = pmic_mpp_populate(state, pad); 870 if (ret < 0) 871 return ret; 872 } 873 874 state->chip = pmic_mpp_gpio_template; 875 state->chip.dev = dev; 876 state->chip.base = -1; 877 state->chip.ngpio = npins; 878 state->chip.label = dev_name(dev); 879 state->chip.of_gpio_n_cells = 2; 880 state->chip.can_sleep = false; 881 882 state->ctrl = pinctrl_register(pctrldesc, dev, state); 883 if (IS_ERR(state->ctrl)) 884 return PTR_ERR(state->ctrl); 885 886 ret = gpiochip_add(&state->chip); 887 if (ret) { 888 dev_err(state->dev, "can't add gpio chip\n"); 889 goto err_chip; 890 } 891 892 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins); 893 if (ret) { 894 dev_err(dev, "failed to add pin range\n"); 895 goto err_range; 896 } 897 898 return 0; 899 900 err_range: 901 gpiochip_remove(&state->chip); 902 err_chip: 903 pinctrl_unregister(state->ctrl); 904 return ret; 905 } 906 907 static int pmic_mpp_remove(struct platform_device *pdev) 908 { 909 struct pmic_mpp_state *state = platform_get_drvdata(pdev); 910 911 gpiochip_remove(&state->chip); 912 pinctrl_unregister(state->ctrl); 913 return 0; 914 } 915 916 static const struct of_device_id pmic_mpp_of_match[] = { 917 { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */ 918 { .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */ 919 { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */ 920 { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */ 921 { }, 922 }; 923 924 MODULE_DEVICE_TABLE(of, pmic_mpp_of_match); 925 926 static struct platform_driver pmic_mpp_driver = { 927 .driver = { 928 .name = "qcom-spmi-mpp", 929 .of_match_table = pmic_mpp_of_match, 930 }, 931 .probe = pmic_mpp_probe, 932 .remove = pmic_mpp_remove, 933 }; 934 935 module_platform_driver(pmic_mpp_driver); 936 937 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); 938 MODULE_DESCRIPTION("Qualcomm SPMI PMIC MPP pin control driver"); 939 MODULE_ALIAS("platform:qcom-spmi-mpp"); 940 MODULE_LICENSE("GPL v2"); 941