1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/gpio/driver.h> 7 #include <linux/interrupt.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_irq.h> 11 #include <linux/pinctrl/pinconf-generic.h> 12 #include <linux/pinctrl/pinconf.h> 13 #include <linux/pinctrl/pinmux.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 #include <linux/types.h> 18 19 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 20 21 #include "../core.h" 22 #include "../pinctrl-utils.h" 23 24 #define PMIC_GPIO_ADDRESS_RANGE 0x100 25 26 /* type and subtype registers base address offsets */ 27 #define PMIC_GPIO_REG_TYPE 0x4 28 #define PMIC_GPIO_REG_SUBTYPE 0x5 29 30 /* GPIO peripheral type and subtype out_values */ 31 #define PMIC_GPIO_TYPE 0x10 32 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1 33 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5 34 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9 35 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd 36 #define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10 37 #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11 38 39 #define PMIC_MPP_REG_RT_STS 0x10 40 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 41 42 /* control register base address offsets */ 43 #define PMIC_GPIO_REG_MODE_CTL 0x40 44 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41 45 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42 46 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44 47 #define PMIC_GPIO_REG_DIG_IN_CTL 0x43 48 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45 49 #define PMIC_GPIO_REG_EN_CTL 0x46 50 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A 51 52 /* PMIC_GPIO_REG_MODE_CTL */ 53 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1 54 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1 55 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7 56 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4 57 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7 58 59 #define PMIC_GPIO_MODE_DIGITAL_INPUT 0 60 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1 61 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2 62 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3 63 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3 64 65 /* PMIC_GPIO_REG_DIG_VIN_CTL */ 66 #define PMIC_GPIO_REG_VIN_SHIFT 0 67 #define PMIC_GPIO_REG_VIN_MASK 0x7 68 69 /* PMIC_GPIO_REG_DIG_PULL_CTL */ 70 #define PMIC_GPIO_REG_PULL_SHIFT 0 71 #define PMIC_GPIO_REG_PULL_MASK 0x7 72 73 #define PMIC_GPIO_PULL_DOWN 4 74 #define PMIC_GPIO_PULL_DISABLE 5 75 76 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */ 77 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80 78 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7 79 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF 80 81 /* PMIC_GPIO_REG_DIG_IN_CTL */ 82 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80 83 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7 84 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf 85 86 /* PMIC_GPIO_REG_DIG_OUT_CTL */ 87 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0 88 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3 89 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4 90 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3 91 92 /* 93 * Output type - indicates pin should be configured as push-pull, 94 * open drain or open source. 95 */ 96 #define PMIC_GPIO_OUT_BUF_CMOS 0 97 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1 98 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2 99 100 /* PMIC_GPIO_REG_EN_CTL */ 101 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7 102 103 #define PMIC_GPIO_PHYSICAL_OFFSET 1 104 105 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */ 106 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3 107 108 /* Qualcomm specific pin configurations */ 109 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1) 110 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2) 111 #define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3) 112 #define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4) 113 #define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5) 114 115 /* The index of each function in pmic_gpio_functions[] array */ 116 enum pmic_gpio_func_index { 117 PMIC_GPIO_FUNC_INDEX_NORMAL, 118 PMIC_GPIO_FUNC_INDEX_PAIRED, 119 PMIC_GPIO_FUNC_INDEX_FUNC1, 120 PMIC_GPIO_FUNC_INDEX_FUNC2, 121 PMIC_GPIO_FUNC_INDEX_FUNC3, 122 PMIC_GPIO_FUNC_INDEX_FUNC4, 123 PMIC_GPIO_FUNC_INDEX_DTEST1, 124 PMIC_GPIO_FUNC_INDEX_DTEST2, 125 PMIC_GPIO_FUNC_INDEX_DTEST3, 126 PMIC_GPIO_FUNC_INDEX_DTEST4, 127 }; 128 129 /** 130 * struct pmic_gpio_pad - keep current GPIO settings 131 * @base: Address base in SPMI device. 132 * @is_enabled: Set to false when GPIO should be put in high Z state. 133 * @out_value: Cached pin output value 134 * @have_buffer: Set to true if GPIO output could be configured in push-pull, 135 * open-drain or open-source mode. 136 * @output_enabled: Set to true if GPIO output logic is enabled. 137 * @input_enabled: Set to true if GPIO input buffer logic is enabled. 138 * @analog_pass: Set to true if GPIO is in analog-pass-through mode. 139 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11). 140 * @num_sources: Number of power-sources supported by this GPIO. 141 * @power_source: Current power-source used. 142 * @buffer_type: Push-pull, open-drain or open-source. 143 * @pullup: Constant current which flow trough GPIO output buffer. 144 * @strength: No, Low, Medium, High 145 * @function: See pmic_gpio_functions[] 146 * @atest: the ATEST selection for GPIO analog-pass-through mode 147 * @dtest_buffer: the DTEST buffer selection for digital input mode. 148 */ 149 struct pmic_gpio_pad { 150 u16 base; 151 bool is_enabled; 152 bool out_value; 153 bool have_buffer; 154 bool output_enabled; 155 bool input_enabled; 156 bool analog_pass; 157 bool lv_mv_type; 158 unsigned int num_sources; 159 unsigned int power_source; 160 unsigned int buffer_type; 161 unsigned int pullup; 162 unsigned int strength; 163 unsigned int function; 164 unsigned int atest; 165 unsigned int dtest_buffer; 166 }; 167 168 struct pmic_gpio_state { 169 struct device *dev; 170 struct regmap *map; 171 struct pinctrl_dev *ctrl; 172 struct gpio_chip chip; 173 }; 174 175 static const struct pinconf_generic_params pmic_gpio_bindings[] = { 176 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0}, 177 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0}, 178 {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0}, 179 {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0}, 180 {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0}, 181 }; 182 183 #ifdef CONFIG_DEBUG_FS 184 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = { 185 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true), 186 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true), 187 PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true), 188 PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true), 189 PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true), 190 }; 191 #endif 192 193 static const char *const pmic_gpio_groups[] = { 194 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", 195 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", 196 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", 197 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 198 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", 199 }; 200 201 static const char *const pmic_gpio_functions[] = { 202 [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL, 203 [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED, 204 [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1, 205 [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2, 206 [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3, 207 [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4, 208 [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1, 209 [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2, 210 [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3, 211 [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4, 212 }; 213 214 static int pmic_gpio_read(struct pmic_gpio_state *state, 215 struct pmic_gpio_pad *pad, unsigned int addr) 216 { 217 unsigned int val; 218 int ret; 219 220 ret = regmap_read(state->map, pad->base + addr, &val); 221 if (ret < 0) 222 dev_err(state->dev, "read 0x%x failed\n", addr); 223 else 224 ret = val; 225 226 return ret; 227 } 228 229 static int pmic_gpio_write(struct pmic_gpio_state *state, 230 struct pmic_gpio_pad *pad, unsigned int addr, 231 unsigned int val) 232 { 233 int ret; 234 235 ret = regmap_write(state->map, pad->base + addr, val); 236 if (ret < 0) 237 dev_err(state->dev, "write 0x%x failed\n", addr); 238 239 return ret; 240 } 241 242 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev) 243 { 244 /* Every PIN is a group */ 245 return pctldev->desc->npins; 246 } 247 248 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev, 249 unsigned pin) 250 { 251 return pctldev->desc->pins[pin].name; 252 } 253 254 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin, 255 const unsigned **pins, unsigned *num_pins) 256 { 257 *pins = &pctldev->desc->pins[pin].number; 258 *num_pins = 1; 259 return 0; 260 } 261 262 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = { 263 .get_groups_count = pmic_gpio_get_groups_count, 264 .get_group_name = pmic_gpio_get_group_name, 265 .get_group_pins = pmic_gpio_get_group_pins, 266 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 267 .dt_free_map = pinctrl_utils_free_map, 268 }; 269 270 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev) 271 { 272 return ARRAY_SIZE(pmic_gpio_functions); 273 } 274 275 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev, 276 unsigned function) 277 { 278 return pmic_gpio_functions[function]; 279 } 280 281 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev, 282 unsigned function, 283 const char *const **groups, 284 unsigned *const num_qgroups) 285 { 286 *groups = pmic_gpio_groups; 287 *num_qgroups = pctldev->desc->npins; 288 return 0; 289 } 290 291 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function, 292 unsigned pin) 293 { 294 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 295 struct pmic_gpio_pad *pad; 296 unsigned int val; 297 int ret; 298 299 if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) { 300 pr_err("function: %d is not defined\n", function); 301 return -EINVAL; 302 } 303 304 pad = pctldev->desc->pins[pin].drv_data; 305 /* 306 * Non-LV/MV subtypes only support 2 special functions, 307 * offsetting the dtestx function values by 2 308 */ 309 if (!pad->lv_mv_type) { 310 if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 || 311 function == PMIC_GPIO_FUNC_INDEX_FUNC4) { 312 pr_err("LV/MV subtype doesn't have func3/func4\n"); 313 return -EINVAL; 314 } 315 if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1) 316 function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 - 317 PMIC_GPIO_FUNC_INDEX_FUNC3); 318 } 319 320 pad->function = function; 321 322 if (pad->analog_pass) 323 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; 324 else if (pad->output_enabled && pad->input_enabled) 325 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; 326 else if (pad->output_enabled) 327 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; 328 else 329 val = PMIC_GPIO_MODE_DIGITAL_INPUT; 330 331 if (pad->lv_mv_type) { 332 ret = pmic_gpio_write(state, pad, 333 PMIC_GPIO_REG_MODE_CTL, val); 334 if (ret < 0) 335 return ret; 336 337 val = pad->atest - 1; 338 ret = pmic_gpio_write(state, pad, 339 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); 340 if (ret < 0) 341 return ret; 342 343 val = pad->out_value 344 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; 345 val |= pad->function 346 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; 347 ret = pmic_gpio_write(state, pad, 348 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); 349 if (ret < 0) 350 return ret; 351 } else { 352 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; 353 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 354 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 355 356 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); 357 if (ret < 0) 358 return ret; 359 } 360 361 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; 362 363 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); 364 } 365 366 static const struct pinmux_ops pmic_gpio_pinmux_ops = { 367 .get_functions_count = pmic_gpio_get_functions_count, 368 .get_function_name = pmic_gpio_get_function_name, 369 .get_function_groups = pmic_gpio_get_function_groups, 370 .set_mux = pmic_gpio_set_mux, 371 }; 372 373 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev, 374 unsigned int pin, unsigned long *config) 375 { 376 unsigned param = pinconf_to_config_param(*config); 377 struct pmic_gpio_pad *pad; 378 unsigned arg; 379 380 pad = pctldev->desc->pins[pin].drv_data; 381 382 switch (param) { 383 case PIN_CONFIG_DRIVE_PUSH_PULL: 384 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS) 385 return -EINVAL; 386 arg = 1; 387 break; 388 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 389 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS) 390 return -EINVAL; 391 arg = 1; 392 break; 393 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 394 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS) 395 return -EINVAL; 396 arg = 1; 397 break; 398 case PIN_CONFIG_BIAS_PULL_DOWN: 399 if (pad->pullup != PMIC_GPIO_PULL_DOWN) 400 return -EINVAL; 401 arg = 1; 402 break; 403 case PIN_CONFIG_BIAS_DISABLE: 404 if (pad->pullup != PMIC_GPIO_PULL_DISABLE) 405 return -EINVAL; 406 arg = 1; 407 break; 408 case PIN_CONFIG_BIAS_PULL_UP: 409 if (pad->pullup != PMIC_GPIO_PULL_UP_30) 410 return -EINVAL; 411 arg = 1; 412 break; 413 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 414 if (pad->is_enabled) 415 return -EINVAL; 416 arg = 1; 417 break; 418 case PIN_CONFIG_POWER_SOURCE: 419 arg = pad->power_source; 420 break; 421 case PIN_CONFIG_INPUT_ENABLE: 422 if (!pad->input_enabled) 423 return -EINVAL; 424 arg = 1; 425 break; 426 case PIN_CONFIG_OUTPUT: 427 arg = pad->out_value; 428 break; 429 case PMIC_GPIO_CONF_PULL_UP: 430 arg = pad->pullup; 431 break; 432 case PMIC_GPIO_CONF_STRENGTH: 433 arg = pad->strength; 434 break; 435 case PMIC_GPIO_CONF_ATEST: 436 arg = pad->atest; 437 break; 438 case PMIC_GPIO_CONF_ANALOG_PASS: 439 arg = pad->analog_pass; 440 break; 441 case PMIC_GPIO_CONF_DTEST_BUFFER: 442 arg = pad->dtest_buffer; 443 break; 444 default: 445 return -EINVAL; 446 } 447 448 *config = pinconf_to_config_packed(param, arg); 449 return 0; 450 } 451 452 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 453 unsigned long *configs, unsigned nconfs) 454 { 455 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 456 struct pmic_gpio_pad *pad; 457 unsigned param, arg; 458 unsigned int val; 459 int i, ret; 460 461 pad = pctldev->desc->pins[pin].drv_data; 462 463 pad->is_enabled = true; 464 for (i = 0; i < nconfs; i++) { 465 param = pinconf_to_config_param(configs[i]); 466 arg = pinconf_to_config_argument(configs[i]); 467 468 switch (param) { 469 case PIN_CONFIG_DRIVE_PUSH_PULL: 470 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS; 471 break; 472 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 473 if (!pad->have_buffer) 474 return -EINVAL; 475 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS; 476 break; 477 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 478 if (!pad->have_buffer) 479 return -EINVAL; 480 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS; 481 break; 482 case PIN_CONFIG_BIAS_DISABLE: 483 pad->pullup = PMIC_GPIO_PULL_DISABLE; 484 break; 485 case PIN_CONFIG_BIAS_PULL_UP: 486 pad->pullup = PMIC_GPIO_PULL_UP_30; 487 break; 488 case PIN_CONFIG_BIAS_PULL_DOWN: 489 if (arg) 490 pad->pullup = PMIC_GPIO_PULL_DOWN; 491 else 492 pad->pullup = PMIC_GPIO_PULL_DISABLE; 493 break; 494 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 495 pad->is_enabled = false; 496 break; 497 case PIN_CONFIG_POWER_SOURCE: 498 if (arg >= pad->num_sources) 499 return -EINVAL; 500 pad->power_source = arg; 501 break; 502 case PIN_CONFIG_INPUT_ENABLE: 503 pad->input_enabled = arg ? true : false; 504 break; 505 case PIN_CONFIG_OUTPUT: 506 pad->output_enabled = true; 507 pad->out_value = arg; 508 break; 509 case PMIC_GPIO_CONF_PULL_UP: 510 if (arg > PMIC_GPIO_PULL_UP_1P5_30) 511 return -EINVAL; 512 pad->pullup = arg; 513 break; 514 case PMIC_GPIO_CONF_STRENGTH: 515 if (arg > PMIC_GPIO_STRENGTH_LOW) 516 return -EINVAL; 517 pad->strength = arg; 518 break; 519 case PMIC_GPIO_CONF_ATEST: 520 if (!pad->lv_mv_type || arg > 4) 521 return -EINVAL; 522 pad->atest = arg; 523 break; 524 case PMIC_GPIO_CONF_ANALOG_PASS: 525 if (!pad->lv_mv_type) 526 return -EINVAL; 527 pad->analog_pass = true; 528 break; 529 case PMIC_GPIO_CONF_DTEST_BUFFER: 530 if (arg > 4) 531 return -EINVAL; 532 pad->dtest_buffer = arg; 533 break; 534 default: 535 return -EINVAL; 536 } 537 } 538 539 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT; 540 541 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val); 542 if (ret < 0) 543 return ret; 544 545 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT; 546 547 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val); 548 if (ret < 0) 549 return ret; 550 551 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT; 552 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; 553 554 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val); 555 if (ret < 0) 556 return ret; 557 558 if (pad->dtest_buffer == 0) { 559 val = 0; 560 } else { 561 if (pad->lv_mv_type) { 562 val = pad->dtest_buffer - 1; 563 val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN; 564 } else { 565 val = BIT(pad->dtest_buffer - 1); 566 } 567 } 568 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val); 569 if (ret < 0) 570 return ret; 571 572 if (pad->analog_pass) 573 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; 574 else if (pad->output_enabled && pad->input_enabled) 575 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; 576 else if (pad->output_enabled) 577 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; 578 else 579 val = PMIC_GPIO_MODE_DIGITAL_INPUT; 580 581 if (pad->lv_mv_type) { 582 ret = pmic_gpio_write(state, pad, 583 PMIC_GPIO_REG_MODE_CTL, val); 584 if (ret < 0) 585 return ret; 586 587 val = pad->atest - 1; 588 ret = pmic_gpio_write(state, pad, 589 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); 590 if (ret < 0) 591 return ret; 592 593 val = pad->out_value 594 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; 595 val |= pad->function 596 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; 597 ret = pmic_gpio_write(state, pad, 598 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); 599 if (ret < 0) 600 return ret; 601 } else { 602 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; 603 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 604 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 605 606 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); 607 if (ret < 0) 608 return ret; 609 } 610 611 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; 612 613 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); 614 615 return ret; 616 } 617 618 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev, 619 struct seq_file *s, unsigned pin) 620 { 621 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 622 struct pmic_gpio_pad *pad; 623 int ret, val, function; 624 625 static const char *const biases[] = { 626 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", 627 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" 628 }; 629 static const char *const buffer_types[] = { 630 "push-pull", "open-drain", "open-source" 631 }; 632 static const char *const strengths[] = { 633 "no", "high", "medium", "low" 634 }; 635 636 pad = pctldev->desc->pins[pin].drv_data; 637 638 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET); 639 640 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL); 641 642 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) { 643 seq_puts(s, " ---"); 644 } else { 645 if (pad->input_enabled) { 646 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); 647 if (ret < 0) 648 return; 649 650 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; 651 pad->out_value = ret; 652 } 653 /* 654 * For the non-LV/MV subtypes only 2 special functions are 655 * available, offsetting the dtest function values by 2. 656 */ 657 function = pad->function; 658 if (!pad->lv_mv_type && 659 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3) 660 function += PMIC_GPIO_FUNC_INDEX_DTEST1 - 661 PMIC_GPIO_FUNC_INDEX_FUNC3; 662 663 if (pad->analog_pass) 664 seq_puts(s, " analog-pass"); 665 else 666 seq_printf(s, " %-4s", 667 pad->output_enabled ? "out" : "in"); 668 seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); 669 seq_printf(s, " %-7s", pmic_gpio_functions[function]); 670 seq_printf(s, " vin-%d", pad->power_source); 671 seq_printf(s, " %-27s", biases[pad->pullup]); 672 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]); 673 seq_printf(s, " %-7s", strengths[pad->strength]); 674 seq_printf(s, " atest-%d", pad->atest); 675 seq_printf(s, " dtest-%d", pad->dtest_buffer); 676 } 677 } 678 679 static const struct pinconf_ops pmic_gpio_pinconf_ops = { 680 .is_generic = true, 681 .pin_config_group_get = pmic_gpio_config_get, 682 .pin_config_group_set = pmic_gpio_config_set, 683 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show, 684 }; 685 686 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 687 { 688 struct pmic_gpio_state *state = gpiochip_get_data(chip); 689 unsigned long config; 690 691 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); 692 693 return pmic_gpio_config_set(state->ctrl, pin, &config, 1); 694 } 695 696 static int pmic_gpio_direction_output(struct gpio_chip *chip, 697 unsigned pin, int val) 698 { 699 struct pmic_gpio_state *state = gpiochip_get_data(chip); 700 unsigned long config; 701 702 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); 703 704 return pmic_gpio_config_set(state->ctrl, pin, &config, 1); 705 } 706 707 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin) 708 { 709 struct pmic_gpio_state *state = gpiochip_get_data(chip); 710 struct pmic_gpio_pad *pad; 711 int ret; 712 713 pad = state->ctrl->desc->pins[pin].drv_data; 714 715 if (!pad->is_enabled) 716 return -EINVAL; 717 718 if (pad->input_enabled) { 719 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); 720 if (ret < 0) 721 return ret; 722 723 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; 724 } 725 726 return !!pad->out_value; 727 } 728 729 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value) 730 { 731 struct pmic_gpio_state *state = gpiochip_get_data(chip); 732 unsigned long config; 733 734 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); 735 736 pmic_gpio_config_set(state->ctrl, pin, &config, 1); 737 } 738 739 static int pmic_gpio_of_xlate(struct gpio_chip *chip, 740 const struct of_phandle_args *gpio_desc, 741 u32 *flags) 742 { 743 if (chip->of_gpio_n_cells < 2) 744 return -EINVAL; 745 746 if (flags) 747 *flags = gpio_desc->args[1]; 748 749 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET; 750 } 751 752 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 753 { 754 struct pmic_gpio_state *state = gpiochip_get_data(chip); 755 unsigned i; 756 757 for (i = 0; i < chip->ngpio; i++) { 758 pmic_gpio_config_dbg_show(state->ctrl, s, i); 759 seq_puts(s, "\n"); 760 } 761 } 762 763 static const struct gpio_chip pmic_gpio_gpio_template = { 764 .direction_input = pmic_gpio_direction_input, 765 .direction_output = pmic_gpio_direction_output, 766 .get = pmic_gpio_get, 767 .set = pmic_gpio_set, 768 .request = gpiochip_generic_request, 769 .free = gpiochip_generic_free, 770 .of_xlate = pmic_gpio_of_xlate, 771 .dbg_show = pmic_gpio_dbg_show, 772 }; 773 774 static int pmic_gpio_populate(struct pmic_gpio_state *state, 775 struct pmic_gpio_pad *pad) 776 { 777 int type, subtype, val, dir; 778 779 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE); 780 if (type < 0) 781 return type; 782 783 if (type != PMIC_GPIO_TYPE) { 784 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", 785 type, pad->base); 786 return -ENODEV; 787 } 788 789 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE); 790 if (subtype < 0) 791 return subtype; 792 793 switch (subtype) { 794 case PMIC_GPIO_SUBTYPE_GPIO_4CH: 795 pad->have_buffer = true; 796 case PMIC_GPIO_SUBTYPE_GPIOC_4CH: 797 pad->num_sources = 4; 798 break; 799 case PMIC_GPIO_SUBTYPE_GPIO_8CH: 800 pad->have_buffer = true; 801 case PMIC_GPIO_SUBTYPE_GPIOC_8CH: 802 pad->num_sources = 8; 803 break; 804 case PMIC_GPIO_SUBTYPE_GPIO_LV: 805 pad->num_sources = 1; 806 pad->have_buffer = true; 807 pad->lv_mv_type = true; 808 break; 809 case PMIC_GPIO_SUBTYPE_GPIO_MV: 810 pad->num_sources = 2; 811 pad->have_buffer = true; 812 pad->lv_mv_type = true; 813 break; 814 default: 815 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype); 816 return -ENODEV; 817 } 818 819 if (pad->lv_mv_type) { 820 val = pmic_gpio_read(state, pad, 821 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL); 822 if (val < 0) 823 return val; 824 825 pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT); 826 pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; 827 828 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); 829 if (val < 0) 830 return val; 831 832 dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK; 833 } else { 834 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); 835 if (val < 0) 836 return val; 837 838 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 839 840 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT; 841 dir &= PMIC_GPIO_REG_MODE_DIR_MASK; 842 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 843 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK; 844 } 845 846 switch (dir) { 847 case PMIC_GPIO_MODE_DIGITAL_INPUT: 848 pad->input_enabled = true; 849 pad->output_enabled = false; 850 break; 851 case PMIC_GPIO_MODE_DIGITAL_OUTPUT: 852 pad->input_enabled = false; 853 pad->output_enabled = true; 854 break; 855 case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT: 856 pad->input_enabled = true; 857 pad->output_enabled = true; 858 break; 859 case PMIC_GPIO_MODE_ANALOG_PASS_THRU: 860 if (!pad->lv_mv_type) 861 return -ENODEV; 862 pad->analog_pass = true; 863 break; 864 default: 865 dev_err(state->dev, "unknown GPIO direction\n"); 866 return -ENODEV; 867 } 868 869 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL); 870 if (val < 0) 871 return val; 872 873 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT; 874 pad->power_source &= PMIC_GPIO_REG_VIN_MASK; 875 876 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL); 877 if (val < 0) 878 return val; 879 880 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT; 881 pad->pullup &= PMIC_GPIO_REG_PULL_MASK; 882 883 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL); 884 if (val < 0) 885 return val; 886 887 if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN)) 888 pad->dtest_buffer = 889 (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1; 890 else if (!pad->lv_mv_type) 891 pad->dtest_buffer = ffs(val); 892 else 893 pad->dtest_buffer = 0; 894 895 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL); 896 if (val < 0) 897 return val; 898 899 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; 900 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK; 901 902 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT; 903 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK; 904 905 if (pad->lv_mv_type) { 906 val = pmic_gpio_read(state, pad, 907 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL); 908 if (val < 0) 909 return val; 910 pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1; 911 } 912 913 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */ 914 pad->is_enabled = true; 915 return 0; 916 } 917 918 static struct irq_chip pmic_gpio_irq_chip = { 919 .name = "spmi-gpio", 920 .irq_ack = irq_chip_ack_parent, 921 .irq_mask = irq_chip_mask_parent, 922 .irq_unmask = irq_chip_unmask_parent, 923 .irq_set_type = irq_chip_set_type_parent, 924 .irq_set_wake = irq_chip_set_wake_parent, 925 .flags = IRQCHIP_MASK_ON_SUSPEND, 926 }; 927 928 static int pmic_gpio_domain_translate(struct irq_domain *domain, 929 struct irq_fwspec *fwspec, 930 unsigned long *hwirq, 931 unsigned int *type) 932 { 933 struct pmic_gpio_state *state = container_of(domain->host_data, 934 struct pmic_gpio_state, 935 chip); 936 937 if (fwspec->param_count != 2 || 938 fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio) 939 return -EINVAL; 940 941 *hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET; 942 *type = fwspec->param[1]; 943 944 return 0; 945 } 946 947 static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip, 948 unsigned int offset) 949 { 950 return offset + PMIC_GPIO_PHYSICAL_OFFSET; 951 } 952 953 static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip, 954 unsigned int child_hwirq, 955 unsigned int child_type, 956 unsigned int *parent_hwirq, 957 unsigned int *parent_type) 958 { 959 *parent_hwirq = child_hwirq + 0xc0; 960 *parent_type = child_type; 961 962 return 0; 963 } 964 965 static int pmic_gpio_probe(struct platform_device *pdev) 966 { 967 struct irq_domain *parent_domain; 968 struct device_node *parent_node; 969 struct device *dev = &pdev->dev; 970 struct pinctrl_pin_desc *pindesc; 971 struct pinctrl_desc *pctrldesc; 972 struct pmic_gpio_pad *pad, *pads; 973 struct pmic_gpio_state *state; 974 struct gpio_irq_chip *girq; 975 int ret, npins, i; 976 u32 reg; 977 978 ret = of_property_read_u32(dev->of_node, "reg", ®); 979 if (ret < 0) { 980 dev_err(dev, "missing base address"); 981 return ret; 982 } 983 984 npins = (uintptr_t) device_get_match_data(&pdev->dev); 985 986 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); 987 if (!state) 988 return -ENOMEM; 989 990 platform_set_drvdata(pdev, state); 991 992 state->dev = &pdev->dev; 993 state->map = dev_get_regmap(dev->parent, NULL); 994 995 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); 996 if (!pindesc) 997 return -ENOMEM; 998 999 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); 1000 if (!pads) 1001 return -ENOMEM; 1002 1003 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); 1004 if (!pctrldesc) 1005 return -ENOMEM; 1006 1007 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops; 1008 pctrldesc->pmxops = &pmic_gpio_pinmux_ops; 1009 pctrldesc->confops = &pmic_gpio_pinconf_ops; 1010 pctrldesc->owner = THIS_MODULE; 1011 pctrldesc->name = dev_name(dev); 1012 pctrldesc->pins = pindesc; 1013 pctrldesc->npins = npins; 1014 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings); 1015 pctrldesc->custom_params = pmic_gpio_bindings; 1016 #ifdef CONFIG_DEBUG_FS 1017 pctrldesc->custom_conf_items = pmic_conf_items; 1018 #endif 1019 1020 for (i = 0; i < npins; i++, pindesc++) { 1021 pad = &pads[i]; 1022 pindesc->drv_data = pad; 1023 pindesc->number = i; 1024 pindesc->name = pmic_gpio_groups[i]; 1025 1026 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE; 1027 1028 ret = pmic_gpio_populate(state, pad); 1029 if (ret < 0) 1030 return ret; 1031 } 1032 1033 state->chip = pmic_gpio_gpio_template; 1034 state->chip.parent = dev; 1035 state->chip.base = -1; 1036 state->chip.ngpio = npins; 1037 state->chip.label = dev_name(dev); 1038 state->chip.of_gpio_n_cells = 2; 1039 state->chip.can_sleep = false; 1040 1041 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state); 1042 if (IS_ERR(state->ctrl)) 1043 return PTR_ERR(state->ctrl); 1044 1045 parent_node = of_irq_find_parent(state->dev->of_node); 1046 if (!parent_node) 1047 return -ENXIO; 1048 1049 parent_domain = irq_find_host(parent_node); 1050 of_node_put(parent_node); 1051 if (!parent_domain) 1052 return -ENXIO; 1053 1054 girq = &state->chip.irq; 1055 girq->chip = &pmic_gpio_irq_chip; 1056 girq->default_type = IRQ_TYPE_NONE; 1057 girq->handler = handle_level_irq; 1058 girq->fwnode = of_node_to_fwnode(state->dev->of_node); 1059 girq->parent_domain = parent_domain; 1060 girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq; 1061 girq->populate_parent_fwspec = gpiochip_populate_parent_fwspec_fourcell; 1062 girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq; 1063 girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate; 1064 1065 ret = gpiochip_add_data(&state->chip, state); 1066 if (ret) { 1067 dev_err(state->dev, "can't add gpio chip\n"); 1068 return ret; 1069 } 1070 1071 /* 1072 * For DeviceTree-supported systems, the gpio core checks the 1073 * pinctrl's device node for the "gpio-ranges" property. 1074 * If it is present, it takes care of adding the pin ranges 1075 * for the driver. In this case the driver can skip ahead. 1076 * 1077 * In order to remain compatible with older, existing DeviceTree 1078 * files which don't set the "gpio-ranges" property or systems that 1079 * utilize ACPI the driver has to call gpiochip_add_pin_range(). 1080 */ 1081 if (!of_property_read_bool(dev->of_node, "gpio-ranges")) { 1082 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, 1083 npins); 1084 if (ret) { 1085 dev_err(dev, "failed to add pin range\n"); 1086 goto err_range; 1087 } 1088 } 1089 1090 return 0; 1091 1092 err_range: 1093 gpiochip_remove(&state->chip); 1094 return ret; 1095 } 1096 1097 static int pmic_gpio_remove(struct platform_device *pdev) 1098 { 1099 struct pmic_gpio_state *state = platform_get_drvdata(pdev); 1100 1101 gpiochip_remove(&state->chip); 1102 return 0; 1103 } 1104 1105 static const struct of_device_id pmic_gpio_of_match[] = { 1106 { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 }, 1107 { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 }, 1108 { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 }, 1109 { .compatible = "qcom,pm8994-gpio", .data = (void *) 22 }, 1110 { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 }, 1111 { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 }, 1112 { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 }, 1113 { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 }, 1114 /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */ 1115 { .compatible = "qcom,pms405-gpio", .data = (void *) 12 }, 1116 { }, 1117 }; 1118 1119 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match); 1120 1121 static struct platform_driver pmic_gpio_driver = { 1122 .driver = { 1123 .name = "qcom-spmi-gpio", 1124 .of_match_table = pmic_gpio_of_match, 1125 }, 1126 .probe = pmic_gpio_probe, 1127 .remove = pmic_gpio_remove, 1128 }; 1129 1130 module_platform_driver(pmic_gpio_driver); 1131 1132 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); 1133 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver"); 1134 MODULE_ALIAS("platform:qcom-spmi-gpio"); 1135 MODULE_LICENSE("GPL v2"); 1136