1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2022, Linaro Limited 6 */ 7 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 12 #include "pinctrl-msm.h" 13 14 #define REG_SIZE 0x1000 15 16 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 17 { \ 18 .grp = PINCTRL_PINGROUP("gpio" #id, \ 19 gpio##id##_pins, \ 20 ARRAY_SIZE(gpio##id##_pins)), \ 21 .funcs = (int[]){ \ 22 msm_mux_gpio, /* gpio mode */ \ 23 msm_mux_##f1, \ 24 msm_mux_##f2, \ 25 msm_mux_##f3, \ 26 msm_mux_##f4, \ 27 msm_mux_##f5, \ 28 msm_mux_##f6, \ 29 msm_mux_##f7, \ 30 msm_mux_##f8, \ 31 msm_mux_##f9 \ 32 }, \ 33 .nfuncs = 10, \ 34 .ctl_reg = REG_SIZE * id, \ 35 .io_reg = 0x4 + REG_SIZE * id, \ 36 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 37 .intr_status_reg = 0xc + REG_SIZE * id, \ 38 .intr_target_reg = 0x8 + REG_SIZE * id, \ 39 .mux_bit = 2, \ 40 .pull_bit = 0, \ 41 .drv_bit = 6, \ 42 .i2c_pull_bit = 13, \ 43 .egpio_enable = 12, \ 44 .egpio_present = 11, \ 45 .oe_bit = 9, \ 46 .in_bit = 0, \ 47 .out_bit = 1, \ 48 .intr_enable_bit = 0, \ 49 .intr_status_bit = 0, \ 50 .intr_target_bit = 5, \ 51 .intr_target_kpss_val = 3, \ 52 .intr_raw_status_bit = 4, \ 53 .intr_polarity_bit = 1, \ 54 .intr_detection_bit = 2, \ 55 .intr_detection_width = 2, \ 56 } 57 58 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 59 { \ 60 .grp = PINCTRL_PINGROUP(#pg_name, \ 61 pg_name##_pins, \ 62 ARRAY_SIZE(pg_name##_pins)), \ 63 .ctl_reg = ctl, \ 64 .io_reg = 0, \ 65 .intr_cfg_reg = 0, \ 66 .intr_status_reg = 0, \ 67 .intr_target_reg = 0, \ 68 .mux_bit = -1, \ 69 .pull_bit = pull, \ 70 .drv_bit = drv, \ 71 .oe_bit = -1, \ 72 .in_bit = -1, \ 73 .out_bit = -1, \ 74 .intr_enable_bit = -1, \ 75 .intr_status_bit = -1, \ 76 .intr_target_bit = -1, \ 77 .intr_raw_status_bit = -1, \ 78 .intr_polarity_bit = -1, \ 79 .intr_detection_bit = -1, \ 80 .intr_detection_width = -1, \ 81 } 82 83 #define UFS_RESET(pg_name, offset) \ 84 { \ 85 .grp = PINCTRL_PINGROUP(#pg_name, \ 86 pg_name##_pins, \ 87 ARRAY_SIZE(pg_name##_pins)), \ 88 .ctl_reg = offset, \ 89 .io_reg = offset + 0x4, \ 90 .intr_cfg_reg = 0, \ 91 .intr_status_reg = 0, \ 92 .intr_target_reg = 0, \ 93 .mux_bit = -1, \ 94 .pull_bit = 3, \ 95 .drv_bit = 0, \ 96 .oe_bit = -1, \ 97 .in_bit = -1, \ 98 .out_bit = 0, \ 99 .intr_enable_bit = -1, \ 100 .intr_status_bit = -1, \ 101 .intr_target_bit = -1, \ 102 .intr_raw_status_bit = -1, \ 103 .intr_polarity_bit = -1, \ 104 .intr_detection_bit = -1, \ 105 .intr_detection_width = -1, \ 106 } 107 108 static const struct pinctrl_pin_desc sm8550_pins[] = { 109 PINCTRL_PIN(0, "GPIO_0"), 110 PINCTRL_PIN(1, "GPIO_1"), 111 PINCTRL_PIN(2, "GPIO_2"), 112 PINCTRL_PIN(3, "GPIO_3"), 113 PINCTRL_PIN(4, "GPIO_4"), 114 PINCTRL_PIN(5, "GPIO_5"), 115 PINCTRL_PIN(6, "GPIO_6"), 116 PINCTRL_PIN(7, "GPIO_7"), 117 PINCTRL_PIN(8, "GPIO_8"), 118 PINCTRL_PIN(9, "GPIO_9"), 119 PINCTRL_PIN(10, "GPIO_10"), 120 PINCTRL_PIN(11, "GPIO_11"), 121 PINCTRL_PIN(12, "GPIO_12"), 122 PINCTRL_PIN(13, "GPIO_13"), 123 PINCTRL_PIN(14, "GPIO_14"), 124 PINCTRL_PIN(15, "GPIO_15"), 125 PINCTRL_PIN(16, "GPIO_16"), 126 PINCTRL_PIN(17, "GPIO_17"), 127 PINCTRL_PIN(18, "GPIO_18"), 128 PINCTRL_PIN(19, "GPIO_19"), 129 PINCTRL_PIN(20, "GPIO_20"), 130 PINCTRL_PIN(21, "GPIO_21"), 131 PINCTRL_PIN(22, "GPIO_22"), 132 PINCTRL_PIN(23, "GPIO_23"), 133 PINCTRL_PIN(24, "GPIO_24"), 134 PINCTRL_PIN(25, "GPIO_25"), 135 PINCTRL_PIN(26, "GPIO_26"), 136 PINCTRL_PIN(27, "GPIO_27"), 137 PINCTRL_PIN(28, "GPIO_28"), 138 PINCTRL_PIN(29, "GPIO_29"), 139 PINCTRL_PIN(30, "GPIO_30"), 140 PINCTRL_PIN(31, "GPIO_31"), 141 PINCTRL_PIN(32, "GPIO_32"), 142 PINCTRL_PIN(33, "GPIO_33"), 143 PINCTRL_PIN(34, "GPIO_34"), 144 PINCTRL_PIN(35, "GPIO_35"), 145 PINCTRL_PIN(36, "GPIO_36"), 146 PINCTRL_PIN(37, "GPIO_37"), 147 PINCTRL_PIN(38, "GPIO_38"), 148 PINCTRL_PIN(39, "GPIO_39"), 149 PINCTRL_PIN(40, "GPIO_40"), 150 PINCTRL_PIN(41, "GPIO_41"), 151 PINCTRL_PIN(42, "GPIO_42"), 152 PINCTRL_PIN(43, "GPIO_43"), 153 PINCTRL_PIN(44, "GPIO_44"), 154 PINCTRL_PIN(45, "GPIO_45"), 155 PINCTRL_PIN(46, "GPIO_46"), 156 PINCTRL_PIN(47, "GPIO_47"), 157 PINCTRL_PIN(48, "GPIO_48"), 158 PINCTRL_PIN(49, "GPIO_49"), 159 PINCTRL_PIN(50, "GPIO_50"), 160 PINCTRL_PIN(51, "GPIO_51"), 161 PINCTRL_PIN(52, "GPIO_52"), 162 PINCTRL_PIN(53, "GPIO_53"), 163 PINCTRL_PIN(54, "GPIO_54"), 164 PINCTRL_PIN(55, "GPIO_55"), 165 PINCTRL_PIN(56, "GPIO_56"), 166 PINCTRL_PIN(57, "GPIO_57"), 167 PINCTRL_PIN(58, "GPIO_58"), 168 PINCTRL_PIN(59, "GPIO_59"), 169 PINCTRL_PIN(60, "GPIO_60"), 170 PINCTRL_PIN(61, "GPIO_61"), 171 PINCTRL_PIN(62, "GPIO_62"), 172 PINCTRL_PIN(63, "GPIO_63"), 173 PINCTRL_PIN(64, "GPIO_64"), 174 PINCTRL_PIN(65, "GPIO_65"), 175 PINCTRL_PIN(66, "GPIO_66"), 176 PINCTRL_PIN(67, "GPIO_67"), 177 PINCTRL_PIN(68, "GPIO_68"), 178 PINCTRL_PIN(69, "GPIO_69"), 179 PINCTRL_PIN(70, "GPIO_70"), 180 PINCTRL_PIN(71, "GPIO_71"), 181 PINCTRL_PIN(72, "GPIO_72"), 182 PINCTRL_PIN(73, "GPIO_73"), 183 PINCTRL_PIN(74, "GPIO_74"), 184 PINCTRL_PIN(75, "GPIO_75"), 185 PINCTRL_PIN(76, "GPIO_76"), 186 PINCTRL_PIN(77, "GPIO_77"), 187 PINCTRL_PIN(78, "GPIO_78"), 188 PINCTRL_PIN(79, "GPIO_79"), 189 PINCTRL_PIN(80, "GPIO_80"), 190 PINCTRL_PIN(81, "GPIO_81"), 191 PINCTRL_PIN(82, "GPIO_82"), 192 PINCTRL_PIN(83, "GPIO_83"), 193 PINCTRL_PIN(84, "GPIO_84"), 194 PINCTRL_PIN(85, "GPIO_85"), 195 PINCTRL_PIN(86, "GPIO_86"), 196 PINCTRL_PIN(87, "GPIO_87"), 197 PINCTRL_PIN(88, "GPIO_88"), 198 PINCTRL_PIN(89, "GPIO_89"), 199 PINCTRL_PIN(90, "GPIO_90"), 200 PINCTRL_PIN(91, "GPIO_91"), 201 PINCTRL_PIN(92, "GPIO_92"), 202 PINCTRL_PIN(93, "GPIO_93"), 203 PINCTRL_PIN(94, "GPIO_94"), 204 PINCTRL_PIN(95, "GPIO_95"), 205 PINCTRL_PIN(96, "GPIO_96"), 206 PINCTRL_PIN(97, "GPIO_97"), 207 PINCTRL_PIN(98, "GPIO_98"), 208 PINCTRL_PIN(99, "GPIO_99"), 209 PINCTRL_PIN(100, "GPIO_100"), 210 PINCTRL_PIN(101, "GPIO_101"), 211 PINCTRL_PIN(102, "GPIO_102"), 212 PINCTRL_PIN(103, "GPIO_103"), 213 PINCTRL_PIN(104, "GPIO_104"), 214 PINCTRL_PIN(105, "GPIO_105"), 215 PINCTRL_PIN(106, "GPIO_106"), 216 PINCTRL_PIN(107, "GPIO_107"), 217 PINCTRL_PIN(108, "GPIO_108"), 218 PINCTRL_PIN(109, "GPIO_109"), 219 PINCTRL_PIN(110, "GPIO_110"), 220 PINCTRL_PIN(111, "GPIO_111"), 221 PINCTRL_PIN(112, "GPIO_112"), 222 PINCTRL_PIN(113, "GPIO_113"), 223 PINCTRL_PIN(114, "GPIO_114"), 224 PINCTRL_PIN(115, "GPIO_115"), 225 PINCTRL_PIN(116, "GPIO_116"), 226 PINCTRL_PIN(117, "GPIO_117"), 227 PINCTRL_PIN(118, "GPIO_118"), 228 PINCTRL_PIN(119, "GPIO_119"), 229 PINCTRL_PIN(120, "GPIO_120"), 230 PINCTRL_PIN(121, "GPIO_121"), 231 PINCTRL_PIN(122, "GPIO_122"), 232 PINCTRL_PIN(123, "GPIO_123"), 233 PINCTRL_PIN(124, "GPIO_124"), 234 PINCTRL_PIN(125, "GPIO_125"), 235 PINCTRL_PIN(126, "GPIO_126"), 236 PINCTRL_PIN(127, "GPIO_127"), 237 PINCTRL_PIN(128, "GPIO_128"), 238 PINCTRL_PIN(129, "GPIO_129"), 239 PINCTRL_PIN(130, "GPIO_130"), 240 PINCTRL_PIN(131, "GPIO_131"), 241 PINCTRL_PIN(132, "GPIO_132"), 242 PINCTRL_PIN(133, "GPIO_133"), 243 PINCTRL_PIN(134, "GPIO_134"), 244 PINCTRL_PIN(135, "GPIO_135"), 245 PINCTRL_PIN(136, "GPIO_136"), 246 PINCTRL_PIN(137, "GPIO_137"), 247 PINCTRL_PIN(138, "GPIO_138"), 248 PINCTRL_PIN(139, "GPIO_139"), 249 PINCTRL_PIN(140, "GPIO_140"), 250 PINCTRL_PIN(141, "GPIO_141"), 251 PINCTRL_PIN(142, "GPIO_142"), 252 PINCTRL_PIN(143, "GPIO_143"), 253 PINCTRL_PIN(144, "GPIO_144"), 254 PINCTRL_PIN(145, "GPIO_145"), 255 PINCTRL_PIN(146, "GPIO_146"), 256 PINCTRL_PIN(147, "GPIO_147"), 257 PINCTRL_PIN(148, "GPIO_148"), 258 PINCTRL_PIN(149, "GPIO_149"), 259 PINCTRL_PIN(150, "GPIO_150"), 260 PINCTRL_PIN(151, "GPIO_151"), 261 PINCTRL_PIN(152, "GPIO_152"), 262 PINCTRL_PIN(153, "GPIO_153"), 263 PINCTRL_PIN(154, "GPIO_154"), 264 PINCTRL_PIN(155, "GPIO_155"), 265 PINCTRL_PIN(156, "GPIO_156"), 266 PINCTRL_PIN(157, "GPIO_157"), 267 PINCTRL_PIN(158, "GPIO_158"), 268 PINCTRL_PIN(159, "GPIO_159"), 269 PINCTRL_PIN(160, "GPIO_160"), 270 PINCTRL_PIN(161, "GPIO_161"), 271 PINCTRL_PIN(162, "GPIO_162"), 272 PINCTRL_PIN(163, "GPIO_163"), 273 PINCTRL_PIN(164, "GPIO_164"), 274 PINCTRL_PIN(165, "GPIO_165"), 275 PINCTRL_PIN(166, "GPIO_166"), 276 PINCTRL_PIN(167, "GPIO_167"), 277 PINCTRL_PIN(168, "GPIO_168"), 278 PINCTRL_PIN(169, "GPIO_169"), 279 PINCTRL_PIN(170, "GPIO_170"), 280 PINCTRL_PIN(171, "GPIO_171"), 281 PINCTRL_PIN(172, "GPIO_172"), 282 PINCTRL_PIN(173, "GPIO_173"), 283 PINCTRL_PIN(174, "GPIO_174"), 284 PINCTRL_PIN(175, "GPIO_175"), 285 PINCTRL_PIN(176, "GPIO_176"), 286 PINCTRL_PIN(177, "GPIO_177"), 287 PINCTRL_PIN(178, "GPIO_178"), 288 PINCTRL_PIN(179, "GPIO_179"), 289 PINCTRL_PIN(180, "GPIO_180"), 290 PINCTRL_PIN(181, "GPIO_181"), 291 PINCTRL_PIN(182, "GPIO_182"), 292 PINCTRL_PIN(183, "GPIO_183"), 293 PINCTRL_PIN(184, "GPIO_184"), 294 PINCTRL_PIN(185, "GPIO_185"), 295 PINCTRL_PIN(186, "GPIO_186"), 296 PINCTRL_PIN(187, "GPIO_187"), 297 PINCTRL_PIN(188, "GPIO_188"), 298 PINCTRL_PIN(189, "GPIO_189"), 299 PINCTRL_PIN(190, "GPIO_190"), 300 PINCTRL_PIN(191, "GPIO_191"), 301 PINCTRL_PIN(192, "GPIO_192"), 302 PINCTRL_PIN(193, "GPIO_193"), 303 PINCTRL_PIN(194, "GPIO_194"), 304 PINCTRL_PIN(195, "GPIO_195"), 305 PINCTRL_PIN(196, "GPIO_196"), 306 PINCTRL_PIN(197, "GPIO_197"), 307 PINCTRL_PIN(198, "GPIO_198"), 308 PINCTRL_PIN(199, "GPIO_199"), 309 PINCTRL_PIN(200, "GPIO_200"), 310 PINCTRL_PIN(201, "GPIO_201"), 311 PINCTRL_PIN(202, "GPIO_202"), 312 PINCTRL_PIN(203, "GPIO_203"), 313 PINCTRL_PIN(204, "GPIO_204"), 314 PINCTRL_PIN(205, "GPIO_205"), 315 PINCTRL_PIN(206, "GPIO_206"), 316 PINCTRL_PIN(207, "GPIO_207"), 317 PINCTRL_PIN(208, "GPIO_208"), 318 PINCTRL_PIN(209, "GPIO_209"), 319 PINCTRL_PIN(210, "UFS_RESET"), 320 PINCTRL_PIN(211, "SDC2_CLK"), 321 PINCTRL_PIN(212, "SDC2_CMD"), 322 PINCTRL_PIN(213, "SDC2_DATA"), 323 }; 324 325 #define DECLARE_MSM_GPIO_PINS(pin) \ 326 static const unsigned int gpio##pin##_pins[] = { pin } 327 DECLARE_MSM_GPIO_PINS(0); 328 DECLARE_MSM_GPIO_PINS(1); 329 DECLARE_MSM_GPIO_PINS(2); 330 DECLARE_MSM_GPIO_PINS(3); 331 DECLARE_MSM_GPIO_PINS(4); 332 DECLARE_MSM_GPIO_PINS(5); 333 DECLARE_MSM_GPIO_PINS(6); 334 DECLARE_MSM_GPIO_PINS(7); 335 DECLARE_MSM_GPIO_PINS(8); 336 DECLARE_MSM_GPIO_PINS(9); 337 DECLARE_MSM_GPIO_PINS(10); 338 DECLARE_MSM_GPIO_PINS(11); 339 DECLARE_MSM_GPIO_PINS(12); 340 DECLARE_MSM_GPIO_PINS(13); 341 DECLARE_MSM_GPIO_PINS(14); 342 DECLARE_MSM_GPIO_PINS(15); 343 DECLARE_MSM_GPIO_PINS(16); 344 DECLARE_MSM_GPIO_PINS(17); 345 DECLARE_MSM_GPIO_PINS(18); 346 DECLARE_MSM_GPIO_PINS(19); 347 DECLARE_MSM_GPIO_PINS(20); 348 DECLARE_MSM_GPIO_PINS(21); 349 DECLARE_MSM_GPIO_PINS(22); 350 DECLARE_MSM_GPIO_PINS(23); 351 DECLARE_MSM_GPIO_PINS(24); 352 DECLARE_MSM_GPIO_PINS(25); 353 DECLARE_MSM_GPIO_PINS(26); 354 DECLARE_MSM_GPIO_PINS(27); 355 DECLARE_MSM_GPIO_PINS(28); 356 DECLARE_MSM_GPIO_PINS(29); 357 DECLARE_MSM_GPIO_PINS(30); 358 DECLARE_MSM_GPIO_PINS(31); 359 DECLARE_MSM_GPIO_PINS(32); 360 DECLARE_MSM_GPIO_PINS(33); 361 DECLARE_MSM_GPIO_PINS(34); 362 DECLARE_MSM_GPIO_PINS(35); 363 DECLARE_MSM_GPIO_PINS(36); 364 DECLARE_MSM_GPIO_PINS(37); 365 DECLARE_MSM_GPIO_PINS(38); 366 DECLARE_MSM_GPIO_PINS(39); 367 DECLARE_MSM_GPIO_PINS(40); 368 DECLARE_MSM_GPIO_PINS(41); 369 DECLARE_MSM_GPIO_PINS(42); 370 DECLARE_MSM_GPIO_PINS(43); 371 DECLARE_MSM_GPIO_PINS(44); 372 DECLARE_MSM_GPIO_PINS(45); 373 DECLARE_MSM_GPIO_PINS(46); 374 DECLARE_MSM_GPIO_PINS(47); 375 DECLARE_MSM_GPIO_PINS(48); 376 DECLARE_MSM_GPIO_PINS(49); 377 DECLARE_MSM_GPIO_PINS(50); 378 DECLARE_MSM_GPIO_PINS(51); 379 DECLARE_MSM_GPIO_PINS(52); 380 DECLARE_MSM_GPIO_PINS(53); 381 DECLARE_MSM_GPIO_PINS(54); 382 DECLARE_MSM_GPIO_PINS(55); 383 DECLARE_MSM_GPIO_PINS(56); 384 DECLARE_MSM_GPIO_PINS(57); 385 DECLARE_MSM_GPIO_PINS(58); 386 DECLARE_MSM_GPIO_PINS(59); 387 DECLARE_MSM_GPIO_PINS(60); 388 DECLARE_MSM_GPIO_PINS(61); 389 DECLARE_MSM_GPIO_PINS(62); 390 DECLARE_MSM_GPIO_PINS(63); 391 DECLARE_MSM_GPIO_PINS(64); 392 DECLARE_MSM_GPIO_PINS(65); 393 DECLARE_MSM_GPIO_PINS(66); 394 DECLARE_MSM_GPIO_PINS(67); 395 DECLARE_MSM_GPIO_PINS(68); 396 DECLARE_MSM_GPIO_PINS(69); 397 DECLARE_MSM_GPIO_PINS(70); 398 DECLARE_MSM_GPIO_PINS(71); 399 DECLARE_MSM_GPIO_PINS(72); 400 DECLARE_MSM_GPIO_PINS(73); 401 DECLARE_MSM_GPIO_PINS(74); 402 DECLARE_MSM_GPIO_PINS(75); 403 DECLARE_MSM_GPIO_PINS(76); 404 DECLARE_MSM_GPIO_PINS(77); 405 DECLARE_MSM_GPIO_PINS(78); 406 DECLARE_MSM_GPIO_PINS(79); 407 DECLARE_MSM_GPIO_PINS(80); 408 DECLARE_MSM_GPIO_PINS(81); 409 DECLARE_MSM_GPIO_PINS(82); 410 DECLARE_MSM_GPIO_PINS(83); 411 DECLARE_MSM_GPIO_PINS(84); 412 DECLARE_MSM_GPIO_PINS(85); 413 DECLARE_MSM_GPIO_PINS(86); 414 DECLARE_MSM_GPIO_PINS(87); 415 DECLARE_MSM_GPIO_PINS(88); 416 DECLARE_MSM_GPIO_PINS(89); 417 DECLARE_MSM_GPIO_PINS(90); 418 DECLARE_MSM_GPIO_PINS(91); 419 DECLARE_MSM_GPIO_PINS(92); 420 DECLARE_MSM_GPIO_PINS(93); 421 DECLARE_MSM_GPIO_PINS(94); 422 DECLARE_MSM_GPIO_PINS(95); 423 DECLARE_MSM_GPIO_PINS(96); 424 DECLARE_MSM_GPIO_PINS(97); 425 DECLARE_MSM_GPIO_PINS(98); 426 DECLARE_MSM_GPIO_PINS(99); 427 DECLARE_MSM_GPIO_PINS(100); 428 DECLARE_MSM_GPIO_PINS(101); 429 DECLARE_MSM_GPIO_PINS(102); 430 DECLARE_MSM_GPIO_PINS(103); 431 DECLARE_MSM_GPIO_PINS(104); 432 DECLARE_MSM_GPIO_PINS(105); 433 DECLARE_MSM_GPIO_PINS(106); 434 DECLARE_MSM_GPIO_PINS(107); 435 DECLARE_MSM_GPIO_PINS(108); 436 DECLARE_MSM_GPIO_PINS(109); 437 DECLARE_MSM_GPIO_PINS(110); 438 DECLARE_MSM_GPIO_PINS(111); 439 DECLARE_MSM_GPIO_PINS(112); 440 DECLARE_MSM_GPIO_PINS(113); 441 DECLARE_MSM_GPIO_PINS(114); 442 DECLARE_MSM_GPIO_PINS(115); 443 DECLARE_MSM_GPIO_PINS(116); 444 DECLARE_MSM_GPIO_PINS(117); 445 DECLARE_MSM_GPIO_PINS(118); 446 DECLARE_MSM_GPIO_PINS(119); 447 DECLARE_MSM_GPIO_PINS(120); 448 DECLARE_MSM_GPIO_PINS(121); 449 DECLARE_MSM_GPIO_PINS(122); 450 DECLARE_MSM_GPIO_PINS(123); 451 DECLARE_MSM_GPIO_PINS(124); 452 DECLARE_MSM_GPIO_PINS(125); 453 DECLARE_MSM_GPIO_PINS(126); 454 DECLARE_MSM_GPIO_PINS(127); 455 DECLARE_MSM_GPIO_PINS(128); 456 DECLARE_MSM_GPIO_PINS(129); 457 DECLARE_MSM_GPIO_PINS(130); 458 DECLARE_MSM_GPIO_PINS(131); 459 DECLARE_MSM_GPIO_PINS(132); 460 DECLARE_MSM_GPIO_PINS(133); 461 DECLARE_MSM_GPIO_PINS(134); 462 DECLARE_MSM_GPIO_PINS(135); 463 DECLARE_MSM_GPIO_PINS(136); 464 DECLARE_MSM_GPIO_PINS(137); 465 DECLARE_MSM_GPIO_PINS(138); 466 DECLARE_MSM_GPIO_PINS(139); 467 DECLARE_MSM_GPIO_PINS(140); 468 DECLARE_MSM_GPIO_PINS(141); 469 DECLARE_MSM_GPIO_PINS(142); 470 DECLARE_MSM_GPIO_PINS(143); 471 DECLARE_MSM_GPIO_PINS(144); 472 DECLARE_MSM_GPIO_PINS(145); 473 DECLARE_MSM_GPIO_PINS(146); 474 DECLARE_MSM_GPIO_PINS(147); 475 DECLARE_MSM_GPIO_PINS(148); 476 DECLARE_MSM_GPIO_PINS(149); 477 DECLARE_MSM_GPIO_PINS(150); 478 DECLARE_MSM_GPIO_PINS(151); 479 DECLARE_MSM_GPIO_PINS(152); 480 DECLARE_MSM_GPIO_PINS(153); 481 DECLARE_MSM_GPIO_PINS(154); 482 DECLARE_MSM_GPIO_PINS(155); 483 DECLARE_MSM_GPIO_PINS(156); 484 DECLARE_MSM_GPIO_PINS(157); 485 DECLARE_MSM_GPIO_PINS(158); 486 DECLARE_MSM_GPIO_PINS(159); 487 DECLARE_MSM_GPIO_PINS(160); 488 DECLARE_MSM_GPIO_PINS(161); 489 DECLARE_MSM_GPIO_PINS(162); 490 DECLARE_MSM_GPIO_PINS(163); 491 DECLARE_MSM_GPIO_PINS(164); 492 DECLARE_MSM_GPIO_PINS(165); 493 DECLARE_MSM_GPIO_PINS(166); 494 DECLARE_MSM_GPIO_PINS(167); 495 DECLARE_MSM_GPIO_PINS(168); 496 DECLARE_MSM_GPIO_PINS(169); 497 DECLARE_MSM_GPIO_PINS(170); 498 DECLARE_MSM_GPIO_PINS(171); 499 DECLARE_MSM_GPIO_PINS(172); 500 DECLARE_MSM_GPIO_PINS(173); 501 DECLARE_MSM_GPIO_PINS(174); 502 DECLARE_MSM_GPIO_PINS(175); 503 DECLARE_MSM_GPIO_PINS(176); 504 DECLARE_MSM_GPIO_PINS(177); 505 DECLARE_MSM_GPIO_PINS(178); 506 DECLARE_MSM_GPIO_PINS(179); 507 DECLARE_MSM_GPIO_PINS(180); 508 DECLARE_MSM_GPIO_PINS(181); 509 DECLARE_MSM_GPIO_PINS(182); 510 DECLARE_MSM_GPIO_PINS(183); 511 DECLARE_MSM_GPIO_PINS(184); 512 DECLARE_MSM_GPIO_PINS(185); 513 DECLARE_MSM_GPIO_PINS(186); 514 DECLARE_MSM_GPIO_PINS(187); 515 DECLARE_MSM_GPIO_PINS(188); 516 DECLARE_MSM_GPIO_PINS(189); 517 DECLARE_MSM_GPIO_PINS(190); 518 DECLARE_MSM_GPIO_PINS(191); 519 DECLARE_MSM_GPIO_PINS(192); 520 DECLARE_MSM_GPIO_PINS(193); 521 DECLARE_MSM_GPIO_PINS(194); 522 DECLARE_MSM_GPIO_PINS(195); 523 DECLARE_MSM_GPIO_PINS(196); 524 DECLARE_MSM_GPIO_PINS(197); 525 DECLARE_MSM_GPIO_PINS(198); 526 DECLARE_MSM_GPIO_PINS(199); 527 DECLARE_MSM_GPIO_PINS(200); 528 DECLARE_MSM_GPIO_PINS(201); 529 DECLARE_MSM_GPIO_PINS(202); 530 DECLARE_MSM_GPIO_PINS(203); 531 DECLARE_MSM_GPIO_PINS(204); 532 DECLARE_MSM_GPIO_PINS(205); 533 DECLARE_MSM_GPIO_PINS(206); 534 DECLARE_MSM_GPIO_PINS(207); 535 DECLARE_MSM_GPIO_PINS(208); 536 DECLARE_MSM_GPIO_PINS(209); 537 538 static const unsigned int ufs_reset_pins[] = { 210 }; 539 static const unsigned int sdc2_clk_pins[] = { 211 }; 540 static const unsigned int sdc2_cmd_pins[] = { 212 }; 541 static const unsigned int sdc2_data_pins[] = { 213 }; 542 543 enum sm8550_functions { 544 msm_mux_gpio, 545 msm_mux_aon_cci, 546 msm_mux_aoss_cti, 547 msm_mux_atest_char, 548 msm_mux_atest_usb, 549 msm_mux_audio_ext_mclk0, 550 msm_mux_audio_ext_mclk1, 551 msm_mux_audio_ref_clk, 552 msm_mux_cam_aon_mclk4, 553 msm_mux_cam_mclk, 554 msm_mux_cci_async_in, 555 msm_mux_cci_i2c_scl, 556 msm_mux_cci_i2c_sda, 557 msm_mux_cci_timer, 558 msm_mux_cmu_rng, 559 msm_mux_coex_uart1_rx, 560 msm_mux_coex_uart1_tx, 561 msm_mux_coex_uart2_rx, 562 msm_mux_coex_uart2_tx, 563 msm_mux_cri_trng, 564 msm_mux_dbg_out_clk, 565 msm_mux_ddr_bist_complete, 566 msm_mux_ddr_bist_fail, 567 msm_mux_ddr_bist_start, 568 msm_mux_ddr_bist_stop, 569 msm_mux_ddr_pxi0, 570 msm_mux_ddr_pxi1, 571 msm_mux_ddr_pxi2, 572 msm_mux_ddr_pxi3, 573 msm_mux_dp_hot, 574 msm_mux_gcc_gp1, 575 msm_mux_gcc_gp2, 576 msm_mux_gcc_gp3, 577 msm_mux_i2chub0_se0, 578 msm_mux_i2chub0_se1, 579 msm_mux_i2chub0_se2, 580 msm_mux_i2chub0_se3, 581 msm_mux_i2chub0_se4, 582 msm_mux_i2chub0_se5, 583 msm_mux_i2chub0_se6, 584 msm_mux_i2chub0_se7, 585 msm_mux_i2chub0_se8, 586 msm_mux_i2chub0_se9, 587 msm_mux_i2s0_data0, 588 msm_mux_i2s0_data1, 589 msm_mux_i2s0_sck, 590 msm_mux_i2s0_ws, 591 msm_mux_i2s1_data0, 592 msm_mux_i2s1_data1, 593 msm_mux_i2s1_sck, 594 msm_mux_i2s1_ws, 595 msm_mux_ibi_i3c, 596 msm_mux_jitter_bist, 597 msm_mux_mdp_vsync, 598 msm_mux_mdp_vsync0_out, 599 msm_mux_mdp_vsync1_out, 600 msm_mux_mdp_vsync2_out, 601 msm_mux_mdp_vsync3_out, 602 msm_mux_mdp_vsync_e, 603 msm_mux_nav_gpio0, 604 msm_mux_nav_gpio1, 605 msm_mux_nav_gpio2, 606 msm_mux_pcie0_clk_req_n, 607 msm_mux_pcie1_clk_req_n, 608 msm_mux_phase_flag, 609 msm_mux_pll_bist_sync, 610 msm_mux_pll_clk_aux, 611 msm_mux_prng_rosc0, 612 msm_mux_prng_rosc1, 613 msm_mux_prng_rosc2, 614 msm_mux_prng_rosc3, 615 msm_mux_qdss_cti, 616 msm_mux_qdss_gpio, 617 msm_mux_qlink0_enable, 618 msm_mux_qlink0_request, 619 msm_mux_qlink0_wmss, 620 msm_mux_qlink1_enable, 621 msm_mux_qlink1_request, 622 msm_mux_qlink1_wmss, 623 msm_mux_qlink2_enable, 624 msm_mux_qlink2_request, 625 msm_mux_qlink2_wmss, 626 msm_mux_qspi0, 627 msm_mux_qspi1, 628 msm_mux_qspi2, 629 msm_mux_qspi3, 630 msm_mux_qspi_clk, 631 msm_mux_qspi_cs, 632 msm_mux_qup1_se0, 633 msm_mux_qup1_se1, 634 msm_mux_qup1_se2, 635 msm_mux_qup1_se3, 636 msm_mux_qup1_se4, 637 msm_mux_qup1_se5, 638 msm_mux_qup1_se6, 639 msm_mux_qup1_se7, 640 msm_mux_qup2_se0, 641 msm_mux_qup2_se0_l0_mira, 642 msm_mux_qup2_se0_l0_mirb, 643 msm_mux_qup2_se0_l1_mira, 644 msm_mux_qup2_se0_l1_mirb, 645 msm_mux_qup2_se0_l2_mira, 646 msm_mux_qup2_se0_l2_mirb, 647 msm_mux_qup2_se0_l3_mira, 648 msm_mux_qup2_se0_l3_mirb, 649 msm_mux_qup2_se1, 650 msm_mux_qup2_se2, 651 msm_mux_qup2_se3, 652 msm_mux_qup2_se4, 653 msm_mux_qup2_se5, 654 msm_mux_qup2_se6, 655 msm_mux_qup2_se7, 656 msm_mux_resout_n, 657 msm_mux_sd_write_protect, 658 msm_mux_sdc40, 659 msm_mux_sdc41, 660 msm_mux_sdc42, 661 msm_mux_sdc43, 662 msm_mux_sdc4_clk, 663 msm_mux_sdc4_cmd, 664 msm_mux_tb_trig_sdc2, 665 msm_mux_tb_trig_sdc4, 666 msm_mux_tgu_ch0_trigout, 667 msm_mux_tgu_ch1_trigout, 668 msm_mux_tgu_ch2_trigout, 669 msm_mux_tgu_ch3_trigout, 670 msm_mux_tmess_prng0, 671 msm_mux_tmess_prng1, 672 msm_mux_tmess_prng2, 673 msm_mux_tmess_prng3, 674 msm_mux_tsense_pwm1, 675 msm_mux_tsense_pwm2, 676 msm_mux_tsense_pwm3, 677 msm_mux_uim0_clk, 678 msm_mux_uim0_data, 679 msm_mux_uim0_present, 680 msm_mux_uim0_reset, 681 msm_mux_uim1_clk, 682 msm_mux_uim1_data, 683 msm_mux_uim1_present, 684 msm_mux_uim1_reset, 685 msm_mux_usb1_hs, 686 msm_mux_usb_phy, 687 msm_mux_vfr_0, 688 msm_mux_vfr_1, 689 msm_mux_vsense_trigger_mirnat, 690 msm_mux__, 691 }; 692 693 static const char * const gpio_groups[] = { 694 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 695 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 696 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 697 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 698 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 699 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 700 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 701 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 702 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 703 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 704 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 705 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 706 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 707 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 708 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 709 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 710 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 711 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", 712 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", 713 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", 714 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", 715 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", 716 "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", 717 "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", 718 "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", 719 "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", 720 "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", 721 "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", 722 "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", 723 "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", 724 "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", 725 "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", 726 "gpio207", "gpio208", "gpio209", 727 }; 728 729 static const char * const aon_cci_groups[] = { 730 "gpio208", "gpio209", 731 }; 732 733 static const char * const aoss_cti_groups[] = { 734 "gpio44", "gpio45", "gpio46", "gpio47", 735 }; 736 737 static const char *const atest_char_groups[] = { 738 "gpio130", "gpio132", "gpio133", "gpio134", "gpio135", 739 }; 740 741 static const char *const atest_usb_groups[] = { 742 "gpio37", "gpio39", "gpio55", "gpio149", "gpio148", 743 }; 744 745 static const char *const audio_ext_mclk0_groups[] = { 746 "gpio125", 747 }; 748 749 static const char *const audio_ext_mclk1_groups[] = { 750 "gpio124", 751 }; 752 753 static const char *const audio_ref_clk_groups[] = { 754 "gpio124", 755 }; 756 757 static const char *const cam_aon_mclk4_groups[] = { 758 "gpio104", 759 }; 760 761 static const char *const cam_mclk_groups[] = { 762 "gpio100", "gpio101", "gpio102", "gpio103", 763 "gpio105", "gpio106", "gpio107", 764 }; 765 766 static const char *const cci_async_in_groups[] = { 767 "gpio71", "gpio72", "gpio109", 768 }; 769 770 static const char *const cci_i2c_scl_groups[] = { 771 "gpio111", "gpio113", "gpio115", "gpio75", "gpio1", 772 }; 773 774 static const char *const cci_i2c_sda_groups[] = { 775 "gpio110", "gpio112", "gpio114", "gpio74", "gpio0", 776 }; 777 778 static const char *const cci_timer_groups[] = { 779 "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", 780 }; 781 782 static const char *const cmu_rng_groups[] = { 783 "gpio129", "gpio128", "gpio127", "gpio122", 784 }; 785 786 static const char *const coex_uart1_rx_groups[] = { 787 "gpio148", 788 }; 789 790 static const char *const coex_uart1_tx_groups[] = { 791 "gpio149", 792 }; 793 794 static const char *const coex_uart2_rx_groups[] = { 795 "gpio150", 796 }; 797 798 static const char *const coex_uart2_tx_groups[] = { 799 "gpio151", 800 }; 801 802 static const char *const cri_trng_groups[] = { 803 "gpio187", 804 }; 805 806 static const char *const dbg_out_clk_groups[] = { 807 "gpio89", 808 }; 809 810 static const char *const ddr_bist_complete_groups[] = { 811 "gpio40", 812 }; 813 814 static const char *const ddr_bist_fail_groups[] = { 815 "gpio36", 816 }; 817 818 static const char *const ddr_bist_start_groups[] = { 819 "gpio37", 820 }; 821 822 static const char *const ddr_bist_stop_groups[] = { 823 "gpio41", 824 }; 825 826 static const char *const ddr_pxi0_groups[] = { 827 "gpio51", 828 "gpio52", 829 }; 830 831 static const char *const ddr_pxi1_groups[] = { 832 "gpio40", 833 "gpio41", 834 }; 835 836 static const char *const ddr_pxi2_groups[] = { 837 "gpio45", 838 "gpio47", 839 }; 840 841 static const char *const ddr_pxi3_groups[] = { 842 "gpio43", 843 "gpio44", 844 }; 845 846 static const char *const dp_hot_groups[] = { 847 "gpio47", 848 }; 849 850 static const char *const gcc_gp1_groups[] = { 851 "gpio86", 852 "gpio134", 853 }; 854 855 static const char *const gcc_gp2_groups[] = { 856 "gpio87", 857 "gpio135", 858 }; 859 860 static const char *const gcc_gp3_groups[] = { 861 "gpio88", 862 "gpio136", 863 }; 864 865 static const char *const i2chub0_se0_groups[] = { 866 "gpio16", 867 "gpio17", 868 }; 869 870 static const char *const i2chub0_se1_groups[] = { 871 "gpio18", 872 "gpio19", 873 }; 874 875 static const char *const i2chub0_se2_groups[] = { 876 "gpio20", 877 "gpio21", 878 }; 879 880 static const char *const i2chub0_se3_groups[] = { 881 "gpio22", 882 "gpio23", 883 }; 884 885 static const char *const i2chub0_se4_groups[] = { 886 "gpio4", 887 "gpio5", 888 }; 889 890 static const char *const i2chub0_se5_groups[] = { 891 "gpio6", 892 "gpio7", 893 }; 894 895 static const char *const i2chub0_se6_groups[] = { 896 "gpio8", 897 "gpio9", 898 }; 899 900 static const char *const i2chub0_se7_groups[] = { 901 "gpio10", 902 "gpio11", 903 }; 904 905 static const char *const i2chub0_se8_groups[] = { 906 "gpio206", 907 "gpio207", 908 }; 909 910 static const char *const i2chub0_se9_groups[] = { 911 "gpio84", 912 "gpio85", 913 }; 914 915 static const char *const i2s0_data0_groups[] = { 916 "gpio127", 917 }; 918 919 static const char *const i2s0_data1_groups[] = { 920 "gpio128", 921 }; 922 923 static const char *const i2s0_sck_groups[] = { 924 "gpio126", 925 }; 926 927 static const char *const i2s0_ws_groups[] = { 928 "gpio129", 929 }; 930 931 static const char *const i2s1_data0_groups[] = { 932 "gpio122", 933 }; 934 935 static const char *const i2s1_data1_groups[] = { 936 "gpio124", 937 }; 938 939 static const char *const i2s1_sck_groups[] = { 940 "gpio121", 941 }; 942 943 static const char *const i2s1_ws_groups[] = { 944 "gpio123", 945 }; 946 947 static const char *const ibi_i3c_groups[] = { 948 "gpio0", "gpio1", "gpio28", "gpio29", "gpio32", 949 "gpio33", "gpio56", "gpio57", "gpio60", "gpio61", 950 }; 951 952 static const char *const jitter_bist_groups[] = { 953 "gpio43", 954 }; 955 956 static const char *const mdp_vsync_groups[] = { 957 "gpio86", 958 "gpio87", 959 "gpio133", 960 "gpio137", 961 }; 962 963 static const char *const mdp_vsync0_out_groups[] = { 964 "gpio86", 965 }; 966 967 static const char *const mdp_vsync1_out_groups[] = { 968 "gpio86", 969 }; 970 971 static const char *const mdp_vsync2_out_groups[] = { 972 "gpio87", 973 }; 974 975 static const char *const mdp_vsync3_out_groups[] = { 976 "gpio87", 977 }; 978 979 static const char *const mdp_vsync_e_groups[] = { 980 "gpio88", 981 }; 982 983 static const char *const nav_gpio0_groups[] = { 984 "gpio154", 985 }; 986 987 static const char *const nav_gpio1_groups[] = { 988 "gpio155", 989 }; 990 991 static const char *const nav_gpio2_groups[] = { 992 "gpio153", 993 }; 994 995 static const char *const pcie0_clk_req_n_groups[] = { 996 "gpio95", 997 }; 998 999 static const char *const pcie1_clk_req_n_groups[] = { 1000 "gpio98", 1001 }; 1002 1003 static const char *const phase_flag_groups[] = { 1004 "gpio0", "gpio2", "gpio3", "gpio10", "gpio11", "gpio12", "gpio13", "gpio59", 1005 "gpio63", "gpio64", "gpio65", "gpio67", "gpio68", "gpio69", "gpio75", "gpio76", 1006 "gpio77", "gpio79", "gpio80", "gpio81", "gpio92", "gpio83", "gpio94", "gpio95", 1007 "gpio96", "gpio97", "gpio98", "gpio99", "gpio116", "gpio117", "gpio119", "gpio120", 1008 }; 1009 1010 static const char *const pll_bist_sync_groups[] = { 1011 "gpio20", 1012 }; 1013 1014 static const char *const pll_clk_aux_groups[] = { 1015 "gpio107", 1016 }; 1017 1018 static const char *const prng_rosc0_groups[] = { 1019 "gpio186", 1020 }; 1021 1022 static const char *const prng_rosc1_groups[] = { 1023 "gpio183", 1024 }; 1025 1026 static const char *const prng_rosc2_groups[] = { 1027 "gpio182", 1028 }; 1029 1030 static const char *const prng_rosc3_groups[] = { 1031 "gpio181", 1032 }; 1033 1034 static const char *const qdss_cti_groups[] = { 1035 "gpio10", "gpio11", "gpio75", "gpio79", 1036 "gpio159", "gpio160", "gpio161", "gpio162", 1037 }; 1038 1039 static const char *const qdss_gpio_groups[] = { 1040 "gpio59", "gpio64", "gpio73", "gpio100", "gpio101", "gpio102", "gpio103", 1041 "gpio104", "gpio105", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", 1042 "gpio115", "gpio116", "gpio117", "gpio120", "gpio138", "gpio139", "gpio140", 1043 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio148", "gpio149", 1044 "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", "gpio156", 1045 "gpio157", 1046 }; 1047 1048 static const char *const qlink0_enable_groups[] = { 1049 "gpio157", 1050 }; 1051 1052 static const char *const qlink0_request_groups[] = { 1053 "gpio156", 1054 }; 1055 1056 static const char *const qlink0_wmss_groups[] = { 1057 "gpio158", 1058 }; 1059 1060 static const char *const qlink1_enable_groups[] = { 1061 "gpio160", 1062 }; 1063 1064 static const char *const qlink1_request_groups[] = { 1065 "gpio159", 1066 }; 1067 1068 static const char *const qlink1_wmss_groups[] = { 1069 "gpio161", 1070 }; 1071 1072 static const char *const qlink2_enable_groups[] = { 1073 "gpio163", 1074 }; 1075 1076 static const char *const qlink2_request_groups[] = { 1077 "gpio162", 1078 }; 1079 1080 static const char *const qlink2_wmss_groups[] = { 1081 "gpio164", 1082 }; 1083 1084 static const char *const qspi0_groups[] = { 1085 "gpio89", 1086 }; 1087 1088 static const char *const qspi1_groups[] = { 1089 "gpio90", 1090 }; 1091 1092 static const char *const qspi2_groups[] = { 1093 "gpio48", 1094 }; 1095 1096 static const char *const qspi3_groups[] = { 1097 "gpio49", 1098 }; 1099 1100 static const char *const qspi_clk_groups[] = { 1101 "gpio50", 1102 }; 1103 1104 static const char *const qspi_cs_groups[] = { 1105 "gpio51", "gpio91", 1106 }; 1107 1108 static const char *const qup1_se0_groups[] = { 1109 "gpio28", "gpio29", "gpio30", "gpio31", 1110 }; 1111 1112 static const char *const qup1_se1_groups[] = { 1113 "gpio32", "gpio33", "gpio34", "gpio35", 1114 }; 1115 1116 static const char *const qup1_se2_groups[] = { 1117 "gpio40", "gpio41", "gpio42", "gpio36", 1118 "gpio37", "gpio38", "gpio39", 1119 }; 1120 1121 static const char *const qup1_se3_groups[] = { 1122 "gpio40", "gpio41", "gpio42", "gpio43", 1123 }; 1124 1125 static const char *const qup1_se4_groups[] = { 1126 "gpio44", "gpio45", "gpio46", "gpio47", 1127 }; 1128 1129 static const char *const qup1_se5_groups[] = { 1130 "gpio52", "gpio53", "gpio54", "gpio55", 1131 }; 1132 1133 static const char *const qup1_se6_groups[] = { 1134 "gpio48", "gpio49", "gpio50", "gpio51", 1135 }; 1136 1137 static const char *const qup1_se7_groups[] = { 1138 "gpio24", "gpio25", "gpio26", "gpio27", 1139 }; 1140 1141 static const char *const qup2_se0_groups[] = { 1142 "gpio63", "gpio66", "gpio67", 1143 }; 1144 1145 static const char *const qup2_se0_l0_mira_groups[] = { 1146 "gpio56", 1147 }; 1148 1149 static const char *const qup2_se0_l0_mirb_groups[] = { 1150 "gpio0", 1151 }; 1152 1153 static const char *const qup2_se0_l1_mira_groups[] = { 1154 "gpio57", 1155 }; 1156 1157 static const char *const qup2_se0_l1_mirb_groups[] = { 1158 "gpio1", 1159 }; 1160 1161 static const char *const qup2_se0_l2_mira_groups[] = { 1162 "gpio58", 1163 }; 1164 1165 static const char *const qup2_se0_l2_mirb_groups[] = { 1166 "gpio109", 1167 }; 1168 1169 static const char *const qup2_se0_l3_mira_groups[] = { 1170 "gpio59", 1171 }; 1172 1173 static const char *const qup2_se0_l3_mirb_groups[] = { 1174 "gpio107", 1175 }; 1176 1177 static const char *const qup2_se1_groups[] = { 1178 "gpio60", "gpio61", "gpio62", "gpio63", 1179 }; 1180 1181 static const char *const qup2_se2_groups[] = { 1182 "gpio64", "gpio65", "gpio66", "gpio67", 1183 }; 1184 1185 static const char *const qup2_se3_groups[] = { 1186 "gpio68", "gpio69", "gpio70", "gpio71", 1187 }; 1188 1189 static const char *const qup2_se4_groups[] = { 1190 "gpio2", "gpio3", "gpio118", "gpio119", 1191 }; 1192 1193 static const char *const qup2_se5_groups[] = { 1194 "gpio80", "gpio81", "gpio82", "gpio83", 1195 }; 1196 1197 static const char *const qup2_se6_groups[] = { 1198 "gpio76", "gpio77", "gpio78", "gpio79", 1199 }; 1200 1201 static const char *const qup2_se7_groups[] = { 1202 "gpio72", "gpio106", "gpio74", "gpio75", 1203 }; 1204 1205 static const char * const resout_n_groups[] = { 1206 "gpio92", 1207 }; 1208 1209 static const char *const sd_write_protect_groups[] = { 1210 "gpio93", 1211 }; 1212 1213 static const char *const sdc40_groups[] = { 1214 "gpio89", 1215 }; 1216 1217 static const char *const sdc41_groups[] = { 1218 "gpio90", 1219 }; 1220 1221 static const char *const sdc42_groups[] = { 1222 "gpio48", 1223 }; 1224 1225 static const char *const sdc43_groups[] = { 1226 "gpio49", 1227 }; 1228 1229 static const char *const sdc4_clk_groups[] = { 1230 "gpio50", 1231 }; 1232 1233 static const char *const sdc4_cmd_groups[] = { 1234 "gpio51", 1235 }; 1236 1237 static const char * const tb_trig_sdc2_groups[] = { 1238 "gpio64", 1239 }; 1240 1241 static const char * const tb_trig_sdc4_groups[] = { 1242 "gpio91", 1243 }; 1244 1245 static const char * const tgu_ch0_trigout_groups[] = { 1246 "gpio64", 1247 }; 1248 1249 static const char * const tgu_ch1_trigout_groups[] = { 1250 "gpio65", 1251 }; 1252 1253 static const char * const tgu_ch2_trigout_groups[] = { 1254 "gpio66", 1255 }; 1256 1257 static const char * const tgu_ch3_trigout_groups[] = { 1258 "gpio67", 1259 }; 1260 1261 static const char *const tmess_prng0_groups[] = { 1262 "gpio92", 1263 }; 1264 1265 static const char *const tmess_prng1_groups[] = { 1266 "gpio94", 1267 }; 1268 1269 static const char *const tmess_prng2_groups[] = { 1270 "gpio95", 1271 }; 1272 1273 static const char *const tmess_prng3_groups[] = { 1274 "gpio96", 1275 }; 1276 1277 static const char *const tsense_pwm1_groups[] = { 1278 "gpio50", 1279 }; 1280 1281 static const char *const tsense_pwm2_groups[] = { 1282 "gpio50", 1283 }; 1284 1285 static const char *const tsense_pwm3_groups[] = { 1286 "gpio50", 1287 }; 1288 1289 static const char *const uim0_clk_groups[] = { 1290 "gpio131", 1291 }; 1292 1293 static const char *const uim0_data_groups[] = { 1294 "gpio130", 1295 }; 1296 1297 static const char *const uim0_present_groups[] = { 1298 "gpio27", 1299 }; 1300 1301 static const char *const uim0_reset_groups[] = { 1302 "gpio132", 1303 }; 1304 1305 static const char *const uim1_clk_groups[] = { 1306 "gpio135", 1307 }; 1308 1309 static const char *const uim1_data_groups[] = { 1310 "gpio134", 1311 }; 1312 1313 static const char *const uim1_present_groups[] = { 1314 "gpio26", 1315 }; 1316 1317 static const char *const uim1_reset_groups[] = { 1318 "gpio136", 1319 }; 1320 1321 static const char *const usb1_hs_groups[] = { 1322 "gpio90", 1323 }; 1324 1325 static const char *const usb_phy_groups[] = { 1326 "gpio11", 1327 "gpio48", 1328 }; 1329 1330 static const char *const vfr_0_groups[] = { 1331 "gpio150", 1332 }; 1333 1334 static const char *const vfr_1_groups[] = { 1335 "gpio155", 1336 }; 1337 1338 static const char *const vsense_trigger_mirnat_groups[] = { 1339 "gpio24", 1340 }; 1341 1342 static const struct pinfunction sm8550_functions[] = { 1343 MSM_PIN_FUNCTION(gpio), 1344 MSM_PIN_FUNCTION(aon_cci), 1345 MSM_PIN_FUNCTION(aoss_cti), 1346 MSM_PIN_FUNCTION(atest_char), 1347 MSM_PIN_FUNCTION(atest_usb), 1348 MSM_PIN_FUNCTION(audio_ext_mclk0), 1349 MSM_PIN_FUNCTION(audio_ext_mclk1), 1350 MSM_PIN_FUNCTION(audio_ref_clk), 1351 MSM_PIN_FUNCTION(cam_aon_mclk4), 1352 MSM_PIN_FUNCTION(cam_mclk), 1353 MSM_PIN_FUNCTION(cci_async_in), 1354 MSM_PIN_FUNCTION(cci_i2c_scl), 1355 MSM_PIN_FUNCTION(cci_i2c_sda), 1356 MSM_PIN_FUNCTION(cci_timer), 1357 MSM_PIN_FUNCTION(cmu_rng), 1358 MSM_PIN_FUNCTION(coex_uart1_rx), 1359 MSM_PIN_FUNCTION(coex_uart1_tx), 1360 MSM_PIN_FUNCTION(coex_uart2_rx), 1361 MSM_PIN_FUNCTION(coex_uart2_tx), 1362 MSM_PIN_FUNCTION(cri_trng), 1363 MSM_PIN_FUNCTION(dbg_out_clk), 1364 MSM_PIN_FUNCTION(ddr_bist_complete), 1365 MSM_PIN_FUNCTION(ddr_bist_fail), 1366 MSM_PIN_FUNCTION(ddr_bist_start), 1367 MSM_PIN_FUNCTION(ddr_bist_stop), 1368 MSM_PIN_FUNCTION(ddr_pxi0), 1369 MSM_PIN_FUNCTION(ddr_pxi1), 1370 MSM_PIN_FUNCTION(ddr_pxi2), 1371 MSM_PIN_FUNCTION(ddr_pxi3), 1372 MSM_PIN_FUNCTION(dp_hot), 1373 MSM_PIN_FUNCTION(gcc_gp1), 1374 MSM_PIN_FUNCTION(gcc_gp2), 1375 MSM_PIN_FUNCTION(gcc_gp3), 1376 MSM_PIN_FUNCTION(i2chub0_se0), 1377 MSM_PIN_FUNCTION(i2chub0_se1), 1378 MSM_PIN_FUNCTION(i2chub0_se2), 1379 MSM_PIN_FUNCTION(i2chub0_se3), 1380 MSM_PIN_FUNCTION(i2chub0_se4), 1381 MSM_PIN_FUNCTION(i2chub0_se5), 1382 MSM_PIN_FUNCTION(i2chub0_se6), 1383 MSM_PIN_FUNCTION(i2chub0_se7), 1384 MSM_PIN_FUNCTION(i2chub0_se8), 1385 MSM_PIN_FUNCTION(i2chub0_se9), 1386 MSM_PIN_FUNCTION(i2s0_data0), 1387 MSM_PIN_FUNCTION(i2s0_data1), 1388 MSM_PIN_FUNCTION(i2s0_sck), 1389 MSM_PIN_FUNCTION(i2s0_ws), 1390 MSM_PIN_FUNCTION(i2s1_data0), 1391 MSM_PIN_FUNCTION(i2s1_data1), 1392 MSM_PIN_FUNCTION(i2s1_sck), 1393 MSM_PIN_FUNCTION(i2s1_ws), 1394 MSM_PIN_FUNCTION(ibi_i3c), 1395 MSM_PIN_FUNCTION(jitter_bist), 1396 MSM_PIN_FUNCTION(mdp_vsync), 1397 MSM_PIN_FUNCTION(mdp_vsync0_out), 1398 MSM_PIN_FUNCTION(mdp_vsync1_out), 1399 MSM_PIN_FUNCTION(mdp_vsync2_out), 1400 MSM_PIN_FUNCTION(mdp_vsync3_out), 1401 MSM_PIN_FUNCTION(mdp_vsync_e), 1402 MSM_PIN_FUNCTION(nav_gpio0), 1403 MSM_PIN_FUNCTION(nav_gpio1), 1404 MSM_PIN_FUNCTION(nav_gpio2), 1405 MSM_PIN_FUNCTION(pcie0_clk_req_n), 1406 MSM_PIN_FUNCTION(pcie1_clk_req_n), 1407 MSM_PIN_FUNCTION(phase_flag), 1408 MSM_PIN_FUNCTION(pll_bist_sync), 1409 MSM_PIN_FUNCTION(pll_clk_aux), 1410 MSM_PIN_FUNCTION(prng_rosc0), 1411 MSM_PIN_FUNCTION(prng_rosc1), 1412 MSM_PIN_FUNCTION(prng_rosc2), 1413 MSM_PIN_FUNCTION(prng_rosc3), 1414 MSM_PIN_FUNCTION(qdss_cti), 1415 MSM_PIN_FUNCTION(qdss_gpio), 1416 MSM_PIN_FUNCTION(qlink0_enable), 1417 MSM_PIN_FUNCTION(qlink0_request), 1418 MSM_PIN_FUNCTION(qlink0_wmss), 1419 MSM_PIN_FUNCTION(qlink1_enable), 1420 MSM_PIN_FUNCTION(qlink1_request), 1421 MSM_PIN_FUNCTION(qlink1_wmss), 1422 MSM_PIN_FUNCTION(qlink2_enable), 1423 MSM_PIN_FUNCTION(qlink2_request), 1424 MSM_PIN_FUNCTION(qlink2_wmss), 1425 MSM_PIN_FUNCTION(qspi0), 1426 MSM_PIN_FUNCTION(qspi1), 1427 MSM_PIN_FUNCTION(qspi2), 1428 MSM_PIN_FUNCTION(qspi3), 1429 MSM_PIN_FUNCTION(qspi_clk), 1430 MSM_PIN_FUNCTION(qspi_cs), 1431 MSM_PIN_FUNCTION(qup1_se0), 1432 MSM_PIN_FUNCTION(qup1_se1), 1433 MSM_PIN_FUNCTION(qup1_se2), 1434 MSM_PIN_FUNCTION(qup1_se3), 1435 MSM_PIN_FUNCTION(qup1_se4), 1436 MSM_PIN_FUNCTION(qup1_se5), 1437 MSM_PIN_FUNCTION(qup1_se6), 1438 MSM_PIN_FUNCTION(qup1_se7), 1439 MSM_PIN_FUNCTION(qup2_se0), 1440 MSM_PIN_FUNCTION(qup2_se0_l0_mira), 1441 MSM_PIN_FUNCTION(qup2_se0_l0_mirb), 1442 MSM_PIN_FUNCTION(qup2_se0_l1_mira), 1443 MSM_PIN_FUNCTION(qup2_se0_l1_mirb), 1444 MSM_PIN_FUNCTION(qup2_se0_l2_mira), 1445 MSM_PIN_FUNCTION(qup2_se0_l2_mirb), 1446 MSM_PIN_FUNCTION(qup2_se0_l3_mira), 1447 MSM_PIN_FUNCTION(qup2_se0_l3_mirb), 1448 MSM_PIN_FUNCTION(qup2_se1), 1449 MSM_PIN_FUNCTION(qup2_se2), 1450 MSM_PIN_FUNCTION(qup2_se3), 1451 MSM_PIN_FUNCTION(qup2_se4), 1452 MSM_PIN_FUNCTION(qup2_se5), 1453 MSM_PIN_FUNCTION(qup2_se6), 1454 MSM_PIN_FUNCTION(qup2_se7), 1455 MSM_PIN_FUNCTION(resout_n), 1456 MSM_PIN_FUNCTION(sd_write_protect), 1457 MSM_PIN_FUNCTION(sdc40), 1458 MSM_PIN_FUNCTION(sdc41), 1459 MSM_PIN_FUNCTION(sdc42), 1460 MSM_PIN_FUNCTION(sdc43), 1461 MSM_PIN_FUNCTION(sdc4_clk), 1462 MSM_PIN_FUNCTION(sdc4_cmd), 1463 MSM_PIN_FUNCTION(tb_trig_sdc2), 1464 MSM_PIN_FUNCTION(tb_trig_sdc4), 1465 MSM_PIN_FUNCTION(tgu_ch0_trigout), 1466 MSM_PIN_FUNCTION(tgu_ch1_trigout), 1467 MSM_PIN_FUNCTION(tgu_ch2_trigout), 1468 MSM_PIN_FUNCTION(tgu_ch3_trigout), 1469 MSM_PIN_FUNCTION(tmess_prng0), 1470 MSM_PIN_FUNCTION(tmess_prng1), 1471 MSM_PIN_FUNCTION(tmess_prng2), 1472 MSM_PIN_FUNCTION(tmess_prng3), 1473 MSM_PIN_FUNCTION(tsense_pwm1), 1474 MSM_PIN_FUNCTION(tsense_pwm2), 1475 MSM_PIN_FUNCTION(tsense_pwm3), 1476 MSM_PIN_FUNCTION(uim0_clk), 1477 MSM_PIN_FUNCTION(uim0_data), 1478 MSM_PIN_FUNCTION(uim0_present), 1479 MSM_PIN_FUNCTION(uim0_reset), 1480 MSM_PIN_FUNCTION(uim1_clk), 1481 MSM_PIN_FUNCTION(uim1_data), 1482 MSM_PIN_FUNCTION(uim1_present), 1483 MSM_PIN_FUNCTION(uim1_reset), 1484 MSM_PIN_FUNCTION(usb1_hs), 1485 MSM_PIN_FUNCTION(usb_phy), 1486 MSM_PIN_FUNCTION(vfr_0), 1487 MSM_PIN_FUNCTION(vfr_1), 1488 MSM_PIN_FUNCTION(vsense_trigger_mirnat), 1489 }; 1490 1491 /* 1492 * Every pin is maintained as a single group, and missing or non-existing pin 1493 * would be maintained as dummy group to synchronize pin group index with 1494 * pin descriptor registered with pinctrl core. 1495 * Clients would not be able to request these dummy pin groups. 1496 */ 1497 static const struct msm_pingroup sm8550_groups[] = { 1498 [0] = PINGROUP(0, cci_i2c_sda, qup2_se0_l0_mirb, ibi_i3c, phase_flag, _, _, _, _, _), 1499 [1] = PINGROUP(1, cci_i2c_scl, qup2_se0_l1_mirb, ibi_i3c, _, _, _, _, _, _), 1500 [2] = PINGROUP(2, qup2_se4, phase_flag, _, _, _, _, _, _, _), 1501 [3] = PINGROUP(3, qup2_se4, phase_flag, _, _, _, _, _, _, _), 1502 [4] = PINGROUP(4, i2chub0_se4, _, _, _, _, _, _, _, _), 1503 [5] = PINGROUP(5, i2chub0_se4, _, _, _, _, _, _, _, _), 1504 [6] = PINGROUP(6, i2chub0_se5, _, _, _, _, _, _, _, _), 1505 [7] = PINGROUP(7, i2chub0_se5, _, _, _, _, _, _, _, _), 1506 [8] = PINGROUP(8, i2chub0_se6, _, _, _, _, _, _, _, _), 1507 [9] = PINGROUP(9, i2chub0_se6, _, _, _, _, _, _, _, _), 1508 [10] = PINGROUP(10, i2chub0_se7, qdss_cti, phase_flag, _, _, _, _, _, _), 1509 [11] = PINGROUP(11, i2chub0_se7, usb_phy, qdss_cti, phase_flag, _, _, _, _, _), 1510 [12] = PINGROUP(12, phase_flag, _, _, _, _, _, _, _, _), 1511 [13] = PINGROUP(13, phase_flag, _, _, _, _, _, _, _, _), 1512 [14] = PINGROUP(14, _, _, _, _, _, _, _, _, _), 1513 [15] = PINGROUP(15, _, _, _, _, _, _, _, _, _), 1514 [16] = PINGROUP(16, i2chub0_se0, _, _, _, _, _, _, _, _), 1515 [17] = PINGROUP(17, i2chub0_se0, _, _, _, _, _, _, _, _), 1516 [18] = PINGROUP(18, i2chub0_se1, _, _, _, _, _, _, _, _), 1517 [19] = PINGROUP(19, i2chub0_se1, _, _, _, _, _, _, _, _), 1518 [20] = PINGROUP(20, i2chub0_se2, pll_bist_sync, _, _, _, _, _, _, _), 1519 [21] = PINGROUP(21, i2chub0_se2, _, _, _, _, _, _, _, _), 1520 [22] = PINGROUP(22, i2chub0_se3, _, _, _, _, _, _, _, _), 1521 [23] = PINGROUP(23, i2chub0_se3, _, _, _, _, _, _, _, _), 1522 [24] = PINGROUP(24, qup1_se7, vsense_trigger_mirnat, _, _, _, _, _, _, _), 1523 [25] = PINGROUP(25, qup1_se7, _, _, _, _, _, _, _, _), 1524 [26] = PINGROUP(26, qup1_se7, uim1_present, _, _, _, _, _, _, _), 1525 [27] = PINGROUP(27, qup1_se7, uim0_present, _, _, _, _, _, _, _), 1526 [28] = PINGROUP(28, qup1_se0, ibi_i3c, _, _, _, _, _, _, _), 1527 [29] = PINGROUP(29, qup1_se0, ibi_i3c, _, _, _, _, _, _, _), 1528 [30] = PINGROUP(30, qup1_se0, _, _, _, _, _, _, _, _), 1529 [31] = PINGROUP(31, qup1_se0, _, _, _, _, _, _, _, _), 1530 [32] = PINGROUP(32, qup1_se1, ibi_i3c, _, _, _, _, _, _, _), 1531 [33] = PINGROUP(33, qup1_se1, ibi_i3c, _, _, _, _, _, _, _), 1532 [34] = PINGROUP(34, qup1_se1, _, _, _, _, _, _, _, _), 1533 [35] = PINGROUP(35, qup1_se1, _, _, _, _, _, _, _, _), 1534 [36] = PINGROUP(36, qup1_se2, ddr_bist_fail, _, _, _, _, _, _, _), 1535 [37] = PINGROUP(37, qup1_se2, ddr_bist_start, _, atest_usb, _, _, _, _, _), 1536 [38] = PINGROUP(38, qup1_se2, _, _, _, _, _, _, _, _), 1537 [39] = PINGROUP(39, qup1_se2, _, atest_usb, _, _, _, _, _, _), 1538 [40] = PINGROUP(40, qup1_se3, qup1_se2, ddr_bist_complete, _, ddr_pxi1, _, _, _, _), 1539 [41] = PINGROUP(41, qup1_se3, qup1_se2, ddr_bist_stop, _, ddr_pxi1, _, _, _, _), 1540 [42] = PINGROUP(42, qup1_se3, qup1_se2, _, _, _, _, _, _, _), 1541 [43] = PINGROUP(43, qup1_se3, jitter_bist, ddr_pxi3, _, _, _, _, _, _), 1542 [44] = PINGROUP(44, qup1_se4, aoss_cti, ddr_pxi3, _, _, _, _, _, _), 1543 [45] = PINGROUP(45, qup1_se4, aoss_cti, ddr_pxi2, _, _, _, _, _, _), 1544 [46] = PINGROUP(46, qup1_se4, aoss_cti, _, _, _, _, _, _, _), 1545 [47] = PINGROUP(47, qup1_se4, aoss_cti, dp_hot, ddr_pxi2, _, _, _, _, _), 1546 [48] = PINGROUP(48, usb_phy, qup1_se6, qspi2, sdc42, _, _, _, _, _), 1547 [49] = PINGROUP(49, qup1_se6, qspi3, sdc43, _, _, _, _, _, _), 1548 [50] = PINGROUP(50, qup1_se6, qspi_clk, sdc4_clk, tsense_pwm1, tsense_pwm2, tsense_pwm3, _, _, _), 1549 [51] = PINGROUP(51, qup1_se6, qspi_cs, sdc4_cmd, ddr_pxi0, _, _, _, _, _), 1550 [52] = PINGROUP(52, _, qup1_se5, ddr_pxi0, _, _, _, _, _, _), 1551 [53] = PINGROUP(53, _, qup1_se5, _, _, _, _, _, _, _), 1552 [54] = PINGROUP(54, _, qup1_se5, _, _, _, _, _, _, _), 1553 [55] = PINGROUP(55, qup1_se5, atest_usb, _, _, _, _, _, _, _), 1554 [56] = PINGROUP(56, qup2_se0_l0_mira, ibi_i3c, _, _, _, _, _, _, _), 1555 [57] = PINGROUP(57, qup2_se0_l1_mira, ibi_i3c, _, _, _, _, _, _, _), 1556 [58] = PINGROUP(58, qup2_se0_l2_mira, _, _, _, _, _, _, _, _), 1557 [59] = PINGROUP(59, qup2_se0_l3_mira, phase_flag, _, qdss_gpio, _, _, _, _, _), 1558 [60] = PINGROUP(60, qup2_se1, ibi_i3c, _, _, _, _, _, _, _), 1559 [61] = PINGROUP(61, qup2_se1, ibi_i3c, _, _, _, _, _, _, _), 1560 [62] = PINGROUP(62, qup2_se1, _, _, _, _, _, _, _, _), 1561 [63] = PINGROUP(63, qup2_se1, qup2_se0, phase_flag, _, _, _, _, _, _), 1562 [64] = PINGROUP(64, qup2_se2, tb_trig_sdc2, phase_flag, tgu_ch0_trigout, _, qdss_gpio, _, _, _), 1563 [65] = PINGROUP(65, qup2_se2, phase_flag, tgu_ch1_trigout, _, _, _, _, _, _), 1564 [66] = PINGROUP(66, qup2_se2, qup2_se0, tgu_ch2_trigout, _, _, _, _, _, _), 1565 [67] = PINGROUP(67, qup2_se2, qup2_se0, phase_flag, tgu_ch3_trigout, _, _, _, _, _), 1566 [68] = PINGROUP(68, qup2_se3, phase_flag, _, _, _, _, _, _, _), 1567 [69] = PINGROUP(69, qup2_se3, phase_flag, _, _, _, _, _, _, _), 1568 [70] = PINGROUP(70, qup2_se3, _, _, _, _, _, _, _, _), 1569 [71] = PINGROUP(71, cci_async_in, qup2_se3, _, _, _, _, _, _, _), 1570 [72] = PINGROUP(72, cci_async_in, qup2_se7, _, _, _, _, _, _, _), 1571 [73] = PINGROUP(73, qdss_gpio, _, _, _, _, _, _, _, _), 1572 [74] = PINGROUP(74, cci_i2c_sda, qup2_se7, _, _, _, _, _, _, _), 1573 [75] = PINGROUP(75, cci_i2c_scl, qup2_se7, qdss_cti, phase_flag, _, _, _, _, _), 1574 [76] = PINGROUP(76, qup2_se6, phase_flag, _, _, _, _, _, _, _), 1575 [77] = PINGROUP(77, qup2_se6, phase_flag, _, _, _, _, _, _, _), 1576 [78] = PINGROUP(78, qup2_se6, _, _, _, _, _, _, _, _), 1577 [79] = PINGROUP(79, qup2_se6, qdss_cti, phase_flag, _, _, _, _, _, _), 1578 [80] = PINGROUP(80, qup2_se5, phase_flag, _, _, _, _, _, _, _), 1579 [81] = PINGROUP(81, qup2_se5, phase_flag, _, _, _, _, _, _, _), 1580 [82] = PINGROUP(82, qup2_se5, _, _, _, _, _, _, _, _), 1581 [83] = PINGROUP(83, qup2_se5, phase_flag, _, _, _, _, _, _, _), 1582 [84] = PINGROUP(84, i2chub0_se9, _, _, _, _, _, _, _, _), 1583 [85] = PINGROUP(85, i2chub0_se9, _, _, _, _, _, _, _, _), 1584 [86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, gcc_gp1, _, _, _, _, _), 1585 [87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, gcc_gp2, _, _, _, _, _), 1586 [88] = PINGROUP(88, mdp_vsync_e, gcc_gp3, _, _, _, _, _, _, _), 1587 [89] = PINGROUP(89, qspi0, sdc40, dbg_out_clk, _, _, _, _, _, _), 1588 [90] = PINGROUP(90, usb1_hs, qspi1, sdc41, _, _, _, _, _, _), 1589 [91] = PINGROUP(91, qspi_cs, tb_trig_sdc4, _, _, _, _, _, _, _), 1590 [92] = PINGROUP(92, resout_n, phase_flag, tmess_prng0, _, _, _, _, _, _), 1591 [93] = PINGROUP(93, sd_write_protect, _, _, _, _, _, _, _, _), 1592 [94] = PINGROUP(94, phase_flag, tmess_prng1, _, _, _, _, _, _, _), 1593 [95] = PINGROUP(95, pcie0_clk_req_n, phase_flag, tmess_prng2, _, _, _, _, _, _), 1594 [96] = PINGROUP(96, phase_flag, tmess_prng3, _, _, _, _, _, _, _), 1595 [97] = PINGROUP(97, phase_flag, _, _, _, _, _, _, _, _), 1596 [98] = PINGROUP(98, pcie1_clk_req_n, phase_flag, _, _, _, _, _, _, _), 1597 [99] = PINGROUP(99, phase_flag, _, _, _, _, _, _, _, _), 1598 [100] = PINGROUP(100, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1599 [101] = PINGROUP(101, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1600 [102] = PINGROUP(102, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1601 [103] = PINGROUP(103, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1602 [104] = PINGROUP(104, cam_aon_mclk4, qdss_gpio, _, _, _, _, _, _, _), 1603 [105] = PINGROUP(105, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1604 [106] = PINGROUP(106, cam_mclk, qup2_se7, _, _, _, _, _, _, _), 1605 [107] = PINGROUP(107, cam_mclk, qup2_se0_l3_mirb, pll_clk_aux, _, _, _, _, _, _), 1606 [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _), 1607 [109] = PINGROUP(109, cci_async_in, qup2_se0_l2_mirb, _, _, _, _, _, _, _), 1608 [110] = PINGROUP(110, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _), 1609 [111] = PINGROUP(111, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _), 1610 [112] = PINGROUP(112, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _), 1611 [113] = PINGROUP(113, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _), 1612 [114] = PINGROUP(114, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _), 1613 [115] = PINGROUP(115, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _), 1614 [116] = PINGROUP(116, cci_timer, phase_flag, _, qdss_gpio, _, _, _, _, _), 1615 [117] = PINGROUP(117, cci_timer, phase_flag, _, qdss_gpio, _, _, _, _, _), 1616 [118] = PINGROUP(118, qup2_se4, cci_timer, _, _, _, _, _, _, _), 1617 [119] = PINGROUP(119, qup2_se4, cci_timer, phase_flag, _, _, _, _, _, _), 1618 [120] = PINGROUP(120, cci_timer, phase_flag, _, qdss_gpio, _, _, _, _, _), 1619 [121] = PINGROUP(121, i2s1_sck, _, _, _, _, _, _, _, _), 1620 [122] = PINGROUP(122, i2s1_data0, cmu_rng, _, _, _, _, _, _, _), 1621 [123] = PINGROUP(123, i2s1_ws, _, _, _, _, _, _, _, _), 1622 [124] = PINGROUP(124, i2s1_data1, audio_ext_mclk1, audio_ref_clk, _, _, _, _, _, _), 1623 [125] = PINGROUP(125, audio_ext_mclk0, _, _, _, _, _, _, _, _), 1624 [126] = PINGROUP(126, i2s0_sck, _, _, _, _, _, _, _, _), 1625 [127] = PINGROUP(127, i2s0_data0, cmu_rng, _, _, _, _, _, _, _), 1626 [128] = PINGROUP(128, i2s0_data1, cmu_rng, _, _, _, _, _, _, _), 1627 [129] = PINGROUP(129, i2s0_ws, cmu_rng, _, _, _, _, _, _, _), 1628 [130] = PINGROUP(130, uim0_data, atest_char, _, _, _, _, _, _, _), 1629 [131] = PINGROUP(131, uim0_clk, _, _, _, _, _, _, _, _), 1630 [132] = PINGROUP(132, uim0_reset, atest_char, _, _, _, _, _, _, _), 1631 [133] = PINGROUP(133, mdp_vsync, atest_char, _, _, _, _, _, _, _), 1632 [134] = PINGROUP(134, uim1_data, gcc_gp1, atest_char, _, _, _, _, _, _), 1633 [135] = PINGROUP(135, uim1_clk, gcc_gp2, atest_char, _, _, _, _, _, _), 1634 [136] = PINGROUP(136, uim1_reset, gcc_gp3, _, _, _, _, _, _, _), 1635 [137] = PINGROUP(137, mdp_vsync, _, _, _, _, _, _, _, _), 1636 [138] = PINGROUP(138, _, _, qdss_gpio, _, _, _, _, _, _), 1637 [139] = PINGROUP(139, _, _, qdss_gpio, _, _, _, _, _, _), 1638 [140] = PINGROUP(140, _, _, qdss_gpio, _, _, _, _, _, _), 1639 [141] = PINGROUP(141, _, _, qdss_gpio, _, _, _, _, _, _), 1640 [142] = PINGROUP(142, _, _, qdss_gpio, _, _, _, _, _, _), 1641 [143] = PINGROUP(143, _, _, qdss_gpio, _, _, _, _, _, _), 1642 [144] = PINGROUP(144, _, _, qdss_gpio, _, _, _, _, _, _), 1643 [145] = PINGROUP(145, _, _, qdss_gpio, _, _, _, _, _, _), 1644 [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), 1645 [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), 1646 [148] = PINGROUP(148, coex_uart1_rx, qdss_gpio, atest_usb, _, _, _, _, _, _), 1647 [149] = PINGROUP(149, coex_uart1_tx, qdss_gpio, atest_usb, _, _, _, _, _, _), 1648 [150] = PINGROUP(150, coex_uart2_rx, _, vfr_0, qdss_gpio, _, _, _, _, _), 1649 [151] = PINGROUP(151, coex_uart2_tx, _, qdss_gpio, _, _, _, _, _, _), 1650 [152] = PINGROUP(152, _, qdss_gpio, _, _, _, _, _, _, _), 1651 [153] = PINGROUP(153, _, nav_gpio2, qdss_gpio, _, _, _, _, _, _), 1652 [154] = PINGROUP(154, nav_gpio0, qdss_gpio, _, _, _, _, _, _, _), 1653 [155] = PINGROUP(155, nav_gpio1, vfr_1, qdss_gpio, _, _, _, _, _, _), 1654 [156] = PINGROUP(156, qlink0_request, qdss_gpio, _, _, _, _, _, _, _), 1655 [157] = PINGROUP(157, qlink0_enable, qdss_gpio, _, _, _, _, _, _, _), 1656 [158] = PINGROUP(158, qlink0_wmss, _, _, _, _, _, _, _, _), 1657 [159] = PINGROUP(159, qlink1_request, qdss_cti, _, _, _, _, _, _, _), 1658 [160] = PINGROUP(160, qlink1_enable, qdss_cti, _, _, _, _, _, _, _), 1659 [161] = PINGROUP(161, qlink1_wmss, qdss_cti, _, _, _, _, _, _, _), 1660 [162] = PINGROUP(162, qlink2_request, qdss_cti, _, _, _, _, _, _, _), 1661 [163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _), 1662 [164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _), 1663 [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _), 1664 [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _), 1665 [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _), 1666 [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _), 1667 [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _), 1668 [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _), 1669 [171] = PINGROUP(171, _, _, _, _, _, _, _, _, _), 1670 [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _), 1671 [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _), 1672 [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _), 1673 [175] = PINGROUP(175, _, _, _, _, _, _, _, _, _), 1674 [176] = PINGROUP(176, _, _, _, _, _, _, _, _, _), 1675 [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _), 1676 [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _), 1677 [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _), 1678 [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _), 1679 [181] = PINGROUP(181, prng_rosc3, _, _, _, _, _, _, _, _), 1680 [182] = PINGROUP(182, prng_rosc2, _, _, _, _, _, _, _, _), 1681 [183] = PINGROUP(183, prng_rosc1, _, _, _, _, _, _, _, _), 1682 [184] = PINGROUP(184, _, _, _, _, _, _, _, _, _), 1683 [185] = PINGROUP(185, _, _, _, _, _, _, _, _, _), 1684 [186] = PINGROUP(186, prng_rosc0, _, _, _, _, _, _, _, _), 1685 [187] = PINGROUP(187, cri_trng, _, _, _, _, _, _, _, _), 1686 [188] = PINGROUP(188, _, _, _, _, _, _, _, _, _), 1687 [189] = PINGROUP(189, _, _, _, _, _, _, _, _, _), 1688 [190] = PINGROUP(190, _, _, _, _, _, _, _, _, _), 1689 [191] = PINGROUP(191, _, _, _, _, _, _, _, _, _), 1690 [192] = PINGROUP(192, _, _, _, _, _, _, _, _, _), 1691 [193] = PINGROUP(193, _, _, _, _, _, _, _, _, _), 1692 [194] = PINGROUP(194, _, _, _, _, _, _, _, _, _), 1693 [195] = PINGROUP(195, _, _, _, _, _, _, _, _, _), 1694 [196] = PINGROUP(196, _, _, _, _, _, _, _, _, _), 1695 [197] = PINGROUP(197, _, _, _, _, _, _, _, _, _), 1696 [198] = PINGROUP(198, _, _, _, _, _, _, _, _, _), 1697 [199] = PINGROUP(199, _, _, _, _, _, _, _, _, _), 1698 [200] = PINGROUP(200, _, _, _, _, _, _, _, _, _), 1699 [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _), 1700 [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _), 1701 [203] = PINGROUP(203, _, _, _, _, _, _, _, _, _), 1702 [204] = PINGROUP(204, _, _, _, _, _, _, _, _, _), 1703 [205] = PINGROUP(205, _, _, _, _, _, _, _, _, _), 1704 [206] = PINGROUP(206, i2chub0_se8, _, _, _, _, _, _, _, _), 1705 [207] = PINGROUP(207, i2chub0_se8, _, _, _, _, _, _, _, _), 1706 [208] = PINGROUP(208, aon_cci, _, _, _, _, _, _, _, _), 1707 [209] = PINGROUP(209, aon_cci, _, _, _, _, _, _, _, _), 1708 [210] = UFS_RESET(ufs_reset, 0xde000), 1709 [211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6), 1710 [212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3), 1711 [213] = SDC_QDSD_PINGROUP(sdc2_data, 0xd6000, 9, 0), 1712 }; 1713 1714 static const struct msm_gpio_wakeirq_map sm8550_pdc_map[] = { 1715 { 0, 118 }, { 2, 90 }, { 3, 101 }, { 8, 60 }, { 9, 67 }, 1716 { 11, 103 }, { 14, 136 }, { 15, 78 }, { 16, 138 }, { 17, 80 }, 1717 { 18, 71 }, { 19, 59 }, { 25, 57 }, { 26, 74 }, { 27, 76 }, 1718 { 28, 62 }, { 31, 88 }, { 32, 63 }, { 35, 124 }, { 39, 92 }, 1719 { 40, 77 }, { 41, 83 }, { 43, 86 }, { 44, 75 }, { 45, 93 }, 1720 { 46, 96 }, { 47, 64 }, { 48, 110 }, { 51, 89 }, { 55, 95 }, 1721 { 56, 68 }, { 59, 87 }, { 60, 65 }, { 62, 100 }, { 63, 81 }, 1722 { 67, 79 }, { 71, 102 }, { 73, 82 }, { 75, 72 }, { 79, 140 }, 1723 { 82, 105 }, { 83, 104 }, { 84, 126 }, { 85, 142 }, { 86, 106 }, 1724 { 87, 107 }, { 88, 61 }, { 89, 111 }, { 95, 108 }, { 96, 109 }, 1725 { 98, 97 }, { 99, 58 }, { 107, 139 }, { 119, 94 }, { 120, 135 }, 1726 { 133, 52 }, { 137, 84 }, { 148, 66 }, { 150, 73 }, { 153, 70 }, 1727 { 154, 53 }, { 155, 69 }, { 156, 54 }, { 159, 55 }, { 162, 56 }, 1728 { 166, 116 }, { 169, 119 }, { 171, 120 }, { 172, 85 }, { 174, 98 }, 1729 { 176, 112 }, { 177, 51 }, { 181, 114 }, { 182, 115 }, { 185, 117 }, 1730 { 187, 91 }, { 188, 123 }, { 190, 127 }, { 191, 113 }, { 192, 128 }, 1731 { 193, 129 }, { 196, 133 }, { 197, 134 }, { 198, 50 }, { 199, 99 }, 1732 { 200, 49 }, { 201, 48 }, { 203, 125 }, { 205, 141 }, { 206, 137 }, 1733 { 207, 47 }, { 208, 121 }, { 209, 122 }, 1734 }; 1735 1736 static const struct msm_pinctrl_soc_data sm8550_tlmm = { 1737 .pins = sm8550_pins, 1738 .npins = ARRAY_SIZE(sm8550_pins), 1739 .functions = sm8550_functions, 1740 .nfunctions = ARRAY_SIZE(sm8550_functions), 1741 .groups = sm8550_groups, 1742 .ngroups = ARRAY_SIZE(sm8550_groups), 1743 .ngpios = 211, 1744 .wakeirq_map = sm8550_pdc_map, 1745 .nwakeirq_map = ARRAY_SIZE(sm8550_pdc_map), 1746 .egpio_func = 9, 1747 }; 1748 1749 static int sm8550_tlmm_probe(struct platform_device *pdev) 1750 { 1751 return msm_pinctrl_probe(pdev, &sm8550_tlmm); 1752 } 1753 1754 static const struct of_device_id sm8550_tlmm_of_match[] = { 1755 { .compatible = "qcom,sm8550-tlmm", }, 1756 {}, 1757 }; 1758 1759 static struct platform_driver sm8550_tlmm_driver = { 1760 .driver = { 1761 .name = "sm8550-tlmm", 1762 .of_match_table = sm8550_tlmm_of_match, 1763 }, 1764 .probe = sm8550_tlmm_probe, 1765 .remove_new = msm_pinctrl_remove, 1766 }; 1767 1768 static int __init sm8550_tlmm_init(void) 1769 { 1770 return platform_driver_register(&sm8550_tlmm_driver); 1771 } 1772 arch_initcall(sm8550_tlmm_init); 1773 1774 static void __exit sm8550_tlmm_exit(void) 1775 { 1776 platform_driver_unregister(&sm8550_tlmm_driver); 1777 } 1778 module_exit(sm8550_tlmm_exit); 1779 1780 MODULE_DESCRIPTION("QTI SM8550 TLMM driver"); 1781 MODULE_LICENSE("GPL"); 1782 MODULE_DEVICE_TABLE(of, sm8550_tlmm_of_match); 1783