1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/of.h> 8 #include <linux/platform_device.h> 9 10 #include "pinctrl-msm.h" 11 12 static const char * const sm8250_tiles[] = { 13 "west", 14 "south", 15 "north", 16 }; 17 18 enum { 19 WEST, 20 SOUTH, 21 NORTH, 22 }; 23 24 #define REG_SIZE 0x1000 25 #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 26 { \ 27 .grp = PINCTRL_PINGROUP("gpio" #id, \ 28 gpio##id##_pins, \ 29 ARRAY_SIZE(gpio##id##_pins)), \ 30 .funcs = (int[]){ \ 31 msm_mux_gpio, /* gpio mode */ \ 32 msm_mux_##f1, \ 33 msm_mux_##f2, \ 34 msm_mux_##f3, \ 35 msm_mux_##f4, \ 36 msm_mux_##f5, \ 37 msm_mux_##f6, \ 38 msm_mux_##f7, \ 39 msm_mux_##f8, \ 40 msm_mux_##f9 \ 41 }, \ 42 .nfuncs = 10, \ 43 .ctl_reg = REG_SIZE * id, \ 44 .io_reg = REG_SIZE * id + 0x4, \ 45 .intr_cfg_reg = REG_SIZE * id + 0x8, \ 46 .intr_status_reg = REG_SIZE * id + 0xc, \ 47 .intr_target_reg = REG_SIZE * id + 0x8, \ 48 .tile = _tile, \ 49 .mux_bit = 2, \ 50 .pull_bit = 0, \ 51 .drv_bit = 6, \ 52 .oe_bit = 9, \ 53 .in_bit = 0, \ 54 .out_bit = 1, \ 55 .intr_enable_bit = 0, \ 56 .intr_status_bit = 0, \ 57 .intr_target_bit = 5, \ 58 .intr_target_kpss_val = 3, \ 59 .intr_raw_status_bit = 4, \ 60 .intr_polarity_bit = 1, \ 61 .intr_detection_bit = 2, \ 62 .intr_detection_width = 2, \ 63 } 64 65 #define SDC_PINGROUP(pg_name, ctl, pull, drv) \ 66 { \ 67 .grp = PINCTRL_PINGROUP(#pg_name, \ 68 pg_name##_pins, \ 69 ARRAY_SIZE(pg_name##_pins)), \ 70 .ctl_reg = ctl, \ 71 .io_reg = 0, \ 72 .intr_cfg_reg = 0, \ 73 .intr_status_reg = 0, \ 74 .intr_target_reg = 0, \ 75 .tile = NORTH, \ 76 .mux_bit = -1, \ 77 .pull_bit = pull, \ 78 .drv_bit = drv, \ 79 .oe_bit = -1, \ 80 .in_bit = -1, \ 81 .out_bit = -1, \ 82 .intr_enable_bit = -1, \ 83 .intr_status_bit = -1, \ 84 .intr_target_bit = -1, \ 85 .intr_raw_status_bit = -1, \ 86 .intr_polarity_bit = -1, \ 87 .intr_detection_bit = -1, \ 88 .intr_detection_width = -1, \ 89 } 90 91 #define UFS_RESET(pg_name, offset) \ 92 { \ 93 .grp = PINCTRL_PINGROUP(#pg_name, \ 94 pg_name##_pins, \ 95 ARRAY_SIZE(pg_name##_pins)), \ 96 .ctl_reg = offset, \ 97 .io_reg = offset + 0x4, \ 98 .intr_cfg_reg = 0, \ 99 .intr_status_reg = 0, \ 100 .intr_target_reg = 0, \ 101 .tile = SOUTH, \ 102 .mux_bit = -1, \ 103 .pull_bit = 3, \ 104 .drv_bit = 0, \ 105 .oe_bit = -1, \ 106 .in_bit = -1, \ 107 .out_bit = 0, \ 108 .intr_enable_bit = -1, \ 109 .intr_status_bit = -1, \ 110 .intr_target_bit = -1, \ 111 .intr_raw_status_bit = -1, \ 112 .intr_polarity_bit = -1, \ 113 .intr_detection_bit = -1, \ 114 .intr_detection_width = -1, \ 115 } 116 117 static const struct pinctrl_pin_desc sm8250_pins[] = { 118 PINCTRL_PIN(0, "GPIO_0"), 119 PINCTRL_PIN(1, "GPIO_1"), 120 PINCTRL_PIN(2, "GPIO_2"), 121 PINCTRL_PIN(3, "GPIO_3"), 122 PINCTRL_PIN(4, "GPIO_4"), 123 PINCTRL_PIN(5, "GPIO_5"), 124 PINCTRL_PIN(6, "GPIO_6"), 125 PINCTRL_PIN(7, "GPIO_7"), 126 PINCTRL_PIN(8, "GPIO_8"), 127 PINCTRL_PIN(9, "GPIO_9"), 128 PINCTRL_PIN(10, "GPIO_10"), 129 PINCTRL_PIN(11, "GPIO_11"), 130 PINCTRL_PIN(12, "GPIO_12"), 131 PINCTRL_PIN(13, "GPIO_13"), 132 PINCTRL_PIN(14, "GPIO_14"), 133 PINCTRL_PIN(15, "GPIO_15"), 134 PINCTRL_PIN(16, "GPIO_16"), 135 PINCTRL_PIN(17, "GPIO_17"), 136 PINCTRL_PIN(18, "GPIO_18"), 137 PINCTRL_PIN(19, "GPIO_19"), 138 PINCTRL_PIN(20, "GPIO_20"), 139 PINCTRL_PIN(21, "GPIO_21"), 140 PINCTRL_PIN(22, "GPIO_22"), 141 PINCTRL_PIN(23, "GPIO_23"), 142 PINCTRL_PIN(24, "GPIO_24"), 143 PINCTRL_PIN(25, "GPIO_25"), 144 PINCTRL_PIN(26, "GPIO_26"), 145 PINCTRL_PIN(27, "GPIO_27"), 146 PINCTRL_PIN(28, "GPIO_28"), 147 PINCTRL_PIN(29, "GPIO_29"), 148 PINCTRL_PIN(30, "GPIO_30"), 149 PINCTRL_PIN(31, "GPIO_31"), 150 PINCTRL_PIN(32, "GPIO_32"), 151 PINCTRL_PIN(33, "GPIO_33"), 152 PINCTRL_PIN(34, "GPIO_34"), 153 PINCTRL_PIN(35, "GPIO_35"), 154 PINCTRL_PIN(36, "GPIO_36"), 155 PINCTRL_PIN(37, "GPIO_37"), 156 PINCTRL_PIN(38, "GPIO_38"), 157 PINCTRL_PIN(39, "GPIO_39"), 158 PINCTRL_PIN(40, "GPIO_40"), 159 PINCTRL_PIN(41, "GPIO_41"), 160 PINCTRL_PIN(42, "GPIO_42"), 161 PINCTRL_PIN(43, "GPIO_43"), 162 PINCTRL_PIN(44, "GPIO_44"), 163 PINCTRL_PIN(45, "GPIO_45"), 164 PINCTRL_PIN(46, "GPIO_46"), 165 PINCTRL_PIN(47, "GPIO_47"), 166 PINCTRL_PIN(48, "GPIO_48"), 167 PINCTRL_PIN(49, "GPIO_49"), 168 PINCTRL_PIN(50, "GPIO_50"), 169 PINCTRL_PIN(51, "GPIO_51"), 170 PINCTRL_PIN(52, "GPIO_52"), 171 PINCTRL_PIN(53, "GPIO_53"), 172 PINCTRL_PIN(54, "GPIO_54"), 173 PINCTRL_PIN(55, "GPIO_55"), 174 PINCTRL_PIN(56, "GPIO_56"), 175 PINCTRL_PIN(57, "GPIO_57"), 176 PINCTRL_PIN(58, "GPIO_58"), 177 PINCTRL_PIN(59, "GPIO_59"), 178 PINCTRL_PIN(60, "GPIO_60"), 179 PINCTRL_PIN(61, "GPIO_61"), 180 PINCTRL_PIN(62, "GPIO_62"), 181 PINCTRL_PIN(63, "GPIO_63"), 182 PINCTRL_PIN(64, "GPIO_64"), 183 PINCTRL_PIN(65, "GPIO_65"), 184 PINCTRL_PIN(66, "GPIO_66"), 185 PINCTRL_PIN(67, "GPIO_67"), 186 PINCTRL_PIN(68, "GPIO_68"), 187 PINCTRL_PIN(69, "GPIO_69"), 188 PINCTRL_PIN(70, "GPIO_70"), 189 PINCTRL_PIN(71, "GPIO_71"), 190 PINCTRL_PIN(72, "GPIO_72"), 191 PINCTRL_PIN(73, "GPIO_73"), 192 PINCTRL_PIN(74, "GPIO_74"), 193 PINCTRL_PIN(75, "GPIO_75"), 194 PINCTRL_PIN(76, "GPIO_76"), 195 PINCTRL_PIN(77, "GPIO_77"), 196 PINCTRL_PIN(78, "GPIO_78"), 197 PINCTRL_PIN(79, "GPIO_79"), 198 PINCTRL_PIN(80, "GPIO_80"), 199 PINCTRL_PIN(81, "GPIO_81"), 200 PINCTRL_PIN(82, "GPIO_82"), 201 PINCTRL_PIN(83, "GPIO_83"), 202 PINCTRL_PIN(84, "GPIO_84"), 203 PINCTRL_PIN(85, "GPIO_85"), 204 PINCTRL_PIN(86, "GPIO_86"), 205 PINCTRL_PIN(87, "GPIO_87"), 206 PINCTRL_PIN(88, "GPIO_88"), 207 PINCTRL_PIN(89, "GPIO_89"), 208 PINCTRL_PIN(90, "GPIO_90"), 209 PINCTRL_PIN(91, "GPIO_91"), 210 PINCTRL_PIN(92, "GPIO_92"), 211 PINCTRL_PIN(93, "GPIO_93"), 212 PINCTRL_PIN(94, "GPIO_94"), 213 PINCTRL_PIN(95, "GPIO_95"), 214 PINCTRL_PIN(96, "GPIO_96"), 215 PINCTRL_PIN(97, "GPIO_97"), 216 PINCTRL_PIN(98, "GPIO_98"), 217 PINCTRL_PIN(99, "GPIO_99"), 218 PINCTRL_PIN(100, "GPIO_100"), 219 PINCTRL_PIN(101, "GPIO_101"), 220 PINCTRL_PIN(102, "GPIO_102"), 221 PINCTRL_PIN(103, "GPIO_103"), 222 PINCTRL_PIN(104, "GPIO_104"), 223 PINCTRL_PIN(105, "GPIO_105"), 224 PINCTRL_PIN(106, "GPIO_106"), 225 PINCTRL_PIN(107, "GPIO_107"), 226 PINCTRL_PIN(108, "GPIO_108"), 227 PINCTRL_PIN(109, "GPIO_109"), 228 PINCTRL_PIN(110, "GPIO_110"), 229 PINCTRL_PIN(111, "GPIO_111"), 230 PINCTRL_PIN(112, "GPIO_112"), 231 PINCTRL_PIN(113, "GPIO_113"), 232 PINCTRL_PIN(114, "GPIO_114"), 233 PINCTRL_PIN(115, "GPIO_115"), 234 PINCTRL_PIN(116, "GPIO_116"), 235 PINCTRL_PIN(117, "GPIO_117"), 236 PINCTRL_PIN(118, "GPIO_118"), 237 PINCTRL_PIN(119, "GPIO_119"), 238 PINCTRL_PIN(120, "GPIO_120"), 239 PINCTRL_PIN(121, "GPIO_121"), 240 PINCTRL_PIN(122, "GPIO_122"), 241 PINCTRL_PIN(123, "GPIO_123"), 242 PINCTRL_PIN(124, "GPIO_124"), 243 PINCTRL_PIN(125, "GPIO_125"), 244 PINCTRL_PIN(126, "GPIO_126"), 245 PINCTRL_PIN(127, "GPIO_127"), 246 PINCTRL_PIN(128, "GPIO_128"), 247 PINCTRL_PIN(129, "GPIO_129"), 248 PINCTRL_PIN(130, "GPIO_130"), 249 PINCTRL_PIN(131, "GPIO_131"), 250 PINCTRL_PIN(132, "GPIO_132"), 251 PINCTRL_PIN(133, "GPIO_133"), 252 PINCTRL_PIN(134, "GPIO_134"), 253 PINCTRL_PIN(135, "GPIO_135"), 254 PINCTRL_PIN(136, "GPIO_136"), 255 PINCTRL_PIN(137, "GPIO_137"), 256 PINCTRL_PIN(138, "GPIO_138"), 257 PINCTRL_PIN(139, "GPIO_139"), 258 PINCTRL_PIN(140, "GPIO_140"), 259 PINCTRL_PIN(141, "GPIO_141"), 260 PINCTRL_PIN(142, "GPIO_142"), 261 PINCTRL_PIN(143, "GPIO_143"), 262 PINCTRL_PIN(144, "GPIO_144"), 263 PINCTRL_PIN(145, "GPIO_145"), 264 PINCTRL_PIN(146, "GPIO_146"), 265 PINCTRL_PIN(147, "GPIO_147"), 266 PINCTRL_PIN(148, "GPIO_148"), 267 PINCTRL_PIN(149, "GPIO_149"), 268 PINCTRL_PIN(150, "GPIO_150"), 269 PINCTRL_PIN(151, "GPIO_151"), 270 PINCTRL_PIN(152, "GPIO_152"), 271 PINCTRL_PIN(153, "GPIO_153"), 272 PINCTRL_PIN(154, "GPIO_154"), 273 PINCTRL_PIN(155, "GPIO_155"), 274 PINCTRL_PIN(156, "GPIO_156"), 275 PINCTRL_PIN(157, "GPIO_157"), 276 PINCTRL_PIN(158, "GPIO_158"), 277 PINCTRL_PIN(159, "GPIO_159"), 278 PINCTRL_PIN(160, "GPIO_160"), 279 PINCTRL_PIN(161, "GPIO_161"), 280 PINCTRL_PIN(162, "GPIO_162"), 281 PINCTRL_PIN(163, "GPIO_163"), 282 PINCTRL_PIN(164, "GPIO_164"), 283 PINCTRL_PIN(165, "GPIO_165"), 284 PINCTRL_PIN(166, "GPIO_166"), 285 PINCTRL_PIN(167, "GPIO_167"), 286 PINCTRL_PIN(168, "GPIO_168"), 287 PINCTRL_PIN(169, "GPIO_169"), 288 PINCTRL_PIN(170, "GPIO_170"), 289 PINCTRL_PIN(171, "GPIO_171"), 290 PINCTRL_PIN(172, "GPIO_172"), 291 PINCTRL_PIN(173, "GPIO_173"), 292 PINCTRL_PIN(174, "GPIO_174"), 293 PINCTRL_PIN(175, "GPIO_175"), 294 PINCTRL_PIN(176, "GPIO_176"), 295 PINCTRL_PIN(177, "GPIO_177"), 296 PINCTRL_PIN(178, "GPIO_178"), 297 PINCTRL_PIN(179, "GPIO_179"), 298 PINCTRL_PIN(180, "SDC2_CLK"), 299 PINCTRL_PIN(181, "SDC2_CMD"), 300 PINCTRL_PIN(182, "SDC2_DATA"), 301 PINCTRL_PIN(183, "UFS_RESET"), 302 }; 303 304 #define DECLARE_MSM_GPIO_PINS(pin) \ 305 static const unsigned int gpio##pin##_pins[] = { pin } 306 DECLARE_MSM_GPIO_PINS(0); 307 DECLARE_MSM_GPIO_PINS(1); 308 DECLARE_MSM_GPIO_PINS(2); 309 DECLARE_MSM_GPIO_PINS(3); 310 DECLARE_MSM_GPIO_PINS(4); 311 DECLARE_MSM_GPIO_PINS(5); 312 DECLARE_MSM_GPIO_PINS(6); 313 DECLARE_MSM_GPIO_PINS(7); 314 DECLARE_MSM_GPIO_PINS(8); 315 DECLARE_MSM_GPIO_PINS(9); 316 DECLARE_MSM_GPIO_PINS(10); 317 DECLARE_MSM_GPIO_PINS(11); 318 DECLARE_MSM_GPIO_PINS(12); 319 DECLARE_MSM_GPIO_PINS(13); 320 DECLARE_MSM_GPIO_PINS(14); 321 DECLARE_MSM_GPIO_PINS(15); 322 DECLARE_MSM_GPIO_PINS(16); 323 DECLARE_MSM_GPIO_PINS(17); 324 DECLARE_MSM_GPIO_PINS(18); 325 DECLARE_MSM_GPIO_PINS(19); 326 DECLARE_MSM_GPIO_PINS(20); 327 DECLARE_MSM_GPIO_PINS(21); 328 DECLARE_MSM_GPIO_PINS(22); 329 DECLARE_MSM_GPIO_PINS(23); 330 DECLARE_MSM_GPIO_PINS(24); 331 DECLARE_MSM_GPIO_PINS(25); 332 DECLARE_MSM_GPIO_PINS(26); 333 DECLARE_MSM_GPIO_PINS(27); 334 DECLARE_MSM_GPIO_PINS(28); 335 DECLARE_MSM_GPIO_PINS(29); 336 DECLARE_MSM_GPIO_PINS(30); 337 DECLARE_MSM_GPIO_PINS(31); 338 DECLARE_MSM_GPIO_PINS(32); 339 DECLARE_MSM_GPIO_PINS(33); 340 DECLARE_MSM_GPIO_PINS(34); 341 DECLARE_MSM_GPIO_PINS(35); 342 DECLARE_MSM_GPIO_PINS(36); 343 DECLARE_MSM_GPIO_PINS(37); 344 DECLARE_MSM_GPIO_PINS(38); 345 DECLARE_MSM_GPIO_PINS(39); 346 DECLARE_MSM_GPIO_PINS(40); 347 DECLARE_MSM_GPIO_PINS(41); 348 DECLARE_MSM_GPIO_PINS(42); 349 DECLARE_MSM_GPIO_PINS(43); 350 DECLARE_MSM_GPIO_PINS(44); 351 DECLARE_MSM_GPIO_PINS(45); 352 DECLARE_MSM_GPIO_PINS(46); 353 DECLARE_MSM_GPIO_PINS(47); 354 DECLARE_MSM_GPIO_PINS(48); 355 DECLARE_MSM_GPIO_PINS(49); 356 DECLARE_MSM_GPIO_PINS(50); 357 DECLARE_MSM_GPIO_PINS(51); 358 DECLARE_MSM_GPIO_PINS(52); 359 DECLARE_MSM_GPIO_PINS(53); 360 DECLARE_MSM_GPIO_PINS(54); 361 DECLARE_MSM_GPIO_PINS(55); 362 DECLARE_MSM_GPIO_PINS(56); 363 DECLARE_MSM_GPIO_PINS(57); 364 DECLARE_MSM_GPIO_PINS(58); 365 DECLARE_MSM_GPIO_PINS(59); 366 DECLARE_MSM_GPIO_PINS(60); 367 DECLARE_MSM_GPIO_PINS(61); 368 DECLARE_MSM_GPIO_PINS(62); 369 DECLARE_MSM_GPIO_PINS(63); 370 DECLARE_MSM_GPIO_PINS(64); 371 DECLARE_MSM_GPIO_PINS(65); 372 DECLARE_MSM_GPIO_PINS(66); 373 DECLARE_MSM_GPIO_PINS(67); 374 DECLARE_MSM_GPIO_PINS(68); 375 DECLARE_MSM_GPIO_PINS(69); 376 DECLARE_MSM_GPIO_PINS(70); 377 DECLARE_MSM_GPIO_PINS(71); 378 DECLARE_MSM_GPIO_PINS(72); 379 DECLARE_MSM_GPIO_PINS(73); 380 DECLARE_MSM_GPIO_PINS(74); 381 DECLARE_MSM_GPIO_PINS(75); 382 DECLARE_MSM_GPIO_PINS(76); 383 DECLARE_MSM_GPIO_PINS(77); 384 DECLARE_MSM_GPIO_PINS(78); 385 DECLARE_MSM_GPIO_PINS(79); 386 DECLARE_MSM_GPIO_PINS(80); 387 DECLARE_MSM_GPIO_PINS(81); 388 DECLARE_MSM_GPIO_PINS(82); 389 DECLARE_MSM_GPIO_PINS(83); 390 DECLARE_MSM_GPIO_PINS(84); 391 DECLARE_MSM_GPIO_PINS(85); 392 DECLARE_MSM_GPIO_PINS(86); 393 DECLARE_MSM_GPIO_PINS(87); 394 DECLARE_MSM_GPIO_PINS(88); 395 DECLARE_MSM_GPIO_PINS(89); 396 DECLARE_MSM_GPIO_PINS(90); 397 DECLARE_MSM_GPIO_PINS(91); 398 DECLARE_MSM_GPIO_PINS(92); 399 DECLARE_MSM_GPIO_PINS(93); 400 DECLARE_MSM_GPIO_PINS(94); 401 DECLARE_MSM_GPIO_PINS(95); 402 DECLARE_MSM_GPIO_PINS(96); 403 DECLARE_MSM_GPIO_PINS(97); 404 DECLARE_MSM_GPIO_PINS(98); 405 DECLARE_MSM_GPIO_PINS(99); 406 DECLARE_MSM_GPIO_PINS(100); 407 DECLARE_MSM_GPIO_PINS(101); 408 DECLARE_MSM_GPIO_PINS(102); 409 DECLARE_MSM_GPIO_PINS(103); 410 DECLARE_MSM_GPIO_PINS(104); 411 DECLARE_MSM_GPIO_PINS(105); 412 DECLARE_MSM_GPIO_PINS(106); 413 DECLARE_MSM_GPIO_PINS(107); 414 DECLARE_MSM_GPIO_PINS(108); 415 DECLARE_MSM_GPIO_PINS(109); 416 DECLARE_MSM_GPIO_PINS(110); 417 DECLARE_MSM_GPIO_PINS(111); 418 DECLARE_MSM_GPIO_PINS(112); 419 DECLARE_MSM_GPIO_PINS(113); 420 DECLARE_MSM_GPIO_PINS(114); 421 DECLARE_MSM_GPIO_PINS(115); 422 DECLARE_MSM_GPIO_PINS(116); 423 DECLARE_MSM_GPIO_PINS(117); 424 DECLARE_MSM_GPIO_PINS(118); 425 DECLARE_MSM_GPIO_PINS(119); 426 DECLARE_MSM_GPIO_PINS(120); 427 DECLARE_MSM_GPIO_PINS(121); 428 DECLARE_MSM_GPIO_PINS(122); 429 DECLARE_MSM_GPIO_PINS(123); 430 DECLARE_MSM_GPIO_PINS(124); 431 DECLARE_MSM_GPIO_PINS(125); 432 DECLARE_MSM_GPIO_PINS(126); 433 DECLARE_MSM_GPIO_PINS(127); 434 DECLARE_MSM_GPIO_PINS(128); 435 DECLARE_MSM_GPIO_PINS(129); 436 DECLARE_MSM_GPIO_PINS(130); 437 DECLARE_MSM_GPIO_PINS(131); 438 DECLARE_MSM_GPIO_PINS(132); 439 DECLARE_MSM_GPIO_PINS(133); 440 DECLARE_MSM_GPIO_PINS(134); 441 DECLARE_MSM_GPIO_PINS(135); 442 DECLARE_MSM_GPIO_PINS(136); 443 DECLARE_MSM_GPIO_PINS(137); 444 DECLARE_MSM_GPIO_PINS(138); 445 DECLARE_MSM_GPIO_PINS(139); 446 DECLARE_MSM_GPIO_PINS(140); 447 DECLARE_MSM_GPIO_PINS(141); 448 DECLARE_MSM_GPIO_PINS(142); 449 DECLARE_MSM_GPIO_PINS(143); 450 DECLARE_MSM_GPIO_PINS(144); 451 DECLARE_MSM_GPIO_PINS(145); 452 DECLARE_MSM_GPIO_PINS(146); 453 DECLARE_MSM_GPIO_PINS(147); 454 DECLARE_MSM_GPIO_PINS(148); 455 DECLARE_MSM_GPIO_PINS(149); 456 DECLARE_MSM_GPIO_PINS(150); 457 DECLARE_MSM_GPIO_PINS(151); 458 DECLARE_MSM_GPIO_PINS(152); 459 DECLARE_MSM_GPIO_PINS(153); 460 DECLARE_MSM_GPIO_PINS(154); 461 DECLARE_MSM_GPIO_PINS(155); 462 DECLARE_MSM_GPIO_PINS(156); 463 DECLARE_MSM_GPIO_PINS(157); 464 DECLARE_MSM_GPIO_PINS(158); 465 DECLARE_MSM_GPIO_PINS(159); 466 DECLARE_MSM_GPIO_PINS(160); 467 DECLARE_MSM_GPIO_PINS(161); 468 DECLARE_MSM_GPIO_PINS(162); 469 DECLARE_MSM_GPIO_PINS(163); 470 DECLARE_MSM_GPIO_PINS(164); 471 DECLARE_MSM_GPIO_PINS(165); 472 DECLARE_MSM_GPIO_PINS(166); 473 DECLARE_MSM_GPIO_PINS(167); 474 DECLARE_MSM_GPIO_PINS(168); 475 DECLARE_MSM_GPIO_PINS(169); 476 DECLARE_MSM_GPIO_PINS(170); 477 DECLARE_MSM_GPIO_PINS(171); 478 DECLARE_MSM_GPIO_PINS(172); 479 DECLARE_MSM_GPIO_PINS(173); 480 DECLARE_MSM_GPIO_PINS(174); 481 DECLARE_MSM_GPIO_PINS(175); 482 DECLARE_MSM_GPIO_PINS(176); 483 DECLARE_MSM_GPIO_PINS(177); 484 DECLARE_MSM_GPIO_PINS(178); 485 DECLARE_MSM_GPIO_PINS(179); 486 487 static const unsigned int ufs_reset_pins[] = { 180 }; 488 static const unsigned int sdc2_clk_pins[] = { 181 }; 489 static const unsigned int sdc2_cmd_pins[] = { 182 }; 490 static const unsigned int sdc2_data_pins[] = { 183 }; 491 492 enum sm8250_functions { 493 msm_mux_aoss_cti, 494 msm_mux_atest, 495 msm_mux_audio_ref, 496 msm_mux_cam_mclk, 497 msm_mux_cci_async, 498 msm_mux_cci_i2c, 499 msm_mux_cci_timer0, 500 msm_mux_cci_timer1, 501 msm_mux_cci_timer2, 502 msm_mux_cci_timer3, 503 msm_mux_cci_timer4, 504 msm_mux_cri_trng, 505 msm_mux_cri_trng0, 506 msm_mux_cri_trng1, 507 msm_mux_dbg_out, 508 msm_mux_ddr_bist, 509 msm_mux_ddr_pxi0, 510 msm_mux_ddr_pxi1, 511 msm_mux_ddr_pxi2, 512 msm_mux_ddr_pxi3, 513 msm_mux_dp_hot, 514 msm_mux_dp_lcd, 515 msm_mux_gcc_gp1, 516 msm_mux_gcc_gp2, 517 msm_mux_gcc_gp3, 518 msm_mux_gpio, 519 msm_mux_ibi_i3c, 520 msm_mux_jitter_bist, 521 msm_mux_lpass_slimbus, 522 msm_mux_mdp_vsync, 523 msm_mux_mdp_vsync0, 524 msm_mux_mdp_vsync1, 525 msm_mux_mdp_vsync2, 526 msm_mux_mdp_vsync3, 527 msm_mux_mi2s0_data0, 528 msm_mux_mi2s0_data1, 529 msm_mux_mi2s0_sck, 530 msm_mux_mi2s0_ws, 531 msm_mux_mi2s1_data0, 532 msm_mux_mi2s1_data1, 533 msm_mux_mi2s1_sck, 534 msm_mux_mi2s1_ws, 535 msm_mux_mi2s2_data0, 536 msm_mux_mi2s2_data1, 537 msm_mux_mi2s2_sck, 538 msm_mux_mi2s2_ws, 539 msm_mux_pci_e0, 540 msm_mux_pci_e1, 541 msm_mux_pci_e2, 542 msm_mux_phase_flag, 543 msm_mux_pll_bist, 544 msm_mux_pll_bypassnl, 545 msm_mux_pll_clk, 546 msm_mux_pll_reset, 547 msm_mux_pri_mi2s, 548 msm_mux_prng_rosc, 549 msm_mux_qdss_cti, 550 msm_mux_qdss_gpio, 551 msm_mux_qspi0, 552 msm_mux_qspi1, 553 msm_mux_qspi2, 554 msm_mux_qspi3, 555 msm_mux_qspi_clk, 556 msm_mux_qspi_cs, 557 msm_mux_qup0, 558 msm_mux_qup1, 559 msm_mux_qup10, 560 msm_mux_qup11, 561 msm_mux_qup12, 562 msm_mux_qup13, 563 msm_mux_qup14, 564 msm_mux_qup15, 565 msm_mux_qup16, 566 msm_mux_qup17, 567 msm_mux_qup18, 568 msm_mux_qup19, 569 msm_mux_qup2, 570 msm_mux_qup3, 571 msm_mux_qup4, 572 msm_mux_qup5, 573 msm_mux_qup6, 574 msm_mux_qup7, 575 msm_mux_qup8, 576 msm_mux_qup9, 577 msm_mux_qup_l4, 578 msm_mux_qup_l5, 579 msm_mux_qup_l6, 580 msm_mux_sd_write, 581 msm_mux_sdc40, 582 msm_mux_sdc41, 583 msm_mux_sdc42, 584 msm_mux_sdc43, 585 msm_mux_sdc4_clk, 586 msm_mux_sdc4_cmd, 587 msm_mux_sec_mi2s, 588 msm_mux_sp_cmu, 589 msm_mux_tgu_ch0, 590 msm_mux_tgu_ch1, 591 msm_mux_tgu_ch2, 592 msm_mux_tgu_ch3, 593 msm_mux_tsense_pwm1, 594 msm_mux_tsense_pwm2, 595 msm_mux_tsif0_clk, 596 msm_mux_tsif0_data, 597 msm_mux_tsif0_en, 598 msm_mux_tsif0_error, 599 msm_mux_tsif0_sync, 600 msm_mux_tsif1_clk, 601 msm_mux_tsif1_data, 602 msm_mux_tsif1_en, 603 msm_mux_tsif1_error, 604 msm_mux_tsif1_sync, 605 msm_mux_usb2phy_ac, 606 msm_mux_usb_phy, 607 msm_mux_vsense_trigger, 608 msm_mux__, 609 }; 610 611 static const char * const tsif1_data_groups[] = { 612 "gpio75", 613 }; 614 static const char * const sdc41_groups[] = { 615 "gpio75", 616 }; 617 static const char * const tsif1_sync_groups[] = { 618 "gpio76", 619 }; 620 static const char * const sdc40_groups[] = { 621 "gpio76", 622 }; 623 static const char * const aoss_cti_groups[] = { 624 "gpio77", 625 }; 626 static const char * const phase_flag_groups[] = { 627 "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", 628 "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio77", 629 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 630 "gpio103", "gpio104", "gpio115", "gpio116", "gpio117", "gpio118", 631 "gpio119", "gpio120", "gpio122", "gpio124", "gpio125", 632 }; 633 static const char * const sd_write_groups[] = { 634 "gpio78", 635 }; 636 static const char * const pci_e0_groups[] = { 637 "gpio79", "gpio80", 638 }; 639 static const char * const pci_e1_groups[] = { 640 "gpio82", "gpio83", 641 }; 642 static const char * const pci_e2_groups[] = { 643 "gpio85", "gpio86", 644 }; 645 static const char * const tgu_ch0_groups[] = { 646 "gpio85", 647 }; 648 static const char * const atest_groups[] = { 649 "gpio24", "gpio25", "gpio26", "gpio27", "gpio32", "gpio33", "gpio34", 650 "gpio35", "gpio36", "gpio37", "gpio85", "gpio86", "gpio87", "gpio88", 651 "gpio89", 652 }; 653 static const char * const tgu_ch3_groups[] = { 654 "gpio86", 655 }; 656 static const char * const tsif1_error_groups[] = { 657 "gpio90", 658 }; 659 static const char * const tgu_ch1_groups[] = { 660 "gpio90", 661 }; 662 static const char * const tsif0_error_groups[] = { 663 "gpio91", 664 }; 665 static const char * const tgu_ch2_groups[] = { 666 "gpio91", 667 }; 668 static const char * const cam_mclk_groups[] = { 669 "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", 670 }; 671 static const char * const ddr_bist_groups[] = { 672 "gpio94", "gpio95", "gpio143", "gpio144", 673 }; 674 static const char * const pll_bypassnl_groups[] = { 675 "gpio96", 676 }; 677 static const char * const pll_reset_groups[] = { 678 "gpio97", 679 }; 680 static const char * const cci_i2c_groups[] = { 681 "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", 682 "gpio107", "gpio108", 683 }; 684 static const char * const qdss_gpio_groups[] = { 685 "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", 686 "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", 687 "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio160", 688 "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", 689 "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", 690 "gpio173", "gpio174", "gpio175", "gpio176", "gpio177", 691 }; 692 static const char * const gcc_gp1_groups[] = { 693 "gpio106", "gpio136", 694 }; 695 static const char * const gcc_gp2_groups[] = { 696 "gpio107", "gpio137", 697 }; 698 static const char * const gcc_gp3_groups[] = { 699 "gpio108", "gpio138", 700 }; 701 static const char * const cci_timer0_groups[] = { 702 "gpio109", 703 }; 704 static const char * const cci_timer1_groups[] = { 705 "gpio110", 706 }; 707 static const char * const cci_timer2_groups[] = { 708 "gpio111", 709 }; 710 static const char * const cci_timer3_groups[] = { 711 "gpio112", 712 }; 713 static const char * const cci_async_groups[] = { 714 "gpio112", "gpio113", "gpio114", 715 }; 716 static const char * const cci_timer4_groups[] = { 717 "gpio113", 718 }; 719 static const char * const qup2_groups[] = { 720 "gpio115", "gpio116", "gpio117", "gpio118", 721 }; 722 static const char * const qup3_groups[] = { 723 "gpio119", "gpio120", "gpio121", "gpio122", 724 }; 725 static const char * const tsense_pwm1_groups[] = { 726 "gpio123", 727 }; 728 static const char * const tsense_pwm2_groups[] = { 729 "gpio123", 730 }; 731 static const char * const qup9_groups[] = { 732 "gpio125", "gpio126", "gpio127", "gpio128", 733 }; 734 static const char * const qup10_groups[] = { 735 "gpio129", "gpio130", "gpio131", "gpio132", 736 }; 737 static const char * const mi2s2_sck_groups[] = { 738 "gpio133", 739 }; 740 static const char * const mi2s2_data0_groups[] = { 741 "gpio134", 742 }; 743 static const char * const mi2s2_ws_groups[] = { 744 "gpio135", 745 }; 746 static const char * const pri_mi2s_groups[] = { 747 "gpio136", 748 }; 749 static const char * const sec_mi2s_groups[] = { 750 "gpio137", 751 }; 752 static const char * const audio_ref_groups[] = { 753 "gpio137", 754 }; 755 static const char * const mi2s2_data1_groups[] = { 756 "gpio137", 757 }; 758 static const char * const mi2s0_sck_groups[] = { 759 "gpio138", 760 }; 761 static const char * const mi2s0_data0_groups[] = { 762 "gpio139", 763 }; 764 static const char * const mi2s0_data1_groups[] = { 765 "gpio140", 766 }; 767 static const char * const mi2s0_ws_groups[] = { 768 "gpio141", 769 }; 770 static const char * const lpass_slimbus_groups[] = { 771 "gpio142", "gpio143", "gpio144", "gpio145", 772 }; 773 static const char * const mi2s1_sck_groups[] = { 774 "gpio142", 775 }; 776 static const char * const mi2s1_data0_groups[] = { 777 "gpio143", 778 }; 779 static const char * const mi2s1_data1_groups[] = { 780 "gpio144", 781 }; 782 static const char * const mi2s1_ws_groups[] = { 783 "gpio145", 784 }; 785 static const char * const cri_trng0_groups[] = { 786 "gpio159", 787 }; 788 static const char * const cri_trng1_groups[] = { 789 "gpio160", 790 }; 791 static const char * const cri_trng_groups[] = { 792 "gpio161", 793 }; 794 static const char * const sp_cmu_groups[] = { 795 "gpio162", 796 }; 797 static const char * const prng_rosc_groups[] = { 798 "gpio163", 799 }; 800 static const char * const qup19_groups[] = { 801 "gpio0", "gpio1", "gpio2", "gpio3", 802 }; 803 static const char * const gpio_groups[] = { 804 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 805 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 806 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 807 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 808 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 809 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 810 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 811 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 812 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 813 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 814 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 815 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 816 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 817 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 818 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 819 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 820 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 821 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", 822 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", 823 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", 824 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", 825 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", 826 "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", 827 "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", 828 "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", 829 "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", 830 "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", 831 "gpio177", "gpio178", "gpio179", 832 }; 833 static const char * const qdss_cti_groups[] = { 834 "gpio0", "gpio2", "gpio2", "gpio44", "gpio45", "gpio46", "gpio92", 835 "gpio93", 836 }; 837 static const char * const qup1_groups[] = { 838 "gpio4", "gpio5", "gpio6", "gpio7", 839 }; 840 static const char * const ibi_i3c_groups[] = { 841 "gpio4", "gpio5", "gpio24", "gpio25", "gpio28", "gpio29", "gpio40", 842 "gpio41", 843 }; 844 static const char * const qup_l4_groups[] = { 845 "gpio6", "gpio14", "gpio46", "gpio123", 846 }; 847 static const char * const qup_l5_groups[] = { 848 "gpio7", "gpio15", "gpio47", "gpio124", 849 }; 850 static const char * const qup4_groups[] = { 851 "gpio8", "gpio9", "gpio10", "gpio11", 852 }; 853 static const char * const qup5_groups[] = { 854 "gpio12", "gpio13", "gpio14", "gpio15", 855 }; 856 static const char * const qup6_groups[] = { 857 "gpio16", "gpio17", "gpio18", "gpio19", 858 }; 859 static const char * const qup7_groups[] = { 860 "gpio20", "gpio21", "gpio22", "gpio23", 861 }; 862 static const char * const qup8_groups[] = { 863 "gpio24", "gpio25", "gpio26", "gpio27", 864 }; 865 static const char * const qup0_groups[] = { 866 "gpio28", "gpio29", "gpio30", "gpio31", 867 }; 868 static const char * const qup12_groups[] = { 869 "gpio32", "gpio33", "gpio34", "gpio35", 870 }; 871 static const char * const qup13_groups[] = { 872 "gpio36", "gpio37", "gpio38", "gpio39", 873 }; 874 static const char * const qup14_groups[] = { 875 "gpio40", "gpio41", "gpio42", "gpio43", 876 }; 877 static const char * const ddr_pxi3_groups[] = { 878 "gpio40", "gpio43", 879 }; 880 static const char * const ddr_pxi1_groups[] = { 881 "gpio41", "gpio42", 882 }; 883 static const char * const vsense_trigger_groups[] = { 884 "gpio42", 885 }; 886 static const char * const qup15_groups[] = { 887 "gpio44", "gpio45", "gpio46", "gpio47", 888 }; 889 static const char * const dbg_out_groups[] = { 890 "gpio44", 891 }; 892 static const char * const qup16_groups[] = { 893 "gpio48", "gpio49", "gpio50", "gpio51", 894 }; 895 static const char * const qup17_groups[] = { 896 "gpio52", "gpio53", "gpio54", "gpio55", 897 }; 898 static const char * const ddr_pxi0_groups[] = { 899 "gpio52", "gpio53", 900 }; 901 static const char * const jitter_bist_groups[] = { 902 "gpio54", 903 }; 904 static const char * const pll_bist_groups[] = { 905 "gpio55", 906 }; 907 static const char * const ddr_pxi2_groups[] = { 908 "gpio55", "gpio56", 909 }; 910 static const char * const qup18_groups[] = { 911 "gpio56", "gpio57", "gpio58", "gpio59", 912 }; 913 static const char * const qup11_groups[] = { 914 "gpio60", "gpio61", "gpio62", "gpio63", 915 }; 916 static const char * const usb2phy_ac_groups[] = { 917 "gpio64", "gpio90", 918 }; 919 static const char * const qup_l6_groups[] = { 920 "gpio64", "gpio77", "gpio92", "gpio93", 921 }; 922 static const char * const usb_phy_groups[] = { 923 "gpio65", 924 }; 925 static const char * const pll_clk_groups[] = { 926 "gpio65", 927 }; 928 static const char * const mdp_vsync_groups[] = { 929 "gpio66", "gpio67", "gpio68", "gpio122", "gpio124", 930 }; 931 static const char * const dp_lcd_groups[] = { 932 "gpio67", 933 }; 934 static const char * const dp_hot_groups[] = { 935 "gpio68", 936 }; 937 static const char * const qspi_cs_groups[] = { 938 "gpio69", "gpio75", 939 }; 940 static const char * const tsif0_clk_groups[] = { 941 "gpio69", 942 }; 943 static const char * const qspi0_groups[] = { 944 "gpio70", 945 }; 946 static const char * const tsif0_en_groups[] = { 947 "gpio70", 948 }; 949 static const char * const mdp_vsync0_groups[] = { 950 "gpio70", 951 }; 952 static const char * const mdp_vsync1_groups[] = { 953 "gpio70", 954 }; 955 static const char * const mdp_vsync2_groups[] = { 956 "gpio70", 957 }; 958 static const char * const mdp_vsync3_groups[] = { 959 "gpio70", 960 }; 961 static const char * const qspi1_groups[] = { 962 "gpio71", 963 }; 964 static const char * const tsif0_data_groups[] = { 965 "gpio71", 966 }; 967 static const char * const sdc4_cmd_groups[] = { 968 "gpio71", 969 }; 970 static const char * const qspi2_groups[] = { 971 "gpio72", 972 }; 973 static const char * const tsif0_sync_groups[] = { 974 "gpio72", 975 }; 976 static const char * const sdc43_groups[] = { 977 "gpio72", 978 }; 979 static const char * const qspi_clk_groups[] = { 980 "gpio73", 981 }; 982 static const char * const tsif1_clk_groups[] = { 983 "gpio73", 984 }; 985 static const char * const sdc4_clk_groups[] = { 986 "gpio73", 987 }; 988 static const char * const qspi3_groups[] = { 989 "gpio74", 990 }; 991 static const char * const tsif1_en_groups[] = { 992 "gpio74", 993 }; 994 static const char * const sdc42_groups[] = { 995 "gpio74", 996 }; 997 998 static const struct pinfunction sm8250_functions[] = { 999 MSM_PIN_FUNCTION(aoss_cti), 1000 MSM_PIN_FUNCTION(atest), 1001 MSM_PIN_FUNCTION(audio_ref), 1002 MSM_PIN_FUNCTION(cam_mclk), 1003 MSM_PIN_FUNCTION(cci_async), 1004 MSM_PIN_FUNCTION(cci_i2c), 1005 MSM_PIN_FUNCTION(cci_timer0), 1006 MSM_PIN_FUNCTION(cci_timer1), 1007 MSM_PIN_FUNCTION(cci_timer2), 1008 MSM_PIN_FUNCTION(cci_timer3), 1009 MSM_PIN_FUNCTION(cci_timer4), 1010 MSM_PIN_FUNCTION(cri_trng), 1011 MSM_PIN_FUNCTION(cri_trng0), 1012 MSM_PIN_FUNCTION(cri_trng1), 1013 MSM_PIN_FUNCTION(dbg_out), 1014 MSM_PIN_FUNCTION(ddr_bist), 1015 MSM_PIN_FUNCTION(ddr_pxi0), 1016 MSM_PIN_FUNCTION(ddr_pxi1), 1017 MSM_PIN_FUNCTION(ddr_pxi2), 1018 MSM_PIN_FUNCTION(ddr_pxi3), 1019 MSM_PIN_FUNCTION(dp_hot), 1020 MSM_PIN_FUNCTION(dp_lcd), 1021 MSM_PIN_FUNCTION(gcc_gp1), 1022 MSM_PIN_FUNCTION(gcc_gp2), 1023 MSM_PIN_FUNCTION(gcc_gp3), 1024 MSM_PIN_FUNCTION(gpio), 1025 MSM_PIN_FUNCTION(ibi_i3c), 1026 MSM_PIN_FUNCTION(jitter_bist), 1027 MSM_PIN_FUNCTION(lpass_slimbus), 1028 MSM_PIN_FUNCTION(mdp_vsync), 1029 MSM_PIN_FUNCTION(mdp_vsync0), 1030 MSM_PIN_FUNCTION(mdp_vsync1), 1031 MSM_PIN_FUNCTION(mdp_vsync2), 1032 MSM_PIN_FUNCTION(mdp_vsync3), 1033 MSM_PIN_FUNCTION(mi2s0_data0), 1034 MSM_PIN_FUNCTION(mi2s0_data1), 1035 MSM_PIN_FUNCTION(mi2s0_sck), 1036 MSM_PIN_FUNCTION(mi2s0_ws), 1037 MSM_PIN_FUNCTION(mi2s1_data0), 1038 MSM_PIN_FUNCTION(mi2s1_data1), 1039 MSM_PIN_FUNCTION(mi2s1_sck), 1040 MSM_PIN_FUNCTION(mi2s1_ws), 1041 MSM_PIN_FUNCTION(mi2s2_data0), 1042 MSM_PIN_FUNCTION(mi2s2_data1), 1043 MSM_PIN_FUNCTION(mi2s2_sck), 1044 MSM_PIN_FUNCTION(mi2s2_ws), 1045 MSM_PIN_FUNCTION(pci_e0), 1046 MSM_PIN_FUNCTION(pci_e1), 1047 MSM_PIN_FUNCTION(pci_e2), 1048 MSM_PIN_FUNCTION(phase_flag), 1049 MSM_PIN_FUNCTION(pll_bist), 1050 MSM_PIN_FUNCTION(pll_bypassnl), 1051 MSM_PIN_FUNCTION(pll_clk), 1052 MSM_PIN_FUNCTION(pll_reset), 1053 MSM_PIN_FUNCTION(pri_mi2s), 1054 MSM_PIN_FUNCTION(prng_rosc), 1055 MSM_PIN_FUNCTION(qdss_cti), 1056 MSM_PIN_FUNCTION(qdss_gpio), 1057 MSM_PIN_FUNCTION(qspi0), 1058 MSM_PIN_FUNCTION(qspi1), 1059 MSM_PIN_FUNCTION(qspi2), 1060 MSM_PIN_FUNCTION(qspi3), 1061 MSM_PIN_FUNCTION(qspi_clk), 1062 MSM_PIN_FUNCTION(qspi_cs), 1063 MSM_PIN_FUNCTION(qup0), 1064 MSM_PIN_FUNCTION(qup1), 1065 MSM_PIN_FUNCTION(qup10), 1066 MSM_PIN_FUNCTION(qup11), 1067 MSM_PIN_FUNCTION(qup12), 1068 MSM_PIN_FUNCTION(qup13), 1069 MSM_PIN_FUNCTION(qup14), 1070 MSM_PIN_FUNCTION(qup15), 1071 MSM_PIN_FUNCTION(qup16), 1072 MSM_PIN_FUNCTION(qup17), 1073 MSM_PIN_FUNCTION(qup18), 1074 MSM_PIN_FUNCTION(qup19), 1075 MSM_PIN_FUNCTION(qup2), 1076 MSM_PIN_FUNCTION(qup3), 1077 MSM_PIN_FUNCTION(qup4), 1078 MSM_PIN_FUNCTION(qup5), 1079 MSM_PIN_FUNCTION(qup6), 1080 MSM_PIN_FUNCTION(qup7), 1081 MSM_PIN_FUNCTION(qup8), 1082 MSM_PIN_FUNCTION(qup9), 1083 MSM_PIN_FUNCTION(qup_l4), 1084 MSM_PIN_FUNCTION(qup_l5), 1085 MSM_PIN_FUNCTION(qup_l6), 1086 MSM_PIN_FUNCTION(sd_write), 1087 MSM_PIN_FUNCTION(sdc40), 1088 MSM_PIN_FUNCTION(sdc41), 1089 MSM_PIN_FUNCTION(sdc42), 1090 MSM_PIN_FUNCTION(sdc43), 1091 MSM_PIN_FUNCTION(sdc4_clk), 1092 MSM_PIN_FUNCTION(sdc4_cmd), 1093 MSM_PIN_FUNCTION(sec_mi2s), 1094 MSM_PIN_FUNCTION(sp_cmu), 1095 MSM_PIN_FUNCTION(tgu_ch0), 1096 MSM_PIN_FUNCTION(tgu_ch1), 1097 MSM_PIN_FUNCTION(tgu_ch2), 1098 MSM_PIN_FUNCTION(tgu_ch3), 1099 MSM_PIN_FUNCTION(tsense_pwm1), 1100 MSM_PIN_FUNCTION(tsense_pwm2), 1101 MSM_PIN_FUNCTION(tsif0_clk), 1102 MSM_PIN_FUNCTION(tsif0_data), 1103 MSM_PIN_FUNCTION(tsif0_en), 1104 MSM_PIN_FUNCTION(tsif0_error), 1105 MSM_PIN_FUNCTION(tsif0_sync), 1106 MSM_PIN_FUNCTION(tsif1_clk), 1107 MSM_PIN_FUNCTION(tsif1_data), 1108 MSM_PIN_FUNCTION(tsif1_en), 1109 MSM_PIN_FUNCTION(tsif1_error), 1110 MSM_PIN_FUNCTION(tsif1_sync), 1111 MSM_PIN_FUNCTION(usb2phy_ac), 1112 MSM_PIN_FUNCTION(usb_phy), 1113 MSM_PIN_FUNCTION(vsense_trigger), 1114 }; 1115 1116 /* Every pin is maintained as a single group, and missing or non-existing pin 1117 * would be maintained as dummy group to synchronize pin group index with 1118 * pin descriptor registered with pinctrl core. 1119 * Clients would not be able to request these dummy pin groups. 1120 */ 1121 static const struct msm_pingroup sm8250_groups[] = { 1122 [0] = PINGROUP(0, SOUTH, qup19, qdss_cti, _, _, _, _, _, _, _), 1123 [1] = PINGROUP(1, SOUTH, qup19, _, _, _, _, _, _, _, _), 1124 [2] = PINGROUP(2, SOUTH, qup19, qdss_cti, qdss_cti, _, _, _, _, _, _), 1125 [3] = PINGROUP(3, SOUTH, qup19, _, _, _, _, _, _, _, _), 1126 [4] = PINGROUP(4, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _), 1127 [5] = PINGROUP(5, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _), 1128 [6] = PINGROUP(6, NORTH, qup1, qup_l4, _, _, _, _, _, _, _), 1129 [7] = PINGROUP(7, NORTH, qup1, qup_l5, _, _, _, _, _, _, _), 1130 [8] = PINGROUP(8, NORTH, qup4, _, _, _, _, _, _, _, _), 1131 [9] = PINGROUP(9, NORTH, qup4, _, _, _, _, _, _, _, _), 1132 [10] = PINGROUP(10, NORTH, qup4, _, _, _, _, _, _, _, _), 1133 [11] = PINGROUP(11, NORTH, qup4, _, _, _, _, _, _, _, _), 1134 [12] = PINGROUP(12, NORTH, qup5, _, _, _, _, _, _, _, _), 1135 [13] = PINGROUP(13, NORTH, qup5, _, _, _, _, _, _, _, _), 1136 [14] = PINGROUP(14, NORTH, qup5, qup_l4, _, _, _, _, _, _, _), 1137 [15] = PINGROUP(15, NORTH, qup5, qup_l5, _, _, _, _, _, _, _), 1138 [16] = PINGROUP(16, NORTH, qup6, _, _, _, _, _, _, _, _), 1139 [17] = PINGROUP(17, NORTH, qup6, _, _, _, _, _, _, _, _), 1140 [18] = PINGROUP(18, NORTH, qup6, _, _, _, _, _, _, _, _), 1141 [19] = PINGROUP(19, NORTH, qup6, _, _, _, _, _, _, _, _), 1142 [20] = PINGROUP(20, NORTH, qup7, _, _, _, _, _, _, _, _), 1143 [21] = PINGROUP(21, NORTH, qup7, _, _, _, _, _, _, _, _), 1144 [22] = PINGROUP(22, NORTH, qup7, _, _, _, _, _, _, _, _), 1145 [23] = PINGROUP(23, NORTH, qup7, _, _, _, _, _, _, _, _), 1146 [24] = PINGROUP(24, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _), 1147 [25] = PINGROUP(25, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _), 1148 [26] = PINGROUP(26, SOUTH, qup8, atest, _, _, _, _, _, _, _), 1149 [27] = PINGROUP(27, SOUTH, qup8, atest, _, _, _, _, _, _, _), 1150 [28] = PINGROUP(28, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _), 1151 [29] = PINGROUP(29, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _), 1152 [30] = PINGROUP(30, NORTH, qup0, _, _, _, _, _, _, _, _), 1153 [31] = PINGROUP(31, NORTH, qup0, _, _, _, _, _, _, _, _), 1154 [32] = PINGROUP(32, SOUTH, qup12, _, atest, _, _, _, _, _, _), 1155 [33] = PINGROUP(33, SOUTH, qup12, atest, _, _, _, _, _, _, _), 1156 [34] = PINGROUP(34, SOUTH, qup12, atest, _, _, _, _, _, _, _), 1157 [35] = PINGROUP(35, SOUTH, qup12, atest, _, _, _, _, _, _, _), 1158 [36] = PINGROUP(36, SOUTH, qup13, atest, _, _, _, _, _, _, _), 1159 [37] = PINGROUP(37, SOUTH, qup13, atest, _, _, _, _, _, _, _), 1160 [38] = PINGROUP(38, SOUTH, qup13, _, _, _, _, _, _, _, _), 1161 [39] = PINGROUP(39, SOUTH, qup13, _, _, _, _, _, _, _, _), 1162 [40] = PINGROUP(40, SOUTH, qup14, ibi_i3c, _, ddr_pxi3, _, _, _, _, _), 1163 [41] = PINGROUP(41, SOUTH, qup14, ibi_i3c, _, ddr_pxi1, _, _, _, _, _), 1164 [42] = PINGROUP(42, SOUTH, qup14, vsense_trigger, ddr_pxi1, _, _, _, _, _, _), 1165 [43] = PINGROUP(43, SOUTH, qup14, ddr_pxi3, _, _, _, _, _, _, _), 1166 [44] = PINGROUP(44, SOUTH, qup15, qdss_cti, dbg_out, _, _, _, _, _, _), 1167 [45] = PINGROUP(45, SOUTH, qup15, qdss_cti, phase_flag, _, _, _, _, _, _), 1168 [46] = PINGROUP(46, SOUTH, qup15, qup_l4, qdss_cti, phase_flag, _, _, _, _, _), 1169 [47] = PINGROUP(47, SOUTH, qup15, qup_l5, phase_flag, _, _, _, _, _, _), 1170 [48] = PINGROUP(48, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), 1171 [49] = PINGROUP(49, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), 1172 [50] = PINGROUP(50, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), 1173 [51] = PINGROUP(51, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), 1174 [52] = PINGROUP(52, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _), 1175 [53] = PINGROUP(53, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _), 1176 [54] = PINGROUP(54, SOUTH, qup17, jitter_bist, _, _, _, _, _, _, _), 1177 [55] = PINGROUP(55, SOUTH, qup17, pll_bist, ddr_pxi2, _, _, _, _, _, _), 1178 [56] = PINGROUP(56, SOUTH, qup18, ddr_pxi2, _, _, _, _, _, _, _), 1179 [57] = PINGROUP(57, SOUTH, qup18, _, _, _, _, _, _, _, _), 1180 [58] = PINGROUP(58, SOUTH, qup18, _, _, _, _, _, _, _, _), 1181 [59] = PINGROUP(59, SOUTH, qup18, _, _, _, _, _, _, _, _), 1182 [60] = PINGROUP(60, SOUTH, qup11, _, _, _, _, _, _, _, _), 1183 [61] = PINGROUP(61, SOUTH, qup11, _, _, _, _, _, _, _, _), 1184 [62] = PINGROUP(62, SOUTH, qup11, _, _, _, _, _, _, _, _), 1185 [63] = PINGROUP(63, SOUTH, qup11, _, _, _, _, _, _, _, _), 1186 [64] = PINGROUP(64, SOUTH, usb2phy_ac, qup_l6, _, _, _, _, _, _, _), 1187 [65] = PINGROUP(65, SOUTH, usb_phy, pll_clk, _, _, _, _, _, _, _), 1188 [66] = PINGROUP(66, NORTH, mdp_vsync, _, _, _, _, _, _, _, _), 1189 [67] = PINGROUP(67, NORTH, mdp_vsync, dp_lcd, _, _, _, _, _, _, _), 1190 [68] = PINGROUP(68, NORTH, mdp_vsync, dp_hot, _, _, _, _, _, _, _), 1191 [69] = PINGROUP(69, SOUTH, qspi_cs, tsif0_clk, phase_flag, _, _, _, _, _, _), 1192 [70] = PINGROUP(70, SOUTH, qspi0, tsif0_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, phase_flag, _, _), 1193 [71] = PINGROUP(71, SOUTH, qspi1, tsif0_data, sdc4_cmd, phase_flag, _, _, _, _, _), 1194 [72] = PINGROUP(72, SOUTH, qspi2, tsif0_sync, sdc43, phase_flag, _, _, _, _, _), 1195 [73] = PINGROUP(73, SOUTH, qspi_clk, tsif1_clk, sdc4_clk, phase_flag, _, _, _, _, _), 1196 [74] = PINGROUP(74, SOUTH, qspi3, tsif1_en, sdc42, phase_flag, _, _, _, _, _), 1197 [75] = PINGROUP(75, SOUTH, qspi_cs, tsif1_data, sdc41, _, _, _, _, _, _), 1198 [76] = PINGROUP(76, SOUTH, tsif1_sync, sdc40, _, _, _, _, _, _, _), 1199 [77] = PINGROUP(77, NORTH, qup_l6, aoss_cti, phase_flag, _, _, _, _, _, _), 1200 [78] = PINGROUP(78, NORTH, sd_write, phase_flag, _, _, _, _, _, _, _), 1201 [79] = PINGROUP(79, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _), 1202 [80] = PINGROUP(80, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _), 1203 [81] = PINGROUP(81, NORTH, phase_flag, _, _, _, _, _, _, _, _), 1204 [82] = PINGROUP(82, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _), 1205 [83] = PINGROUP(83, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _), 1206 [84] = PINGROUP(84, NORTH, phase_flag, _, _, _, _, _, _, _, _), 1207 [85] = PINGROUP(85, SOUTH, pci_e2, tgu_ch0, atest, _, _, _, _, _, _), 1208 [86] = PINGROUP(86, SOUTH, pci_e2, tgu_ch3, atest, _, _, _, _, _, _), 1209 [87] = PINGROUP(87, SOUTH, atest, _, _, _, _, _, _, _, _), 1210 [88] = PINGROUP(88, SOUTH, _, atest, _, _, _, _, _, _, _), 1211 [89] = PINGROUP(89, SOUTH, _, atest, _, _, _, _, _, _, _), 1212 [90] = PINGROUP(90, SOUTH, tsif1_error, usb2phy_ac, tgu_ch1, _, _, _, _, _, _), 1213 [91] = PINGROUP(91, SOUTH, tsif0_error, tgu_ch2, _, _, _, _, _, _, _), 1214 [92] = PINGROUP(92, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _), 1215 [93] = PINGROUP(93, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _), 1216 [94] = PINGROUP(94, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _), 1217 [95] = PINGROUP(95, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _), 1218 [96] = PINGROUP(96, NORTH, cam_mclk, pll_bypassnl, qdss_gpio, _, _, _, _, _, _), 1219 [97] = PINGROUP(97, NORTH, cam_mclk, pll_reset, qdss_gpio, _, _, _, _, _, _), 1220 [98] = PINGROUP(98, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1221 [99] = PINGROUP(99, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1222 [100] = PINGROUP(100, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1223 [101] = PINGROUP(101, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1224 [102] = PINGROUP(102, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1225 [103] = PINGROUP(103, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), 1226 [104] = PINGROUP(104, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), 1227 [105] = PINGROUP(105, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1228 [106] = PINGROUP(106, NORTH, cci_i2c, gcc_gp1, qdss_gpio, _, _, _, _, _, _), 1229 [107] = PINGROUP(107, NORTH, cci_i2c, gcc_gp2, qdss_gpio, _, _, _, _, _, _), 1230 [108] = PINGROUP(108, NORTH, cci_i2c, gcc_gp3, qdss_gpio, _, _, _, _, _, _), 1231 [109] = PINGROUP(109, NORTH, cci_timer0, qdss_gpio, _, _, _, _, _, _, _), 1232 [110] = PINGROUP(110, NORTH, cci_timer1, qdss_gpio, _, _, _, _, _, _, _), 1233 [111] = PINGROUP(111, NORTH, cci_timer2, qdss_gpio, _, _, _, _, _, _, _), 1234 [112] = PINGROUP(112, NORTH, cci_timer3, cci_async, _, _, _, _, _, _, _), 1235 [113] = PINGROUP(113, NORTH, cci_timer4, cci_async, _, _, _, _, _, _, _), 1236 [114] = PINGROUP(114, NORTH, cci_async, _, _, _, _, _, _, _, _), 1237 [115] = PINGROUP(115, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), 1238 [116] = PINGROUP(116, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), 1239 [117] = PINGROUP(117, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), 1240 [118] = PINGROUP(118, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), 1241 [119] = PINGROUP(119, NORTH, qup3, phase_flag, _, _, _, _, _, _, _), 1242 [120] = PINGROUP(120, NORTH, qup3, phase_flag, _, _, _, _, _, _, _), 1243 [121] = PINGROUP(121, NORTH, qup3, _, _, _, _, _, _, _, _), 1244 [122] = PINGROUP(122, NORTH, qup3, mdp_vsync, phase_flag, _, _, _, _, _, _), 1245 [123] = PINGROUP(123, NORTH, qup_l4, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _), 1246 [124] = PINGROUP(124, NORTH, qup_l5, mdp_vsync, phase_flag, _, _, _, _, _, _), 1247 [125] = PINGROUP(125, SOUTH, qup9, phase_flag, _, _, _, _, _, _, _), 1248 [126] = PINGROUP(126, SOUTH, qup9, _, _, _, _, _, _, _, _), 1249 [127] = PINGROUP(127, SOUTH, qup9, _, _, _, _, _, _, _, _), 1250 [128] = PINGROUP(128, SOUTH, qup9, _, _, _, _, _, _, _, _), 1251 [129] = PINGROUP(129, SOUTH, qup10, _, _, _, _, _, _, _, _), 1252 [130] = PINGROUP(130, SOUTH, qup10, _, _, _, _, _, _, _, _), 1253 [131] = PINGROUP(131, SOUTH, qup10, _, _, _, _, _, _, _, _), 1254 [132] = PINGROUP(132, SOUTH, qup10, _, _, _, _, _, _, _, _), 1255 [133] = PINGROUP(133, WEST, mi2s2_sck, _, _, _, _, _, _, _, _), 1256 [134] = PINGROUP(134, WEST, mi2s2_data0, _, _, _, _, _, _, _, _), 1257 [135] = PINGROUP(135, WEST, mi2s2_ws, _, _, _, _, _, _, _, _), 1258 [136] = PINGROUP(136, WEST, pri_mi2s, gcc_gp1, _, _, _, _, _, _, _), 1259 [137] = PINGROUP(137, WEST, sec_mi2s, audio_ref, mi2s2_data1, gcc_gp2, _, _, _, _, _), 1260 [138] = PINGROUP(138, WEST, mi2s0_sck, gcc_gp3, _, _, _, _, _, _, _), 1261 [139] = PINGROUP(139, WEST, mi2s0_data0, _, _, _, _, _, _, _, _), 1262 [140] = PINGROUP(140, WEST, mi2s0_data1, _, _, _, _, _, _, _, _), 1263 [141] = PINGROUP(141, WEST, mi2s0_ws, _, _, _, _, _, _, _, _), 1264 [142] = PINGROUP(142, WEST, lpass_slimbus, mi2s1_sck, _, _, _, _, _, _, _), 1265 [143] = PINGROUP(143, WEST, lpass_slimbus, mi2s1_data0, ddr_bist, _, _, _, _, _, _), 1266 [144] = PINGROUP(144, WEST, lpass_slimbus, mi2s1_data1, ddr_bist, _, _, _, _, _, _), 1267 [145] = PINGROUP(145, WEST, lpass_slimbus, mi2s1_ws, _, _, _, _, _, _, _), 1268 [146] = PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _), 1269 [147] = PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _), 1270 [148] = PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _), 1271 [149] = PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _), 1272 [150] = PINGROUP(150, WEST, _, _, _, _, _, _, _, _, _), 1273 [151] = PINGROUP(151, WEST, _, _, _, _, _, _, _, _, _), 1274 [152] = PINGROUP(152, WEST, _, _, _, _, _, _, _, _, _), 1275 [153] = PINGROUP(153, WEST, _, _, _, _, _, _, _, _, _), 1276 [154] = PINGROUP(154, WEST, _, _, _, _, _, _, _, _, _), 1277 [155] = PINGROUP(155, WEST, _, _, _, _, _, _, _, _, _), 1278 [156] = PINGROUP(156, WEST, _, _, _, _, _, _, _, _, _), 1279 [157] = PINGROUP(157, WEST, _, _, _, _, _, _, _, _, _), 1280 [158] = PINGROUP(158, WEST, _, _, _, _, _, _, _, _, _), 1281 [159] = PINGROUP(159, WEST, cri_trng0, _, _, _, _, _, _, _, _), 1282 [160] = PINGROUP(160, WEST, cri_trng1, qdss_gpio, _, _, _, _, _, _, _), 1283 [161] = PINGROUP(161, WEST, cri_trng, qdss_gpio, _, _, _, _, _, _, _), 1284 [162] = PINGROUP(162, WEST, sp_cmu, qdss_gpio, _, _, _, _, _, _, _), 1285 [163] = PINGROUP(163, WEST, prng_rosc, qdss_gpio, _, _, _, _, _, _, _), 1286 [164] = PINGROUP(164, WEST, qdss_gpio, _, _, _, _, _, _, _, _), 1287 [165] = PINGROUP(165, WEST, qdss_gpio, _, _, _, _, _, _, _, _), 1288 [166] = PINGROUP(166, WEST, qdss_gpio, _, _, _, _, _, _, _, _), 1289 [167] = PINGROUP(167, WEST, qdss_gpio, _, _, _, _, _, _, _, _), 1290 [168] = PINGROUP(168, WEST, qdss_gpio, _, _, _, _, _, _, _, _), 1291 [169] = PINGROUP(169, WEST, qdss_gpio, _, _, _, _, _, _, _, _), 1292 [170] = PINGROUP(170, WEST, qdss_gpio, _, _, _, _, _, _, _, _), 1293 [171] = PINGROUP(171, WEST, qdss_gpio, _, _, _, _, _, _, _, _), 1294 [172] = PINGROUP(172, WEST, qdss_gpio, _, _, _, _, _, _, _, _), 1295 [173] = PINGROUP(173, WEST, qdss_gpio, _, _, _, _, _, _, _, _), 1296 [174] = PINGROUP(174, WEST, qdss_gpio, _, _, _, _, _, _, _, _), 1297 [175] = PINGROUP(175, WEST, qdss_gpio, _, _, _, _, _, _, _, _), 1298 [176] = PINGROUP(176, WEST, qdss_gpio, _, _, _, _, _, _, _, _), 1299 [177] = PINGROUP(177, WEST, qdss_gpio, _, _, _, _, _, _, _, _), 1300 [178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _), 1301 [179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _), 1302 [180] = UFS_RESET(ufs_reset, 0xb8000), 1303 [181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6), 1304 [182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3), 1305 [183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0), 1306 }; 1307 1308 static const struct msm_gpio_wakeirq_map sm8250_pdc_map[] = { 1309 { 0, 79 }, { 1, 84 }, { 2, 80 }, { 3, 82 }, { 4, 107 }, { 7, 43 }, 1310 { 11, 42 }, { 14, 44 }, { 15, 52 }, { 19, 67 }, { 23, 68 }, { 24, 105 }, 1311 { 27, 92 }, { 28, 106 }, { 31, 69 }, { 35, 70 }, { 39, 73 }, 1312 { 40, 108 }, { 43, 71 }, { 45, 72 }, { 47, 83 }, { 51, 74 }, { 55, 77 }, 1313 { 59, 78 }, { 63, 75 }, { 64, 81 }, { 65, 87 }, { 66, 88 }, { 67, 89 }, 1314 { 68, 54 }, { 70, 85 }, { 77, 46 }, { 80, 90 }, { 81, 91 }, { 83, 97 }, 1315 { 84, 98 }, { 86, 99 }, { 87, 100 }, { 88, 101 }, { 89, 102 }, 1316 { 92, 103 }, { 93, 104 }, { 100, 53 }, { 103, 47 }, { 104, 48 }, 1317 { 108, 49 }, { 109, 94 }, { 110, 95 }, { 111, 96 }, { 112, 55 }, 1318 { 113, 56 }, { 118, 50 }, { 121, 51 }, { 122, 57 }, { 123, 58 }, 1319 { 124, 45 }, { 126, 59 }, { 128, 76 }, { 129, 86 }, { 132, 93 }, 1320 { 133, 65 }, { 134, 66 }, { 136, 62 }, { 137, 63 }, { 138, 64 }, 1321 { 142, 60 }, { 143, 61 } 1322 }; 1323 1324 static const struct msm_pinctrl_soc_data sm8250_pinctrl = { 1325 .pins = sm8250_pins, 1326 .npins = ARRAY_SIZE(sm8250_pins), 1327 .functions = sm8250_functions, 1328 .nfunctions = ARRAY_SIZE(sm8250_functions), 1329 .groups = sm8250_groups, 1330 .ngroups = ARRAY_SIZE(sm8250_groups), 1331 .ngpios = 181, 1332 .tiles = sm8250_tiles, 1333 .ntiles = ARRAY_SIZE(sm8250_tiles), 1334 .wakeirq_map = sm8250_pdc_map, 1335 .nwakeirq_map = ARRAY_SIZE(sm8250_pdc_map), 1336 }; 1337 1338 static int sm8250_pinctrl_probe(struct platform_device *pdev) 1339 { 1340 return msm_pinctrl_probe(pdev, &sm8250_pinctrl); 1341 } 1342 1343 static const struct of_device_id sm8250_pinctrl_of_match[] = { 1344 { .compatible = "qcom,sm8250-pinctrl", }, 1345 { }, 1346 }; 1347 1348 static struct platform_driver sm8250_pinctrl_driver = { 1349 .driver = { 1350 .name = "sm8250-pinctrl", 1351 .of_match_table = sm8250_pinctrl_of_match, 1352 }, 1353 .probe = sm8250_pinctrl_probe, 1354 .remove = msm_pinctrl_remove, 1355 }; 1356 1357 static int __init sm8250_pinctrl_init(void) 1358 { 1359 return platform_driver_register(&sm8250_pinctrl_driver); 1360 } 1361 arch_initcall(sm8250_pinctrl_init); 1362 1363 static void __exit sm8250_pinctrl_exit(void) 1364 { 1365 platform_driver_unregister(&sm8250_pinctrl_driver); 1366 } 1367 module_exit(sm8250_pinctrl_exit); 1368 1369 MODULE_DESCRIPTION("QTI sm8250 pinctrl driver"); 1370 MODULE_LICENSE("GPL v2"); 1371 MODULE_DEVICE_TABLE(of, sm8250_pinctrl_of_match); 1372